Parallel Processing

and Pipelining
Parallel processing
Parallel processing is a term used to denote a large class of techniques that
are used to provide simultaneous data processing tasks for the purpose of
increasing the computational speed of a computer system.
Instead of Processing each instruction sequentially in a conventional
computer , a parallel processing system is able to perform concurrent data
processing to achieve faster execution time.
For example while an instruction is being executed in the Alu, the next
instruction can be read from memory.
The purpose of parallel processing is to speed up the computer processing
capability and increases its throughput.
Parallel processing
Parallel processing can be viewed from various levels of
complexity . At the lowest level we distinguish between serial
and parallel operations by the types of registers used.
Shift registers operate in serial fashion one bit at a time while
registers with parallel load operate with all the bits of the word
simultaneously.
Parallel processing at a higher level of complexity can be
achieved by having a multiplicity of functional units.
Parallel processing
There are variety of ways that parallel processing can be classified. It can be
considered from the internal organization of the processors ,from the
interconnection structure between processors or the flow of information
between the system.
One classification introduced by M.J. Flynn considers the organization of a
computer system by the number of instructions and data stream
manipulated simultaneously.
The normal operation of a computer is to fetch instructions from memory
and execute them in the processor .
The sequence of instructions read from memory constitutes an instruction
stream.
The operations performed on the data in the processor constitutes a data
stream.
Maximum Speed up:
Instruction Pipeline
An instruction pipeline reads instruction from the memory while previous
instructions are being executed in other segments of the pipeline.
Thus we can execute multiple instructions simultaneously.
In the most general case computer needs to process each instruction in
following sequence of steps:
1.Fetch the instruction from memory (FI)
2.Decode the instruction(DA)
3.Calculate the effective address
4.Fetch the operands from memory (FO)
5.Execute the instruction (EX)
6.Store the result in the proper place
Stall: A stall is a cycle in the pipeline without new input.
Pipeline Hazards:
Dependencies in a pipelined processor
There are mainly three types of dependencies possible in a
pipelined processor. These are :
1) Structural Dependency
2) Control Dependency
3) Data Dependency
These dependencies may introduce stalls in the pipeline.
Stall : A stall is a cycle in the pipeline without new input.
Structural dependency
This dependency arises due to the resource conflict in the
pipeline. A resource conflict is a situation when more than
one instruction tries to access the same resource in the same
cycle.
A resource can be a register, memory, or ALU.
Control Dependency (Branch
Hazards)
This type of dependency occurs
during the transfer of control
instructions such as BRANCH,
CALL, JMP, etc.
On many instruction
architectures, the processor will
not know the target address of
these instructions when it needs
to insert the new instruction into
the pipeline.
Due to this, unwanted
instructions are fed to the
pipeline.
Data Hazard
Data hazards occur when instructions that exhibit data
dependence, modify data in different stages of a pipeline.
Hazard cause delays in the pipeline. There are mainly three
types of data hazards:

1) RAW (Read after Write) [Flow/True data dependency]

2) WAR (Write after Read) [Anti-Data dependency]
3) WAW (Write after Write) [Output data dependency]
 Let there be two instructions I and J, such that
J follow I. Then,
•RAW hazard occurs when instruction J tries to
read data before instruction I writes it.
Eg:
I: R2 <- R1 + R3
J: R4 <- R2 + R3
•WAR hazard occurs when instruction J tries to
write data before instruction I reads it.
Eg:
I: R2 <- R1 + R3
J: R3 <- R4 + R5
•WAW hazard occurs when instruction J tries to
write output before instruction I writes it.
Eg:
I: R2 <- R1 + R3
J: R2 <- R4 + R5
WAR and WAW hazards occur during the out-
of-order execution of the instructions.
THANKYOU