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CHAPTER 5
TRANSISTORS
Introduction
Transistors are three-layered, three- terminal and two-junction electronic devices constructed of doped
semiconductor and whose voltage-current relationship is controlled by a third voltage or current. We may
regard a transistor as a controlled voltage or current source. The word transistor is the combination of two
words. TRANsfer and reSISTOR(transfer and resistor) which means transfer of electrical power from a low
resistive circuit to a high resistive circuit.
They were demonstrated by a team of scientists at Bell laboratories in 1947 and their introduction brought an
end to the age of vacuum tube devices due to some of their merits over vacuum tubes such as:
Transistors are used in such applications as signal amplifiers, electronic switches, oscillators, design of digital
logics, memory circuits etc. Depending on their majority and minority charge carriers, transistors can be
classified as:
Bipolar transistors are so named because their operation involves both electrons and holes. Charge flow in
such transistors is due to bidirectional diffusion of charge carriers across a junction between two regions of
different charge concentrations. Thus, in bipolar transistors the charge carriers are electrons and holes
(majority charge carriers and minority charge carriers) they are principally called Bipolar Junction Transistors
(BJTs).
In Unipolar transistors only one carrier type is involved in charge flow due to drift. This charge carrier is either
electrons or holes as majority charge carriers only. Since only one type of charge is current carrier, such
transistors are called Unipolar Junction Transistors (UJTs). The unipolar junction transistors are mainly known
as Field Effect Transistors (FETs). FETs are to be discussed in the next chapter.
By design, most of the BJT collector current is due to the flow of charges injected from a high-concentration
emitter into the base where they are minority carriers that diffuse toward the collector, and so BJTs are
classified as minority-carrier devices or current controlled devices while FETs are said to be voltage controlled
devices.
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1. A thin layer of P-type material is sandwiched between two N-type materials which is then known as an
NPN transistor Fig.5.1 (a).
2. A thin layer of N-type material is sandwiched between two P-type materials to form a PNP transistor
Fig.5.1. (b).
(a) (b)
(c) (d)
Each semiconductor region is connected to a terminal, appropriately labeled: emitter (E), base (B) and
collector (C). The arrow head on the emitter always indicates to the N-type region and to the conventional
current flow direction.
In both NPN and PNP transistors constructions, the base region is physically located between the emitter and
the collector and is made from lightly doped, high resistive material. Itallows most of the charge carriers to pass
through it from the emitter to the collector (current controlling).The emitter region is usually of low resistive
material, which is heavily doped andsupplies majority charge carriers. The collector region is doped slightly
lower than the emitter regionand it collects the most majority charge carriers. Therefore, due to the above
cases the depletion layers penetrate into the base region (Fig.5.3) and a transistor is considered as a
combination of two pn-junction diodes (Fig.5.1c). In other words, we can see that there are two junctions
shared between the three terminals, the Emitter-base junction and Collector-base junction.
Principles of Operation
For their appropriate (correct) operation both NPN and PNP transistors must be properly biased.
Biasing can be defined as a dc voltage and current that is applied to an electronics device to set up the desired
dc operating points.
The operating point of a device, also known as bias point, quiescent point, or Q-point, is the point on the
output characteristics that shows the DC collector–emitter voltage (Vce) and the collector current (Ic) with no
ac input signal applied. The term is normally used in connection with devices such as transistorsunder their dc
conditions.
Generally, there are four different junction-biasing combinations to have four distinct regions of operation.
Regions of Operation
Forward-Active (or simply, Active): The base–emitter junction is forward biased and the base–
collector junction is reverse biased. Most bipolar transistors are designed to afford the greatest
common-emitter current gain, ßdc or βF, in forward-active mode. If this is the case, the collector–
emitter current is approximately proportional to the base current, but many times larger, for small
base current variations.
Saturation: With both junctions forward-biased, a BJT is in saturation mode and facilitates high
current conduction from the emitter to the collector. This mode corresponds to a logical "on", or a
closed switch.
Cutoff: In cutoff, biasing conditions opposite of saturation (both junctions reverse biased) are present.
There is very little current, which corresponds to a logical "off", or an open switch.
Reverse-Active (or Inverse-Active or Inverted): By reversing the biasing conditions of the forward-
active region, a bipolar transistor goes into reverse-active mode. In this mode, the emitter and
collector regions switch roles. Because most BJTs are designed to maximize current gain in forward-
active mode, the ßdc or βF in inverted mode is several times smaller. This transistor mode is seldom
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used, usually being considered only for failsafe conditions and some types of bipolar logic. The reverse
bias breakdown voltage to the base may be an order of magnitude lower in this region.
In Summary
In most times for both PNP and NPN transistors, the emitter-base junction (EB) is forward-biased while the
collector-base junction (CB) is reverse-biased to use the device as an amplifier, oscillator, mixer, detector, and
so on. The working principle of NPN transistor is discussed here and that of PNP transistor is similar except the
fact that roles of free electrons and holes are interchanged as well as current directions and biasing polarities are
reversed.
In the NPN transistor (Fig.5.2 &Fig. 5.3), the EB junction is forward-biased by V BE, so that the majority charge
carriers (electrons) are emitted from the emitter into the base because the negative potential of the battery of
VBE repels the electrons from the N-type material (emitter).
The collector-base junction (CB) is reverse-based by V BC to collect or attract the most of emitted electrons (say,
about 99%) crossing the CB junction as collector current (I C). Some of the charge carriers from the emitter,
which do not reach the collector (say, about1%), entering the base (recombination) and flow through the base
back to the emitter.
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This is a very small current and known as the base current (I B). Thus, the emitter current (IE) is the total
transistor current which is the sum of base current and collector current (I C).
IE = IC + IB------------------------------------------------ (5.1)
Since IB is very much small, IE and IC are almost equal(IC = IE). Where, is fraction of emitter current which
flows to collector (0.98 - 0.998).
The small base current IBcontrols themuch larger collector current IC.ICis proportional to IB. This is
generally known as the transistor effect.
In the case of a PNP transistor, holes will bedrawn from the emitter into the base region by the forward bias,
and will then be pulled into thecollector region by the higher negative bias
Since the CB junction is reverse-biased, a very small minority charge carrier, called
Reveres Saturation Current, flows through the junction. This current is termed as collector-base-leakage-
current (ICBO). ICBO means, current flowing form collector to the base when the emitter junction is open. This is
due to thermally generated electron-hole pairs even during normal operation. We can now define another
equation adding the effect of ICBO that indicates the total collector current as:
IC = IE + ICBO.------------------------------------------------------------------(5.2)
Note! The circuit current flowing direction is opposite to the electrons (majority charge carriers) drift
direction, because of conventional current direction. (See Fig.3.2 & Fig.3.3).
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The basic Structure of junction field effect transistor is formed from a bar of n/p SC material
called channel with a region of p/n material embedded in each side (fig. 4.1).Top and bottom of
the channel is connected through an ohmic contact to a terminal referred to as, respectively, the
drain (D) and source(S).The two embedded regions are electrically connected and form the
Gate. In practice, the channel is always lightly doped than the gate.
Figure 5.4: Junction Field Effect Transistors basic construction and their symbols
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The region to the right of the pinch-off locus on the figure is the region typically employed in
linear amplifiers (amplifiers with min distortion of the applied signal) and is commonly referred
to as the constant-current, saturation, or linear amplification region. In the ohmic region JFET
can be use as variable resistors of value given as
r d= ro
V GS
( 1− )2
VP
Where ro is the resistance of the channel before applying VGS and Vp is the pinch-off voltage
[( )]
2
V GS
I DS =I DSS 1−
V GS( pinchoff )
Figure 5.10 shows the basic construction of n-channel depletion type MOSFET. The Drain (D)
and Source (S) are connected to the n-doped regions. These N-doped regions are connected via
an n-channel. This n-channel is connected to the Gate (G) via a thin insulating layer of SiO 2. The
n-doped material lies on a p-doped substrate that may have an additional terminal connection
called SS.
Consider the circuit given in the figure 5.11. If the V GS is set to zero and VDS is made to increase,
the effect will be to establish a current similar to that established through the channel of the
JFET. But if VGS is increase negatively, it will tend to pressure electrons toward the p-type
substrate and attract holes from the p-type substrate as shown in Fig. 5.11. Depending on the
magnitude of the negative bias established by V GS, a level of recombination between electrons
and holes will occur that will reduce the number of free electrons in the n-channel available for
conduction.
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The more negative the bias, the higher the rate of recombination. The resulting level of drain
current is therefore reduced with increasing negative bias for V GS as shown. This is called
depletion mode operation.
For positive values of VGS, the positive gate will draw additional electrons (free carriers) from
the p-type substrate due to the reverse leakage current and establish new carriers through the
collisions resulting between accelerating particles. As the gate-to-source voltage continues to
increase in the positive direction. This is called enhancement mode operation.
The Drain (D) and Source (S) connect to the n-doped regions. The Gate (G) connects to the p-
doped substrate via a thin insulating layer of SiO2. There is no channel. The n-doped material
lies on a p-doped substrate that may have an additional terminal connection called SS.
Basic Operation
The Enhancement-type MOSFET only operates in the enhancement mode. Hence, V GS is always
positive and as VGS increases, ID increases. But if VGS is kept constant and VDS is increased, then
ID saturates (IDSS) after the saturation level, VDSsat is reached.
where ,VT is threshold voltage or voltage at which the MOSFET turns on.
k is a constant that can be determined by using the formula:
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P-type FET
The p-channel FET is similar to the n-channel except that the voltage polarities and current
directions are reversed. And regarding response time, as electrons are more mobile than holes,
there will be considerable delay of current in p-channels compared to n-channel FETs.
MOSFET Handling
MOSFETs are very static sensitive. Because of the very thin SiO2 layer between the external
terminals and the layers of the device, any small electrical discharge can establish an unwanted
conduction.
Protection:
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
•Apply voltage limiting devices between the Gate and Source, such as back-to-
back Zeners to limit any transient voltage