0298-W1403570 NT Dg3002ih Ang 03 03

DEFIGARD 3002 IH
Technical Manual
Version 1.13 March 2003
SCHILLER MEDICAL S.A.S

ZAE SUD
4, rue Louis pasteur
BP 90050
F-67162 WISSEMBOURG CEDEX
Téléphone : +33 (0) 3 88 63 36 00
Télécopie : +33 (0) 3 88 94 12 82
Internet : http://www.schiller-medical.com
E.mail : info@schiller.fr
Part No. W1403570

CONTENTS
Page
WARNING..................................................................................................................... 6
NOTE CONCERNING CIRCUIT DIAGRAMS ............................................................... 7
1. INTRODUCTION .................................................................................................... 9
1.1. Presentation ................................................................................................... 9
1.2. Technical characteristics ................................................................................ 11
1.3. Cleaning ......................................................................................................... 18
1.4. List of component abbreviations .................................................................... 19
1.5. List of abbreviations used on diagrams.......................................................... 20
2. OPERATION .......................................................................................................... 28
2.1. General operation .......................................................................................... 28
2.2. Power supplies ............................................................................................... 29
2.3. ECG acquisition ............................................................................................. 30
2.3.1. Acquisition via the 3-lead patient cable ............................................. 30
2.3.2. Acquisition via defibrillation electrodes .............................................. 31
2.3.3. Type of patient cable ......................................................................... 31
2.4. ECG signal processing................................................................................... 32
2.4.1. Amplification and filtering................................................................... 32
2.4.2. Detection of stimulation or defibrillation impulses.............................. 32
2.4.3. QRS complex detection..................................................................... 33
2.4.4. Detection of overshoot and derivation change .................................. 33
2.5. Sound module ................................................................................................ 33
2
2.6. The central unit .............................................................................................. 34
2.6.1. Memory space ................................................................................... 34
2.6.2. The characters EPROM .................................................................... 37
2.6.3. Safeguarding the work RAMs and the timer ...................................... 37
2.6.4. The decoder ...................................................................................... 37
2.6.5. Input and output switching circuit....................................................... 39
2.6.6. Multiplexing and A/D conversion ....................................................... 42
2.6.7. Interruption request hold.................................................................... 43
2.6.8. Watchdog and reset system .............................................................. 44
2.6.9. Interface with the LCD controller ....................................................... 45
2.6.10. The graph interface ........................................................................... 46
2.6.11. Micro-communication ........................................................................ 47
2.7. LCD controller circuit ...................................................................................... 47
2.7.1. LCD controller : old version screen.................................................... 47
2.7.2. LCD controller : new version screen.................................................. 50
2.8. The high voltage circuit .................................................................................. 52
2.8.1. Defibrillator AC power supply ............................................................ 52
2.8.2. HV generator control relay................................................................. 53
2.8.3. The high-voltage generator................................................................ 53
2.8.4. High-voltage measuring circuit at HV converter primary winding....... 55
2.8.5. HV condenser charge timing diagram ............................................... 55
2.8.6. Battery test timing diagram ................................................................ 57
2.8.7. High voltage module .......................................................................... 58
2.8.8. The HV measurement circuit on the HV condenser terminals........... 59
2.8.9. Monitoring circuit for the contact of the patient relay ......................... 61
2.8.10. The defibrillator-test detection circuit ................................................. 62
3
2.9. Defibrillator control ......................................................................................... 63
2.9.1. Supply and battery charge................................................................. 63
2.9.2. The on/off system .............................................................................. 64
2.9.3. Manual semiautomatic locking .......................................................... 67
2.9.4. Selected energy reference ................................................................ 67
2.9.5. Charge/discharge control................................................................... 68
2.9.6. Control logic....................................................................................... 69
2.9.7. Defibrillator safety mechanisms......................................................... 75
2.9.8. Patient current measurement ............................................................ 79
2.9.9. The "Defi-ready" indicator light .......................................................... 79
2.9.10. Graph triggering via the buttons of the hand-held electrodes............ 80
2.9.11. Defibrillation module coding .............................................................. 81

2.9.12. The semiautomatic defibrillator function ............................................ 81
2.9.13. Other functions .................................................................................. 82
2.10. Options........................................................................................................... 83
2.10.1. Communication with the CPU............................................................ 83
2.10.2. External stimulator............................................................................. 88
2.10.3. VF/VT detection................................................................................. 91
3. TEST AND REPLACEMENT OF PRINTED CIRCUITS ......................................... 95
3.1. Unit disassembly and removal of printed circuits ........................................... 95
3.2. Adjustment of the "ECG preamplifier and CPU" circuit .................................. 97
3.3. Adjustment of the "defibrillator control" circuit ................................................ 97
3.4. Adjustment of the "high voltage" circuit .......................................................... 98
3.5. Adjustment of the "external stimulator" circuit ................................................ 99
4. LIST OF SCHEMATICS AND DIAGRAMS............................................................. 100
4
5. LIST OF COMPONENTS ....................................................................................... 103
6. DEVICE MODIFICATION ....................................................................................... 105
6.1. CPU/preamplifier printed circuit...................................................................... 105
6.2. LCD controller printed circuit (old version) ..................................................... 106
6.3. High voltage printed circuit ............................................................................. 107
6.4. Defibrillator control printed circuit ................................................................... 108
6.5. External stimulator printed circuit ................................................................... 110
6.6. CPU communication printed circuit ................................................................ 111
6.7. VF/VT detection printed circuit ....................................................................... 111
6.8. Device wiring .................................................................................................. 112
5
WARNING
_______
This manual should be considered as forming integral part of

the equipment unit it describes.
It is vital for correct operation of the unit and for the safety of
the patient and operator that the contents of this manual be
read and understood.
The maker considers himself responsible for the safety,

reliability and characteristics of the unit only provided:
− the installation, extensions, adjustements, modifications or

repairs are carried out by the maker or by persons
authorized by the maker.
− the electrical installation of the room containing it complies

with the applicable regulations.
− the unit is used in accordance with the operating

instructions.
This manual relates to the unit at the time of going to press.
The maker undertakes to supply all separated pieces for ten

years.
All rights are reserved for units, circuits, procedures and

registered names mentioned in this manual.
The unit has not been designed for uses other than those
specifically described in this manual, which may be hazardous.
6
NOTE CONCERNING CIRCUIT DIAGRAMS
_________________
* Two types of diagram format have been used :
− single sheet diagrams,
− hierarchic diagrams consisting of several sheets of which the first

being the principal diagram and the others being sub-diagrams.
example: the figure below shows the principal diagram of a

printed circuit containing three sub-diagrams, each of
which corresponds to a part of the printed circuit.
J1
12345
SOUS-SCHEMA 1 SOUS-SCHEMA 2 SOUS-SCHEMA 3
SIGNAL G (A2) (D1) SIGNAL I

SIGNAL C (A3)
SP1 D[0..7] (C3)
(B1) SIGNAL A
SIGNAL H (B3) (C4) SIGNAL H
SIGNAL D (D3)
SIGNAL E (C7) (B3) SIGNAL E

SP2
(A1) SIGNAL B 3.SCH
SIGNAL F (D5) (B4) SIGNAL F
D[0..7] (D7) D[0..7]
1.SCH 2.SCH
SCHEMA PRINCIPAL
ART NO :
DRAWN APPROV MODIFICATION PRT NO :
DWG NO :
DSK NO :
SHT NO :
* Several leads (or buses) can be linked to each other on the same
diagram by a specific term (called a "label"), i.e. by the same name
assigned to each lead (or bus).
example:
-R E S E T
* The specific "module port" symbols are used to link signals which are
on different sub-diagrams.
example:
VR EF
7
* The "labels", "module ports" and signals framed by sub-diagrams
shown on the principal diagram are always associated with a reference
in brackets.
examples:
SOUS SCHEMA 1
S IG N A L E (A 6 )
-R E S E T (B 3 ) VREF (D 5 )
S IG N A L F (C 7 )
1 .S C H
For a "label", this reference corresponds to co-ordinates on the same

sheet, whilst for a "module port", the reference corresponds to co-
ordinates on the principal diagram.
On the principal diagram, the reference corresponds to co-ordinates on
the sub-diagram in which it is shown.
8
1. INTRODUCTION
1.1. PRESENTATION
The DEFIGARD 3002 IH is a cardiac monitoring and electrotherapy unit for

emergency hospital use (operating theater, recovery room, intensive care unit,
electro-physiological examination room, stretcher transport between ambulance
and hospital bed) and mobile use.
The DEFIGARD 3002 IH is a compact and lightweight portable unit allowing

patient monitoring, printout of monitored parameters, and defibrillation. The
following options are available :
− adhesive-electrode defibrillation module,

− internal-electrode defibrillation module,
− arterial oxygen saturation SpO2 (DEFIGARD 3002 IH S),
− external stimulation (DEFIGARD 3002 IH P).
On request, a version without recorder can be supplied

(DEFIGARD 3002 IH WOR).
The following options will be available at a later date :
− semiautomatic defibrillation module (SAD),

− ventricular tachycardia or fibrillation (VF/VT) detection,
− external serial interface.
The DEFIGARD 3002 IH can be powered either by the ac supply, an internal

battery, or an external power source, thus allowing the unit to be used on all sites
after being adapted, if necessary.
The unit can be easily user-configured to provide different modes of operation.
The following data are displayed on a color LCD screen :
− ECG signal with indication of measured signal source,

− heart rate and alarm limits (with audible monitoring),
− operating mode,
− continuous defibrillation status (messages and energy values),
− status of cardiac monitoring and unit operation by display of error and
warning messages,
− pulse waveform and blood oxygen saturation level (optional),
− stimulation-related data.
The in-built recorder allows printout of curves with their corresponding data and a
list of events followed by trend curves.
9
Defibrillation is achieved in a simple and safe manner (centralization of
commands on the patient extension module and electrodes, display of all
defibrillation steps on the screen). The energy stored in the condenser and
delivered is continuously displayed on the screen for the detection of any
technical or operational anomalies. Furthermore, a safety mechanism ensures
automatic internal discharge of the condenser if the stored energy is not used.
The triggering of the defibrillation impulse can be either non-synchronized
(ventricular tachycardia or ventricular fibrillation) or synchronized (flutter and
auricular fibrillation, supraventricular tachycardia, etc.).
Depending on required operation, defibrillation can be achieved using hand-held

electrodes, adhesive electrodes (optional, or internal electrodes).
The cardiac stimulation option is intended for use as an emergency transthoracic

pacemaker. This type of pacemaker is to be used in the event of a third-degree
auriculo-ventricular block with severe bradycardia and/or Adams-Stokes
syncope.
The unit operates either in Demand Mode or at constant frequency.
In Demand Mode, the stimulator output impulses are inhibited with each QRS
detection. It remains in this status until the spontaneous heart rate of the patient
falls below the selected stimulation frequency.
The cardiac stimulator option also comprises an "OVERDRIVE" function which
allows the reduction (also for transthoracic stimulation) of certain supraventricular
tachycardia and certain types of ventricular tachycardia.
The SpO2 option allows the display of the pulse curve and arterial oxygen
saturation level.
10
1.2. TECHNICAL SPECIFICATIONS
SUPPLY
Mains supply
Unit classification : 1
Nominal voltage : 230 V / 115 V A.C. - 50 / 60 Hz
Maximum current
protection : · 0.8 AT / 250 V fuses (230 V mains network)
· 1.6 AT / 250 V fuses (115 V mains network)
Battery supply
Battery : NiCad - 14,4 V - 1,7 Ah
Autonomy : 2 h ECG monitoring without recorder or 50

defibrillation impulsions at 360 J
Recharge : automatic when the unit is connected to the mains
Charge verification : by indicator lights
Recharge time : 16 hours (80 % of the maximum capacity)
External 12 V supply
Input signal : 11 to 30 V / 10 A
Connector : 2 pin - ref. CS0222340 - fab. FRBCON
11
MONITOR
ECG signal
Input : · insulated - type CF

· acquisition by 3 lead patient cable, 5 lead
patient cable with selector or by defibrillation
electrodes
· derivations I, II or III or ECG through
defibrillation electrodes
· impedance: 2.5 MΩ at 10 Hz
· protected against defibrillation, stimulation and
electric bistouri
· rejection rate in common mode > 100 dB
· input noise < 35 µV
· unplugged electrode detection
· leak current < 0.1 µA
Input voltage : · dynamic : +/-5 mV

· common mode : +/- 1 V
· differential mode : +/- 1 V
Band pass : · with patient cable : 0.5 - 35 Hz at -3 dB

· with defibrillation electrodes : 1 - 35 Hz at -3 dB
Heart rate range : 10 to 300 beats/min
Calibration : 1 mV scale on the screen and on the printout
Sensibility : 0.25 - 0.5 - 1 - 2 cm/mV
QRS indicator : audible and visual
LCD screens
Passive matrix screen : · type : LCD screen of FSTN type

(old version) · dimensions : 121 x 92 mm
· colour
· 2 track
Scan speed : 25 mm/s
Scan direction : left to right
Trace freeze : by push button
Contrast : 2 button control
12
Passive matrix screen : · type : LCD screen of FSTN type
(black and white screen) · dimensions : 121 x 92 mm
· black and white
· 2 track
Active matrix screen : · type : LCD screen of TFT type

(new version) · dimensions : 179 x 127 mm
· colour
· 2 track
Alarms
Technical alarms : · visual and audible

· 3 minute alarm reject possible
Physiological alarms : · visual and audible

· 3 minute or permanent alarm reject possible
Memory
Trend : 2 or 6 hours
Events : 500 maximum
13
RECORDER
Type : thermal head recorder (8 points/mm)

(thermal head working life: 50 km of paper)
Paper width : 50 mm
Paper length : 45 m roll of paper
Paper advance speed : 25 - 50 mm/s (selection via configuration menu)
Signal sensitivity : same as for screen
Band pass : · with patient cable : 0.5 - 35 Hz at - 3 dB or

0.05 - 35 Hz at - 3 dB (selection with
configuration menu)
· with defibrillation electrodes : 1 - 35 Hz at - 3 dB
Triggering : · manual
· automatic on high or low limit overshoot alarms,
asystolie alarm, charge request or shock
delivery
SPO2 RATE AND PULSE
Input : finger probe or "Y" universal probe
Measuring range : 0 to 100 %
Accuracy : · ± 2 % in the 70 to 99 % range

· ± 3 % in the 50 to 69 % range
SpO2 average with 8 or 16 cardiac beats according to

configuration
Indicator of signal level : with a level bar on screen
Pulse tracing : with automatic gain
PACEMAKER
Operating mode : · demand (DEM)

· asynchronous (FIX)
· overdrive (OVD) : the selected frequency is
multiplied by 2
14
Stimulus : · square signal of 40 ms
· frequency : 40 - 50 - 60 - 70 - 80 - 90 - 100 -
110 - 120 - 130 - 140 - 150 - 160 - 175 - 190 -
210 p/min
· amplitude : 0 - 35 - 45 - 50 - 55 - 60 - 65 - 70 -
75 - 80 - 85 - 90 - 100 - 115 - 130 - 150 mA
Output : adhesive stimulation or defibrillation electrodes
DEFIBRILLATOR
Electrodes
Paddles : CF type
Adhesive electrodes
(option) : CF type
Internal electrodes (option) : CF type
Functions
Display : · selected energy

· delivered energy
Energy selection : by rotating selector
Energies selected over : · 0 - 5 - 10 - 20 - 30 - 50 - 100 - 200 - 300 - 360 J

50 Ω using paddles and adhesives electrodes
· 0 - 5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 - 50 J with
internal electrodes
Functioning modes : · asynchronous

· synchronous
Defibrillator test : measurement of the energy delivered across a

50 Ω test resistor
Safety : internal safety discharge visualised on screen
15
Performance
Nominal service : · 50 maximum energy charges with no delay

between charge cycles (fully charged battery)
· unlimited number of charges with 3 minutes
between each charge cycle (non-stop service
with intermittent charging on mains supply)
Discharge time across a

100 Ω resistor : approximately 4.8 ms for all energies (at 1/3 of
Umax)
Discharge time across a
50 Ω resistor : approximately 2.5 ms for all energies (at 1/3 of
Umax)
Condenser charge time :
· battery fully charged : 8 s
· after 15 maximum
energy discharges : 8s
Oscillogram of a discharge across 25, 50 and 100 Ω
resistors at maximum energy
20 A / square
25 Ohms
50 Ohms
100 Ohms
2 ms / square
16
PHYSICAL ENVIRONMENTAL SPECIFICATIONS
Dimensions : · width : 340 mm

· height : 210 mm without handle
· depth : 305 mm
Mass : approximately 9,75 kg
Operating temperature
extremes : 0 to + 40 °C
Storage temperature
extremes : -10 to + 50 °C
Degree of protection
given by the envelopes : IP 23 with bag
17
1.3. CLEANING
The external surfaces of the unit and the cables can be cleaned using alcohol
soaked cotton.
During cleaning, the unit should be switched off. No liquids should be allowed to
enter the unit ; if however this does occur, the unit should be cleaned and a full
verification is necessary.
The patient cables should be gas sterilised.
The paddles should be carefully cleaned after each use. The conducting cream
should be removed using hot soapy water.
The defibrillation and stimulation electrodes are for single use only.
The internal paddles and their extension cables can be treated by autoclave
(max : 144 °C).
A sponge soaked in hot soapy water can be used to clean the probes.
18
1.4. LIST OF COMPONENT ABBREVIATIONS
Abbreviation Description
BAT Battery - cell

BZ Buzzer
C Capacitor
CTR Cathode ray tube
D Diode - current regulating diode - Schottky diode

DN Diode network
DP LED display
DZ Zener diode - tunnel diode
E Arrester
F Fuse
FB Ferrit bead
FH Fuse holder
J Connector - connection bar - Faston lug

JP Jumper
L Inductance
LA Lamp - neon - indicator light
LD Electroluminescent diode (LED)
LS Loud speaker
M Motor
P Potentiometer
PB Push button
Q Cristal
R Resistor - varistor
RA Adjustable resistor
RB Rectifying bridge
RG Regulator
RL Relay
RN Resistor network
S Socket
SP Solder point
SW Switch - commutator - disconnector
T Transistor
TN Transistor network
TP Test point
TR Transformer
U Integrated circuit - optocoupler
19
1.5. LIST OF ABBREVIATIONS USED ON SCHEMATICS
A[0..15] Bus for addresses originating from the main CPU

ABF[0..15] Buffered address bus
AC1/2/3/4 AC supply voltage
ADMUX[0..5] A/D conversion control signals for multiplexing
ALE Address validation signal
ALRMGRPH Signal indicating a problem on the graph CPU
-ANALYSE Signal originating from the ANALYSIS key on the
semiautomatic module (active at 0 V)
APEX Signal measured on the patient's body with hand-held APEX
electrode
BANK0/1 Selection signals for memory space in extended memory
BATCHLED Battery charge LED indicator light
BATTV1 Permanent battery-voltage (0 - 5 V) monitoring signal
BATTV2 Battery-voltage monitoring signal during the battery test
CAPV HV measurement voltage on the terminals of the HV
condenser (0 - 8 V)
CAPV1 HV measurement voltage on primary winding of HV
converter (0 - 5 V)
CAPV2 Signal CAPV after Potentiometer P2 (0 - 5 V)
-CASB Validation signal for the line addresses of the VIDEO RAM
U5
-CASF Validation signal for the line addresses of the VIDEO RAM
U6
-CH Trigger control signal for CHARGE
-CHARGERL Activation signal for CHARGE relay (active at 0 V)
CHGTDERI Signal indicating a change of derivation
CL1 Signal for the transfer of serial data to the shifting registers of
the LCD screen
CL2L Control signal for serial data shift
CLDSTRT Coding signal for the type of initialization
(coldstart/warmstart)
CLOCK 16-MHz clock signal for micro-communication
COL-VO Variable negative voltage for LCD screen contrast
adjustment
CONFIG Signal originating from the keyboard key for the display of
the configuration menu
CONTR- Signal originating from the keyboard key for the reduction of
screen contrast
CONTR+ Signal originating from the keyboard key for the increase of
screen contrast
20
-CSADC A/D converter U44 selection signal for communication with
the µC
-CSAR42 Write and read selection signal for the graph registers
-CSDAC D/A converter selection signal
-CSDEF Selection signals for the input and output switching circuits
U81 and U85
-CSDIV Selection signal for the input switching circuit U94
-CSDUAL Selection signal for the RAM DUAL PORT
A/D converter U20 selection signal from VFVT detection
-CSGRAPH Selection signals for the input and output switching circuits
U78 and U83
-CSHORO Selection signal for the timer U39
CSINTR Selection signals for the input and output switching circuits
U80 and U86
-CSI/O Input/output register U21/U22 signal selection from VF/vT
detection
-CSKEYS Selection signal for the input switching circuit U65
-CSLCD Selection signal for the bidimensional buffer U53
-CSLCDBF Selection signal for the LCD controller
-CSMUX Selection signal for the switching circuit U84
-CSRAM1 Selection signal for the work RAM U70
-CSRAM2 Selection signal for the work RAM U71
-CSSTIM Selection signals for the input and output switching circuits
U79 and U87
-CSVOICE D/A converter selection signal
-CSUART UART U18 selection signal
-CSWDOG Selection signal for the for the input switching circuit U88 and
reset signal for the counter U46 and the switching circuit
U45B
21
D[0..7] Bus for data originating from the CPU
DBF[0..7] Bus for buffered data to the DUAL PORT RAM
DEFCHARGE Charge phase indication signal (active at +5 V)
DEFDISCH Defibrillator discharge indicator signal (active at +5 V)
DEFELEC Electrode fault indication signal
DEFMOD[0...3] Coding signal of the defibrillation module connected to the
unit
DEFREADY Hold phase indication signal (active at +5 V)
-DEFSEC Defibrillator technical fault indication signal (active at 0 V)
-DEFTEST Defibrillator test detection signal (active at 0 V)
-DEPAS Inhibition signal for ventricular fibrillation QRS in the event of
an overshoot of the ECG signal or a change of derivation
DERI0/1 Derivation selection signals
DETROMP Signal originating from the identification pin of the 3- or 5-pin
patient cable
DGR[0..7] Buffered data bus from recorder
-DISCH DISCHARGE trigger signal
-DISCHENRL Relay activation signal DISCHARGE VALIDATION (active at
0 V)
-DISPOFF LCD screen on/off control signal
DLCD[0..7] Buffered data bus to the character EPROM and the LCD
controller
-DT Datas transfer signal
DUMPLED Not used
ECGFV ECG signal during fibrillation
ECGGRAPH ECG signal for printout on graph
ECGMAX/2 Maximum amplitude of the ECG signal divided by 2
ECG-PACE ECG signal without PACE component
ECGVISU ECG signal for screen display
ECGX1000 Amplified ECG signal with gain = 1000
ECGX6 ECG signal at the preamplifier output (gain = 6)
ELECF Signal measured on the patient's body at Point F with a
patient cable
ELECL Signal measured on the patient's body at Point L with a
patient cable
ELECR Signal measured on the patient's body at Point R with a
patient cable
-EOC Signal indicating the end of conversion by A/D converter U44
EVENTS Control signal originating from the keyboard for printout of
events
EXTIN RS232 serial link (via the 9-pin connector)
EXTOUT RS232 serial link (via the 9-pin connector)
-EXTPWR Signal indicating operation from external power supply
(active at 0 V)
FLM LCD screen image synchronization signal
FREQ0/1/2/3 Stimulation frequency coding signals
FV Factory test signal
22
GAIN0/1 Selection signal for final gain of ECG signal
GAINECG Signal originating from the keyboard for selection of ECG
gain
GAINSON Signal originating from the keyboard for selection of QRS
beep volume
GEL Signal originating from the keyboard for freeze/unfreeze of
screen waveforms
GEST HV generator control signal (active at +5 V)
GNDF1 Ground for hand-held electrodes
GNDP Floating ground for the preamplification part of the
defibrillator's ECG
GRAPHE Signal originating from the keyboard for waveform printout
HPOUT Sound signal sent to loudspeaker
-HVPRES Signal indicating the presence of high voltages (active at low
level)
IO/1/2/3 Stimulation current coding signals
IDELVR Analog coding signal of stimulation current amplitude
IMPSTIM Validation signal for the generation of a stimulation impulse
-INT0/1 Interruption lines
-INTCHGTDER Interrupt signal due to a change of derivation
-INTCHOC Coding signal for the origin of the defibrillator shock
interruption
-INTCOM Synchronization signal in the communication between the
micro-master and the micro-communication
-INTECG Coding signal for the origin of the QRS synchronization
signal interruption (QRS synchro)
-INTEOC Coding signal for the origin of end of conversion interruption
-INTPACE Coding signal for the origin of stimulus detection interruption
(originating from preamplifier)
-INTSTIM Coding signal for stimulation synchronization interruption
(originating from stimulator)
-INTUART Interrupt signal from the serial connection
IO0/1/2/3 Coding signal for the selected stimulation current
IPAT Analog coding signal of amplitude of patient current (0 - 5 V)
IPK1 Patient current measurement signal
-LIMIT Lower detection limit signal for ventricular fibrillation QRS
detection
LINEPWLED AC supply presence indicator LED
LINEPWR Signal indicating the presence of ac supply voltage
-LINEPWR Signal indicating the presence of ac supply voltage (active at
0 V)
MODEDEFI Signal indicating that ECG signal acquisition is via the hand-
held electrodes
MODEDEM Signal indicating stimulation mode (DEMAND mode)
MODEFIX Signal indicating stimulation mode (FIXE mode)
MODEOD Signal indicating stimulation mode (OVERDRIVE mode)
MODESYNC Signal originating from the keyboard key for SYNCHRO
mode validation
23
NEWWINDOW Analyses window reinitialization signal from VF/VT CPU
NIVALRM Signal originating from the keyboard key for alarm limit
selection
NOANALYSE Factory test signal
NU1/2/3/4/5 Signals not used
ODSW Stimulation-impulse validation signal in OVERDRIVE mode
ONOFF1/2 Signals originating from on/off push button
OVERV1 Safety signal HT1 (active at high level)
-PACE Signal for pace detection duration
PACER Inhibition signal from QRS detection when he get a
stimulation impulsion
PATRL Activation signal for PATIENT relay (active at high level)
-PATRL Activation signal for PATIENT relay (active at 0 V)
PATRLSEC Signal indicating that one of the contacts of the patient relay
is closed (0 - 8 V)
PE Protection ground
PSEN EPROM (program code) U76 validation signal
24
-RAS Row address strobe signal
RAZCHGTDER Reset signal for the derivation change switching circuit
-RAZCHOC Reset signal for the memorization switching circuit for -
INTCHOC interruption
RAZCOM Micro-communication reset signal
-RAZECG Reset signal for the memorization switching circuit for -
INTECG interruption
-RAZEOC Reset signal for the memorization switching circuit for -
INTEOC interruption
RAZFV Micro-VF reset signal
-RAZPACE Reset signal for the memorization switching circuit for -
INTPACE interruption
-RAZSTIM Reset signal for the memorization switching circuit for -
INTSTIM interruption
-RAZUART Reset signal for the serial connection memorization switching
circuit
-RD Read validation signal
-RDBF Buffered validation signal for read
-RDBK0/1 Access line to the various graph status registers
-RDGRPH Signal to read the graph CPU registers
-RDRDYBF Signal indicating to the microcontroller that graph CPU status
registers can be read
RDY Signal indicating that the LCD controller is ready to receive
new data
READY "Defibrillator ready" indicator signal (active at high level)
-READY "Defibrillator ready" indication signal (active at low level)
REC Signal originating from graph trigger key
RECSTART Graph trigger signal
RESET Reset signal originating from the watchdog circuit
RETROECL LCD screen backlighting control signal
RJCTALRM Signal originating from the keyboard key for alarm rejection
-RLDSA Activation signal for the manual/semiautomatic locking relay
(active at 0)
RPTALRM Alarm repeat signal
-RSTCTRL Signal provoking control logic reset in the event of a
technical problem (active at low level)
RSTFV VF/VT detection CPU reset signal
-RSTGRPH Graph CPU reset signal
-RSTUART UART U18 reset signal
-RSTVOICE Voice synthesis reset signal
25
SACHARGE Charge trigger signal in semiautomatic mode
SAVEMEMO Inhibition signal for work RAM access in the event of +5 V
failure
SAWSEL0/1 Energy selection signal in semiautomatic mode
SECDISCH Signal indicating a safety discharge (active at +5 V)
SLCTDERV Signal originating from the keyboard key for derivation
selection
SON0/1/2 Selection signal for QRS beep volume
SPO2 Signal originating from the keyboard key for On/Off control of
the SpO2 option
SPO2IN Coding serial signal for the SpO2 module
SPO2ON Control signal for power supply to the SPO2 board
STARTDEF CHARGE/DISCHARGE cycle trigger signal (active at +5 V)
STERNUM Signal measured on the patient's body using STERNUM
hand-held electrode
STRTCONV Battery test control signal (active at +5 V)
SURVT3 Signal used for short-circuit monitoring of T3
-SYNCBF Data transmission synchronization signal coming from graph
SYNCDEF Synchronized defibrillation control signal (active at +5 V)
SYNCSTIM QRS signal for stimulation Demand Mode
SYNTHENB Signal indicating that a vocal message should be emitted
Analog signal of the vocal message originating from the
SYNTHVOC voice synthesis circuit (optional)
TBAT Battery test activation signal
TESTBATT Signal originating from the keyboard key for battery test
control
-TESTDEF Defibrillator test indication signal (active at 0 V)
TOPQRS Logic part of -TOPQRS signal
-TOPQRS QRS complex detection signal
+UBATT 14.4-V nominal NiCad battery voltage
+UCHARGE Voltage present throughout a CHARGE/DISCHARGE cycle
+UDEF Power supply voltage to the defibrillator section
+UDISCHEN Power supply voltage to the patient relay coils
+UEXT External power supply voltage (11 - 30 V, 8 A)
+UHVGEN Power supply voltage to the high voltage generator
+ULNPWR Rectified ac supply voltage for defibrillator
+UMONIT Power supply voltage to the monitor section
26
+V +7.7 V ±0.2 V voltage
+V0 Variable negative voltage for LCD screen contrast
adjustment
+V1 +8.3 V ±0.2 V voltage
-V1 -7.7 V ±0.2 V voltage
VALVLCD LCD screen commuted supply voltage (approximately -23 V)
+VF Floating ECG preamplifier supply voltage for the ECG
signals originating from the patient cable
-VF Floating ECG preamplifier supply voltage for the ECG
signals originating from the patient cable
+VF1 Floating ECG preamplifier supply voltage for the ECG
signals originating from the defibrillation electrodes
-VF1 Floating ECG preamplifier supply voltage for the ECG
signals originating from the defibrillation electrodes
VIN Input voltage from the power supply source (ac supply,
battery, or external direct current)
-VLCD LCD screen supply voltage (approximately -23 V)
VOICE Analog signal for sound to transmit
VRAM Supply voltage for RAM and timer operation
VREF Energy selection signal
VSPO2 Supply voltage of around 9 V for the SpO2 option
WDLCD Inhibition signals for the negative supplies for the LCD
screen in the event of LCD controller failure
-WR Write validation signal
-WRBF Buffered validation signal for write
-WRGRPH Graph CPU register write signal
WRKRAM Selection signal for the interior or extended (exterior)
memory
-WRRDYBF Signal indicating to the microcontroller that the graph CPU is
ready to receive new data/controls
WSEL Selected energy indication analog signal
+13.5V Supply voltage to RL1 of defibrillator, of the screen, of the
recorder, of the sound unit, etc.
-23VCM Commuted supply voltage to the LCD screen (VALVLCD)
+2.5V +2.5-V reference voltage
-2.5V -2.5-V reference voltage
+2.5VF Floating ECG preamplifier +2.5-V reference voltage
-2.5VF Floating ECG preamplifier -2.5-V reference voltage
3BRINS Signal indicating that a 3-lead patient cable is being used
50-60HZ 50-Hz or 60-Hz filter selection signal
5BRINS Signal indicating that a 5-lead patient cable is being used
+5V Supply voltage to the defibrillator control section and the
monitor logic section (+5 V)
+8V Supply voltage to the defibrillator control section (+8 V)
27
2. OPERATION
2.1. GENERAL OPERATION
Note: indications in brackets comprising a letter and a number correspond to the

Cartesian coordinates on the corresponding electronic schematic.
The DEFIGARD 3002 IH is technically divided into two sub-assemblies:

− The upper part of the unit contains the electronics for monitoring functions.
− The lower part of the unit contains the electronics for defibrillation functions.
The monitoring function includes the following components:
− An ECG preamplifier for processing the input signal measured on the patient.
− A central unit which controls the communication between the various
functional sections.
− An LCD controller.
− An LCD screen for curve and data display.
− An LCD power supply.
− A recorder for the printout of curves and data.
− a control keyboard.
It also comprises the following optionally available functions:
− A communication circuit linking the central unit to the circuits of the optional
function modules (SpO2, VF detection, serial linking).
− An SpO2 circuit.
− A VF detection circuit.
− A stimulator.
The defibrillation section essentially comprises two electronic circuits: the

defibrillator control circuit and the high voltage circuit.
The defibrillation section is connected to a HV condenser, a discharge inductor,
a 50-Ω resistor, a defibrillator test detection torus, and an electrode connection
module, and controls the various defibrillation functions:
− The HV generator.
− HV measurement.
− Charge/discharge control signals.
− Defibrillator monitoring.
− Patient current measurement.
− Defibrillator test.
− Semiautomatic function, etc.
The defibrillation section also comprises the unit power supply. The various
voltages required by the defibrillator and monitor are generated from the ac
supply, a 14.4-V battery, or an external supply.
28
2.2. POWER SUPPLIES
(see schematics on Pages 103, 104, 106 or 111, 112, 114 or 119, 120, 122)
* The Power Supply Source

(Schematic 1/7)
Voltage VIN (C6) from the power source can vary between 11 and 30 V. This
source is connected at J1 (C8) on the Central Unit and Preamplifier printed
circuit and originates from the defibrillator.
* The Main Power Supplies

(Schematic 4/7)
A first chopper regulator RG4 (D8) in association with the transformer TR1,
the diode D13, and the capacitors C63 and C64 generates a 13.5 V voltage
(D5) and a sufficiently high current to power the screen backlighting, the
recorder, the sound circuits, etc.
A second chopper regulator RG5 (C8) in association with the 3-12 winding of
TR2, D7, C69, and C71 produces the +5 V voltage (D5) to power the logic
section, display control, and extension logic systems.
The 4-11 and 5-10 windings of TR2 produce the energy required by the Non-
Floating ECG Treatment section by generating in association with D9, C74,
and RG7 a voltage +V1 of +8.3 V ±0.2 V (C5) and in association with D10,
C77, and RG8 a voltage -V1 of -7.7 V ±0.2 V (C5).
The voltage -VLCD of -23 V ± 1 V (C5), required for LCD screen functionning,
is produced by the 6-9 winding of TR2 in association with D8, C72, RG6, and
DZ10.
The 7-8 winding of TR2 in association with D11 and C80 supplies the VSPO2
(C5) voltage of approximately 12 V for a current of 100 mA for the supply of
the SpO2 option.
* ECG Preamplifier Power Supply

(Schematic 2/7)
The transformer TR2 (described below) has a final winding (insulated) which
gathers the energy necessary to the floating ECG preamplifier whose
connection is located on the floating part of the printed circuit at SP1 and SP2
(A6).
Along with RG2 and DZ14, the +VF voltage of +7.7 V ±0.2 V (A4) is obtained
and with RG1, C48, C49, RG3, and DZ15, the -VF voltage of -7.7 V ±0.2 V
(A4) is obtained.
Still in this floating part, an electrically insulated sub-assembly is contained:

the ECG Acquisition via Defibrillation Electrodes section. This section is
powered by the voltages +VF1 (C7) and -VF1 (B7) produced by D3, C53, D5,
C54, TR4, the astable built around U63B, and the driver U3 (+VF1 = 7.5 V
±0.2 V; -VF1 = 6.9 V ±0.2 V).
29
2.3. ECG ACQUISITION
(see Pages 103, 104 or 111, 112 or 119, 120)
2.3.1. Acquisition via the 3-lead patient cable

(Schematic 2/7)
The patient cable is connected to the green connector located on the

upper chassis of the DEFIGARD 3002 IH.
An internal link cable transports the acquisition signal voltages to

Connector J2 (D8, Schematic 1/7) of the Central Unit and Preamplifier
printed circuit.
The exploders E1, E2, and E3 (D6, C6) protect the floating section
against overvoltages (defibrillation shocks, electrostatic discharges).
The resistors R71, R72, and R73, and the diodes DN1, DN2, and DN3,
protect the inputs of the Multiplexers U1 and U2 (C4, B4).
Multiplexers U1 and U2 are controlled by the CPU as a function of the

chosen derivation using U9 and U10 (D1).
U1 transmits two of the three acquisition signals to the differential

amplifier built around U5 and U32A (C2), via a HF filter (L1, L2, C1, C2).
Amplifier U32B (B3), its surrounding components, and the upper stage of
U2 allow control and therefore reduction of the common mode voltages.
A 1.1 V signal (junction point of R69 and R68) (C4) is supplied to the
ECG acquisition electrodes via the high resistance resistors R225, R3,
R226, and R4.
U4 mounted as a follower, transmits to the electrode fault detection unit

(U6 and U7) (B2) the voltages resulting from the following combination:
1.1 V voltage/electrode polarization voltage/patient electrode
resistance/R225, R3, R226, and R4.
The comparators U6 and U7 switch for voltages above +0.95 V and

below -0.95 V and send an electrode fault message to the CPU via U12.
The signal, output from the differential stage, is transmitted to the

insulating amplifier U11 (A1) via the lower stage of the multiplexer U2.
The comparators of U8 (A2) allow a too high input differential voltage to

be detected and so activate the optocoupler U12.
30
2.3.2. Acquisition via defibrillation electrodes
(Schematic 2/7)
The signals APEX and STERNUM, present on the conductor J5 (D8,

Schematic 1/7) of the printed circuit, originate from an internal link cable
connected to the defibrillator.
These signals (B8, A8) limited to 90 V in the defibrillator section, are

again limited to the supply voltages ±VF1 with R74, R75, DN4, and DN5
and frequency-limited with L7, L8, C50, and C51.
Preamplification is carried out by U93, differential by U63A (B5),

insulation between the two floating sections by TR3, and
modulation/demodulation of the preamplified signals by U98 and U99
(synchronized with the energy transfer frequency for the power supply to
the ECG Preamplifier via the Defibrillation Electrodes).
2.3.3. Type of patient cable

(Schematic 2/7)
Via R81, a voltage is applied to Pin 5 of J2 (D8, Schematic 1/7) and to

the "-" inputs of U34's comparators. This voltage is dependent of the
resistor in the patient cable between pins 5 and 4 of J2.
If a 3-lead patient cable is used, and in view of the short-circuit existing in

the 3-lead patient cable connector, U34B supplies the diode of the
optocoupler U13 which generates the 3BRINS signal and sends it to the
CPU.
If a 5-lead patient cable is used, and in view of the 2.2 kΩ resistance

existing in the 5-lead patient cable connector, U34B is at a low level,
U34A is at a high level and therefore supplies the diode of the
optocoupler U35 which hence generates the 5BRINS signal and sends it
to the CPU.
If there is no patient cable connected, the signals 3BRINS and 5BRINS

remain at a high level.
31
2.4. ECG SIGNAL PROCESSING
(see Pages 103, 105 or 111, 113 or 119, 121)
2.4.1. Amplification and filtering

(Schematic 3/7)
Originating from the floating section and depending on derivation choice,

a signal with a gain of 6 which is subjected to a low-pass filter by U14A
(D8) is present at the output of the insulating amplifier U11 (A1,
Schematic 2/7).
The signal at the output of U14A (D8) has its direct component removed
by the 0.05-Hz high-pass filter (C23, R24), then undergoes a 12-fold
amplification by U20A, is again subject to a 14-fold amplification by
U20B to which the base-line drift adjustment is associated (P1, R33).
The signal at the output of U20B (D5) then has a gain of 1000; it is then
low-pass filtered at 45 Hz by U20C, then crosses U20D (C4) and is
subject to the final operator-defined gain: the CPU generates the signals
GAIN0 and GAIN1 (D8) which control the binary attenuation multiplexer
U25 of the ECG signal.
At the output of U20D (C4), the ECG signal can have a gain of 250, 500,
1000, or 2000: it crosses a switchable 50/60-Hz rejecter filter with the
help of U33; it is then amplitude-limited at ±3.3 V by R77, DZ5, and DZ6
to enter the multiplexer U29 (D1) in which the summation on the possible
PACE+30ms signal and the high-pass filtering of the ECG waveform
displayed on the LCD screen are performed.
Note: in the event of ECG signal acquisition via the defibrillation

electrodes, the initial high-pass filtering (C23, R24) (D7) is
modified by the conduction of R25 in U19D (controlled by the
MODEDEFI signal) by bringing the band-pass for the final ECG
signal from 1 to 35 Hz (graph + screen).
2.4.2. Detection of stimulation or defibrillation impulses

(Schematic 3/7)
Impulsion detection is carried out in the non-floating section with signal

gain at 6.
U14B (A8) and its associated components detect a sudden variation in
slope and trigger the 65-ms monostable U16A via the comparators of
U15.
At the same time, U18's comparators (B7) detect a large amplitude
variation (> ±75 mV) of the signal present with respect to its average
value (R38, C16).
Superposing the slope variations (U18) and amplitude variations (U16)
gives information concerning the detection duration of stimuli at the
output of U17A or on TP7.
This logic signal triggers a 30 ms monostable U90A to facilitate the
visualization of very short stimuli, and an 85 ms monostable U90B which,
associated with U31B/C/D and T5 (B2), avoids false QRSs being
counted.
32
2.4.3. QRS complex detection
(Schematic 3/7)
Present at TP2 (D4), the 1000-gain ECG signal is conformed in a band-

pass filter built around U24 (C4).
The resulting signal is double-alternation rectified by U26B/C; the
comparator U26A detects the overshoot of the rectified signal (with QRS
component) with respect to the envelope of the same signal (U26D,
(D2)), associated with R60/C36.
This detection triggers the 195 ms monostable U28A which generates

the TOPQRS signal on TP3.
2.4.4. Detection of overshoot and derivation change

(Schematic 3/7)
With all continuous components removed at TP6 (C1), the ECG signal at
its final gain (A5) is averaged by R22 and C27, and compared at ±2 V
with U22 which detects if the ECG signal goes out of the visualization
frame (graph or screen).
U23C collects this overshoot information and triggers a 160-ms

monostable U28B which acts on the capacitive link C23/R24 (D7) by
conduction of R26 via U19C (C7), which results in the ECG curve being
recentered.
In the event of a change of derivation, the monostable U28B (A2) is also

activated by the signal CHGTDERI (A5) originating from the CPU and its
adapter (U21A, C110, U23A).
2.5. SOUND MODULE

(see Page 106, 114 or 122 Schematic 4/7)
The various sounds are emitted by a loudspeaker connected to J13 (C8,

Schematic 1/7) on the printed circuit.
This loudspeaker (HPOUT signal, (A1)) is attacked, via C93, by the audio
amplifier U37 (A2) with a gain of one, and whose input signal comes from the
multiplexer U38 (A4) via U36D.
Eight different analog signals are multiplexed by the control-logic signals from the
CPU: SON0, SON1, and SON2 (B8). With its surrounding components, U36B
(B6) generates three sinusoidal signals of different amplitudes but with the same
frequency; U36A (A6) produces similar signals at a different frequency.
U36C (A6) serves as an amplifier for the audio input originating from the voice
synthesis option.
U96A (A7) produces a continuous voltage, necessary for the operation of
Oscillators U36A/B/C.
33
2.6. THE CENTRAL UNIT
(see Pages 103, 106, 107, 108, 109 or 111, 114, 115, 116, 117 or 119, 122, 123,
124, 125)
The central unit (micro-master) controls, processes, and checks the control
signals sent to the various functional sections of the unit.
− Preamplifier checks.
− Alarm management.
− Screen control.
− Keyboard management.
− Control of graph signals.
− Management of the defibrillator-monitor interface.
− Micro-communication checks.
− Stimulator checks.
The central unit is built around the microcontroller U72 (D5, Schematic 5/7)
driven by the 16-MHz quartz Q1.
The data bus has an 8-bit architecture; it is multiplexed with the eight lightweight
address bits to obtain a 16-bit address bus.
The register U74 (D5, Schematic 2/7), mounted as a demultiplexer, allows the 8-
bit lightweight addresses to be locked using the signal ALE from Pin 33 of the
microcontroller. When the ALE signal is in state 1, the outputs of U74 follow the
input states. When the ALE signal goes to the 0 state, the inputs are insulated
from the outputs and output states of U74 are held until the ALE signal next goes
to the 1 state. These states code for the addresses A[0..7].
2.6.1. Memory space

(Schematic 5/7)
The memory space addressable by the microcontroller comprises:
− 64 kilo-octets of program memory.

− 64 kilo-octets of work memory (internal memory) and address
memory for the various peripherals.
− 256 kilo-octets of extended memory.
The program is contained in the EPROM U76 (D4) with a 64-kilo-octet

memory. It is under the control of the signals ALE and PSEN. PSEN
originating from Pin 32 of U72 operates the memory selection (PSEN = 0
--> program memory).
34
Access to the Program EPROM
ALE
-PSEN
PORT A PCR A0-A7 PCR A0-A7 PCR
PORT C A8-A15 A8-A15
PCR = Program Code Read
The internal memory of 64 kilo-octets is divided into several blocks. The

first block of 60 kilo-octets is used by the circuits U70 (C4) and U71 (B4),
and the 32-kilo-octet RAMs allowing various variables to be saved. The
contents of these memories is safeguarded when power is removed from
the system.
The second block of 2 kilo-octets is used by the circuit U9 (on the
optional printed circuit W4P41540A); it is a 2-kilo-octet DUAL PORT
RAM.
The remainder of the memory space is divided into 16 128-octet sub-
blocks, each allowing a peripheral to be addressed. This division is
carried out by the decoder U73 (B7).
The following table shows the organization of the internal memory space:
0000 - EFFF Work RAMs
F000 - F7FF Dual Port RAM (-CSDUAL)
F800 Address signal -CSLCD
F880 Address signal -CSAR42
F900 Address signal -CSGRPH
F980 Address signal -CSKEYS
FA00 Address signal -CSMUX
FA80 Address signal -CSADC
FB00 Address signal -CSDEF
FB80 Address signal -CSINTR
FC00 Address signal -CSWDOG
FC80 Address signal -CSDIV
35
FD00 Address signal -CSHORO
FD80 Address signal -CSDAC
FE00 Address signal -CSSTIMU
FE80 X
FF00 X
FF80 X
The internal addressable memory space is under the control of the

address bus and the signals -RD, -WR, and WRKRAM (WRKRAM = 1).
Decoding of the work RAMs U70 (C4) and U71 (B4) is controlled by the
signal WRKRAM and the bus A[12..15] via U67 and U68 (C5 and B5).
These two circuits control at the same time the passage to the Work
RAM Safeguard mode using the signal SAVEMEMO (see Section 2.6.3.
Safeguard of the Work RAMs Contents). During normal operation, Inputs
12 and 13 of U67B, and Input 13 of U68B should be at 1. Access to the
contents of the work RAMs is gained using -CSRAM1, -CSRAM2, -RD,
-WR, A[0..14], and D[0..7] (-CSRAM1 = 0 for U70; -CSRAM2 = 0 for
U71; -RD = 0 for read; -WR = 0 for write).
The 256-kilo-octet extended memory space is under the control of the

address bus ABF[0..15] and the signals -RD, -WR, WRKRAM
(WRKRAM = 0), BANK0, and BANK1. The first 64 kilo-octets are
occupied by the characters EPROM U69 (A4).
BANK1 BANK0 ABF[0..15] WRKRAM = 0
0 0 0000 - FFFF Characters EPROM
0 1 0000 - FFFF X
1 0 0000 - FFFF X
1 1 0000 - FFFF X
36
2.6.2. The characters EPROM
(Schematic 5/7)
Access to the characters EPROM is achieved using the data bus

DLCD[0..7] via the bidirectional buffer U53 (A2), and the address bus
ABF[0..15] via the buffers U54 and U55 (A7), under the control of
WRKRAM, BANK0, BANK1, and -RD.
When the signals WRKRAM, BANK0, BANK1, and -RD are in a low
state, the characters EPROM is validated. At the same time, WRKRAM
validates the bidirectional buffer U53 via U50D. The direction of data
transmission through U53 is controlled by the signal -RD; when -RD is in
a low state, data transmission direction is from DLCD[0..7] to D[0..7].
2.6.3. Safeguarding the work RAMs and the timer

(Schematic 5/7)
The printed circuit comprises a function allowing the safeguard of the

contents of the work memories U70 (C4) and U71 (B4), and of the timer
registers U39 (B4) when the unit is switched off or in the event of a
failure of the +5 V supply. This safeguard is ensured by a 3.6-V lithium
battery.
When the unit is switched on, the supply voltage VRAM is generated
from the +5 V voltage via D15 (B5). In the absence of the +5 V voltage,
the power supply is ensured by the battery via D14.
A SAVEMEMO impulse originating from the watchdog function is
generated whenever the +5 V signal falls below 4.5 V. The shape (and
amplitude) of the SAVEMEMO impulse follows the shape of the falling
+5 V signal. Via T6, this impulse forces and holds Outputs 8 of U67B
and U68B into a high state, thus inhibiting all access to the RAMs. In
safeguard mode, the output levels of U67B and U68B corresponds to the
battery voltage.
4,5 V
+5 V
SAVEMEMO
outputs 8 of
U67B and 68B
"active" mode "safeguard" mode
37
At power-up, a SAVEMEMO impulse originating from the watchdog
function is generated, thus ensuring the passage from the Safeguard
mode to the Active mode of the work RAMs.
+5 V 4,5 V
SAVEMEMO
outputs 8 of
U67B and 68B
"safeguard" mode "active" mode
The signals -CSRAM1, -CSRAM2, -WR and -RD give access to the work
RAMs:
− -CSRAM1 = 0 and -WR = 0: write access to the RAM U70.
− -CSRAM1 = 0 and -RD = 0: read access to the RAM U70.
− -CSRAM2 = 0 and WR = 0: write access to the RAM U71.

− -CSRAM2 = 0 and -RD = 0: read access to the RAM U71.
The signals -CSHORO, -WR, and -RD give access to the timer:
− -CSHORO = 0 and -WR = 0: write access to timer.
− -CSHORO = 0 and -RD = 0: read access to timer.
2.6.4. The decoder

(Schematic 5/7)
The role of the decoder U73 (B7) is to generate decoding impulses for
the validation of the various input and output switching circuits and
functions. The output state of the various signals depends on the status
of the lines A[7..10] (see table of internal memory space). Validation of
U73 is controlled by a decoding logic circuit built around U89 and
dependent of A[11..15] and WRKRAM (WRKRAM must be at 1).
38
2.6.5. Input and output switching circuits
(Schematic 6/7 and 7/7)
The input and output switching circuits (74HC573) form the interface
between the CPU and the various functional sections and modules, via
the data bus D[0..7] and the control lines -CS..., -WR, and -RD.
The switching circuits U88, U80, U79, U78, and U81 (D7, C7, C7, A7,
and A7 respectively, Schematic 6/7), U65, U66, and U94 (D3, C3, and
B3 respectively, Schematic 7/7) are input configured. They are validated
by a low level on Input EN which results from an OR logic combination
(U77A, U75D, C, A, U77B, U64C, B, and U75B) of the signal -RD and
the signals originating from the decoder U73 (B7, Schematic 5/7). When
an EN input passes to a low state, the data present at the input of the
corresponding switching circuit are transferred to the data-bus side and
are read by the microcontroller. When Input EN passes to a high state,
the data-bus side passes to a high impedance state.
The input switching circuit U88 allows the transfer of signals present on
the unit's configuration jumper J14 (D8, Schematic 6/7); these signals
indicate the presence of the modules SpO2, VF (ventricular fibrillation
detection), graph, stimulator, external RS232 interface, and emulator (for
software adjustment). The presence of the jumpers forces the switching
circuit input to 0.
The input switching circuit U80 allows the transfer of the microcontroller's
interruption signals and of this coding for the functionning mode of the
stimulator.
The input switching circuit U79 also allows the transfer of signals
originating from the stimulator. These signals operate the coding of the
stimulation frequency and the stimulation current.
FREQ3 FREQ2 FREQ1 FREQ0 Frequency (BPM)

0 0 0 0 40
0 0 0 1 50
0 0 1 0 60
0 0 1 1 70
0 1 0 0 80
0 1 0 1 90
0 1 1 0 100
0 1 1 1 110
1 0 0 0 120
1 0 0 1 130
1 0 1 0 140
1 0 1 1 150
1 1 0 0 160
1 1 0 1 175
1 1 1 0 190
1 1 1 1 210
I3 I2 I1 I0 Current (mA)
39
0 0 0 0 0
0 0 0 1 35
0 0 1 0 45
0 0 1 1 50
0 1 0 0 55
0 1 0 1 60
0 1 1 0 65
0 1 1 1 70
1 0 0 0 75
1 0 0 1 80
1 0 1 0 85
1 0 1 1 90
1 1 0 0 100
1 1 0 1 115
1 1 1 0 130
1 1 1 1 150
The input switching circuit U78 allows the transfer of various input
signals.
The input switching circuit U81 allows the transfer of signals originating
from the defibrillator. The signals DEFMOD0, 1, 2, and 3 operate coding
to indicate the type of defibrillation cassette connected to the unit.
DEFMOD3 DEFMOD2 DEFMOD1 DEFMOD0 Cassette
0 0 0 1 Hand-held
electrodes
0 0 1 0 Internal electrodes
0 1 0 0 External
electrodes
1 0 0 0 Semiautomatic
mode
1 1 1 1 No cassette
The input switching circuits U65 and U66 allow the transfer of signals
present on the keyboard.
The input switching circuit U94 allows the transfer of signals present on
keyboard (not used) and of various input signals.
40
The input switching circuits U84, U86, U87, U83, and U85 (D6, C6, C6,
A6, and A6 respectively, Schematic 6/7) are output configured. They are
validated by a high state on Input C1 which results in a NOR logic
combination (U82C, D, A, U57D, and U82B) of the signal -WR and the
signals originating from the decoder U73 (B7, Schematic 5/7). When a
C1 input passes to a high state, the data-bus line states are transferred
to the output of the switching circuit. When the C1 input passes to a low
state, the outputs are insulated from the inputs and the data remain
memorized in the outputs.
The output switching circuit U84 allows the transfer of multiplexing

signals which control the successive passage of the various signals in
the A/D converter.
Signal for
ADMUX5 ADMUX4 ADMUX3 ADMUX2 ADMUX1 ADMUX0
conversion
0 0 0 0 0 0 ECGVISU
0 0 0 0 0 1 ECGGRAPH
0 0 0 0 1 0 ECG-PACE
0 0 0 1 0 0 GNDTEST
0 0 0 1 0 1 +2.5VTEST
0 0 0 1 1 0 +5VTEST
0 0 1 1 X X BATTV1
0 0 1 1 X X IDELVR
0 1 0 0 X X WSEL
0 1 0 1 X X CAPV2
0 1 1 0 X X IPAT
0 1 1 1 X X BATTV2
The output switching circuit U86 allows the transfer of RAZ signals of
interruption switching circuit for the backlighting signal.
The output switching U87 circuit allows the transfer of defibrillator control
signals.
The output switching circuit U83 allows the transfer of various signals
including the selection signals for the ECG derivations and the selection
signals for the ECG signal gain.
DERI1 DERI0 Derivation

0 0 I
0 1 II
1 0 III
1 1 DEFI
GAIN1 GAIN0 ECG gain

0 0 0.25
0 1 0.5
1 0 1
1 1 2
41
The output switching circuit U85 allows the transfer of various signals
including the selection signals for the QRS beep volume.
SON2 SON1 SON0 Amplitude Sound frequency

0 0 0 off
0 0 1 low F1
0 1 0 medium F1
0 1 1 high F1
1 0 0 voice synthesis
1 0 1 high F2
1 1 0 medium F2
1 1 1 low F2
2.6.6. Multiplexing and A/D conversion

(Schematic 6/7)
The control signals ADMUX[0..5] originating from the output switching

circuit U84 (D6) have voltage levels between 0 and 5 V. Using the
voltage level adapters built around U91 and U92 (C4 and D4), the
voltage levels between 0 and 5 V are transformed into -V and +V voltage
levels suitable for controlling the multiplexers which are powered by +V
and -V.
The analog signals ECGVISU, ECGGRAPH, ECG-PACE whose range is

centered on 0, are multiplexed a first time through U42 (C4) then attack
a voltage follower U41B. U41A imposes a +2.5 V shift to bring the signal
range to between 0 and 5 V. The output of U41A attacks a second
multiplexer U43 (C2) which directs the signals to the input of the A/D
converter U44 (B1) via a voltage follower U41D.
Inputs 12, 14, and 15 of U42 (ground, +2.5 V, and +5 V) are reference
voltages which serve for the A/D converter test.
The analog signals BATTV1, IDELVR, WSEL, CAPV2, IPAT, and

BATTV2 whose range is between 0 and 5 V, attack directly the second
multiplexer U43. The networks connected to the inputs of the analog
signals BATTV1, IDELVR, WSEL, CAPV2, IPAT, and BATTV2, made up
of resistors, diodes, and capacitors, serve to protect the inputs of the
second mutiplexer against overvoltages (signals originating from the
defibrillator).
C104 and R133 (C1) form the RC network of the clock of the A/D
converter (520 kHz). When the signals -CSADC and -WR go to 0, U44
starts a conversion. The passage of EOC to 0 indicates the end of the
conversion, which results in an interrupt request. The data are recovered
by the microcontroller using the data bus D[0..7] and the control signals
-CSADC and -RD (-CSADC = 0 and -RD = 0).
42
-CSADC
-WR
-RD
-EOC
start of end of conversion reading of data

conversion of available ready for another
data conversion
2.6.7. Interruption request hold

(Schematic 4/7)
This function allows interruption requests to be saved while waiting to be

processed.
Interruption requests are divided into two groups:
− The first group is made up of the interruption requests -TOPQRS and

-EOC (D4). Both of these interruption requests use the same
interruption line -INT0 which is located at Output 3 of U58A (TP18).
− The second group is made up of the interruption requests -PACE,
DEFDISCH, and IMPSTIM (C4). All three of these interruption
requests use the same interruption line -INT1 which is located at
Output 8 of U50C (TP17).
When an interruption request is given, the input of the concerned

memorization switching circuit(s) passes to the high state (U61B (D3),
U61A (D3), U60B (C3), U60A (C3), and U45A (C3)). This rising front
forces the output of the memorization switching circuit(s) to the low state.
A low state on one or more of the switching circuits results in the -INT0
(or -INT1) line being pushed to a low state, which indicates to the
microcontroller that an interruption has been requested. As soon as the
microcontroller recognizes that an interruption has been requested, it
interrogates the lines -INTEOC, -INTECG, -INTSTIM, -INTCHOC, and -
INTPACE via the register U80 (C7, Schematic 6/7) to determine the
origin of the interruption request(s). It then resets the concerned
switching circuit(s) using the control signal(s) -RAZEOC, -RAZECG,
RAZSTIM, -RAZCHOC, or -RAZPACE via the register U86 (C6,
Schematic 6/7) and executes the routine.
Example of a TOPQRS interruption request sequence:
43
TOPQRS
-INTECG
-RAZECG
2.6.8. Watchdog and reset system

(Schematic 7/7)
The watchdog's task is to monitor proper functioning of the program,

generate a reset signal at power-up, and monitor the level of the +5 V
signal.
The reset impulse RESET can be triggered by three situations:
− In the first case, the reset impulse is generated at power-up on

Output 6 of U49 (A7).
− In the second case, the reset impulse can be generated by the +5 V

monitoring circuit, built around U49 (A7); this circuit generates an
impulsion if the +5 V signal falls below +4.5 V.
− In the third case, a reset impulse can be triggered by the circuit which
monitors proper program functioning (watchdog). The principle of this
monitoring is based on the repetition of the impulse of the -CSWDOG
signal in a given time period.
At power-up, the impulse generated by U49 initializes the counter U46

via U48C. Output 4 is chosen to attack the circuit built around C125,
R137, and D20 which will generate the reset impulse (RESET) (the
other outputs of U46 remain not connected). The choice of this output
depends on the timer frequency of the counter U46 (Pin 10) and of the
delay between two -CSWDOG impulsions. The timer of the counter
U46 is built around U47A and U47E and generates a square signal
with a period of approximately 16.5 ms.
When two -CSWDOG impulsions are too far apart, or in the absence
of a signal, the output of the counter passes to a high level, thus
provoking a reset impulsion RESET.
-CSWDOG
D20
output 6
of U48B
44
Depending on the origin of the RESET impulse, the microcontroller
runs a different initialization sequence.
If the origin of the RESET impulse is the monitoring of the +5 V signal,
the CLDSTRT output of the memorization switching circuit passes to a
high state (case of power-up). A low state on Input 10 of U45B forces
the CLDSTRT output to 1. The first impulse of the -CSWDOG resets
the CLDSTRT output to 0.
If the RESET impulse originates from the counter U46, the CLDSTRT
output of the memorization switching circuit remains in a low state.
The SAVEMEMO impulse serves to ensure the passage to the work

RAM safeguard mode in the event of a drop in the +5 V signal.
2.6.9. Interface with the LCD controller

(Schematic 5/7)
The interface which ensures the link with the LCD controller comprises
the following:
− Control logic allowing the inhibition of LCD screen negative supply
voltages during power-up and in the event of a problem on the LCD
controller printed circuit.
− Switching transistors T1, T2, T3, and T4 allowing the verification of the
negative supply voltages.
− A D/A converter allowing the adjustment of the contrast voltage.
At power-up, the voltages VALVLCD and COL-VO (D1) are inhibited,

giving the LCD controller time to complete its initialization phase. This is
achieved using an impulse generated by C208, R180, and D24 (D3)
which is longer than the RESET impulse. Output 8 of U95C passes to a
high state and blocks the transistors T1 and T3 and thus cuts the
negative voltages VALVLCD and COL-VO which supply the LCD screen.
The WDLCD signal indicates proper functioning of the LCD controller

board; when this signal passes to a high state, the voltages VALVLCD
and COL-VO are cut.
+5V
WDLCD
RESET
output 8
of U95C
VALVLCD
COL-VO
45
The contrast voltage COL-VO is adjusted by the D/A converter U62 (C3)
and the operational amplifier U40 (C2). Via the data bus D[0..7] and the
control lines -CSDAC and -WR, the converter receives the coding data
for the contrast voltage from the microcontroller (-CSDAC = 0 and -WR =
0). The operational amplifier U40B is mounted as an inverter with a gain
of 5.6.
The data buffer U53 (A2) is bidirectional. It is controlled by three signals -

RD, -CSLCD, and WRKRAM. The signal -RD determines the direction of
data transmission. When it is in a high state, transmission direction is
from D[0..7] to DLCD[0..7].
When Output 11 of U50D (B2) is in a high state, the bus D[0..7] is
insulated from the bus DLCD[0..7].
2.6.10 The graph interface

(Schematic 5/7)
Communication with the graph is achieved using the data bus DGR[0..7]
(B1) via the bidirectional buffer U52 (B2). When the signal -CSAR42 is in
a low state, it validates the bidirectional buffer; the signal -RD imposes
the data transmission direction (when it is in a low state, transmission
direction is from DGR[0..7] to D[0..7]).
The signals -RDGRPH and -WRGRPH (C6) are read and write impulses
from the registers of the graph CPU. These impulses are generated from
the impulse -CSAR42 associated with -RD (for -RDGRPH) and -WR (for
-WRGRPH) via the two OR gates (U48A and U48D) (C8).
The signals -WRRDYBF, -RDRDYBF, and -SYNCBF (D8) attack the PB

port of the microcontroller U72 via the buffer U56B (D7). When the signal
-WRRDYBF is in the low state, this indicates that the graph CPU can
send new data and/or commands. When the signal -RDRDYBF is in the
low state, this indicates that the state datas of graph CPU can be read by
the main microcontroler. The signal -SYNCBF is a synchronization signal
for the transmission of graphics and alphanumeric data.
The signal ALRMGRPH passes to a high state when there is a problem

with the graph.
The signals RDBK0 and RDBK1 are coding signals from the graph CPU
status registers (B8, Schematic 6/7).
46
2.6.11 Micro-communication interface
(Schematic 5/7)
The impulse -CSDUAL (B6) allows the validation of access to the DUAL
PORT RAM. The decoding signal -CSDUAL is generated from A[11..15]
via U89B, U47F, U95B, and U77C (B7). Communication with the DUAL
PORT RAM is achieved using the data bus DBF[0..10] via the
bidirectional buffer U51 (C2) and the address bus ABF[0..10] via the
buffers U54 and U55 (A7).
When the signal -CSDUAL is in the low state, it validates the buffer U51.
The signal -RD selects the direction of data transmission; when -RD is in
the low state, the transmission direction is from DBF[0..7] to D[0..7].
2.7. LCD CONTROLLER CIRCUIT

(see Page 127, 129, 131, 133, Schematic 1/1)
2.7.1. LCD controller : old version screen
The LCD controller circuit ensures the interface between the central unit
(micro-master) and the LCD screen. It comprises:
− A 20-MHz clock built around U9 and U4E.

− Video RAMs U5 and U6.
− Output buffers U1 and U2.
− A watchdog function built around U7, U4, and U8.
− A controller U3 (EMP7128).
The data sent by the micro-master using the data bus DLCD[0..7], the
address bus ABF[0..2], and the control lines -WRBF and -CSLCDBF are
received by the controller U3.
-CSLCDBF
-WRBF
DLCD[0..7]
ABF[0..2]
The data stored in the video memory (U5 and U6) are re-read by the
controller U3 and transmitted to the LCD screen using the data bus
D[0..7] via the buffers U1 and U2.
The control signals CL2L, CL2U, CL1, and FM generated by the

controller U3 serve for display management of the LCD screen.
47
50,40 µs
3 X Tosc
0,150 µs
324 325 326 327 328 329 330 331 332 333 334 335 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ... 318 319 320 321 322 323 324 325 326 327 328 329 330
CL2U
CL2L
CL1
450 ns
CL1
FLM
50 µs
12,10 ms
48
The signal -DISPOFF generated by the controller U3 (EMP7128) allows
the LCD display to be switched off; when this signal is at 1, the display is
on, and off when the signal is at 0.
The signal RETROECL controls the on/off of the backlighting; when this
signal is at 1, the backlighting is on.
The signal READY generated by the controller U3 indicates to the micro-
master that it is ready to receive new data (in the case of a fast micro-
controller). This control line is currently not used.
P1 allows adjustment of the backlighting brightness. Maximum
brightness is obtained when the P1 value is at a minimum. This can also
be achieved by short-circuiting Pins 4 and 5 of J2 (P1 isn't mounted).
The watchdog function consists of generating a control signal WDLCD

which inhibits the supply signals VALVLCD and COL-VO in the event of
signal FLM failing. The oscillator built around U4D and U4C generates a
square signal with a period of approximately 352 µs (2840 Hz).
At power-up and as soon as the signal FLM is present, the counter 4040
and the output WDLCD of U8A are reset. As long as the impulses
generated by the FLM signal are present, Output 4 of U7 remains at 0. In
the event of a failure of the signal FLM, and after approximately 22 ms,
Output 4 of U7 passes to 1, which also results in the WDLCD signal
passing to 1, causing the voltages VALVLCD and COL-VO to be cut.
+5 V
pin 10
of U7
pin 11
of U7
pin 1
of U8A
12 ms 12 ms 22 ms 12 ms
WDLCD
49
2.7.2. LCD controller : new version screen
The "LCD controller" printed circuit ensures the function of controller for
the TFT LCD colour screen and for the LCD black and white screen.
It comprises :
n a 24MHz clock (U8),
n video RAMs U2 and U3,
n a buffer circuit U5,
n a watchdog function built around U6, U4 and U7,
n a controller U1 (whose programmation depends on screen type used).
Communication between the controller and the micro-master
The communication between the video controller U1 and the micro-

master is realizing through the data bus DLCD[0..7], the address bus
ABF[0..2], the command signals -CSLCDBF, WRBF and the READY
signal (generated by the video controller, he indicated to the micro-
master that it is ready to receive new data).
TFT colour screen
The communication between the controller and the TFT screen made
through J1 and J2 (H.S, D.E., RED, GREEN and BLUE signals from U1.
U5 is abuffer circuit for the signals enumerate above.
V.S.
63 µs
15,5 ms
H.S.
32 µs
D.E.
190 µs 5 µs
The RETROECL signal controls the LCD screen luminance ; it is at "1"
50
Watchdog
The watchdog generates a "WDLCD" signal inhibits the power supply (-

V0 and -VEE for the black and white LCD screen and VRTR for the TFT
LCD screen) of the LCD screen in the event of signal V.S. (F.L.M.)
failing. The oscillator built around U4C and U4D generates a square
signal (approximately 352 µs).
At power up and as soon as the signal V.S. (F.L.M.), the counter 4040
and the output WDLCD of U7A are reset. As long as the impulses
generated by the V.S. (F.L.M.) signal are present, output 4 of U6
remains at "0", what's force WDLCD to"1", causing the voltages -VEE
and -V0 to be at "0V". The passing at "oV" of the -VEE voltage, cause
the blocking of T1 who switch off the VRTR power who supply the TFT
LCD screen.
Black and white screen
The communication between the controller and the black and white
screen made through J3 and J4 (FLM, CL1, CL2, D[0..3]. The signal -
DISPOFF controls the ON/OFF system of the LCD screen ; when this
signal is at "0", the LCD screen is OFF.
The signal RETROECL controls the ON/OFF of the backlighting ; when
this signal is at "1", the backlighting is on.
FLM
42 µs
10,1 ms
CL1
42 µs
CL2
23 µs
42 µs
250 ns
500 ns
51
2.8. THE HIGH-VOLTAGE CIRCUIT
(see Page 135 or 137, Schematic 1/1)
The high-voltage circuit comprises various functions:
· AC power supply for the defibrillator section.

· HV generator control relays.
· HV generator.
· High-voltage circuit.
· Patient current measurement.
· Monitoring circuit for the patient relay contacts.
· HV measuring circuit on the HV condenser terminals.
· HV measuring circuit on the primary winding of the HV converter.
· Defibrillator test detection circuit.
2.8.1. Defibrillator AC power supply
The ac power supply for the defibrillator section essentially comprises

two components:
− The ac supply transformer TR1 (D8).
− The rectifying bridge RB1 (D7).
The filtering capacitor of the rectified secondary voltage is C9 (D8); it is

located at the input of the HV generator (see general overview of the
defibrillator section).
The general technical specifications of the transformer TR1 are as

follows:
− Primary windings: 2 x 115 V.
− Secondary windings: 2 x 9 V connected in series.
− Useful power: 45 VA.
− The transformer comprises two in-built thermo-switches (primary),
ensuring overload protection.
The supply voltage +ULNPWR is of the order of 23 V = when the

defibrillator is on standby.
52
2.8.2. HV generator control relay
To start the HV generator, two actions are required:

− Activation of the charge relay RL1 (D7).
− Signal GEST at high level (C8).
-CHARGERL
0 t
GEST
0 t
0 t
activation of the HV generator
2.8.3. The high-voltage generator
The high-voltage generator is built around U1 (LM393) (C6) and U2

(UC3843A) (B5) which drive the HV converter TR2 (D4). U2 is a PWM
chopper regulator which controls the two switching transistors T4 and T5.
The oscillator comprises two feedback loops:
a) Current servo-assistance terminating the conducting phase.

b) The VDS voltage monitoring system to start a conduction cycle.
Current servo-assistance is carried out using R8 (B4). The voltage at the

terminals of R8 reflects the primary current of the HV converter TR2.
The start of each conducting cycle, after complete demagnetization of
the ferrite, is driven by the combination of T2 (D5) and its surrounding
components when a falling VDS front occurs.
Because the duration required for demagnetization is a function of the

secondary voltage amplitude, the oscillator frequency will progressively
increase over the course of charging.
53
Signals from HV Generator
Battery test sequence operation.
VDS
90 V
35 V
0 t
VGS
0 t
ID
21 A
0 50 µs 35 µs t
0 t
phase de phase de phase de
conduction démagnétisation conduction
?
The above graph gives the signals from the HV generator at a given time
during the battery test sequence. The supply voltage to the HV generator
is 14.4 V (nominal voltage of a NiCad battery containing twelve 1.2-V
cells).
54
2.8.4. High-voltage measuring circuit at HV converter primary winding
Because the HV converter TR2 (D4) is mounted as a Flyback type

accumulation, the primary voltage is proportional to the secondary
voltage during the demagnetization phase. This proportionality is
exploited by a circuit which measures the secondary voltage via the VDS
voltage on the primary winding of the HV converter.
This circuit, called HV1 Measurement, allows two functions:

− Generation of a signal allowing charging to be stopped (when the
selected energy level is reached): CAPV1.
− Generation of a safety signal in the event of a fault on the standard
path: OVERV1 (this safety signal also deactivates the HV generator).
This measurement circuit HV1 is based on a transistor T1 in a current-

mirror setup. The voltage at the terminals of R9 (C6) produces the
measurement signal: CAPV1.
The potentiometer P1 (D6) allows to set the charge stop. The circuit U1A
(C6) supplies the signal OVERV1 which also inhibits the oscillator U2
(B5).
2.8.5. HV condenser charge timing diagram
The curve on the following page shows the main signal variations as a
function of time for the HV condenser.
All the control signals are supplied by the defibrillator-control printed
circuit (W4P41536).
55
CHARGE
key
0 t
-CHARGERL
0 t
activation of the charge relay RL1

STARTDEF
activation of the safety discharge relay RL3

80 ms
GEST
0 t
VDS
T4,T5
90 V
75 V
+U ALIM
GENE. HT
0 t
CAPV1
sel. energy
level 360 J
0 t
activation of of the discharge
validation relay RL2
-DISCHENRL
0 t
35 ms
(the indicated amplitudes and durations have a +/- 10 % tolerance)
56
2.8.6. Battery test timing diagram
The following curves show the variation of the main signals as a function
of time during a battery test.
The control signals are also supplied by the defibrillator-control printed
circuit (W4P41536).
TEST BATT
key
0 t
-CHARGERL
0 t
activation
of the charge relay RL1
GEST
0 2s t
VDS
T4,T5
90 V
35 V
+ U ALIM
GENE. HT
0 t
(the indicated amplitudes and durations have a +/- 10 % tolerance)
57
2.8.7. High-voltage module
The printed circuit W4P41535 also comprises the high-voltage module,

with the exception of two components which are wired into the lower
chassis. These two components are:
− The high-voltage condenser 32 µF/5.2 kV (C4).
− The discharge inductance coil 26 mH/7.2 Ω (D3).
The high-voltage module fills a certain number of roles:

− Charging the HV condenser.
− Safety discharge of the HV condenser.
− Discharge of the HV condenser via the discharge inductance coil and
the patient relays.
− Protection of the ECG preamplifier from the defibrillator.
− Patient current measurement at defibrillation.
* Charging the HV Condenser
The HV converter TR2 operating in the accumulation regime directly

generates on the secondary winding the high voltage required for
charging the HV condenser.
HV rectification is achieved by the diode D8 (D4). Resistor R7
protects the diode D8 by limiting the current during a short-circuit
discharge of the HV condenser.
* Safety Discharge of the HV Condenser
The safety discharge circuit comprises the following components:

− RL3 (C3): safety discharge relay.
− R23 (D3) and R46 (C3): safety discharge resistors.
− U4 (C3): optocoupler giving an indication of the safety discharge
(the signal DUMPLED is not used on the DEFIGARD 3002 IH).
* Patient Discharge Circuit of the HV Condenser
The patient discharge circuit essentially comprises the discharge

inductance coil (26 mH/7.2 Ω) and patient relays RL4 (D2) and RL5
(C2).
The inductance coils L1 (D3), L2 (C3), L3 (D2), and L4 (B2), for high-
frequency filtering.
* Protection Circuit of Defibrillator ECG-Preamplifier
The protection of the defibrillator's ECG preamplifier against

defibrillation impulses is achieved by the resistors R47 and R48, and
the exploder E1 (D2 and C2).
58
* Patient-Current Measurement during Defibrillation
The printed circuit W4P41535 comprises the patient-current

measuring stage. The measuring circuit is based on the use of a
current transformer TR3 (B1) whose primary winding is crossed by
the defibrillation current.
The current value is obtained at the terminals of R37 and R38,

Galvanic insulation from the HV circuit being ensured by TR3.
The figure below represents the signal IPK1 for a 360-J discharge
across 50 Ω.
IPK1(V)
500 mV
0 t (ms)
t
10 = 3,7 ms
(the indicated amplitudes and durations have a ±10 % tolerance)
2.8.8. The HV measurement circuit on the HV condenser terminals
A second HV measuring circuit, called Measurement HT2, independent

from the measuring circuit HT1, is built using resistive dividers R34, R35,
R33, and R36, and U3A (A4 and A3).
The measurement circuit HT2 measures the high voltage directly at the
terminals of the HV condenser. The two resistive dividers R34-R35 and
R33-R36 are ground-referenced (0 V battery).
The operational amplifier U3A is mounted as a differential amplifier and
supplies the signal CAPV. The signal CAPV is directly proportional to the
high voltage:
HT
CAPV = ---------
1100
59
The signal CAPV is used to carry out three functions:
− Inhibition of charging during the safety discharge phase.
− Display of energy during the charging, holding, and safety discharge
phase.
− Fills the role of an additional safety circuit (safety HT2).
Note: These three functions are located on the defibrillator control

printed circuit (W4P41536).
The figure below shows the evolution of the CAPV signal over a
CHARGE/DISCHARGE cycle at 360 J.
STARTDEF
0 t
charging holding discharge
phase phase phase
Tmax = 20 s
H.T.
safety
5,2 kV discharge
0 t
CAPV
4,7 V
0 t
60
2.8.9. Monitoring circuit for the contacts of the patient relay
The function of fault detection on a contact of the patient relay is carried

out by the two resistive dividers R29, R25, and R26, and the operational
amplifier U3B (A2 and A1).
The principle is the same as that for the measurement circuit HT2. The
operational amplifier U3B is also mounted as a differential amplifier and
supplies the signal PATRLSEC.
The PATRELSEC allows the safety system to be triggered if one of the
patient relays sticks.
The two high-voltage resistors R29 and R30 are located on the soldered
side of the printed circuit W4P41535. However, the test of this function
does not require access to the underside of the printed circuit.
The figure below shows the evolution of the signal PATRLSEC during
the test of this function.
activation of patient
H.T. relay on open circuit
600 V
0 t
charging hold safety
discharge
PATRLSEC
6V
0 t
The 600 V charge voltage corresponds to an energy of 5 J (the indicated

amplitudes have a 10 % tolerance).
61
2.8.10 The defibrillator-test detection circuit
The defibrillator-test detection circuit comprises three essential functions:

− The 50 Ω discharge resistor.
− A detection torus.
− A shaping circuit.
The 50-Ω discharge resistor and the detection torus are located in the
electrode support chassis. The shaping circuit is integrated into the high-
voltage printed circuit W4P1535.
The signal supplied by the detection winding is rectified by RB2 (A8)

before attacking T7. R42 and C18 allow impulse duration to be
increased. The output signal thus generated is called -DEFTEST.
The figure below shows the signals relating to a defibrillator test for a
selected energy of 100 J.
I(A)
34 A
100 J defibrillation impulse
0 t
detection t 10 = 4,4 ms
torus
30 V
signal from detection torus on charge
R = 10 kO
0 t
50 µs
RB2(+)
3V
0 t
-DEFTEST
0 t
130 ms
The indicated amplitudes and durations have a ±30 % tolerance.
62
2.9. DEFIBRILLATOR CONTROL
(see Pages 139, 140, 141, 142 or 144, 145, 146, 147 or 149, 150, 151, 152)
The printed circuit for defibrillator control comprises various functions:
· Power supply to monitor section.

· Power supply via the external input (11 - 30 V).
· Battery charge circuit.
· On/Off system.
· Locking of Manual/Semiautomatic Mode.
· Selected energy reference.
· Charge/discharge control.
· Control logic.
· Relay control circuits.
· Defibrillator safety circuit.
· Patient current measurement.
· Graph triggering via hand-held electrodes.
· Defibrillator semiautomatic mode.
2.9.1. Supply and battery charge

(Schematic 2/4)
The printed circuit W4P41536 comprises the monitor section power

supply, the battery charge circuit (via ac supply), and the power supply
via the external input (11 - 30 V).
Power to the monitor section is supplied via the ac-supply transformer
TR1 (D8). The secondary voltage is rectified by the rectifying bridge RB1
and filtered by the capacitor C58. The rectified voltage is approximately
23 V =.
When the DEFIGARD 3002 IH is connected to the ac supply, the

presence of the ac supply is indicated by an LED on the front panel.
This indication is given by the signal LINEPWLED via R96 and D17 (D3).
The transistor T7 (D1) also supplies this information to the CPU
(W4P41537) via R96, R111, and D14 (-LINEPWR signal).
Battery charging (14.4 V/1.7 Ah) through the main network is

accomplished using the supply voltage +ULNPWR (see W4P41535)
which is the ac supply for the defibrillator section. The regulator RG1
(B5), mounted as a constant current source, supplies the battery charge
current. The fuse F1 protects the battery in the event of overcharging.
The battery charge current is 125 mA ±5 %.
Battery charging (14.4 V/1.7 Ah) through the external DC network is

accomplished using a DC/DC converter (RG4) wich supply the current
regulator (RG1). Characteristics from charging battery with the main
network or the 11V-30V input are strictly identycal (charging 80% in 16
h). The voltage converter built around RG4 and TR2 is a fly back
configuration. The output voltage straightening and filtering are
respectively assured from D29 and C78.
63
The output voltage (+24V) is regulated through the resistor bridge (R64
and R65). The diodes D30 and D31 constitute reverse lock diodes
between the +ULNPWR output and the switching regulator output (RG4
and TR2).
The transistor T6 supplies the LED (battery charge indicator) using the
signal BATCHLED.
The power supply for the DEFIGARD 3002 IH is provided by two distinct
supply voltages:
· +UMONIT: monitor section supply voltage.

· +UDEF: defibrillator supply voltage.
Power supply for the DEFIGARD 3002 IH using the incorporated battery
is provided using the two diodes with common anodes DN4 (B7).
When the DEFIGARD 3002 IH is supplied by an external direct-voltage

source (11 - 30 V), the relays RL3 and RL4 (D5) are activated. The two
supply voltages (+UMONIT and +UDEF) are then provided by the
external voltage source. The diode D19 provides circuit protection
against accidental polarity inversion, the fuse F4 (8 AT) protects the
power supply against a possible overvoltage. The transistor T10
supplies a control signal -EXTPWR to the CPU (W4P41537) to indicate
the presence of an external power source.
2.9.2. The on/off system

(Schematic 2/4)
The On/Off system is built around U26, U22, T8, RL2, and the
associated components. The circuit made up of U26A (C5) constitutes
an anti-rebound switching circuit. U26B is mounted as a Flip-Flop circuit.
Pressing the On/Off button (signal ONOFF1) results in a supply voltage
of approximately +5 V being established on the cathode of DZ6 (C5) via
R90 and D13. The switching circuit U26B is reset by C71 and R127.
After a rebound inhibition period (approximately 10 ms), Output Q (Pin 1,
U26A) goes to the high state, also provoking the passage to the high
state of Output Q (Pin 15, U26B). The conduction of the transistor T8
provokes the activation of the On/Off relay RL2 (C2). At the same time,
the output of the open-collector comparator (Pin 7, U22) is held at zero
for a duration determined by C66 and R60 (B6). The closing of the
contacts of the On/Off relay RL2 provokes the appearance of the supply
voltages +UMONIT and +UDEF. The auto-supply of the circuits U26 and
U22 is now carried out by R63 and D16 (C3). Pressing the On/Off
button a second time results in a change of state on the switching circuit
U26B (after a rebound inhibition time) and the DEFIGARD 3002 IH is
switched off (see signal evolution as a function of time during an On/Off
cycle on the following page).
64
On/Off Cycle
On/Off
push button
0 t
cathode DZ6
pin 16 of U26B
0 t
RESET
pin 12 of U26B
0 t
RESET
pin 4 of U26A
0 t
Q
pin 1 of U26A
0 t
-Q
pin 2 of U26A
0 t
SET
pin 7 of U26A
0 t
Q
pin 15 of U26B
0 t
10 ms 10 ms
RL2
0 t
exitation of On/Off relay RL2
65
The On/Off system also comprises an automatic power-down circuit built
around U22 (B3). The non-inverting input (Pin 2) is connected to a
potential of approximately +2.5 V (reference of DZ6). Voltage monitoring
is carried out on +UMONIT using the resistors R102, R103, R113, and
T9 (C3). When the DEFIGARD 3002 IH functions on the ac supply, the
automatic power-down system has no effect. Depending on the power
source used (internal battery or external supply), the system has two
distinct power-down trigger levels. This function is accomplished using
the transistor T9 and R113. For battery operation, the dividing bridge is
made up of R102 and R103 in parallel with R113. When the unit is
powered via the external direct-voltage input, the dividing bridge is made
up of R102 and R103.
Power Source Automatic Power-Down Trigger

Levels
Internal battery (14.4 V - 1.7 Ah) Approximately 12 V
External direct-voltage input Approximately 10.5 V
When the signal on the inverting input (Pin 3, U22) falls below the
reference voltage (+2.5 V), the open-collector comparator goes to the
high impedance state. This results in T8 being blocked, deactivating
RL2 and switching the unit off.
The defibrillator section requires three supply voltages:

− +UDEF: supply voltage for the defibrillator section which varies as a
function of the DEFIGARD 3002 IH power supply. It can be
measured at TP1 (B1).
− +8 V: supply voltage for the analog circuits supplied by RG2
(LM317T). It can be measured at TP2 (B1).
− +5 V: supply voltage for the logic circuits supplied by the regulator
RG3 (78L05). It can be measured at TP3 (B1).
The continuous monitoring of the battery voltage is carried out by the

CPU (W4P41537) via the signal BATTV1 (C1).
66
2.9.3. Manual/semiautomatic locking
(Schematic 3/4)
Locking of the manual or semiautomatic functioning mode is achieved by

the relay RL1 (A7). Energy selection and charge triggering commands
can have two origins:
1) Manual operator-commands from the hand-held, adhesive, and

internal electrode modules.
2) CPU (W4P41537) commands during semiautomatic operation.
The activation of the relay RL1 during use of the semiautomatic module
validates CPU energy selection and charge triggering.
2.9.4. Selected energy reference

(Schematic 3/4)
The circuit which produces the selected energy reference comprises the
elements DZ1, U2A (B8), U19 (A7), and the associated components.
DZ1 is a +5.0-V voltage reference which supplies the reference potential
by division. In Manual Mode, the dividing bridge is formed by R6 and a
resistor selected by the energy selector. In Semiautomatic Mode, the
dividing bridge is formed by R6 and a resistor selected by the analog
multiplexer U19. The operational amplifier U2A is mounted as a follower
to supply the signal WSEL. The signal WSEL has two functions:
− Constitutes the reference for the charge-stop circuit.
− Supplies an indication of selected energy to the CPU (W4P41537).
Manual Mode
Selected WSEL
Energy
0 5.00 V The above table gives the voltage
5J 0.51 V of the signal WSEL as a function
10 J 0.74 V of the selected energy, for the
20 J 1.03 V hand-held and adhesive electrode
30 J 1.27 V modules.
50 J 1.64 V
100 J 2.31 V
200 J 3.28 V (the signal WSEL has tolerances of
300 J 4.01 V ±5 %).
360 J 4.40 V
67
Selected WSEL
Energy
0 5.00 V
5J 0.51 V The above table gives the voltage
10 J 0.74 V of the signal WSEL as a function
15 J 0.90 V of the selected energy, for the
20 1.03 V internal electrode module.
25 J 1.16 V
30 J 1.27 V (the signal WSEL has tolerances
35 J 1.38 V of ±5 %).
40 J 1.47 V
50 J 1.64 V
Semiautomatic Mode
Selected
SAWSEL1 SAWSEL0 WSEL
Energy
0 0 200 J 3.28 V
0 1 300 J 4.03 V
1 0 360 J 4.40 V
1 1 5.00 V
The above table gives the voltage of the signal WSEL as a function of
the control signals (SAWSEL0, SAWSEL1) supplied by the CPU in the
Semiautomatic Mode.
2.9.5. Charge/discharge control

(Schematic 3/4)
The charge trigger circuit is made up of the operational amplifier U4A

(A6) and the associated components. In Manual Mode, charging is
triggered when one of the two buttons on the hand-held, adhesive, or
internal electrode module is pressed. In Semiautomatic Mode, the signal
SACHERGE supplied by the CPU (W4P41537) triggers charging via
U14F (A7) (ULN2004A).
The discharge control circuit is made up of two channels which are
activated by pressing one of the two push-buttons (BP1, BP2) of the
defibrillation modules. One of the channels is made up of the
operational amplifier U4B (A6) and its associated components for
command-logic control which in turn saturates the transistor T3 (A2); the
other channel directly controls the conduction of T2 (D7). When both
transistors T2 and T3 are saturated, the patient relay is activated.
68
2.9.6. Control logic
(Schematic 3/4)
The control-logic circuit generates all the control signals for the HV
generator and the various relays.
* Reset at Power-Up
The reset of the control-logic switching circuits is provoked by U18

(B4). U18 (TL7705) is a voltage monitoring circuit (+5 V) which is
itself controlled by Output -Q of U15 (Pin 2) (D2, Schematic 4/4).
U15A is the defibrillator's SAFETY switching circuit. At power-up, the
output of U18 (Pin 6) is therefore at the high logic level provoking the
reset of the STARTDEF switching circuit U8A (D4).
The three other switching circuits LOAD U8B (C2), CFULL U9B (B2),
and DISCH U9A (A2) are also reset by U21B.
+5V
0 t
SAFETY
switching circuit
pin 2 of U15A
0 t
TL7705 3 ms
pin 6 of U18
0 t
switching circuit
STARTDEF
pin 4 of U8A
0 t
switching circuit
STARTDEF
pin 1 of U8A
0 t
pin 10 of U8B
pin 4 of U9A
pin 10 of U9B
0 t
pin 13 of U8B
pin 1 of U9A
pin 13 of U9A
0 t
69
* Charge Inhibition
After powering-up, charging is inhibited for around 3.3 s. This

inhibition is achieved using U24A (D5) and the time-constant circuit
formed by R114 and C62.
When the energy selector is in position 0, charging is forbidden. This

is achieved using the comparator U3D (C7) and the associated
components. A low logic level on TP5 provokes the reset of the
switching circuit U8A (D4) and all of the logic-control circuits.
A reset and a safety discharge of the defibrillator, during charging for

example, is also provoked by U3D when the selected energy is
modified by the operator.
* Charging of the HV Condenser
The appearance of a low logic level on TP7 (A6) provokes the start of
charging. The signal is inverted by U11A (C5) then differentiated by
C34 and R52. At the output of U17A, an impulse appears which
triggers charging if the following two conditions are filled:
a) The HV condenser is discharged.

b) The charge relay (RL1, W4P41535) contacts are open.
The signal allowing verification of HV condenser discharge is

supplied by the operational amplifier U7B (B6, Schematic 4/4) and
the associated components. The non-inverting input of U7B (Pin 5) is
at a potential of 0.24 V ±5 %. This potential is generated by the Zener
diode DZ2 and the resistors R84 and R24. The inverting input of
U7B is connected to the signal CAPV via R117 and C57 (TP10).
When the voltage at the terminals of the HV condenser is less than
200 V, the output of U7B is at a high level and validates charging.
The signal which allows the opening of the charge relay (RL1,
W4P41535) contact to be checked is supplied by the operational
amplifier U2B (D6). The non-inverting input is at a potential of 2.5 V;
the inverting input detects the signal +UCHARGE via R74 and R75.
When the contact of RL1 is open, the output of U2B is also at a high
level thus validating charging.
The impulsion at the output of U17A (D4) provokes the reset of the
SAFETY switching circuit U15A (D2, Schematic 4/4) using U25C, and
also provokes a low logic level at the output of U18 (Pin 6) (B1).
Because the STARTDEF switching circuit U8A (D4) is no longer
reset, its output increases to a high level and supplies the
STARTDEF signal.
70
The active signal STARTDEF (C1) provokes the opening of the
contacts of the safety discharge relay (RL3, W4P41535), and the
activation of the charge relay (RL1, W4P41535). The opening of the
contacts of the safety discharge relay is directly provoked by the
conduction of T6 on W4P41535.
The activation of the charge relay is controlled using U25B, U23A,
D22, R61, DZ5, and the open-collector driver U14B (D1 and D2).
The HV generator is then started after a delay of approximately

80 ms imposed by the time-constant circuit formed by R53 and C35
(C3). The output of the LOADC switching circuit U8B passes to a
high logic level and generates via U25A (C1) the signal GEST. From
this moment, the HV generator charges the HV condenser (see
explanations in § 2.8.5.).
TP7
0 t
pin 1 of U17A
0 t
10 ms - 20 ms
SAFETY
switching circuit
pin 2 of U15A
0 t
TP15
STARTDEF
pin 1 of U8A
0 t
5 ms - 10 ms
activation of charge relay RL1 and

safety discharge relay RL3
GEST
TP13
0 t
60 - 100 ms
71
The diagram of signal evolution as a function of time on the previous
page shows the evolution of signals for the first charge after unit
power-up this sequence includes the resetting of the SAFETY
switching circuit U15A) (D2, Schematic 4/4).
When the STARTDEF switching circuit U8A (D4) is active, its output
-Q goes to the low logic level via U12A (B5) and activates the counter
U16 (B4). In the event of a technical fault, the charge sequence last
more than 20 s, Output Q12 of U16 goes to a high level and using
U11E, U21A, and U12B provokes the reset of the control logic (reset
of U8A).
During normal HV condenser charging, the signal CAPV1 (B8) is
used to stop charging. When the amplitude of the signal CAPV1 is
equal to the voltage level corresponding to the selected energy, the
comparator U3C (B7) generates an impulse at TP6 whose low level
provokes the reset of the LOADC switching circuit U8B (C2) via the
inverter U11C and the gates U21C and U21B. This stops the HV
generator. This end of charge impulse also resets the counter U16
via the gate U12A.
GEST
TP13
0 t
Tmax = 20 s (U16)
TP6
0 t
RESET
pin 2
of U16
0 t
2 - 5 ms
CFULL
TP16
0 t
30 - 50 ms Tmax = 20 s
(U16)
When Output -Q of the LOADC switching circuit U8B (C2) goes to a

high logic level, Output Q of the CFULL switching circuit U9B (B2) is
also active after the delay imposed by the time-constant circuit
formed by R56 and C42.
72
* The Holding Phase
Output Q of the CFULL switching circuit U9B activates the discharge

validation relay RL2 (W4P41535) via the buffer U14C. The
defibrillator is now ready to be discharged. The holding phase lasts a
maximum of 20 s. If at the end of this time, the patient relays have
not been activated, Output Q12 of U16 passes to the high state and
provokes via U11E, U21A, and U12B the resetting of the control logic
and a safety discharge as the STARTDEF signal comes down to
zero.
STARTDEF
TP15
0 t
GEST
TP13
0 t
CFULL
TP16
0 t
Tmax = 20 s
DEFI READY safety
activation RL2 discharge
(discharge validation relay)
* Activation of the Patient Relays
For the patient relays RL4 and RL5 (W4P41535) to be activated, the
two transistors T2 (D7) and T3 (A2) must be conducting. The
transistor T2 is directly controlled by the push-buttons for discharge
triggering via the components D10, R42, C32, R110, and R44 (A8).
The transistor T3 is controlled by the DISCH switching circuit U9A
(A2). For the DISCH switching circuit U9A to be triggered by U17B,
the following four conditions must be filled:
− Activation of BP1 (TP7 at a low level).
− Activation of BP1 and BP2 (TP8 at a low level).
− CFULL signal active (defi - ready) (TP16 at a high level).
− SYNCDEF signal active.
The signal SYNCDEF is generated by the printed circuit W4P41537

and corresponds directly to the mode of discharge selected by the
operator.
73
Direct Mode
SYNCDEF
0 t
Synchronous Mode (ECG acquisition via patient cable or adhesive

electrodes)
SYNCDEF
0 t
activation discharge
synchro button in presence of ECG signal in synchronized mode
When Output Q of the DISCH switching circuit U9A passes to the

high level, the transistor T3 conducts thus activating the patient relay;
the differentiation circuit formed by R49 and C29 (A5) provokes the
reset of the counter U16 via U12A, and the gate U21D (B4) validates
Output Q5 of the counter U16 via R50 and C30 (A4). After 160 ms,
Output Q5 of U16 passes to the high level and provokes the resetting
of the STARTDEF switching circuit U8A via U21D, U21A, and U12B.
Two cases can now arise:
1) The energy is discharged across a low resistance, in which case

the HV condenser contains no more energy after 160 ms of
activation of the patient relay.
2) The energy is discharged across a high resistance, in which case

the HV condenser still contains a certain amount of energy which
will be dissipated in the resistors R23 and R46 when the safety
discharge relay (RL3, W4P41535) is deactivated when the signal
STARTDEF passes to the low level.
74
Signal Evolution during Discharge across 50 Ω
CFULL
TP16
0 t
pin 13 direct mode
of U17B BP1 and BP2
pressed
0 t
DISCH
TP17
0 t
RESET activation of patient relay
pin 12
of U16
0 t
Q5
U16
0 t
T = 160 ms
STARTDEF
TP15
0 t
patient
current
0 t
2.9.7. Defibrillator safety mechanisms

(Schematic 4/4)
The defibrillator's safety functions are built around the elements U6,
U23B, U3A, U3B, U7A, U15A, T1, and the associated components. The
safety switching circuit is formed by U15A which is controlled by U23B.
Five technical safety mechanisms can trigger the switching circuit U15A
(D2):
1) Monitoring of T2.
2) Monitoring of T3.
3) Monitoring of the patient relay.
4) High-voltage safety signal OVER1 (W4P41535).
5) High-voltage safety signal OVER2.
75
In order to check the proper function of the SAFETY switching circuit
U15A, this circuit is triggered at power-up. Charging provokes the
resetting of the switching circuit U15A via U25C. Because of this, a
possible technical fault on the defibrillator will not block the defibrillator
but will result in the display of a DEFI ERROR message and a safety
discharge due to T1 (D1) becoming conducting. The operational
amplifier U23B (D3) triggers the switching circuit U15A when one of the
open-collector comparators U6B, U6D, U6C, U3A, or U3B (D6, C6, B6)
goes to zero.
+5V
SET 0 t
SAFETY M/A detection of a technical
switching circuit fault by U6B, U6C,
pin 6 of U15A U6D, U3A or U3B
Q 0 t
60 - 80 ms
SAFETY.
switching circuit
pin 1 of U15A
0 t
-DEFSEC
TP14
0 t
reset of
pin 1 of U17A défibrillator
and safety
discharge
0 trigger of t
of charging
RL1 charge relay
activation
RL1 W4P41535
0 t
charging of
H.V.
condenser
0 t
76
When a technical fault is detected, the signal -DEFSEC passes to 0 V
due to the conduction of T1 (D1). Consequently the driver U14B (D1,
Schematic 3/4) deactivates the charge relay RL1 (W4P41535) and thus
provokes a safety discharge. Output -Q of U15A (D2) resets the circuits
of the control logic via U18 (B4), U12B (B3), and U8A (D4).
* Monitoring of Transistor T2
Monitoring of T2 is carried out by U6A (D7), U6D (D6), and their

associated components. This monitoring is valid only when the signal
STARTDEF is active (during one defibrillation cycle). A possible
source-drain short-circuit of T2 in the conditions discussed above
provokes the charging of C16 via R33 given that the output of the
comparator U6A is in a high-impedance state. After a duration of
between 800 ms and 1 s, the signal -DEFSEC (D1) passes to the low
level via U6D, U23B, and U15A, provoking the resetting of the
defibrillator and the safety discharge.
STARTDEF
TP15
source of T2 0 t
+UCHARGE
+4V
0 t
drain of T2 technical fault on T2
TP12 (drain-source short-circuit)
+UCHARGE
+4V
0 t
-DEFSEC
TP14
0 t
0,8 - 1 s
77
* Monitoring of Transistor T3
Monitoring of Transistor T3 is carried out by the comparator U6B (D6)

and by the associated components R29, C15 (D6), R71, and D9 (A2,
Schematic 3/4). The monitoring of T3 for faults is carried out
continuously. In effect, the conduction of T3 provokes the discharge
of C15 via R29 (D6) and D9 (A2, Schematic 3/4). When T3 is
conducting for more than 500 ms, the output of U6B (D6) passes to a
low level triggering the SAFETY switching circuit U15A (D2) thus
provoking a reset of the defibrillator and a safety discharge.
* High-Voltage Safety via the CAPV Signal
The first high-voltage safety circuit is formed by U3A (C6) and its
associated components.
The comparator's reference voltage is supplied by DZ2 (B8). In the

event of a fault on the normal end-of-charge circuit, the voltage CAPV
becomes equal to the reference voltage (5.1 V), the comparator U3A
triggers the safety switching circuit U15A (D2) thus provoking the
reset of the defibrillator and a safety discharge.
In practice, this circuit is triggered when the voltage on the terminals

of the HV condenser is approximately 5600 V.
* High-Voltage Safety via the OVERV1 Signal
The signal OVERV1 generated on the printed circuit W4P41535 also

triggers the switching circuit U15A (D2) via the comparator U6C (C6)
and the associated components in the event of a fault on the normal
end-of-charge circuit, and if the first safety circuit described above
fails.
In practice, this circuit is triggered when the voltage on the terminals
of the HV condenser is approximately 5700 V.
78
* Monitoring of the Patient Relay
The signal PATRLSEC at TP9 (B8) supplied by the printed circuit

W4P41535 allows the patient relay to be monitored.
In the event of a voltage being present on the contacts of the patient
relay, the signal PATRLSEC passes to the high state, thus causing
the diode D5 to be blocked via U7A. From this instant, the capacitor
C11 is charged via R26. In practice, the comparator U3B triggers the
safety switching circuit U15A when the voltage is present on one of
the branches of the patient relay contacts for more than 300 ms
(+ 20 %). Under normal operation, the voltage is present for no more
than 160 ms, which corresponds to the activation time of the patient
relay.
2.9.8. Patient current measurement

(Schematic 4/4)
The patient current is measured via the current transformer TR3 on the
printed circuit W4P41535. The signal IPK1 (B4) (evolution of patient
current) is filtered by the components R85 and C45 before attacking the
peak detection stage built around U5A and D4. Peak amplitude is
memorized over the duration of patient relay activation by the capacitor
C43 via U13A. The capacitor is discharged by U13B and the resistor
R21. The operational amplifier U5B (B1) has a gain of between 2 and
6.7, depending on the adjustment of P1. The output signal IPAT is
adjusted by P1 in order to obtain a conversion factor of 1 V for 30 A.
2.9.9. The "Defi-ready" indicator lights

(Schematic 3/4)
The indicator lights for the trigger buttons CHARGE/SHOCK are

powered by T4 and U14D when the defibrillator is ready to be
discharged. During the holding phase, the signal CFULL is active (high
level); consequently the driver U14D provokes the conduction of T4
which supplies power to the indicator lights.
79
2.9.10 Graph triggering via the buttons of the hand-held electrodes
(Schematic 4/4)
The triggering of the recorder by the button located one of the hand-held
electrodes is accomplished via U1, U10, and the associated
components. The graph control signal which goes to the CPU
(W4P41537) is called RECSTART.
* Signal CFULL = 0
In this case, the transistor T4 (D8) is blocked. Pressing the graph

trigger button provokes the presence of the supply voltage +8 V on
the signal REC (Pin 6 of J11 (C7), Schematic 1/4) via R78 and R76
(D8). The non-inverting input of U1A is at a higher voltage than the
inverting input (+6 V), the output of the comparator U1A passes to the
high level provoking a high level on the signal RECSTART via the
gates U10A and U10D.
* Signal CFULL = 1
In this case, the transistor T4 (D8) is saturated to provoke the

illumination of the end of charge LEDs. The signal -READY (Pin 5 of
J11 (C7), Schematic 1/4) is at a low logic level. Pressing the graph
trigger button results in a change in the voltage on the REC signal.
The comparator U1B (C8) detects this voltage change and its output
passes to the high level, thus triggering the graph (signal RECSTSRT
active) via U10B and U10D.
80
2.9.11 Defibrillation module coding
(Schematic 4/4)
The identification of the defibrillation module connected to the unit is

accomplished via the four coding lines: DEFMOD0, DEFMOD1,
DEFMOD2, DEFMOD3 (A3). This coding is read by the CPU
(W4P41537).
Defibrillation Modules DEF DEF DEF DEF

MOD0 MOD1 MOD2 MOD3
Hand-held electrodes 1 0 0 0
Internal electrodes 0 1 0 0
Adhesive electrodes 0 0 1 0
Semiauto. module 0 0 0 1
No module inserted 1 1 1 1
2.9.12 The semiautomatic defibrillator function

(Schematic 3/4)
The semiautomatic function is entirely handled by the printed circuit

W4P41537 via four control lines:
− -ANALYSE
− SAWSEL0
− SAWSEL1
− SACHARGE
Semiautomatic Mode is only available by inserting the Semiautomatic

Module which activates the relay RL1 (A7), signal -RLDSA at zero. From
this instant, energy level selection is accomplished using SAWSEL0 and
SAWSEL1 for the control of the analog multiplexer U19 (4051). The
Semiautomatic Mode table in § 2.9.4. gives the multiplexer's output
voltage as a function of the selected energy. Triggering of a charge
cycle is accomplished using the signal SACHARGE (A8) which activates
the driver U14F (ULN2004A) to start charging via U4A (A6).
The signal -ANALYSE ((A3), Schematic 4/4) originating from the

ANALYSE key on the semiautomatic module indicates to the CPU
(W4P41537) that the button for starting an ECG signal analysis
sequence has been pressed.
81
2.9.13 Other functions
(Schematic 3/4)
* The Battery Test Function
The battery test is triggered by the CPU (W4P41537) using the signal
STARTCONV (C5). After the TEST BATT key has been pressed, the
STARTCONV signal is active for 2 s. The gate U24C (C3) prevents a
battery test during a defibrillator cycle. The output of U24C provokes
if necessary a reset of the safety switching circuit via the
differentiating circuit formed by C68, R37 (C4, Schematic 4/4), and
the gate U25C. The signal TBAT also provokes the activation of the
CHARGE relay via U25B, U23A (D2), and U14B (D1), the passage to
the high state of the signal GEST via U25A (C1), and the activation of
the TEST BATT relays RL5 and RL6 via the driver U14E (A8, A7, and
A6, Schematic 2/4).
The evolution of the battery charge state is checked by the CPU

(W4P41537) via the signal BATTV2 (D6) which is the voltage
+UCHARGE divided by the resistors R74 and R75 (D7).
* The Safety Discharge Signal
The signal which indicates that the defibrillator is proceeding with a

safety discharge of the HV condenser is generated by the gates
U12C, U11F (D3), and U20D (D1). This signal, called SECDISCH, is
active at the high logic level.
* The Signal CAPV2
The display of energy during the HV condenser holding phase is

accomplished by the signal CAPV2 (C5, Schematic 4/4). The
adjustment of the display is accomplished using the adjustable
potentiometer P2 from the signal CAPV (C8, Schematic 4/4).
* Logic Signal Buffering
The logic signals from the defibrillator section are buffered by the
circuit U20 (4050) before being sent to the CPU printed circuit
(W4P41537).
82
2.10. OPTIONS
2.10.1. Communication with the CPU

(see Page 144)
The role of the CPU communication board is to ensure the interface

between the CPU (micro-master) and the various options (SpO2, FV,
external serial port).
The CPU communication board is made up of the following components:
- A central unit comprising a microcontroler U1 (D8), an address/data

demultiplexing circuit U2 (D6), a program EPROM U3 (D4), a working
RAM U6 (C4) and decoder for selection signals U4 (C6).
- UART circuits:
### U7(C3) for communication with the SpO2 option.
### U8 (D3) for external communication (serial port).
- A DUAL PORT RAM U9 (B4, B6) for communication between the

CPU (micro-master) and the CPU (micro-communication). Access to
the DUAL PORT RAM occurs alternately in synchronization with the
signal -INTCOM.
- A D/A converter U15 (A3) which carries out the conversion of the
digital SpO2 signal into an analog signal.
- An interruption memorization (A6 thru A8) originating from the SpO2

UART and the serial port UART.
- 2.5 and 1-MHz clocks (B2, B3).
The table below shows memory space allocation for micro-

communication:
0000 - 7FFF WORKING RAM
8000 - 87FF - CSCMDUA

8800 - 8FFF - CSSPO²
9000 - 97FF - CSEXT
9800 - 9FFF - CSDAC
A000 - A7FF - CS..... (N.U.)
A800 - AFFF - CS..... (N.U.)
B000 - B7FF - CS..... (N.U.)
B800 - BFFF - CS..... (N.U.)
C000 - FFFF NOT USED
83
The central unit is built around the micro-communication circuit U1 (D8)
driven by a 16-MHz clock originating from the central unit of the micro-
master via U5B. The data bus has an 8-bit architecture, multiplexed with
the 8 low order address bits to obtain an address bus over 16 bits. U2
(D6) is mounted as a demultiplexer; ALE and PSEN allow differentiation
between the data addresses.
When ALE is set to "1", the outputs of U2 (ACM[0..7]) follow the state of
the inputs of U2 (DCM[0..7]). When ALE goes to "0", the inputs are
insulated and the states present on the outputs are maintained until ALE
switches back to "1". These states code for ACM[0..7].
Access to the Program EPROM:
ALE
-PSEN
PORT A PCR ACM0-ACM7 PCR ACM0-ACM7 PCR
PORT C ACM8-ACM15 ACM8-ACM15
PCR = Program Code Read
Coding of the working RAM U6 (C4) is carried out with the help of
ACM15. When ACM15 = "0", the working RAM is decoded.
Access to the contents of the working RAM is achieved with ACM15 =
"0" and -WRCM = "0" for a write, and ACM15 = "0" and -RDCM = "0" for
a read.
The role of the decoder U4 is to generate validation impulses for the

decoding of the DUAL PORT RAM, of the D/A converter and the UART
circuits.
When ACM15 = "1" and ACM14 = "0", the decoder is validated;
ACM[11....13] codes for the impulses at the decoder output.
84
### Micro-Communication Reset
The RSTCOM signal (D8) is the micro-communication reset impulse.

It can originate from two sources:
### At power-up, via the R1, C25 network (B7).
### During operation due to an impulse RAZCOM (B8) generated by
the micro-master via an output port.
The signal RSTFV is a reset impulse for the micro-FV. It functions in
the same way as the impulse RSTCOM. At power-up, it is generated
by the R1, C25 network and during operation by an impulse RAZFV
generated by the micro-master via an output port.
### The DUAL PORT RAM
The DUAL PORT RAM, which ensures the interface between the
micro-master CPU and the micro-communication CPU, can be
accessed by the micro-master and the micro-communication.
Access to the DUAL PORT RAM by the micro-communication is

carried out via the data bus DCM[0..7], the address bus ACM[0..10],
-CSCMDUA (in the "0" state), and -WRCM (in the "0" state for a
write), and from -RDCM (in the "0" state for a write). Access to the
DUAL PORT RAM by the micro-master is achieved via J1, using the
data bus DBF[0..7], the address bus ABF[0..10], -CSDUAL (in the "0"
state), and -WRBF (in the "0" state for a write), and -RDBF (in the "0"
state for a read). Access to the DUAL PORT RAM for both
microprocessors is carried out alternately in synchronization with the
signal -INTCOM. -INTCOM is generated by the micro-master via an
output switch (situated on the micro-master CPU).
When the signal -INTCOM is in the "1" state, the micro-master
accesses the DUAL PORT RAM; and when it is in the "0" state, the
micro-communication accesses the DUAL PORT RAM.
10 ms approx. 7 ms approx.
-INTCOM
access to DUAL PORT RAM access to DUAL PORT RAM
by the micro-master by the micro-communication
85
* Memorization of Interruption Requests
Certain events require real-time processing. This processing request

results in an interruption via the INTR line (D8).
The INTR line supports interruptions originating from the SpO2 UART
and the external interface UART. Because there are several possible
origins for an interruption request, and there is only one interruption
line, it is necessary to memorize the origins of the interruption
requests. This is carried out using U12, U10, and U5 (A6 thru A8).
When there is an interruption request, the concerned line (SPO2FULL
or EXTFULL) goes to "1", which results in the concerned switch going
to "0" thus forcing the INTR line to "0".
In return, the micro-communication interrogates the memorization

switches using the lines -INTSPO2 and -INTEXT to determine the
origin of the interruption. At the end of interruption processing, the
micro-communication generates an impulse (-RAZSPO2 or -RAZEXT)
(D8) to reset the concerned switch.
e.g.: Interruption originating from the SpO2 UART.
SPO2FULL
-INTSPO2
-RAZSPO2
* The UARTs
The two UARTs U7 and U8 (C3, D3) are attacked by a 2.5-MHz

square signal (Pin 18) generated by the 5.086-MHz clock (B3) then
divided by 2 by U11A (B3).
The SpO2 UART (U7) ensures the interface between the micro-
communication and the SpO2 option. Access to the contents of the
UART registers is achieved when ACM15 is in the "1" state, -CSSPO2
is in the "0" state, and -WRCM is in the "0" state for a write or when
ACM15 is in the "1" state, -CSSPO2 is in the "0" state, and -RDCM is
in the "0" state for a read.
The MRSPO2 signal from U7 (Pin 39) allows the micro-
communication to send a reset impulse to the SpO2 UART.
When the SPO2FULL signal passes to the "1" state (Pin 33 of U7), an
interruption request is triggered.
SpO2IN (C1) is the transmission line from the SpO2 option to the
SpO2 UART (U7).
SpO2OUT (C2) is the transmission line for commands from the SpO2
UART (U7) to the SpO2 option.
86
The SpO2ON signal (C1) originating from the micro-master CPU via
an output switch (situated on the micro-master CPU) controls the
transistors T1 and T2 which supply the SpO2 option. When SpO2ON
is in the "1" state, power is supplied to the SpO2 option.
VSpO2 is the supply voltage for the SpO2 option.
The external interface UART (U8) ensures the interface between the
micro-communication and an external serial port.
The interface on the micro-communication side is identical to that of
the SpO2.
The interface on the external serial port side is carried out via U14
(MAX220) (D1) which puts the lines EXTOUT and EXTIN in the V24
standard ("0" state = -12 V; "1" state = +12 V). Data transmission is
achieved via a connector situated at the rear of the unit.
* The D/A Converter
The role of the D/A converter U15 (A3), associated with U16B and
U16A, is to convert the digital SpO2 signal into an analog signal. This
signal is available at the connector at the rear of the unit.
The digital data of the SpO2 curve are received by the micro-
communication via the SpO2 UART. These data are then transmitted
to the D/A converter via the data bus DCM[0..7], -CSDAC (in the "0"
state) and -WRCM (in the "0" state).
-CSDAC
-WRCM
DCM[0..7] DCM[0..7] DCM[0..7]
The voltage Vref of the D/A converter (Pin 15 of U15) is between 4.4
and 4.9 V.
Output 1 of the D/A converter U15 attacks an operational amplifier
(mounted as a unit-gain summing inverter), then a second operational
amplifier mounted as an inverter which restores the analog SpO2
signal.
87
2.10.2. External Stimulator
(see Page 148 or 150)
The stimulator comprises three main parts:
* a power section,
* a 40-ms square-wave generator,
* a constant-current generator.
The power section generates the energy required to deliver, from a

non-floating voltage between 11 and 30 V, 75-V/40-ms square wave
across a 500-Ω load at a rate of up to 420 per minute. It is made up of
an analog on/off switch, a non-floating voltage reducer, a forward-type
converter with insulated windings, and a buffer capacitor from which the
energy to be delivered to the patient is read.
The square-wave generator operates using manual selection of

operating mode and frequency, and also as a function of the
presence/absence of external QRS synchronization impulses. Clock
frequency is provided by a stable time base generated by two counters:
one provides the 40-ms intervals and the other is used to generate
longer intervals as a function of the P/min set-point.
The constant-current generator delivers a constant current to the patient

during the 40-ms square wave, which has been manually selected. It is
made up of a decoding circuit, circuits for transmission to the floating
section, and a current generator which is controlled by the decoding
circuit.
There is also a section which is equivalent to an insulated ammeter

which supplies a voltage to the CPU which is proportional to the
delivered current.
* Power Supply to Circuits
By positioning the mode switch SW1 (A8) on either position FIX, DEM,
or OVD, T6 becomes passing and supplies a voltage-reducing
converter which comprises principally RG1, T8, D1, L2, and C18.
The voltage obtained at the terminals of C18 is close to +8 V (A5);
and is used to supply the midpoint of the primary winding of
transformer TR1 (D3) and give the voltage +5 V via RG2 (A6).
The +5 V voltage supplies all the control circuits of the non-floating
section and is used to produce the voltage -5 V via RG4 (A5). This
voltage is used for the analog circuits U7 (B3) and U12 (A3, A4) which
transmit a positive or zero voltage to the CPU with no delay which
represents the current actually delivered to the patient.
88
The primary winding of TR1 is attacked in push-pull mode using T1
and T2 (D4) which are both controlled by U14 whose control signals
are the result of a combination of the fixed 31.25 kHz frequency
generated by U1 (D7) and a validation signal originating from the
floating section via U15 (C3). This validation signal depends on the
voltage attained at the terminals of C8 (measurement using the
sequence R19, P1, U16C) (D2) and the instantaneous charge current
of C9 (measurement at the terminals of R20 using the sequence T3
and U16B) (D2).
TR1 transfers the energy or the power to the floating section and
principally to the buffer capacitor C9 whose charge is close to 1 Joule.
U21 (D4) is supplied by the signal +8 V and controlled with a 62.5-kHz

signal generated by U1 (D7); it attacks the primary winding of the
impulse transformer TR2 to obtain an auxiliary +VF floating voltage of
the order of +8 V which ensures permanent operation of the various
optocouplers and current measurement with U22 (B1, B2).
U16A, T4, and R24 (D2) form a safety sequence; in the event of a
failure of +VF (stimulation function stopped or malfunction), U16A no
longer blocks T4, and C9 discharges through R24.
* The Generation of 40-ms Square Waves
U1 (D7) generates a 32-µs time-base by dividing the 4-MHz signal

produced by the quartz crystal Q1.
The circuits U11 and U3A (B6) multiply this time-base by 1250 to
supply impulses every 40 ms when U11 is validated. This validation is
given by the switching circuit U8A (C5) and depends mainly on the
frequency (in P/min.) preselected by the operator.
Depending on the frequency selected by the hexadecimal coder SW2

(D7), the contents of the memory U5 (D6) are compared with the
outputs of a counter U4 (D6), whose clock frequency is generated
using U2 and U3B, using U6. Impulses are delivered every 6.24 ms,
i.e., 195 times 32 µs.
When the two octets at the input of U6 coincide, the output of U6

triggers the switching circuit U8A which validates the counter U11
(B6).
After 40 ms, U11 resets U8A to the "0" state via Pin 4. However, a
40-ms square wave was present at the output Q of U8A and the
information has transited through the floating section via U10 (C2).
89
In FIX mode, data pin 5 of U8A is always in the "1" state. In OVD
mode (overdrive), this pin is in the "1" state only if the push-button
PB1 is pressed.
In DEM mode (demand), the counter U4 (C6) is reset by the QRS

impulse whenever a rising front of an external synchronization impulse
appears. This impulse transits via C13, R58, U24D, U24C, and U26D
(B7) and acts on Pin 11 to validate the operation of U4. This pin also
receives a brief impulse generated by U8A, via C15, R60, and U26C
(B7) as soon as the 40-ms square wave appears.
In OVD mode, the hexadecimal addresses selected by U5 (D6) are

between 10 and 1F due to Pin 7 being set to the "1" state, using the
signal emitted by the mode switch SW1 (A8). Still in overdrive mode,
Pin 1 of U6 disables operation of the octet comparer as long as the
push-button PB1 is in its rest position, i.e., not pressed.
* Selection of Current to be Delivered
Switch SW3 (C4) (hexadecimal coding) selects the contents of the

memory U25 (C3). The contents are made up of a binary combination
over 5 bits. Each bit controls, via an optical link, a Darlington transistor
in U16 whose emitter is connected to the floating mass.
During the appearance of the 40-ms square wave, T5 (C1) conducts
and DZ2 is powered; resistors R10 thru R14 can thus be crossed by a
current of 5, 10, 20, 40, and 80 mA respectively as a function of the
data present at the output of the memory U25.
* Measurement of the Current Delivered to the Patient
The adhesive electrodes on the patient are connected to the

connector J2 (D1). The current which passes through the patient also
passes through the measurement resistor composed of P3 and R37
(D2).
A differential amplifier, built around U22B (B1), generates a voltage,
referenced with respect to the floating mass, which is directly
proportional to the current delivered to the patient.
U22A and U23 allow the linear transfer of the analog data "delivered
current" to the non-floating section. At Output 5 of U23 (A2), a Diode
without threshold (D5, U12A) alternately charges C24 or C22 (B3) at
each stimulation impulse. The voltage at the terminals of C22 or C24
is read and impedance adapted by U12B.
U26A and U8B (B4) allow the alternation between memorization,
measurement, and charge on C22 or C24; this is carried out at each
stimulation impulse or after 1.6 s to discharge C22 or C24 during
standby mode of the overdrive.
90
2.10.3 VF/VT detection
The VF/VT detection printed circuit (W4P41541A) comprises various

functions :
− ECG signal amplification and filtering,

− QRS detection,
− ECG signal lower limiting,
− central unit,
− automatic gain control.
∗ ECG signal amplification and filtering
The signal ECGX1000 out of ECG amplifier is amplified with a 1.5

gain by the amplifier U5B associated with R1 and RN4B, with
suppression of any possible offset by the capacitive coupling C1. U1A
and U1B formed a 20 Hz band-pass filter ; it is following from a 50 Hz
rejector filter built around U1C and U1D.
∗ QRS detection
The ECG signal used to extract the QRS tops is a signal from the
automatic gain control to obtain an optimal detection whatever the
input signal amplitude. To do this, the signal digitized by U20 is
immediately reconvert into analogic by U28. This signal is injectabled
into the QRS detection function.
To extract the QRS complexes from the signal, a controlled source

active band-pass filter is built around U5C, with a 12 Hz central
frequency, an 8 Hz lower frequency (-3dB) and an 18 Hz upper
frequency (-3dB).
The circuit U4A associated with DN1 forms a double alternance
rectifier to allow the analysis of the negative QRS impulsions.
The comparator U4D is a peak detector with a variable limit, function
of the maximum amplitude of the last QRS, the elapsed time since the
last QRS (D1, R24, R25 and C14) (1 second time constant) and a
fixed value (R22, R23).
The output of U7A generates a hardware interrupt on the
microcontroler U10.
∗ ECG signal lower limiting
The fibrillation detector is inhibited if the signal present at the input is

less than 0.15 mV. This inhibition is carried out by comparing the
average signal memorised in C17 with the limit fixed by R30, R31 and
U5A (2.5 second time constant). The output U7C inhibits the QRS
detectors and invalidates the analysis.
∗ Automatic gain control

91
The ECG dynamic input being very large (5 mV), in order to simplify
the ventricular fibrillation detection algorithms (zero criterion), an
automatic gain control allows the converter to always use full scale.
To carry out this automatic gain control, the absolute value of the
signal maximum is stored in C17 which serves as a conversion
reference to the converter U14. At the halfway point of this signal, half
of the ECG signal is subtracted (U27A). In this way, the signal base
line is near to the converter's reference ($7F) and the QRS complex's
R point corresponds to the converter's extreme value ($00 or $FF)
(depending on complex's direction).
∗ Central unit : the architecture
The heart of the system is architectured around the microcontroler

U10 with a 16 MHz frequency using the quartz Q1. This microcontroler
has an 8 bit architecture with 16 address bits (64 kilo-octets
addressable) multiplexed with the 8 data bits. It comprises 256 octets
of internal memory, three 16 bit programmable timers, 3 input/output
ports, 2 interrupt inputs and 1 serial link.
The data/address demultiplexing is carried out by the register U11

controlled by the signal ALE (Address Latch Enable) which is directly
generated by the microcontroler (pin 33 of U18). This signal is in a
high state when the address is present on the bus.
The external memory space addressable by the microcontroler has a

64 kilo-octets capacity (16 address bits named A0 - A15). This
memory space is doubled into 64 kilo-octets of working memory and
64 kilo-octets of program memory using the signal PSEN (Program
Store ENable). Reading or writing operations in the working memory
field are controlled by the signals -RD (ReaD) (pin 19 of U18) and -
WR (WRite) (pin 18 of U10). The program memory field is entirely
used by the EPROM U12 of a 64 kilo-octets capacity. The
microcontroller does not have specific addressing for the input/output
peripherals. This is why the working memory field is divided into two
parts (1 RAM field, 1 peripheral field) by using the MSB (Most
Significant Bit) of the address bus A15. The lowest 32 kilo-octets
($0000 to $7FFFF) are occupied by the static RAM U13 which is only
selected if A15 is in a low state. The upper 32 kilo-octets ($8000 to
$FFFF) are occupied by the address decoder U18 which is only
selected if A15 is in a high state. These 32 kilo-octets are themselves
divided into 4 kilo-octets slices ($1000) by the addresses A12, A13
and A14. On each one of these 4 kilo-octets zones it is possible to
lodge an input/output peripheral.
92
The following table shows the memory space organisation:
$F000 Unused
$E000 Unused
$D000 Unused
$C000 D/A converter U28
$B000 UART serial connection U18
$A000 Unused
$9000 Input interface U21 and output interface U22
$8000 A/D converter U14
$7FFF
32 kilo-octets RAM
U13
$0000
∗ Central unit : interrupt handling
Four sources of interruption share 2 interrupt inputs on the

microcontroller (pins 14 and 15 of U10). These sources are:
− fibrillation QRS detection signal (pin 15 of U10),

− change of derivation signal (pin 11 of U24A),
− the -TEST signal (pin 9 of U7D)(not used)
− the serial connection signal used for the factory test (pin 1 of
U25B).
So that the microcontroller knows without any ambiguity the origin of

an interrupt, the sources have been divided into two groups.
− 1st group : QRS detection signal,

− 2nd group : change in derivation signal, serial connection signal,
test signal
Each source is memorised in a flip-flop circuit:
− -TEST signal in U24A,

− change in derivation signal in U24B,
− serial connection signal in U25B.
The Q outputs of the flip-flop circuits are sent to the logic OR gates to
generate a interrupt signal : -INT0 (pin 14 of U10)
The -Q outputs of the flip-flop circuits are connected to the input

register U21.
When an interrupt is generated, the microcontroller reads the state of
the register U16, only taking notice of the bits relevant to this interrupt
93
(D0 to D2). As soon as the interrupt is detected, a reset signal for the
corresponding flip-flop circuit (bits 0, 1or 2 of U22) is generated.
∗ Central unit : the watch dog
It is made up of two monostables U8A and U8B; in the event of a

software error, this circuit generates a 10 ms reset impulse (R39, C23,
U8A).
Under normal running conditions, with each software cycle, a reset of
the first monostable is carried out by the signal -WD from the
microcontroller (pin 17 of U10). If the time between two -WD
impulsions becomes greater than the time constant of the first
monostable U8A (R28, C22 and C60), it generates a low state on its -
Q output which initialises the second monostable U8B.
∗ Central unit : the communication
The transmission of analysis results is done via the internal serial links
of the microcontroller RXD (pin 11 of U18) and TXD (pin 13 of U10).
Via the connector J1, the two wires are directly connected to the
master microcontroller of the DEFIGARD 3002 IH.
Every 100ms, the microcontroller of the "VF/VT detection" printed

circuit send a frame to the principal microcontroller containing the
state of the board. This states are in number of four :
1. too small signal (-LIMIT signal active)

2. parasite signal
3. no fibrillation
4. fibrillation
The serial link format is : 1 start bit, 8 data bits, 1 special bit, 1 stop bit.
∗ Central unit : the voice synthesis
The voice synthesis is an independant function of the fibrillation

detection function. She is used at the time of a semiconductor mode
functioning to emit the AHA protocol directives through the
loudspeaker from the DEFIGARG 3002 IH.
When a sentence is to emit, the monitors principal processor send a

sentence number to the processor signal U15. This one get back the
sentence samples to emit from memory U16 and U17. This samples
are converted by the D/A converter integrated to the signal processor
U15. The analogical signal is transmited to the loudspeaker through
pin 6 of J1.
94
3. TEST AND REPLACEMENT OF PRINTED CIRCUITS
3.1. UNIT DISASSEMBLY AND REMOVAL OF PRINTED CIRCUITS
Before carrying out any operations, disconnect the power cord, the battery, and
the electrode module.
* Removing the Battery
Turn the unit around, unscrew the six screws holding the rectangular cover
and remove cover. Disconnect the connector and remove battery.
* Unit Disassembly
Turn the unit around and unscrew the five screws located at the bottom of the
wells. Turn the unit with the front facing you while holding the two chassis
sections together, and place the unit handle in front of you (careful with the
screws!). Lift the upper chassis and turn around with the rear facing you. You
should now have in front of you:
− In front: the lower chassis containing the defibrillator.
− At the back: the upper chassis containing the monitor.
To detach the two sections, disconnect the connectors J1 (four pins), J3 (flat
cable), and J5 (three pins).
* Removal of Printed Circuits from the Monitor Section
The visible printed circuit is the circuit W4P41537 (ECG and CPU
preamplifier). To remove this circuit, disconnect the two keyboard flat cables
J9 and J10, the connectors J2, J13, J6, and J11, and the shielding ground
cables J15 and J16, then unscrew the seven screws holding the printed
circuit.
To remove the printed circuits W4P41538 (LCD controller) and CFP57 (LCD
screen power supply), it is not necessary to remove the upper printed circuit
W4P41537; simply extract the holding chassis which is beneath this printed
circuit. To do this, disconnect the two keyboard flat cables J9 and J10, the
connectors J2, J13, J6, and J11, the shielding ground cables J15 and J16,
then unscrew the six screws directly screwed to the partly visible gray
sections. Lift the assembly and turn it around.
The printed circuit W4P41538 can thus be removed by disconnecting the
connectors J2 and J3, unscrewing the screw which holds the brace for the
upper part of the circuit, and sliding this circuit out of its guide rails.
The circuit CFP57 is then accessible. To remove this circuit, unscrew the four
screws which secure the screen to the chassis and the two screws on the
circuit.
95
* Removal of Printed Circuits from the Defibrillator Section
Unscrew the seven screws holding the upper printed circuit. Disconnect J4,
J10, J11, J3, J5, J1, J2, J6, and J7. The printed circuit W4P41536
(defibrillator control) can then be removed.
The next circuit, W4P41542 (shielding board), is held by one screw which
must be unscrewed to gain access to the next circuit. Lift the circuit
W4P41542 and remove the cables retained by clips.
To remove the last board, W4P41538 (high-voltage circuit), disconnect J5,

J6, J7, J8, J4, J2, J3, and J1, and unscrew the four screws and four braces
which secure it to the chassis.
In the event of a printed circuit being damaged, the whole of the printed circuit in
question should be replaced. No adjustments or tests are necessary after
replacement (settings determined at the factory) :
− LCD controler,
− LCD screen power supply (CFP57),
− external connector filter,
− SpO2 filter.
The replacement of such a circuit has no influence on the functioning of the

other circuits and therefore no adjustments are required for other circuits.
However, the following circuits may require adjustment if replaced :
− CPU/preamplifier,
− high voltage,
− defibrillator control.
96
3.2. ADJUSTMENT OF THE "ECG PREAMPLIFIER AND CPU" CIRCUIT
Point
Poten- Target
Measuring of
Adjustment instrument measu- tiome- value and Remarks
ter tolerances
rement
Connect a 3-lead
cable at the input
ECG signal Oscilloscope TP4 P1 0 mV with inputs short-
offset ± 20 mV circuited
bet- Connect the

Power supply ween terminal + of the
voltage of Voltmeter TP10 P2 -23,5 V voltmeter on TP10
LCD display and ± 0,25 V and the terminal -
(VALVLCD) TP24 on TP24
3.3. ADJUSTMENT OF THE "DEFIBRILLATOR CONTROL" CIRCUIT
Point
Poten- Target
Measuring of
Adjustment tiome- value and Remarks
instrument measu-
ter tolerances
rement
value Printout
Patient Monitor on Ipat = 60 A Selected energy
current section graph P1 +0 A 300 J
paper -1 A
Holding
phase energy Monitor LCD P2 Display Selected energy
display section screen 300 J ±5 J 300 J
97
3.4. ADJUSTMENT OF THE "HIGH-VOLTAGE" CIRCUIT
Point
Poten- Target
Measuring of
ter tolerances
rement
Defibril- Joulometer
Joulometer lation P1 display Selected energy
Stopping 300 J
paddles 300 J ±5 J
charging of
the HV HV measu- Charge vol-
converter rement on +HV tage shown
Selected energy
HV conden- and P1 in the table
300 J
ser terminals -HV below
using divider ±40 V
Charge voltage with C = 32 µF/5.2 kV
C = 32 µF ±5 %
Cm = Cminimum
CM = Cmaximum
Cav = Caverage
Cm = 30.1 µF Cm = 30.6 µF Cm = 31.1 µF Cm = 31.6 µF Cm = 32.1 µF Cm = 32.6 µF Cm = 33.1 µF Cm = 33.6 µF

Wdel/ CM = 30.5 µF CM = 31.0 µF CM = 31.5 µF CM = 32.0 µF CM = 32.5 µF CM = 33.0 µF CM = 33.5 µF CM = 34.0 µF
50 Ω Cav = 30.3 µF Cav = 30.8 µF Cav = 31.3 µF Cav = 31.8 µF Cav = 32.3 µF Cav = 32.8 µF Cav = 33.3 µF Cav = 33.8 µF
5J 616 V 611 V 606 V 601 V 597 V 592 V 588 V 583 V
10 J 871 V 864 V 857 V 850 V 844 V 837 V 831 V 825 V
20 J 1232 V 1222 V 1212 V 1203 V 1193 V 1184 V 1175 V 1166 V
30 J 1509 V 1497 V 1485 V 1473 V 1461 V 1450 V 1439 V 1429 V
50 J 1948 V 1932 V 1917 V 1902 V 1887 V 1872 V 1858 V 1844 V
100 J 2755 V 2733 V 2711 V 2689 V 2668 V 2648 V 2628 V 2608 V
200 J 3896 V 3864 V 3834 V 3803 V 3774 V 3745 V 3717 V 3689 V
300 J 4772 V 4733 V 4695 V 4658 V 4622 V 4586 V 4552 V 4518 V
360 J 5200 V 5185 V 5143 V 5103 V 5063 V 5024 V 4986 V 4949 V
98
3.5. ADJUSTMENT OF THE "EXTERNAL STIMULATOR" CIRCUIT
Point
Poten- Target
Measuring of
ter tolerances
rement
Maximum
output voltage termi- The measurement
for the power Voltmeter nals of P1 96 V is carried out
generator C9 ±2V without charge
Baseline for
the Mode: fix
measurement Voltmeter SP5 P2 15 mV Selected current:
of the patient ± 5 mV 0 mA
current
bet-
Amplitude of ween Connect a 500-Ω
delivered Voltmeter SP5 P3 2.99 V load at the input
current and ± 0.01 V and select a
SP6 150-mA current
99
4. LIST OF SCHEMATICS AND DIAGRAMS
DWG PRINT DESIGNATION PAGE
W3S41537A Schematic CPU/preamplifier 1/7 103

Schematic CPU/preamplifier 2/7 104
W3L41537A W4P41537A CPU/preamplifier implantation 110
W3S41537B Schematic CPU/preamplifier 1/7 111

W3L41537B W4P41537B CPU/preamplifier implantation 118
W3S41537C Schematic CPU/preamplifier 1/7 119

W3L41537C W4P41537C CPU/preamplifier implantation 126
Old version :
W4S41538A LCD controller schematic 127
W4L41538A W4P41538A LCD controller implantation 128
W4S41538B LCD controller schematic 129

W4L41538B W4P41538B LCD controller implantation 130
New version :
W4S141597 TFT LCD controller schematic 131
W4L141597 W4P141597 TFT LCD controller implantation 132
New version :
W4S141651 B/W LCD controller schematic 133
W4L141651 W4P141651 B/W LCD controller implantation 134
100
W4S141674 Backlight converter support schematic 135
W4L141674 W4P141674 Backlight converter support
implantation 136
W3S41535A High-voltage schematic 137

W3L41535A W4P41535A High-voltage implantation 138
W3S41535B High-voltage schematic 139

W3L41535B W4P41535B High-voltage implantation 140
W3S41536A Defibrillator control schematic 1/4 141

Defibrillator control schematic 2/4 142
W3L41536A W4P41536A Defibrillator control implantation 145
W3S41536B Defibrillator control schematic 1/4 146

W3L41536B W4P41536B Defibrillator control implantation 150
W3S41536C Defibrillator control schematic 1/4 151

W3L41536C W4P41536C Defibrillator control implantation 155
W4S41548 Hand-held electrode interconnection

schematic 156
W4L41548 W4P41548 Hand-held electrode interconnection
implantation 157
W4S41545A Hand-held electrode energy selection

schematic 158
W4L41545A W4P41545A Hand-held electrode energy selection
implantation 159
W4S141569 External connector filter schematic 160

W4L141569 W4P141569 External connector filter implantation 161
W3S41540A CPU communication schematic 162

W4L41540A W4P41540A CPU communication implantation 163
101
W4S141570 Sp02 filter schematic 164
W4L141570 W4P141570 Sp02 filter implantation 165
W3S141539B External pacemaker schematic 166

W4L141539B W4P141539B External pacemaker implantat. 1/2 167
External pacemaker implantat. 2/2 168
W3S141539C External pacemaker schematic 169

W4L141539C W4P141539C External pacemaker implantat. 1/2 170
External pacemaker implantat. 2/2 171
W3S41541A VF/VT detection schematic 1/2 172

VF/VT detection schematic 2/2 173
W3L41541A W4P41541A VF/VT detection implantation 174
W4S41557A Control support for adhesive or internal 175

electrodes schematic
W4L41557A W4P41557A Control support for adhesive or internal 176
electrodes implantation
W4S41546 Energy selection for adhesive and 177

internal electrodes schematic
W4L41546 W4P41546 Energy selection for adhesive and 178
internal electrodes implantation
W3S41560 General wiring schematic 179

W3S41560A General wiring schematic 180
W4S41567 Hand-held electrode module wiring
schematic 181
W4S141599 Adhesive electrodes wiring schematic 182
W4S141600 Internal electrodes wiring schematic 183
102
5. LIST OF COMPONENTS
PRINT CA DESCRIPTION PAGE
W4P41537A W1411304 CPU/preamplifier printed circuit 186
W4P41537B W1411304 CPU/preamplifier printed circuit 201
W4P41537C W1411304 CPU/preamplifier printed circuit 216
Old version :
W4P41538A W1411305 LCD controller printed circuit 231
W4P41538B W1411305 LCD controller printed circuit 233
New version :
W4P141597 W1411567 TFT LCD controller printed circuit 235
New version :
W4P141597 W1411571 N/B LCD controller printed circuit 237
W4P141674 W1411782 Backlight converter support printed

circuit 239
W4P41535A W1411302 High-voltage printed circuit 240
W4P41535B W1411302 High-voltage printed circuit 244
W4P41536A W1411303 Defibrillator control printed circuit 248
W4P41536B W1411303 Defibrillator control printed circuit 256
W4P41536B W1411303 Defibrillator control printed circuit 263
W4P41548 W1411313 Hand-held electrode 270

interconnection printed circuit
W4P41545A W1411314 Hand-held electrode energy 271

selection printed circuit
184
W4P41569 W1411530 External connector filter printed 272
circuit
W4P41540A W1411307 CPU communication printed circuit 273
W4P41570 W1411531 Sp02 filter printed circuit 275
W4P141539B W1411306 External pacemaker printed circuit 276
W4P141539C W1411306 External pacemaker printed circuit 280
W4P41541A W1411308 VF/VT detection printed circuit 284
W4P41557A W1411361 Control support for adhesive

electrodes printed circuit 288
W4P41557A W1411526 Control support for internal

W4P41546 W1411315 Energy selection for adhesive

W4P41546 W1411316 Energy selection for internal

185
6. MODIFICATION OF DEVICE
6.1. CPU/PREAMPLIFIER PRINTED CIRCUIT
W4P41537A
Article
Index of Number
number of
printed of ECL Modifications
printed
circuit version
circuit
W1411304 A 1 Circuit diagram creation
W1411304 B 2 Deletion of D31 (0 Ω)
Change of diodes D6 and D12 (1N4937 →

MBR160)
Addition of C219 (100 nF) in parallel with

C66
Change of C61 value (1µF → 10 µF)
Change of R190 value (274 kΩ → 221 kΩ)
Deletion of capacitor C76 (1000 µF) and

replacement by a diode D32 (1N5818)
Addition of C220 (100 nF) and R274

(475 kΩ)
Deletion of R145 (0 Ω)
Addition of C221 (180 pF)
W1411304 B 3 Addition of D33 (BAS32)
W1411304 C 4 Various modifications (see value table and

circuit diagram)
W1411304 C 5 Change of values of R26 (20 kΩ →

6,81 kΩ) and R156 (10 kΩ → 100 kΩ)
W1411304 C 6 Addition of resistor R289 (2,21 kΩ)
W1411304 C 7 Deletion of R125 and change of values of

R93 (1 kΩ → 1,1 kΩ), R1, R2 (10 MΩ →
4,7MΩ) and R219, R224 (10 MΩ →3,3 MΩ)
W1411304 C 8 Addition of C223, C224, C225 capacitors (3

X 1 nF) in parallel with C174, C178, C162.
292
W1411304 C 9 Change of U72 référence (80C32 →
80C251)
W1411304 C 10 Addition of R290 (10kΩ)
W1411304 C 11 Linking between the 7 and the 8 pin from

J11
W1411304 C 12 Change of value of L9 (100 µH → 470µH)
6.2. LCD CONTROLLER PRINTED CIRCUIT (old version)
W4P41538A
Article
Index of Number
number of
printed
circuit version
circuit
W1411305 A 2 Addition of resistances R7 to R19

(13 X 562 Ω)
W1411305 B 3 Replacement of resistances R8 to R19 (12

X 562 Ω) by 3 resistance networks RN3,
RN4 and RN5 (4 X 562 Ω)
293
6.3. HIGH VOLTAGE PRINTED CIRCUIT
W4P41535A
Article
Index of Number
number of
printed
circuit version
circuit
W1411302 A 2 Change of R14 value (3,92 kΩ → 4,22 kΩ)
W1411302 B 3 Addition of D21 (DO24-S10)
W1411302 B 4 Addition of 2 heat shrinkable sleeves above

the 2 ferrites
W1411302 B 5 Change of R43 value (22,1 kΩ → 1 kΩ)
294
6.4. DEFIBRILLATOR CONTROL PRINTED CIRCUIT
W4P41536A
Article
Index of Number
number of
printed
circuit version
circuit
W1411303 A 2 Change of R48 value (56,2 kΩ → 61,9 kΩ)
W1411303 B 3 Change of DZ5 value (4,7 V → 3,9 V)
Addition of a resistor R129 (0 Ω)
Addition of a circuit containing D25, R128,

R69, C72, U14A and R70
Change of D6 référence (BAS32 →

1N4148)
Deletion of circuit containing U14G, R69,

R82, T5 and R70
Addition of a circuit containing RU1, C73,

L2 and C74
Change of C71 value (100 nF → 1 uF) and

addition of D27 (BAS32)
Change of R48 value (61,9 kΩ → 56,2 kΩ)
W1411303 B 4 Replacement of R125 (470 Ω) with R126

(0 Ω)
W1411303 B 5 Addition of a dividing bridge containing

R130, R131 (2 X 47,5 kΩ) and C75 (47 nF)
Change of R100 value (22,1 kΩ → 10 kΩ)
295
W1411303 C 6 Deletion of R126 (0Ω)
Substitute of R130 (47.5kΩ) and R131

(47.5kΩ) with R125 (47.5kΩ) and R126
(47.5kΩ)
Change of R100 value (22.1kΩ → 10kΩ)
Change of R98 value (100kΩ → 150kΩ)
Change of D6 référence (1N4148 →

BAS32)
Addition of a circuit containing C76, C77,

C78, DZ7, D26, D28, D29, R82, RG4, TR2,
D30, D31
W1411303 C 7 Change of R58 value (22,1 kΩ → 1 kΩ)
296
6.5. EXTERNAL PACEMAKER PRINTED CIRCUIT
W4P41539B
Article
Index of Number
number of
printed
circuit version
circuit
W1411306 B 1 Circuit diagram creation
W1411306 B 2 Change of F2 value (0,8 AT)
Addition of L3 (2 X 0,4 mH), C32 (10 nF)

and C33 (10 nF)
Addition of L1 (23 µH), C4 (10 nF) and C5

(680 nF)
W1411306 C 3 No electronical modification
W1411306 C 4 Change of values of L1 (23 µH → 68 µH),

R7 (10 kΩ → 3,32 kΩ), R8 (365 Ω → 1 kΩ)
and R9 (365 Ω → 10 Ω)
Deletion of C10 (100 nF)
W1411306 C 5 Change of PB1
W1411306 C 6 Addition of DZ3 Zener diode (3,9 V)
W1411306 C 7 Change of values of RN4 (1 MΩ → 100

kΩ), R38 and R39 (33,2 kΩ → 3,32 kΩ),
C20 (1nF → 10 nF) and P2 (2 MΩ → 200
KΩ )
297
6.6. CPU COMMUNICATION PRINTED CIRCUIT
W4P41540A
Article
Index of Number
number of
printed
circuit version
circuit
W1411307 A 2 Addition of C29, C30, C31, C32, C33, C34

capacitors (6 X 1 nF) in parallel with C1,
C3, C6, C7, C8, C10.
6.7. VF/VT DETECTION PRINTED CIRCUIT
W4P41541A
Article
Index of Number
number of
printed
circuit version
circuit
W1411308 A 2 Addition of C60 (47µF) in parallel with C22
298
6.8. DEVICE WIRING
Article
Index of Number
number of
printed
circuit version
circuit
W14S0130 1 Circuit diagram creation
W14S0130 2 Addition of printed circuits W4P141569

(external connector filter) and W4P141560
(SpO2 filter)
W14S0130 3 Addition of R125 in the cable linking J5 to

HV condenser
Change of color of wire from pin 4 of J3 to

pin 4 of J20
W14S0130 A 4 Change of LCD screen into TFT or

black/white screen
Addition of printed circuit W4P141674

(backlight converter support) for B/W
screen
299

0298-W1403570 NT Dg3002ih Ang 03 03

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DEFIGARD 3002 IH

Version 1.13 March 2003

SCHILLER MEDICAL S.A.S

Part No. W1403570

NOTE CONCERNING CIRCUIT DIAGRAMS ............................................................... 7

1.1. Presentation ................................................................................................... 9

1.2. Technical characteristics ................................................................................ 11

1.3. Cleaning ......................................................................................................... 18

1.4. List of component abbreviations .................................................................... 19

1.5. List of abbreviations used on diagrams.......................................................... 20

2.1. General operation .......................................................................................... 28

2.2. Power supplies ............................................................................................... 29

2.3. ECG acquisition ............................................................................................. 30

2.3.1. Acquisition via the 3-lead patient cable ............................................. 30

2.3.2. Acquisition via defibrillation electrodes .............................................. 31

2.3.3. Type of patient cable ......................................................................... 31

2.4. ECG signal processing................................................................................... 32

2.4.1. Amplification and filtering................................................................... 32

2.4.2. Detection of stimulation or defibrillation impulses.............................. 32

2.4.3. QRS complex detection..................................................................... 33

2.4.4. Detection of overshoot and derivation change .................................. 33

2.5. Sound module ................................................................................................ 33

2.6.1. Memory space ................................................................................... 34

2.6.2. The characters EPROM .................................................................... 37

2.6.3. Safeguarding the work RAMs and the timer ...................................... 37

2.6.4. The decoder ...................................................................................... 37

2.6.5. Input and output switching circuit....................................................... 39

2.6.6. Multiplexing and A/D conversion ....................................................... 42

2.6.7. Interruption request hold.................................................................... 43

2.6.8. Watchdog and reset system .............................................................. 44

2.6.9. Interface with the LCD controller ....................................................... 45

2.6.10. The graph interface ........................................................................... 46

2.6.11. Micro-communication ........................................................................ 47

2.7. LCD controller circuit ...................................................................................... 47

2.7.1. LCD controller : old version screen.................................................... 47

2.7.2. LCD controller : new version screen.................................................. 50

2.8. The high voltage circuit .................................................................................. 52

2.8.1. Defibrillator AC power supply ............................................................ 52

2.8.2. HV generator control relay................................................................. 53

2.8.3. The high-voltage generator................................................................ 53

2.8.4. High-voltage measuring circuit at HV converter primary winding....... 55

2.8.5. HV condenser charge timing diagram ............................................... 55

2.8.6. Battery test timing diagram ................................................................ 57

2.8.7. High voltage module .......................................................................... 58

2.8.8. The HV measurement circuit on the HV condenser terminals........... 59

2.8.10. The defibrillator-test detection circuit ................................................. 62

2.9.1. Supply and battery charge................................................................. 63

2.9.2. The on/off system .............................................................................. 64

2.9.3. Manual semiautomatic locking .......................................................... 67

2.9.4. Selected energy reference ................................................................ 67

2.9.5. Charge/discharge control................................................................... 68

2.9.6. Control logic....................................................................................... 69

2.9.7. Defibrillator safety mechanisms......................................................... 75

2.9.8. Patient current measurement ............................................................ 79

2.9.9. The "Defi-ready" indicator light .......................................................... 79

2.9.10. Graph triggering via the buttons of the hand-held electrodes............ 80

2.9.11. Defibrillation module coding .............................................................. 81

2.9.13. Other functions .................................................................................. 82

2.10.1. Communication with the CPU............................................................ 83

2.10.2. External stimulator............................................................................. 88

2.10.3. VF/VT detection................................................................................. 91

3. TEST AND REPLACEMENT OF PRINTED CIRCUITS ......................................... 95

3.1. Unit disassembly and removal of printed circuits ........................................... 95