VLSI Design (20404606) UNIT-V Practical Aspects and Testability Introduction to Testing Reject Gad dips) + Testing is a manufacturing step. It is required to guarantee a fault free product or it tells whether a system is good or bad. Out ‘Test pattens Applied from tester 10001 10010 00000 riiit Tnpurs Golden response How to test a chip “Chip” while testing is called “ Design Under Test” (DUT) estgn veut) + Response analyzer contains fault free design results stored in it. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 12VLSI Design (20404606) UNIT-V When D.U.T produces the response corresponding to input test pattem, it compares this response with already stored results. If these are matched, D.U.T is fault free, else it has a fault and reject the chip. For generating input test pattern, we use a machine “ATPG” ie “Automatic Test Patten Generator”. The test pattem is a binary sequence. When to do Testing? Can be carried out at various levels: — At chip level, when chips are manufactured. = At the board level, when chips are integrated on the board level — At the system level, when several boards are assembled together ‘Test Generation A test is a sequence of test patterns, called test veetors, applied to the CUT whose outputs are ‘monitored and analysed for the correct response Exhaustive testing — applying all possible test patterns to CUT Functional testing — testing every truth table entry for a combinational logic CUT — Neither of these are practical for large CUTs Fault coverage is a quantitative measure of quality of a set of test vectors Fault coverage of a given set of test vectors. Fault coverage= Novo lke detected X 100 Te No -of foulte in te Ut " 100% fault coverage may be impossible due to undetectable faults number of detected faults ‘fault detection efficiency = —— —___—_____—. total number of faults - number of undetectable faults N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 13VLSI Design (20404606) UNIT-V ‘Test Generation System Since ATPG is nuch slower than fault simulation, the fault list is trimmed with use o a fault simulator after Detected each vector is generate Fault Simulate to Test Set Vectors Automatic Test Pattern Generation (ATPG) + Algorithms generating sequence of test vectors for a given circuit based on specific fault models. Fault Simulation + Enmlates fault models in CUT and applies test vectors to determine fault coverage. + Simulation time can be reduced by parallel, deductive, and concurrent fault simulation, Design For Testability (DFT) + Design technique that makes test generation and test application easier and cost effective. + Itis very difficult to control and observe the intemal flip flops. + DET techniques help in making the internal flip Hops easily controllable and observable. + Basically it converts the sequential circuit test generation problem to combinational circuit test generation problem Advantages of DFT: + Shorter time to market + Reduce design style + Reduced cost + To improve quality * Controllability: setting or resetting nodes in the system by driving input pins of the chip, * Observability: Observing a node in the system by watching external output pins of the chip Disadvantages of DET — Chip area over head — Performance overhead, ie speed decreases N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 14VLSI Design (20404606) UNIT-V + DET techniques generally fall into one of the following three categories: “Ad hoe DFT techniques + Level-sensitive scan design (LSSD) or scan design, ¢ Built-in self-test (BIST) Ad hoc DFT technique + Ad hoc testing combines a collection of tricks and techniques that can be used to increase the Observability and controllability of a design and that ae generally applied in an application dependent fashion + Itis a strategy to enhance the design testability without making much change to design style. Le == (a) Design with low testability (b) Adding a multiplexer (selector) improves testability. + An example of such a technique is shows a simple processor with its data memory, Under normal configuration, the memory is only accessible through the processor + Writing and reading a data valne into and ont of a single memory position requires a number of clock cycles. + The controllability and observability of the memory can be dramatically improved by add multiplexers on the data and address buses, + During normal operation mode, these selectors direet the memory ports to the processor. + During test, the data and address ports are connected directly to the I/O pins, and testing the memory can proceed more efficiently + It is often worth while to introduce extra hardware that has no functionality except improving the testability. Advantage + Itprovides more systematic and automatic approach to enhance the design testability. Disadvantages: N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 15VLSI Design (20404606) UNIT-V + Experts and tools not always available. + Test generation mnst often be manually performed with no guarantee of high fault coverage + Design iterations may be needed, which is very time consuming, BUILT IN SELF TEST (BIST) + When circuits or design increase in size, testing them is a difficult process, ic it increases the cost. + So, we are including the testing features in the design itself, it simplifies or reduces our testing cost or procedure * Built-in self-test is the capability of a circuit (chip, board, or system) to test itself. BIST represents a merger of the concepts of built-in test (BIT) and self-test. Chip 70% design , Testing Features i.e ATPG & Response analyzer in built Chi -tesieoriteell Test Generator le Chip = Vevey b dvd db ee edy Circuit Under Test (CUT) —| devo dvd d dvd Response comparator Good/Bad BIST techniques can be classified into two categories, namely i On-line BIST, which includes concurrent and non-concurrent techniques, ii, Off-line BIST, which includes functional and structural approaches. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 16VLSI Design (20404606) UNIT-V In on-line BIST, testing occurs during normal functional operating conditions; ie., the circuit under test (CUT) is not placed into a test mode where normal fimetional operation is locked out. Concurrent on-line BIST is a form of testing that oceurs simultaneously with normal finetional operation. In non-coneurrent on- line BIST, testing is carried out while a system is in an idle state. This is often accomplished by executing diagnostic software routines (macrocode) or diagnostic firmware routines (microcode). The test process can be interrupted at any time so that normal operation can resume. Off-line BIST deals with testing a system when it is not carrying out its normal functions. Systems, boards, and chips can be tested in this mode. This form of testing is also applicable at the manufacturing, field, depot, and operational levels. Often Off-line testing is carried out using on-chip or on-board test- pattem. generators (TPGs) and output response analyzers (ORAS). Off-line testing does not detect errors in real time, ie., when they first occur, as is possible with many on-line concurrent BIST techniques Fer oftesing —— Off-line Ondine oS Functional — Structural Concurrent Nonconcurent v Functional off-line BIST deals with the execution of a test based on a functional description of the CUT and often employs a functional, or high-level, fault model. v Structural off-line BIST deals with the execution of a test based on the structure of the CUT. Off-Line BIST Architectures Off-line BIST architectures at the chip and board level can be classified according to the following criteria 1. Centralized or distributed BIST circuitry; 2. Embedded or separate BIST elements. BIST architectures consist of several key elements, namely 1. Test-pattern generators; 2. Output-response analyzers: 3. The circuit under test; 4, A distribution system (DIST) for transmitting data from TPGs to CUTs and from = CUTs to ORAS; 5. BIST controller for controlling the BIST circuitry and CUT during self-test. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 17VLSI Design (20404606) UNIT-V Centralized BIST architecture ‘The general form ofa centralized BIST architecture is shown in the below figure. Chip, board, or system controller L a Here several CUTs share TPG and ORA circuitry. This leads to reduced overhead but increased test time. During testing, the BIST controller may carry out one or more of the following fimnetions: 1. Single-step the CUTs through some test sequence 2. Inhibit system clocks and control test clocks. 3. Communicate with other test controllers, possibly using test busses. Chip, board, or system TPG |—> CUT [->]ORA TPG|_={cuT|_={oRA The distributed BIST architecture is shown in above figure. Here each CUT is associated with its own TPG and ORA circuitry. This leads to more overhead but less test time and usually more accurate diagnosis N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 18VLSI Design (20404606) UNIT-V Advantages Test pattems generated on chip, controllability increased. Test can be on line or offline Test can run at circuit speed, more realistic; shorter test time; easier delay testing Extemal test equipment greatly simplified Easily adapting to engineering changes Ten Marks Questions 1 aay ew Explain the two phase clocking with circuit diagram in sequential circuits. Draw the 4 bit dynamic shift register using NMOS and CMOS with stick diagrams Explain bus line architecture for NMOS and CMOS with different classes. Discuss the general arrangement of a 4-bit arithmetic process. Explain the design of a 4-bit shifter in detail Explain in detail about design for testability. What is design for testability? Discuss about the built in self test. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 19TEST AND TEST AQ) UITY Desrn Enpnen — DeAignay Es _ : o = ce he ts crete Lbthematign & grt Verfition tage 4 ek destyad Y usin Enyineess met necgys oy shecificstions al fundlen ccd, an md sSulbon & feakey tele Thpicll Lesipe Begnee/ = Reshenable HAR Pyicd ‘waflemertatien, of te Aysiqns- — We Ad. tol gee am. consi hen p.ctdyr Vie mmanfact ding ss siete 8 PexPmance veqpitementd be stint Bon of Ze leat Bd nopaivell epee By Pe We coppers} tien Tet EmyineeX > 3 the Mieke tet thetegion & Plays ae emaching ot wh vcbsitity of acs. “yrs sheciabgd ersifment & ephorete heat He xf é iwdludl in devdlobnet of hea laly | chp test cost — assy cheb sdk Vite Ge bear = shox Ah Intpateh ite yc] | _ saoy fai an : ahh Wm Senvie = $looo% : vat YW spot te tat ot the ch level or coma hoyedy ad Poasible . | abdeton aistay are very costly in tenes of. tne. &. monet. fied . 3 Desir PS Tutebity (@rD: ta on pret Pest of och Lean: ~) Sof Peat meade, of. testakiltty bet ‘ite tee Ot Ake D 30h of reinimwom dof aver js x hecfiene Fd fealty arditethe nthe dei of xc,system Poti omen def: Sen shle partition of a syften (ck) vite Sob sterab, exch ° which Js » self cavitaane anh indebendent od bevible. ey: Abt Lites path chap Be arta) \ sll corteined >the alse ‘ > bot sim Je >the shitter oe tt, > Doviny Qvetet Fy yy wd cee pawthe. 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