Name Ashish hupta

Enrellment BT1cS035
Deparment’ CSE
Microprocessors and Microconthollers
Assignmen! -4
9.1 Draw the Architedture c 8085 Micvoprece ssor and
Explain all -RST
the65
5.5 RST peiphurals datails .
oTRAP in SOD SID
+INTA
-INTR
Ans

Intermt contrel Senal I/o contvel

J &-bit internol data bus 1

Accumoto Temp req Flag Tnstruchen Bveq (8)|Ceg (8) Register

array
regysBer Dreg (8)E reg (3)
(Areg) 8 8 H reg (B) L reg ()
Stack Pointer (lb)
Instrvetn
Anthmetic decoder and |Program counter (1c)
machine
logicol unit <ycle Incrementer/
decrementer address
encoding aeh LI6)

TIming and control

CLK Address Data Jaddress
GEN Contrel status DMA RESET |bufer btfer (8)
Reody IN out
Reset
RESET

As- As AD ADo
addhess bus address /doda bus
8085 Micvoprocessr Architechuve
 8-bit microprecessor. that
ne 085 micrsprscessor is an
the mid 1970's
. 34 was
W0s developed by Sntel in Dersonal compuling:
widly Used in Ahe early
the days of
consists e several
microprecessor
the Architecture o 8085 regislers, pragram
compohends , in luding the accumdlader,
Key register , dato bus ,
inshructian register,
cOUnter stack bointer , instrucien
address bus. control bus ele. is vsed to
The aceumulator is an 8- bit reqister ha
and legicad results. 9
9t is the most and
sBore arithmeic the 8085 microprocessor such
in
commonly vsed registeraithmetie and logical peraiens
is Dsed to þerform þerations
addiion subtracion and bitwise
eneral- þurb05e rgisles
8085 microprocesser has six to
L which can be,csmbined
1. The
including B,c,D,E, Hand The B andC registers ca
form þaits
16- bit register the BCregister pair, the D
be combined to torm combined to torm the 9
and E vegisters canbe be
Hand L registers can be
DE reqisBer bair , and
comboined egisterhait these reister
to torm the HL stere
paits ate commonly Used to mem ory address es
and other laBa.
The preq ram counter is a6- bit register, tha contains
the memory address efthe neyt nstruetien to be
executed the pregqram cauhteris incremented after
each instrucion is executed which llbos4he
micrehvecessor to executethe instuctinsin sequence
The stack boinler is a lb- bit vegieter, that is' vsed to
1

manaqe Ahe stack: The stack is secton o mem@ry

thad is vsedto stere lata temporarilysuch a
Subrouine addresses and ether data heaek
bointer is ysedto keep 4rack o the top of stack
The instruehon regisBer is an - bit regiser thot
Contains the current instrueion being
executed
The instroehen register is sed by the micrapraces8r
te decoda and execute nstrsctiens
The 9085 MPU þerforms he funelions vsing three sets
of Comm Unicatien lines called buses,the address bUS,
the data
data bus and the contrel bus
Ais Addvess Bs

Memony Trput
Da

Conel Bus
addlress Bus : T6e address bus has a ayou o lb lines
geherally idenlified as Aoto Ays The address
bus is uni direc honal: bs 4ou in ene direchen - trem the
MPU to þeri pheral devices. TheMPU vses he address bus
to berform the irst gunchom; identgng a þei phurala

memang lecaian . 4n compoter system each

Peripheral memar locahi en is idunifiedby a binary
ondhe
humber called address and address
he add ress bus is vsed
to carry a l6- bi! addhess.the nom ber o addkess lines
of the MPU determines ts copacity to identify diferent
mory locahens (or þeribherals) the B085 MPU ith
nemory
its I616 address lines is cahale o aadressing a455
GyK ) memory locations4he
(generoly knoon as G4K)
address bus is a I6- bit bus thot is Usedto address
memory and other dvices the address bus 1s osed to
select the memDvy location r Juvice that he miroprecesser
wants to accesS.

Dota Bus : The data eus isa avo ot eight ines vsed
for clata ftoo these ines are bidlrecional
Aato low Ahese- in both direchons betoeen the MPUdmd
memory and peripheraldevices. the MPU uses thu data
bus to herform the Secono mclion: aetaing Birany
intormoion the ight data ines enable Hhe MU to
 Manupulde 8. bit dada tanging om oo to bus FF (2256)
is Ill
the largest number com abheor "on the databit micreprocessor -
the 80B5 is Known os 8-
(255,6)
micoprcess or such as the intel s0g6 and Moto rela
Kn euwn as
000 hove 16 data lines ', these, they ate
I6 - bit wicvoprocessors. is vsed to tanser
8- bit bus hat
The data bus is anmicropre cessor and emory or other
data betseen 4he
davices .
is tombrised o varieus
contrel bus
The contrel
canrg sychronizaien signds
Control bus: The
Single lines that
to performthe third
The MpU USes such lines not graups
iming sigals these are
Joneion þreviding
addresse, o data buses but individva
ot lines ike bulse to indicoBe Ahe MPU
that previde a
lines
cortvol sigral
shecifie
erades shecifie
eheraien. the MPU. generaBes
eperaiensSuch as memoy read or Tð wite)
for eveg signals Vsed to idanty a
these are
it perfoms ohich the MPUintends tocommunscaBe
device 4tabe te read
ilth the' mermory -for exomple
To communicate
CAn instrocionh trom the memeny locotsn- the MPU deceded
bit oddress on the bus is
blaces the l6
extemal legic circuit the MPU sends the
pulse to the cireit called mevmor reod as the
conhel sigmal. the bulse ativotes he memory
chip and the contents e the memory locatien are
(8- bt data) ore placea on the jdata bus and
brouqht insidu the Vnicreprocess0r:
 Address Bus
1G Bit Memeru Address
Memory
Deco
ur
202
MPU
F2:I1D

2 6DS
2606

MEMR Data
Memary Rood
The contel bus is a set el sighale 4hotthecontrols
read
the
and wnte
oheraions o the micvo proce ssor, ncluclvg
obevaions . the conttol bus inc ludss the signals svch as
signal and
Ahe read sigrals , ite sgal, intewut
the vead is vsed to read data from meme
reset sigral is used toorite data
.

ether duvices and write ignal the intempt sighal is

davices
to memry er cther the micvol
microprecessor hat an
Used to signal
ocCured and
the 4he esen reset signal is vsed
ha sccured its mitial state.
micro -- er
processer
þrocesA to
to veset the 8- -þuvpoe micssprecessor
8085 is an
bit qeneval
Jallboing tontional omits
it Con sists e+of the
legic Unit CALW) : a is used to bevtorm
Athmeic and
mothemaieal ohexoin
addiion, muliblicaien suchacion, divisien doremyt like
inerement ete Diterent oheraions arc
ate carried gut
AAhmahhrations,
ALU al oberahons Bt Bit shifhina
shiting oheralions
and eperai ens.
Flag Regiter : is an 9-ft reister thad store,
edther o accumulator
or 4, dahendig vpon whidh
valoe is sto red in the acumlatar
b i l a g vegistor
Contains 8- bit out ot
 ahd rest ot -bit are " dont cave condiions " 4he
Jlag vegiser is tho dynamie register becavse ofter
each
operaien to chhck whthu the result is
zero , esiive or negafive. okuthr hre is any
veview
8-bt numbersoctured or rot , r tor comparisoh oy ho oo
VmerUS chey cay Jlag is chached. so, Jor
oant speraions toto chuck
chuckavi the cowterts if we
to chck the beh gur o siven tesult
then we COn Se
chudk So, oe can tlag egister to verida and
stadus register and thot th tay register is
it is bsed to chck
the status et cowent oealon ohich is
carried cut by ALr. being
The Jags cttected by the avthuma'e and logic
are

eherahi ons in the ALU. n mest e hese

the result is stored in speaikens
the accumulotor therefote
the Aags generally refeet data condlisns i the
aceumldor - with ser excpion the descipbons and
SOme
condh iom of the fags are Jlouos
æ) S- sgn flag: AHer Athe execvtisn ot an awthm ehc
r logie oþeraion ,i bit D, o4 the
vesulB Cusually in thu accumulator) is 4the sgn lag
is sel. the laq is vsed oith eigned numbets Sh
is 14he numberi will be
a gven bgte
viewed as
negaive
Da
number, if tis Othe number
will be COh Sidored þesitive . Sn arithmete
eheraHens.
with signed numbers , bit Da is resewed tor indicaking
the sign the remaining
Seven blk is used to veptesend
Ahe mognitude ot oa' number: However, this Jag fog is
iwelevant for the eeraiens the vnsigned nombers.
theretore , theandunsigned numbers even if bit Da e a
the tlaq isset,it doe, net mean
Ahol the result is negolive.
Z- zeY9 lag : The zeve fiag is set if the
ALU eheatien
and the Aloa is reset it
tesults in ß esulls
thu
by
by
the resul4 is not 0. The Jog is nmodifjed
the ether registers
In the accumulator as ell os

AC- Aoxilliang Carng Slag Sn Aitthrneke oheraien,cohan

careySaeherated by the
is
digt Da and bassed ehon tote digt
dig Du Du the AC faq iS

set the flag is vsed only iternally for BcD jor

(Binary
Decimal) eberaiens and is no avai lable
Codd seqyence ey a rogam
the proqrammer to change the
with a jumpinterachen
arithmetic or oheralion,
lgjicalnumber
resul has ah even e
if the
1's , the flag is set. 44t has on ode number of
a's , he lag is reset

CY- Cawy Sag: 3 arithmeic sheaian tesults in a

Carry the cany aq is set,otherwise
t is reset. the cavry be
lag olse serveA as a errouw
lag Jor subttacion
The bit pesi ions rescved Jar the Sags in Hhe Hlag
ste.
Dy D Ds Du D D Di Do
AC P

Amonq theavihmetic,the Ac Hlag isdeesvsednotintenally

fue flags, theinswcien indvd
for BD
ditionod jmþ instrucions bose on Ahe NC- gag of
remaing jout lagsthe Z and cy flags
the sed
are theA! mest cowmoy
Anstueion Ragcter and
and deceder: 44 is an 8-bit gister
whun an instoctien
4etched fom memorm thun t is slored in thu instrucien
wegjister . ånshucken hrodhr decsdos hepart
ifomatien presut
Prsat
In the inshruction reqister. they are ot ALU.hen
inshucien is fehched Arem memery and 4he desdr
ducods the instruc hien and establishus the seayence os
events Cnd
to follaw. Aho imstrycliem teaisBer is not þroqramna
- ble Cannet be accesSed threugh ang insructien

Regisher Ainay : Thee ave 6geeral ohose vegisters in

þrecessor, ie. B,c,D, E,H and
8085 L
each regisher con hold 8-bit dota. thus registers
in pair to hold l6- bit data and
Athuir pairing combination is ike B-c, D-E and H-L
Too addihenal registers called temjororrg registers
and are
ineludud in the veqisler aray
in the
34 holda hu temyoray data of avithmelie ond
legical eperations. thuu egislers ave vsed to hld
g- bit dada drig the executien e some
inshochons However because huy are ysed internaly
thuy are not available to th reg rammer.
Timiy and Contel This onit synchvonige al the
micvopreces oreherations oth tu
leck and generotes the cenhel signals necessaty sr
Communication between the microproceas or anel
petphrals
similar to aa sync þulse in
the contol siqnals are

an oscillescepe. the RD and WR gnals are

Cunc bolses
gnc þulses indicatng the aailability o dato en Ahu
dota bus llouing are the timing and com
.

sigals, okiuoich conth ol extema and internal circuits

 -Contial Signals : READY, 0, WR,LE
- sAudus Sqnals So ,S, TO/H
-DMA Signals HOLD, HLDA
- RESET Siqnals RESCTIN , RESET OUT
* INTR (apul)-4e! Revest: Tis is vsed as a
Similar to tho NT genal
Signa
furpese regisBer intewp!, it is
" INTA (0tput):-mtemt Aknbwledge : This is
used to
" RST 1.5 (nbut) :
Aeknoudedg an Jnterupt.
" RST 6-5
Restart 3nterbts : these are vectoted
" RST 5.5
ntemt that Aransfer the progrom Cenhel
to specific memory lecaliens: Hhuy
highur þrierihes than the INTR imtenthave
Amena thuse three the fiovtty ordr
is 15.65 and 5.5
" TRAP (3-pu): This is nonmoskalble interutt and ha, thu
higogl poiority
. HOLD (4-þut): This sigpal imdicates that
such a DMA CDirect Manno Aece)
Conteller is teayeHng the vuse o addreses and
data bases.
. HLDA (Otot); Mod Aaknouledg The Siagnal acbnoldges
the Hold reqyet.
Ready CAbul) : Thu sigal is wsed to dulay the
microprecessor
Raad or orite cycle
untl a slaw- shondig þeiphenal, is vcady fo send
Unil
or accept data. whon
hun Hhthuw ssgnals goes
lo.
 Ahe wiereptcesA or uoaits tor an iwteqral number e
cleck yle unillges high
. VESET IN: shn tho signal en tho
pin gpes
Counter is eet hto zere. ,the Juses re
thi-state and the MPU is reset
" RESET OUT Thu Siaval mdicates the MPU is be teset.
Ahe signol can be vsed to teset ther
davices
Serial input loutut conhal: A! chdtals Ahu sevial data
Communicaien by Using these
too instwehens : STDC Serial Aput data) and soD
(Seial output Data) and SaD LSerial Sutut Data)
An seria thansmissien , data bits ar sent Ovet a
Slinge ine, ene bit ot a Aime such as ho
to Arans missi eh
Cver tele phon lines.
Addvess bus and Dota bus: Dota bus carries the dota
to be
hreas cddress bus caries the locationstored 44 is bidirec ienal
to uhere it sheuld
be stored and it is ni direcisnal 4t is used to
transfer the dat and address I/o duvices:
AAdvess Butfer and Address - dato bufer : h centend
stack pointer and the progtom counter is stored in thu
leadadl in
he address buffer and address - dado bufer to
communicate with the CoU. Ths memty and
cennectec to tha T/0
chibs are buses th CPU con
exchange the dasired dlota usith hu memery and
I o chips
Ademt Cortrel: As Athe nome Sugg2ss, # conhols thu
intenops a proces · whn a
micr opvocesset is execuing a wai bratam ond whinevo
main program
an
intenopt the wric oprocessor shits the
centtel tom the main preg ram to þroces thu incoming
.
request AHter
goes back to thuthe reqyest
veqyest inin completed the contol
main prog ram
Thu 5 intewubt sigals in go85 micre processsr.
INTR, RST 75, RST 65, RST 55,TRAP