34

2.11 Error Codes

It is impossible to avoid the interference of noise, which causes errors in the

received binary data at other systems. The bits of the data may change (either 0 to
1 or 1 to 0) during transmission. Therefore error detection and correction code play
an important role in the transmission of data from one source to another. There are
four method for detect errors:

2.11.1 Parity Method for Error Detection

There are two parity methods, even and odd. In the even parity method, the value
of the bit is chosen so that the total number of 1s in the transmitted signal,
including the parity bit, is even. Similarly, with odd parity, the value of the bit is
chosen so that the total number of 1s is odd.
Even parity (ep): makes the total no. of 1΄s even

Odd parity (op): makes the total no. of 1΄s odd

Example: Assign the proper even parity bit to the following code groups:
(a) 1010 (b) 111000 (c) 101101 (d) 1000111001001 (e) 101101011111
Sol.

Make the parity bit either 1 or 0 as necessary to make the total number of 1s
even. The parity bit will be the left-most bit (color).

(a) 01010 (b) 1111000 (c) 0101101 (d) 0100011100101 (e) 1101101011111
 35

Example: An odd parity system receives the following code groups: 10110, 11010,
110011, 110101110100, and 1100010101010. Determine which groups, if any,
are in error.

Sol. Since odd parity is required, any group with an even number of 1s is
incorrect. The following groups are in error: 110011 and 1100010101010.

2.11.2 Checksum Method

Checksums are similar to parity bits except, the number of bits in the sums is larger
than parity and the result is always constrained to be zero. That means if the
checksum is zero, an error is detected. A checksum of a message is an arithmetic
sum of codewords of a certain length. The sum is stated by means of 1’s
complement and stored or transferred as a code extension of the actual code word.
At the receiver, a new checksum is calculated by receiving the bit sequence from
the transmitter.

Checksum of messages = M1 + M2 + M3 + M4 + … = 0 0 0 0 0

Example: If k = 4 and n =8, find the checksum of four segments: (10110011

10101011 01011010 11010101), along with each transmitted message, the
checksum of all the messages are also transmitted.

Sol. K=4, n=8

10110011 10110011
10101011 10101011
01011110 01011110
1 1
01011111 01011111
01011010 01011010
10111001 10111001
11010101 11010101
10001110 10001110
1 1
Sum: 10001111 10001111
Checksum: 01110000 01110000
Sum: 11111111
Complement = 00000000
Conclusion = Accept data
At sender side At receiver side
 36

2.11.3 Cyclic Redundancy Check (CRC)

In cyclic redundancy code (CRC), the transmitted bit sequence is:

TX RX

Series data + CRC data data + CRC data

The transmitted CRC is compared with the RX CRC and if they match then there
are no errors. If they do not match then error is there.

Example: Determine the transmitted CRC for the following byte of data (D) and
generator code (G). Verify that the remainder is 0. D: 11010011, G: 1010

Sol.
Since the generator code has four data bits, add four 0s (blue) to the data byte. The
appended data (D') is
 37

Example: During transmission, an error occurs in the second bit from the left in
the appended data byte generated in Example above. The received data is
D’ = 100100110100 Apply the CRC process to the received data to detect the error
using the same generator code (1010)

Sol.

2.11.4 Hamming Code (HC)

The Hamming code is used to detect and correct a single-bit error in a transmitted
code. To accomplish this, 4 redundancy bits are introduced in a 7-bit group of data
bits. These redundancy bits are interspersed at bit positions 2n (n = 0, 1, 2, 3) within
the original data bits. At the end of the transmission, the redundancy bits have to
be removed from the data bits. A recent version of the Hamming code places all
the redundancy bits at the end of the data bits, making their removal easier than
that of the interspersed bits.
 38

7-bits Hamming code is used commonly

Parity bits = 3 bits (p1, p2, p3)

Data bits = 4 bits (d1, d2, d3, d4)

2P ≥ n + P +1 Position of p from (20, 21, 22) 2n where {n= 0, 1, ……., n}

p1 = d1 d2 d4 All d except d3
p2 = d1 d3 d4 All d except d2
P3 = d2 d3 d4 All d except d1

Example: Determine the Hamming code word (7, 4) for the transmitted data
1011 over the noisy communication channel.
Sol.
Step 1: Find parity bit to constructing bit location table.
Bits position 1 2 3 4 5 6 7
Status P1 P2 d1 P3 d2 d3 d4
Code word 0 1 1 0 0 1 1

p1 = d1 d2 d4  1 0 1=0
p2 = d1 d3 d4  1 1 1=1
P3 = d2 d3 d4  0 1 1=0

Step 2: Enter data in the syndrome.

A = p1 d1 d2 d4  0 1 0 1=0
B = p2 d1 d3 d4  1 1 1 1=0
C = P3 d2 d3 d4  0 0 1 1=0

CBA = 000 No error detection

 39

Chapter 3
Logic GATES

3.1 Logic Gates

Circuits used to process digital signals are called Logic gates. Logic gates operates
with binary numbers. All voltages used with Logic gates will be either "High" or
"Low". In positive Logic, a High voltage means a binary digits "1", while a Low
voltage means a binary digits "0". All digital systems are constructed using these
Logic gates. Logic symbols are used to identify these circuits.

3.1.1 NOT (Inverter) gate

The inverter (NOT circuit) performs the operation called inversion or
complementation. The inverter changes one logic level to the opposite level. In
terms of bits, it changes a "1" to a "0" and a "0" to a "1".

𝑋=𝐴

Example: A waveform is applied to an inverter in following figure. Determine the

output waveform corresponding to the input and show the timing diagram.
According to the placement of the bubble, what is the active output state?
 40

Sol.

The output waveform is exactly opposite to the input (inverted), as shown in

following figure, which is the basic timing diagram. The active or asserted output
state is 0.

3.1.2 The AND Gate

The AND gate is one of the basic gates that can be combined to form any logic
function. An AND gate can have two or more inputs and performs what is known
as logical multiplication.

𝑋 =𝐴∙𝐵

The total number of possible combinations of binary inputs to a gate is determined

by the following formula:
𝑁 = 2𝑛
 41

Where N is the number of possible input combinations and n is the number of

input variables.

Example: (a) Develop the truth table for a 3-input AND gate. (b) Determine the
total number of possible input combinations for a 4-input AND gate.
Sol.

a) There are eight possible input combinations (23 = 8) for a 3-input AND gate.
The input side of the truth table shows all eight combinations of three bits.
The output side is all 0s except when all three input bits are 1s.

Truth table for a 3-input AND gate

b) N = 24 = 16. There are 16 possible combinations of input bits for a 4-input

AND gate.

Example: If two waveforms, A and B, are applied to the AND gate inputs as in
following figure, what is the resulting output waveform?
 42

Sol.
The output waveform X is HIGH only when both A and B waveforms are HIGH
as shown in the timing diagram.

A and B are both HIGH during these four time intervals; therefore, X is HIGH

Example: For the two input waveforms, A and B, in following figure, show the
output waveform with its proper relation to the inputs.

Sol.
The output waveform is HIGH only when both of the input waveforms are HIGH
as shown in the timing diagram.
 43

3.1.3 The OR Gate

The OR gate is another of the basic gates from which all logic functions are
constructed. An OR gate has two or more inputs and one output, as indicated by
the standard logic symbols in Figure below, where OR gates with two inputs are
illustrated.

𝑋 =𝐴+𝐵

Example: If the two input waveforms, A and B, in following figure are applied to
the OR gate, what is the resulting output waveform?

Sol.
The output waveform X of a 2-input OR gate is HIGH when either or both input
waveforms are HIGH as shown in the timing diagram. In this case, both input
waveforms are never HIGH at the same time.

When either input or both inputs are HIGH, the output is HIGH
 44

3.1.4 The NAND Gate

The NAND gate is a popular logic element because it can be used as a universal
gate; that is, NAND gates can be used in combination to perform the AND, OR,
and inverter operations.

𝑋 = ̅̅̅̅̅̅
𝐴∙𝐵
Example: If the two waveforms A and B shown in following figure are applied to
the NAND gate inputs, determine the resulting output waveform?

Sol.
Output waveform X is LOW only during the four time intervals when both input
waveforms A and B are HIGH as shown in the timing diagram.
 45

Example: Show the output waveform for the 3-input NAND gate in following
figure with its proper time relationship to the inputs?

Sol.
The output waveform X is LOW only when all three input waveforms are HIGH
as shown in the timing diagram.

Example: For the 4-input NAND gate in the following figure, operating as a
negative-OR gate, determine the output with respect to the inputs?
 46

Sol.
The output waveform X is HIGH any time an input waveform is LOW as shown
in the timing diagram.

3.1.5 The NOR Gate

The NOR gate, like the NAND gate, is a useful logic element because it can also
be used as a universal gate; that is, NOR gates can be used in combination to
perform the AND, OR, and inverter operations.

𝑋 = ̅̅̅̅̅̅̅̅
𝐴+𝐵
 47

Example: If the two waveforms shown in following figure are applied to a NOR
gate, what is the resulting output waveform?

Sol.
Whenever any input of the NOR gate is HIGH, the output is LOW as shown by
the output waveform X in the timing diagram.

Example: If Show the output waveform for the 3-input NOR gate in following
figure with the proper time relation to the inputs?
 48

Sol.
The output X is LOW when any input is HIGH as shown by the output
waveform X in the timing diagram.

Example: A device is needed to indicate when two LOW levels occur

simultaneously on its inputs and to produce a HIGH output as an indication.
Specify the device?

Sol.
A 2-input NOR gate operating as a negative-AND gate is required to produce a
HIGH output when both inputs are LOW, as shown in following figure

Example: As For the 4-input NOR gate operating as a negative-AND in the

following figure, determine the output relative to the inputs?
 49

Sol.
Any time all of the input waveforms are LOW, the output is HIGH as shown by
output waveform X in the timing diagram.

3.1.6 The Exclusive-OR Gate

The XOR gate has two or more inputs. For two inputs XOR, the output is similar
to that from the OR gate except it is "0" when both inputs are "1". In general, an
XOR gate gives an output value of "1" when there is an odd number of 1's on the
inputs to the gate.

=1

𝑋 = 𝐴 ⊕𝐵
 50

Truth table for a 3-input XOR gate

Input Output
A B C X

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Example: A certain system contains two identical circuits operating in parallel.

As long as both are operating properly, the outputs of both circuits are always the
same. If one of the circuits fails, the outputs will be at opposite levels at some time.
Devise a way to monitor and detect that a failure has occurred in one of the
circuits?

Sol.
The outputs of the circuits are connected to the inputs of an XOR gate as shown
in following figure. A failure in either one of the circuits produces differing
outputs, which cause the XOR inputs to be at opposite levels. This condition
produces a HIGH on the output of the XOR gate, indicating a failure in one of the
circuits.
 51

3.1.7 The Exclusive-NOR Gate

The output in this gate is equivalent to inverting the output from the XOR gate.
In general, an XNOR gate gives an output value of "1" when there is an even
number

=1

𝑋 = 𝐴 ⊙𝐵

Truth table for a 3-input NOR gate

Input Output
A B C X

0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
 52

Example: Determine the output waveforms for the XOR gate and for the XNOR
gate, given the input waveforms, A and B, in following figure?

Sol.
The output waveforms are shown in previous figure.
Notice that the XOR output is HIGH only when both inputs are at opposite levels.
Notice that the XNOR output is HIGH only when both inputs are the same.