Analog Electronic Circuits – 2022-2023

Design Project Report

Group data

Group number Abbas Ismail - Raed Awad

Name – Student 1 Abbas Ismail

Name – Student 2 Raed Awad

Goal:

Design of the 2stage OpAmp such that it passes the given specifications (insert your specs below):

𝐶𝐶𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 [𝑝𝑝𝑝𝑝] 4

DC gain [dB] 47

𝑓𝑓𝐺𝐺𝐺𝐺𝐺𝐺 [MHz] 20

Phase margin (PM) [deg] > 70

Output swing [V] > 0.7

Plan: Design of the 2-stage OpAmp on paper (10 points)

1) Calculate the 𝑉𝑉𝑂𝑂𝑂𝑂 , 𝑔𝑔𝑚𝑚 , 𝐼𝐼𝐷𝐷𝐷𝐷 and L of each transistor (see exceptions under “Remark”) and the required 𝐶𝐶𝑀𝑀
𝑔𝑔 𝑔𝑔
and 𝑅𝑅𝑀𝑀 in the OpAmp circuit. For that, insert all your calculations as well as your 𝑔𝑔 𝑚𝑚 -, 𝐼𝐼𝑚𝑚 -plots you used
𝑑𝑑𝑑𝑑 𝐷𝐷
for your handcalculations below:
Hints:
𝑔𝑔𝑚𝑚 𝑔𝑔𝑚𝑚
• First, plot and across 𝑉𝑉𝑂𝑂𝑂𝑂 and gatelength L and do it again across 𝑉𝑉𝐺𝐺𝐺𝐺 , as presented in the
𝑔𝑔𝑑𝑑𝑑𝑑 𝐼𝐼𝐷𝐷
1 session. Think about whether to create the plots for a PMOS or for a NMOS device.
st

• Then, based on those plots, start your calculations.

• Furthermore, you can assume the following:
(1) the OpAmp is designed in triple-well-technology (i.e. 𝑉𝑉𝑆𝑆𝑆𝑆 = 0); (2) 𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 ≈ 𝑉𝑉𝑂𝑂𝑂𝑂 and 𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 ≥
1
50𝑚𝑚𝑚𝑚 across 𝑉𝑉𝑂𝑂𝑂𝑂 ; (3) 𝐶𝐶𝑀𝑀 = ⋅ 𝐶𝐶𝐿𝐿
4
Remarks:
• For Mp5, Mp7 and Mp8 you are not required to calculate the 𝑔𝑔𝑚𝑚

Plots used for the handcalculations:

Graph For Input Transistor Mp2

𝑔𝑔
Figure 1: 𝑔𝑔 𝑚𝑚 vs 𝑉𝑉𝑂𝑂𝑂𝑂 across gatelength 𝐿𝐿
𝑑𝑑𝑑𝑑
 Graph For Input Transistor Mp2

𝑔𝑔
Figure 2: 𝑔𝑔 𝑚𝑚 vs 𝑉𝑉𝐺𝐺𝐺𝐺 across gatelength 𝐿𝐿
𝑑𝑑𝑑𝑑

Graph for Output Transistor Mn6

𝑔𝑔
Figure 3: 𝑔𝑔 𝑚𝑚 vs 𝑉𝑉𝑂𝑂𝑂𝑂 across gatelength 𝐿𝐿
𝑑𝑑𝑑𝑑
Graph for Output Transistor Mn6

𝑔𝑔𝑚𝑚
Figure 4: vs 𝑉𝑉𝐺𝐺𝐺𝐺 across gatelength 𝐿𝐿
𝑔𝑔𝑑𝑑𝑑𝑑

Graph For Input Transistor Mp2

𝑔𝑔𝑚𝑚
Figure 5: vs 𝑉𝑉𝑂𝑂𝑂𝑂 across gatelength 𝐿𝐿
𝐼𝐼𝐷𝐷
Graph For Input Transistor Mp2

𝑔𝑔𝑚𝑚
Figure 6: vs 𝑉𝑉𝐺𝐺𝐺𝐺 across gate length 𝐿𝐿
𝐼𝐼𝐷𝐷

gds of the transistor Mp2

Handcalculations:

gm plot = 0.27mS for L=200nm for the transistor Mp2

Using the graph: Finding the gain efficiency of Mn3 and Mn4 to find gm:
Using the graph: Gm plot for the transistors Mn3 and Mn4:

Gm plot for the transistor Mn6:

2) Place all the calculated voltages (in the blackbox) and all currents (in the red box) on the circuit
depicted below and calculate also:
𝑉𝑉𝑐𝑐𝑐𝑐,𝑖𝑖𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚 𝑉𝑉𝑖𝑖𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑉𝑉𝐺𝐺𝑆𝑆3 + 𝑉𝑉𝑇𝑇1 = 0.116𝑉𝑉

𝑉𝑉𝑐𝑐𝑐𝑐,𝑖𝑖𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚 𝑉𝑉𝑖𝑖𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑉𝑉𝑂𝑂𝑉𝑉7 + 𝑉𝑉𝐺𝐺𝑆𝑆1 + 𝑉𝑉𝐷𝐷𝐷𝐷 = 0.617 𝑉𝑉

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑉𝑉𝑂𝑂𝑉𝑉6 = 0.142 𝑉𝑉

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑉𝑉𝐷𝐷𝐷𝐷 − �𝑉𝑉𝑂𝑂𝑉𝑉5 � = 1.042𝑉𝑉

𝑃𝑃𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑃𝑃𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 = 𝑉𝑉𝐷𝐷𝐷𝐷 �𝐼𝐼𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 + 𝐼𝐼𝑀𝑀𝑝𝑝7 + 𝐼𝐼𝑀𝑀𝑝𝑝5 � = 0.4 𝑚𝑚𝑚𝑚

815.95mV

853.35mV 0.03mA 0.2mA

0.13mA
0.372V

199.62mV
0.2V
Design: Implementation of the OpAmp in MATLAB and LTspice (10 points):

3) Based on your handcalculations, create your OpAmp design in MATLAB. After completion, please insert
your final and entire MATLAB code after the appendix (i.e. at the end of this report-document).
Remark:
• Please make sure that all widths W are below 1mm

4) Fill out both tables depicted below. All values are to be determined in MATLAB.

Device sizes and bias point parameters according to MATLAB

W L Ids VOV gm gds gm/gds Vds,sat Vds

Device
[μm] [nm] [μA] [V] [S] [S] [-] [V] [V]

Mp1 0.997 200 16.11 -0.2 8.60e^- 14.6 -189.09 -400.00

1.2566e^- 6 e^-3 e^-3
4
Mp2 0.997 200 16.11 -0.2 8.60e^- 14.6 -189.09 -400.00
1.2566e^- 6 e^-3 e^-3
4
Mn3 0.512 200 16.11 0.2 1.753e^- 6.74 e^- 143.27 399.20
4 6 e^-3 e^-3
Mn4 0.512 200 16.11 0.2 1.753e^- 6.74 e^- 143.27 399.20
4 6 e^-3 e^-3
Mp5 463.01 500 186.50 0 74.63 -58.48 -550.00
e^-6 e^-3 e^-3
Mn6 5.60 200 186.50 0.2 2e^-3 61.36 32.59 142.36 550.00
e^-6 e^-3 e^-3
Mp7 89.99 500 32.23 0 19.42 -59.38 -300.80
e^-6 e^-3 e^-3
Mp8 375.17 500 128.91 0 98.29 -59.59 -239.12
e^-6 e^-3 e^-3

Device Units Value

CM pF 1

RM Ω 2486.8

IBIAS A 0.13e^-3

5) Based on the parameters filled in the table above, design your OpAmp in LTspice. After completion,
please insert your final and entire LTspice-netlist after the appendix (i.e. at the end of this report-
document).
Experiment (10 points):

In this section you will simulate the following:

A. Frequency Response in MATLAB and LTspice

B. Noise contribution in LTspice
C. Linearity in LTspice

Note on how to present graphs in general:

• When you make a graph, put labels on every axis to make clear what you are showing. Also, show the units!
• When you plot multiple curves on one graph, add a legend.
A. Frequency Response in MATLAB and LTspice

Note on how to present graphs in this sub-section:

• For magnitude plots use dB (linear scale) vs. Hz (logarithmic scale)
• for phase plots use ° (linear scale) vs. Hz (logarithmic scale).
6) Simulate 𝐴𝐴𝑣𝑣 (small voltage gain) with 𝐶𝐶𝑀𝑀 and 𝑅𝑅𝑀𝑀 in MATLAB and LTspice. Then, paste both 𝐴𝐴𝑣𝑣 -curves in
seperate plots below such that the difference between MATLAB and LTspice can be clearly seen. In
addition to that, indicate the resulting phase margin (PM) in both plots.

Plots:

Using the frequency response plot of the MATLAB simulation: For 0 (dB) of magnitude, the phase margin
is 89.6 (deg)

LTSPICE Plot:

The Y left axis represents the magnitude in (dB)

The X-axis represents the frequency in (Hz)
The Y right axis represents the phase in (deg)
Pdom=165KHz using MATLAB

Pdom=158KHz using LTSPICE

Simulator PM (deg)

MATLAB 89.6

LTspice 90.1

7) Explain, analyse and interpret the results in “6)”. Furthermore, if you observe significant differences
between MATLAB and LTspice, explain why.

The results of the MATLAB simulation: We placed the zero in the right half plane at the non-dominant pole
frequency to compensate for the non-dominant pole and achieve this phase margin. This resulted in two
poles and one negative zero remaining. We can see that the phase never reaches -180° in the MATLAB
bode diagram. This is so that the zero at the double of the pole frequency can offset the effects of the
second pole.
The results of the LTSPICE simulation: At high frequencies, the phase keeps decreasing. This is due to two
factors: First, in LTSPICE, the non-dominant pole is not perfectly compensated. This indicates that the
system is still only slightly influenced by the non-dominant pole. Second, the Miller compensation
capacitor's impedance decreases at high frequencies, resulting in the resistor being in parallel with the
output resistances of the first and second stage. So, the gain of the operational amplifier is reduced by the
additional conductance.

The phase margin has a different value between MATLAB (89.6 deg) and LTSPICE (90.1 deg), and this
difference appears since the frequency of the dominant pole in LTSPICE simulation is lower than the
frequency of the dominant pole in MATLAB, and this difference is frequency leads to increases the phase
margin in LTSPICE more than that one in MATLAB.

8) Simulate 𝐴𝐴𝑣𝑣 in LTspice for the following cases:

a. No compensation network (𝐶𝐶𝑀𝑀 = 𝑅𝑅𝑀𝑀 = 0).
b. With compensation capacitor but no compensation resistor (𝑅𝑅𝑀𝑀 = 0).
c. With both the compensation capacitor and the compensation resistor.
Then, show all 3 cases in seperate plots such that the differences are clearly visible. Furthermore,
indicate on each plot the resulting PM.

Plot:

a. No compensation network (𝐶𝐶𝑀𝑀 = 𝑅𝑅𝑀𝑀 = 0)

b. With compensation capacitor but no compensation resistor (𝑅𝑅𝑀𝑀 = 0)

c. With both the compensation capacitor and the compensation resistor

The Y left axis represents the magnitude in (dB)
The X-axis represents the frequency in (Hz)
The Y right axis represents the phase in (deg)

Case PM [deg]

No compensation network 9.38

No compensation resistor 71.95

With both the compensation 90.1

9) Explain, analyse and interpret the results in “8)”.

a. No compensation network (𝐶𝐶𝑀𝑀 = 𝑅𝑅𝑀𝑀 = 0)

The dominant pole and the non-dominant pole are located at a high frequency when there is no
compensation at all. Due to the low phase margin of 9.38°, this results in a high (175 MHz) unity gain
frequency at the expense of the phase margin.

b. With compensation capacitor but no compensation resistor (𝑅𝑅𝑀𝑀 = 0)

The presence of the compensation capacitor causes pole splitting between the dominant and non-
dominant poles. As a result, the dominant pole will shift to lower frequencies, while the non-dominant pole
will shift to higher frequencies. As a result, the unity gain frequency decreases to 42 MHz, but the phase
margin increases to 71.95°.

c. With both the compensation capacitor and the compensation resistor

The added compensation resistor allows us to move the positive zero to the left half plane. In our case, the
non-dominant pole was compensated using the positive zero. The phase margin consequently increased
significantly because of this. Up until very high frequencies, the phase stays at -90°. The non-dominant
pole's absence also causes a slight increase in the unity gain frequency.
B. Noise contribution in LTspice

10) Simulate the output-referred noise voltage power density 𝑑𝑑𝑣𝑣 �����������
2
𝑜𝑜𝑜𝑜𝑜𝑜,𝑒𝑒𝑒𝑒 �∆𝑓𝑓 over an appropriate frequency
�����������
range in LTspice. Then, insert the 𝑑𝑑𝑣𝑣 2
�∆𝑓𝑓-plot below.
𝑜𝑜𝑜𝑜𝑜𝑜,𝑒𝑒𝑒𝑒

Plots:

The Y left axis represents the magnitude in (dB)

The X-axis represents the frequency in (Hz)
The Y right axis represents the phase in (deg)

11) Explain, analyse and interpret the results in “10)”.

At low frequencies we see an exponential decrease in the output noise power spectral density. This
characteristic to the flicker noise (1/f noise) which is dominant at low frequencies. When the flicker noise
becomes negligible, the noise contribution is dominated by the white noise.

12) Simulate the input-referred noise spectral density by using the .NOISE option in LTspice. Also, by using
LTspice, determine the total output integrated noise of the OpAmp. For that, take the integration
bandwidth from 10 kHz to 10 ⋅ 𝑓𝑓𝐺𝐺𝐺𝐺𝐺𝐺 . Furthermore, copy and paste the top 9 contributing elements
using "View->SPICE Error Log" option and insert that list below.
The Y left axis represents the magnitude in (dB)
The X-axis represents the frequency in (Hz)
The Y right axis represents the phase in (deg)

The spice error log from LTSPICE:

13) Explain, analyse and interpret the results in “12)”.

We first notice a region at low frequencies where the flicker noise predominates when we analyze the
input referred rms noise. Then a region of constant noise appears, which is known as white noise.
Additionally, noise increases at very high frequencies because of the additional contribution and the
decrease in gain.
The total output integrated rms noise of the OTA is 0.00469 Vrms. The biggest contributors to the total
output noise are Mp1, Mp2, Mp3, and Mp4 which is to be expected since the noise generated at the input
is then amplified by the gain of the OTA. Normally one would expect the input transistors Mp1 and Mp2 to
generate the most noise since in the output noise, the noise coming from these transistors is multiplied by
the gain, and the contribution of the output noise of the transistors Mn3 and Mn4 is smaller than the total
voltage gain and smaller than the contributions of Mn1 and Mn2, because the flicker noise is inversely
proportional to the area of the transistor, Mp1 and Mp2 generate less noise than Mn3 and Mn4, where the
width of transistors Mn1 and Mn2 is bigger than the width of transistors Mn3 and Mn4.
The noise generated by Mp5 and Mn6 only undergoes the amplification of the second stage, which makes
its contribution to the total output noise significantly smaller than the previous transistors. The noise
contribution of Mp7 is also small since it is split equally over the two branches of the OTA and generates
therefore a common mode disturbance which is rejected by the common mode rejection of the OTA.
Transistor Mp8 generates noise which has an impact on Mp7 and Mp5, but since both transistors have a
small noise contribution the same will hold true for Mp8.
C. Linearity in LTspice

14) Simulate the output voltage amplitude and voltage gain as a function of the input voltage amplitude in
LTspice. Then, insert the plots below and indicate the 1-dB compression point.

Plots:

The output voltage amplitude and voltage gain as a function of the input voltage amplitude:
Vout for input Vin 13: Vout=-19.52dBVrms

Vout table for PSS:

Gain (dB) x Vin (V) in a semi-log scale: Gain Curve

Vout (V) x Vin (V) in a log-log scale: Compression Curve

15) Explain, analyse and interpret the results in “14)”.

In the figure of "final_project_pss", for an input 13, the amplitude is 0.01V,so the output at 10Khz of input
frequency is calculated as follow:
Vin=0.01V
Vin = 20 × log10(0.01/√2) = -43dBVrms
Vout = -19.52dBVrms
Gain = -19.52-(-100) = 80.48dBV
The same calculations for the rest Vin.

We analyzed the linearity of the amplifier for input signals with varying amplitudes by measuring the
amplitude of the fundamental tone in the output signal. Prior to the compression point, a linear
relationship between the output and input voltage can be observed. This is because in this range, the first-
order linear coefficient K1 has the most significant impact on the output of the fundamental tone.
However, the overall contribution to the fundamental tone can be represented by:

3
𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐾𝐾1 𝐴𝐴1 + 𝐾𝐾 𝐴𝐴3
4 3 1

As the input amplitude is increased, the output will surpass the maximum permissible output voltage range,
causing the transistors in the second stage to enter the triode region. Further increases in input will result
in the clipping of the output signal, preventing further amplitude increases and reaching saturation of the
output voltage. Additionally, as the compression point is approached, the gain begins to decrease.
 Conclusion (10 points):

16) Conclude your experiment by filling the editable fields in the performance table depicted below

from
Metric Units Specification hand- MATLAB LTspice
calculations

DC gain magnitude 223.87 233.88 121.15 116.14

DC gain dB 47 47.38 41.6663 41.3

Gain-Bandwidth frequency MHz 20 20 20 20

𝑓𝑓𝐺𝐺𝐺𝐺𝐺𝐺

Dominant pole frequency kHz 425.53 423 165 158

𝑓𝑓𝑑𝑑𝑑𝑑𝑑𝑑

PM ° > 70 91.21 89.6 90.1

𝑉𝑉𝑖𝑖𝑖𝑖,𝑐𝑐𝑐𝑐,𝑚𝑚𝑚𝑚𝑚𝑚 − 𝑉𝑉𝑖𝑖𝑖𝑖,𝑐𝑐𝑐𝑐,𝑚𝑚𝑚𝑚𝑚𝑚 V 0.501 0.501 0.46

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 V > 0.7 0.9 0.9 0.856

𝑃𝑃𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 mW 0.4 0.4 0.4

���������
2
𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜,𝑒𝑒𝑒𝑒 (output-referred noise) Vrms 0.00469

17) Comment about the deviations between hand calculation, MATLAB and LTspice values found above.
Conclude, what the causes of such deviations are.

There are deviations between the hand calculation and the MATLAB and LTSPICE simulation in the DC gain,
Gain Band Width frequency, and the dominant pole frequency.
For the DC gain, the values of the specifications and the hand calculation are almost the same (around
47dB) bigger than the values of the MATLAB and LTSPICE that are also around 41dB since the models are
not identical so some little difference in the parameters may occurs this issue especially the difference is
not very big.
For the frequency of the dominant pole 𝑓𝑓𝑑𝑑𝑑𝑑𝑑𝑑 , which is equal to GBW divided by the DC gain, the values of
the specifications and hand calculation are almost the same (around 423KHz), and the same for the values
of the MATLAB and LTSPICE simulation which are almost the same (around 160KHz), and this difference
between the 2 values is because the difference of the DC gain band width that is divided by a big GBW
frequency value that may occurs this gap.
Some possible causes of this deviation include also: The hand calculations or simulation may use incorrect
values for key system parameters, leading to large errors in the results. Or The MATLAB simulation may be
configured improperly, resulting in inaccurate results. Maybe also Some effects that should be considered
may be neglected in the hand calculations or simulation.

18) If you have results which are not passing the specifications: conclude for each of those result what the
cause is and what you need to do in order to make it pass, if you were repeating this experiment.

As a final result of all the calculation, we meet all the requirements and specifications in the hand
calculation where all the width are less than 1mm, and the values are logic.
Also, in the MATLAB simulation an LTSPICE, all the specifications are respected in the result and we get a
values near from the specifications in the most cases except the differences in the values that are discussed
in the previous question.
By repeating this experiment, we need to redo the calculation again and see if we change the inversion
level for some transistors what will happens to the gap if it can be eliminated.
Appendix:

Insert your MATLAB code here:

%% Analog Electronics final project

clc;

%close all;

clear;

addpath(genpath('circuitDesign'));

addpath(genpath('functions'));

addpath(genpath('models'));

load('UMC65_RVT.mat');

%% Initializations

designkitName = 'umc65';

circuitTitle = 'Analog Design - Project';

elementList.nmos = {'Mn3','Mn4','Mn6'};

elementList.pmos = {'Mp1','Mp2','Mp5','Mp7','Mp8'};

choice.maxFingerWidth = 10e-6;

choice.minFingerWidth = 200e-9;

simulator = 'spectre';

simulFile = 0;

simulSkelFile = 0;
spec = [];

analog = cirInit('analog',circuitTitle,'top',elementList,spec,choice,...

designkitName,NRVT,PRVT,simulator,simulFile,simulSkelFile);

analog = cirCheckInChoice(analog, choice);

%% Project: circuit

disp(' ');

disp(' VDD VDD VDD ');

disp(' | | | ');

disp(' Mp8-+---------Mp7---------------------Mp5 ');

disp(' |--+ | | ');

disp(' | +--+--+ node 3-> +-----+---OUT ');

disp(' | | | | | ');

disp(' | IN1--Mp1 Mp2--IN2 | | ');

disp(' | | | | | ');

disp(' | node 1->| |<-node 2 | Cl ');

disp(' | |--+ +------+-Cm---Rm----+ | ');

disp(' Ibias Mn3-+-Mn4 | | | ');

disp(' | | | +-----------Mn6 | ');

disp(' | | | | | ');

disp(' GND GND GND GND GND ');

%% AI: Implement your OpAmp according to your handcalculations

%Our Specifications

spec.VDD = 1.1;
spec.fGBW= 20e6;

spec.GBW=spec.fGBW*(2*pi);

spec.Cl = 4e-12;

spec.Cm =spec.Cl/4;

spec.gain=47;

spec.swing=0.8; %we need an output swing >0.7

%% Mn6

Mn6.lg=200e-9;

Mn6.vov=0.2; %approx, working in Strong Inversion

Mn6.gm=4*spec.fGBW*(2*pi)*spec.Cl; %formula to cacl gm6

Mn6.vds=0.55; %VDD/2

Mn6.vsb=0;

Mn6.vth= tableValueWref('vth',NRVT,Mn6.lg,0,Mn6.vds,Mn6.vsb); %fixed

Mn6.vgs=Mn6.vov + Mn6.vth; %formula

Mn6.w= mosWidth('gm',Mn6.gm,Mn6);

Mn6.ids=(Mn6.gm*Mn6.vov)/2; %formula

Mn6 = mosNfingers(Mn6);

Mn6 = mosOpValues(Mn6);

%% Mp2

Mp2.lg=200e-9; %approx

Mp2.vov=-0.2; %weak inversion

Mp2.vds=-0.4;%approx with condition that |Vds|>|Vov|

Mp2.vsb=0; %always

Mp2.vth= tableValueWref('vth',PRVT,Mp2.lg,0,Mp2.vds,Mp2.vsb);

Mp2.vgs=Mp2.vov + Mp2.vth; %formula

Mp2.gm=2*pi*spec.fGBW*spec.Cm; %formula

Mp2.w=mosWidth('gm',Mp2.gm,Mp2);

Mp2.ids=(Mp2.gm*Mp2.vov)/2; %formula

Mp2 = mosNfingers(Mp2);

Mp2 = mosOpValues(Mp2);

%% Mp1

Mp1= cirElementCopy(Mp2, Mp1); %same as Mp2 (diff pair)

%gmp1=1.26*10^-4S

%% Mn4

Mn4.lg=200e-9; %approx

Mn4.vov=0.0;%approx moderte inversion

Mn4.vds=Mn6.vgs;

Mn4.vsb=0;

Mn4.vth= tableValueWref('vth',NRVT,Mn4.lg,0,Mn4.vds,Mn4.vsb);

Mn4.vgs=Mn4.vds; %it has the same vgs as Mn3, where Vgs=Vds because Mn3 is diode connected

Mn4.ids=Mp2.ids; %same current in Mn4, Mp2, Mp1

Mn4.w=mosWidth('ids',Mn4.ids,Mn4);
Mn4 = mosNfingers(Mn4);

Mn4 = mosOpValues(Mn4);

%% Mn3

Mn3= cirElementCopy(Mn4, Mn3); %current mirror

%% Drain voltage Mp7

Vd= Mn4.vds-Mp2.vds; %%

%% Mp7

%%

Mp7.lg=500e-9; % Long channel -> Better current source

Mp7.vov=-0.0; % mderate inversion

Mp7.vds= -(spec.VDD-Vd);

Mp7.vsb=0;

Mp7.vth=tableValueWref('vth',PRVT,Mp7.lg,0,Mp7.vds,Mp7.vsb);

Mp7.vgs=Mp7.vov + Mp7.vth;

Mp7.ids=2*Mp2.ids;

Mp7.w= mosWidth('ids',Mp7.ids,Mp7);

Mp7 = mosNfingers(Mp7);

Mp7 = mosOpValues(Mp7);

%% Mp8

Mp8.lg=500e-9; % Long channel

Mp8.vov=-0.2; % Strong inversion

Mp8.vsb=0;

Mp8.vgs=Mp7.vgs;

Mp8.vds=Mp8.vgs;

Mp8.vth= tableValueWref('vth',PRVT,Mp8.lg,0,Mp8.vds,Mp8.vsb);

Mp8.ids=4*Mp7.ids; %4 times more than in Mp7

Mp8.w= mosWidth('ids',Mp8.ids,Mp8);

Mp8 = mosNfingers(Mp8);

Mp8 = mosOpValues(Mp8);

%% Mp5

Mp5.lg=500e-9;

Mp5.vov=-0.0; %w

Mp5.vds=-(spec.VDD-Mn6.vds);

Mp5.vsb=0;

Mp5.vth= tableValueWref('vth',PRVT,Mp5.lg,0,Mp5.vds,Mp5.vsb);

Mp5.vgs=Mp7.vgs; %current mirrors

Mp5.ids=Mn6.ids; %connected in series

Mp5.w= mosWidth('ids',Mp5.ids,Mp5);
Mp5 = mosNfingers(Mp5);

Mp5 = mosOpValues(Mp5);

%% AI: Fill out the empty variables required to plot the transfer-function.

% meaning of each variable see comment and

% location of nodes see line 31

AvDC1 = -Mp1.gm/(Mp2.gds+Mn4.gds); % DC gain 1st stage

AvDC2 = -Mn6.gm/(Mp5.gds+Mn6.gds); % DC gain 2nd stage

C1 =(Mp1.cdb+Mp1.cgd+2*Mn3.cgs+2*Mn3.cgb+Mn3.cgd); % Capacitance on node 1

G1 =(Mn3.gm+Mn3.gds+Mp1.gds); % Admittance on node 1

C2 =(spec.Cm*Mn6.gm/(Mn6.gds+Mp5.gds)); % Capacitance on node 2 %Miller cap will mult the gain of

second stage

G2 =(Mp2.gds+Mn4.gds); % Admittance on node 2

C3 =spec.Cl; % Capacitance on node 3

G3 =Mn6.gm ; % Admittance on node 3

gainn=AvDC1*AvDC2;

%% AI: Set-up Rm, Cc and CL and calculate the zero required for the transfer-fct

%spec.Cm = spec.CL/4;

%spec.Cl = 4e-12;

spec.Rm = 1/(abs(G3/C3)*spec.Cm) + 1/Mn6.gm;

%spec.Rm = 0;

z1 = 1/((1/Mn6.gm - spec.Rm)*(spec.Cm));
%% AI: Fill out the empty variables required for the performance summary

Vin_cm_min = Mn3.vov+Mn3.vth+Mp1.vth;

Vin_cm_max = spec.VDD-abs(Mp1.vgs)-abs(Mp7.vov);

Vout_cm_min = Mn6.vdsat;

Vout_cm_max = spec.VDD-abs(Mp5.vdsat);

Pdiss = spec.VDD * (Mp8.ids + Mp7.ids + Mp5.ids);

p1 = G1/C1;

p2 = G2/C2;

p3 = G3/C3;

z2 = 2*p1;

if abs(p2)<abs(p3)

fGBW = gainn*p2/(2*pi);

else

fGBW = gainn*p3/(2*pi);

end

%% Sanity check (do not modify)

disp('======================================');

disp('= Transistors in saturation =');

disp('======================================');

if mosCheckSaturation(Mp1)

fprintf('\nMp1:Success\n')

end

if mosCheckSaturation(Mp2)

fprintf('Mp2:Success\n')

end

if mosCheckSaturation(Mn3)

fprintf('Mn3:Success\n')

end

if mosCheckSaturation(Mn4)

fprintf('Mn4:Success\n')

end

if mosCheckSaturation(Mp5)

fprintf('Mp5:Success\n')

end

if mosCheckSaturation(Mn6)

fprintf('Mn6:Success\n')

end

if mosCheckSaturation(Mp7)

fprintf('Mp7:Success\n')

end

if mosCheckSaturation(Mp8)

fprintf('Mp8:Success\n\n')

end
%% Summary of sizes and biasing points (do not modify)

disp('======================================');

disp('= Sizes and operating points =');

disp('======================================');

analog = cirElementsCheckOut(analog); % Update circuit file with

% transistor sizes

mosPrintSizesAndOpInfo(1,analog); % Print the sizes of the

% transistors in the circuit file

fprintf('IBIAS\t= %6.2fmA\nRc\t= %6.2f Ohm\nCm\t= %6.2fpF\n\n',Mp8.ids/1e-3,spec.Rm,spec.Cm/1e-12);

%% Performance summary (do not modify)

disp('======================================');

disp('= Performance =');

disp('======================================');

fprintf('\nmetrik \t result\n');

fprintf('Vin,cm,min [mV] \t%.0f\n',Vin_cm_min/1e-3);

fprintf('Vin,cm,max [mV] \t%.0f\n',Vin_cm_max/1e-3);

fprintf('Vout,cm,min [mV] \t%.0f\n',Vout_cm_min/1e-3);

fprintf('Vout,cm,max [mV] \t%.0f\n',Vout_cm_max/1e-3);

fprintf('Vout,cm,max [mV] \t%.0f\n',Vout_cm_max/1e-3);

fprintf('GBW: \t %d MHz \t %d MHz\n',...

spec.fGBW/1e6,round(fGBW/1e6));
fprintf('Pdiss [mW] \t%.1f\n',Pdiss/1e-3);

fprintf('gain dB: \t %d dB \t\t %g dB\n',...

spec.gain,20*log10(gainn));

%% Ploting transfer function (do not modify)

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

% if control toolbox in Matlab is available

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

s = tf('s');

% transfer function

TF1 = AvDC1*AvDC2*((1+s*C1/(2*G1))*(1-s*(1/z1)))/ ...

((1+s*C1/G1)*(1+s*C2/G2)*(1+s*C3/G3));

freq = logspace(1,12,1e3);

figure(1)

hax=axes;

bode(TF1,2*pi*freq); grid on;

xline(abs(G1/C1)./(2*pi),'--r','p1','LabelVerticalAlignment','bottom')

xline(abs(G2/C2)./(2*pi),'--b','pd','LabelVerticalAlignment','bottom')

xline(abs(G3/C3)./(2*pi),'--k','p3')

xline(abs(z2)./(2*pi),'--m','z2','LabelVerticalAlignment','bottom')

xline(abs(z1)./(2*pi),'--g','z1','LabelVerticalAlignment','bottom')

legend('Bode','p1', 'pd', 'p3','z2', 'z1')

h = gcr;

setoptions(h,'FreqUnits','Hz');
title('Frequency response Opamp');

hold all

Insert your LTspice netlist here:

vdd N001 0 1.1

vcm N006 0 0.6

E1 vinn N006 N006 vinp 1

V1 vinp N006 SINE(0 {amp} 10k) AC 10m

Mp8 N002 N002 N001 N001 p_11_sprvt l=500n w=128.9u

Mp7 N003 N002 N001 N001 p_11_sprvt l=500n w=32.2u

Mp1 N005 vinn N003 N003 p_11_sprvt l=200n w=16.11u

Mp2 vinter vinp N003 N003 p_11_sprvt l=200n w=16.11u

Mn4 vinter N005 0 0 n_11_sprvt l=200n w=16.11u

Mn3 N005 N005 0 0 n_11_sprvt l=200n w=16.11u

Mn6 vout vinter 0 0 n_11_sprvt l=200n w=186.5u

Mp5 vout N002 N001 N001 p_11_sprvt l=500n w=186.5u

Rm vout N004 2486.8

Cm N004 vinter 1p

Ibias N002 0 0.13m

Cload vout 0 4p

.model NMOS NMOS

.model PMOS PMOS

.lib C:\Users\lenovo\Documents\LTspiceXVII\lib\cmp\standard.mos

.include BSIM4_UMC65.lib
.op

.tran 10m

.step dec param amp 1u 100m 3

.param amp=1n

.backanno

.end