Q No L Question A B C D E Answer

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1. Which table shows the logical Function table Truth table Routing table ASCII table B
state of a digital circuit output
for every possible
combination of logical states
in the inputs
2. Which one of the following 1⊕0=1 1⊕1⊕0=1 1⊕1⊕1=1 1⊕1=0 B
logic expression is incorrect?

3. Don't cares in a map are X Y Z W A

distinguished from 0's and 1's
by

4. A(A + B) = ? AB 1 (1 + AB) A D

5. Sum – of-Products 2-level OR- AND 2-level AND- 2-level XOR logic Both 2-level OR- B
expressions can be logic circuits OR logic circuits AND and NOR logic
implemented using circuits circuits

6. (A + B)(A’ * B’) = ? 1 0 AB AB' B

7. Complement of the (A’ + B)(C’ + D) (A + B’)(C’ + (A’ + B)(C’ + D) (A + B’)(C + D’) B

expression A’B + CD’ is __ D)
8. Simplify Y = AB’ + (A’ + AB’ + C AB + AC A’B + AC’ AB + A A
B)C.

9. The boolean function A + BC AB + BC (A + B)(A + C) A’B + AB’C (A + C)B

is a reduced form of B

10. Which of the following Corners in the same Corners in the Diagonal corners Overlapping C
combinations cannot be row same column combinations
combined into K-map groups?

11. The expression EX-OR SOP POS NOR B

Y=AB+BC+AC shows the
_________ operation.

12. The number of full and half- 8 half-adders, 8 1 half-adder, 15 16 half-adders, 0 4 half-adders, 12 full- B
adders required to add 16-bit full-adders full-adders adders
numbers is----- full-adders

13. A product term containing all Minterm MAXTERM Midterm ∑ term A

K variables of the function in
either complemented or
uncomplemented form is
called a ----------
14. The canonical sum of product AB + BB + A’A AB + AB’ + BA + BA’ + A’B’ AB’ + A’B + A’B’ B
form of the function y(A,B) = A’B
A + B is __

15. A variable on its own or in its Product Term Literal Sum Term Word B
complemented form is known
as a __
16. Canonical form is a unique SOP Minterm Boolean Expressions POS C
way of representing _____

17. There are _____________ 0 2 8 1 C

Minterms for 3 variables (a, b,
c).

18. ____ expressions can be POS LITERALS SOP NONE C

implemented using either (1)
2-level AND-OR logic
circuits or (2) 2-level NAND
logic circuits.
19. A Karnaugh map (K-map) is Venn Diagram Cycle Diagram Block diagram Triangular Diagram A
an abstract form of
____________ diagram
organized as a matrix of
squares.

20. There are ______ cells in a 4- 12 16 18 8 B

variable K-map.

21. The K-map based Boolean Impact Non Impact Force Complementarity
reduction is based on the B
following Unifying Theorem:
A + A’ = 1.
22. The prime implicant which Essential Prime Implicant Complemen Prime Complement A
has at least one element that is Implican
not present in any other
implicant is known as ____
23. Product-of-Sums expressions 2-level OR-AND 2-level OR- 2-level XOR logic BOTH A&B D
can be implemented using ___ logic circuits AND logic circuits
circuits

24. Don’t care conditions can be Registers Terms K-maps Latches C

used for simplifying Boolean
expressions in __

25. Derive the Boolean A

expression for the logic circuit
shown below:

26. Applying DeMorgan's A

theorem to the
expression , we get ___
27. An AND gate with schematic NOT OR NOR NAND C
"bubbles" on its inputs
performs the same function as
a(n)________ gate.
28. A truth table for the SOP 2 3 4 8 D
expression
has how
many input combinations
29. How many gates would be 1 2 4 5 D
required to implement the
following Boolean expression
before simplification?
XY + X(X + Z) + Y(X + Z)
30. Simplify Y=AB'+(A'+B)C AB'+C AB+AC A'B+AC' AB+A A

31 0-0-1 is equal to Difference = 1 Difference = 1 Difference = 0 Difference = 0 B

Borrow =0 Borrow =1 Borrow =0 Borrow =1

32 The code where successive Alphanumeric code D

bits are differ by single bit is BCD Excess 3 Gray

33 C
x + xy = 0 1 x x’

34 A
Other name of NOT gate Inverter equalizer OR d) AND

35 C
(x')' is equal to 0 1 x x’

36 Adders adds 2 bits is called so needs two input and All of these D
because a full generates two output
adder involves
two half-adders
37 A combinational circuit is Input combination input input combination at present output and the A
one in which the output at the time combination that time and the previous output
depends on the and the previous previous input
output combination
38 Parallel adders are combinational logic sequential logic both (a) and (b) None of these A
circuits circuits

39 A full adder circuit can be 2 4 1 3 A

designed with the help of how
many half adders

40 The binary subtraction of 0 – Difference = 0, Difference = 1, Difference = 1, A

Difference =
0=? borrow = 0 borrow = 0 borrow = 1 0,
borrow = 1