EE2026

Digital Design
MODULE INTRODUCTION
Chua Dingjuan elechuad@nus.edu.sg

Slides credit to Prof Massimo Alioto and Prof YP Xu

Course Description
First course on digital systems
oIntroduces fundamental digital logic, digital circuits, and
programmable devices
oThe course also provides an overview of computer systems
oThis course provides students with an understanding of the
building blocks of modern digital systems and methods of
designing, simulating and realizing such systems
oThe emphasis of this module is on understanding the
fundamentals of digital design across different levels of
abstraction using Hardware Description Languages
oDeveloping valuable design skills for the design of digital
systems through FPGAs and state-of-the-art CAD tools, as
required by the job market (exciting projects)
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Module Team
Lecturer : Dr. Chua Dingjuan
Lab Instructors :
Mr. Christopher Moy (B01, B03)
Dr. Goh Shu Ting (B02)
Tutors :
Dr. Chua Dingjuan, Mr. Christopher Moy, Dr. Goh Shu
Ting, Mr. Yu Juezhao
Lab Officers:
Mr. Ho Fook Mun, Ms. Chia Meow Hwa and Mdm. Goh
Kah Seok

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Module Lecture Structure
Contents
Part 1 (Combinational Logic)
◦ Number systems + Verilog
◦ Boolean Algebra and logic gates + Verilog
◦ Gate-level design and minimization + Verilog
◦ Combinational logic blocks and design + Verilog

Part 2 (Sequential Logic)

◦ Basic Sequential Logic Blocks - Flip-flops + Verilog
◦ Counters + Verilog
◦ Combining combinational/sequential building blocks + Verilog
◦ Finite State Machines + Verilog

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Module Organization (Refer Canvas)
Week Lab Lecture Tutorial

WK 1 ✓

WK 2 (CDE Day, no classes on WED PM) ✓ Tutorial – 1

WK 3 Lab 1 ✓ Tutorial – 2

WK 4 Lab 2 ✓ Tutorial – 3

✓
Lab 3 No Lecture on
WK 5 Tutorial – 4
(Wed AM and Wed PM) Monday due to
LNY PH
Lab 3 ✓
WK 6
(Mon AM) Mid-Term Quiz

Recess Week

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Module Organization (Refer Canvas)
Week Lab Lecture Tutorial

WK 7 Project 1 ✓ Tutorial – 5

✓
WK 8 Project 2 Tutorial – 6

WK 9 Project 3 ✓ Tutorial – 7

WK 10 Verilog Evaluation ✓ Tutorial – 8

WK 11 Tutorial – 9

Project 4 - Assessment and

WK 12
Demo

WK 13 Final Quiz

No final exam ☺
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Module Assessment
Component Assessment Weight
Quizzes Total 40%
o Mid-Term Quiz 20%
o Part 2 Weekly Canvas Quizzes 5%
o Part 2 Final Quiz 15%
Labs Total 30%
o Lab Assignment 1 3%
o Lab Assignment 2 6%
o Lab Assignment 3 10%
o Verilog Evaluation 11%
Design Project – Team Work Total 30%
o Project basic features (specified) 30%
o Enhanced features (open-ended)

No final exam ☺
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Expected Learning Outcomes
Expected learning outcome (Part 1)
◦ Be able to perform conversion between binary, octal, hexadecimal
and decimal number systems, and solve simple problems;
◦ Understand Boolean Algebra, and manipulate and simplify Boolean
functions using theorems and postulates;
◦ Be able to design simple combinational logic circuits based on Truth
table and Karnaugh Map
◦ Be able to design complex combinational logic circuits using Hardware
Description Languages (Verilog) and/or combinational building blocks
◦ Be able to simulate complex combinational blocks and verify their
proper functionality through behavioural simulation
◦ Be able to design combinational logic circuits for practical problems /
applications

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Expected Learning Outcomes
Expected learning outcome (Part-2)
◦ Be able to describe simple sequential logic circuits based on functional
descriptions
◦ Be able to describe simple sequential logic circuits based on state
transition diagrams
◦ Be able to design complex logic circuits using Hardware Description
Languages (Verilog) and/or sequential/combinational building
blocks/IPs
◦ Be able to simulate complex blocks and verify their proper
functionality through behavioural simulation
◦ Be able to design complex logic circuits for practical problems /
applications

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LAB / PROJECT REMINDER
o EE2026 is a hands-on module →
significant lab and project time / components
o Software : Xilinx Vivado 2018.2
o Unfortunately, this software is not supported on Mac
operating systems (only windows / linux)
o Referring to installation instructions provided on Canvas,
please install the software by end of Week 2
o If you have difficulties accessing a windows-based system,
please check in with us.

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Module information
Course materials
◦ Canvas (everything about the course)

Need Help?
◦ Tutors (tutorial questions)
◦ TAs and GAs (labs and projects)
◦ During lab sessions
◦ Face-to-face consultation with lecturer:
◦ by appointment

Reference book (download from NUS library)

◦ D. Harris, S. Harris, Digital Design and Computer Architecture
(1st ed.), Morgan Kaufmann, 2007

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Why study this module?
The module is about the fundamentals of digital systems,
which is important if you are interested in the design of
digital circuits and systems, especially if you plan to
specialize in the following areas:
◦ Integrated circuit design (very important)
◦ Digital integrated circuits (very important)
◦ Embedded systems and Computer Architecture (very important)
It’s the first module about Hardware Description Language
(HDL), which is widely used for digital system design and
modeling
You will also learn analytical and problem solving skills
through the projects (practical design problems)
It also serves as prerequisite for other modules at senior
levels.

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EE2026:
Not Just Another Module…
Think & do: strong foundations, real-world design
◦ Industry-relevant project

– This year: machine learning and human-machine interfaces

handwritten input

text output (classification)

your design on FPGA board

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EE2026: Quite Unique…
Design skills in very high demand

◦ FPGA designer (startups, SMEs, MNCs)

◦ Semiconductor industry

AND SO ON AND SO FORTH…

◦ Not capital intensive: create YOUR OWN technology/company

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INTRODUCTION
 Analog vs. Digital Circuit
•Analog circuit deals with continuous signals
•Digital circuit deals with signals having discrete levels

V Analog signal V Digital signals

t t

➢Analog circuit is more susceptible to noise

➢Digital circuit is a binary system which is much more robust

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Why digital?
o Robustness (reliability)
o Programmability
o Scalability (in integrated circuit technology)
o Cost

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Technology Scaling
Transistors got smaller over time (at a relentless pace)

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1 0.8 m 0.5 m
0.35 m 0.25 m
0.18 m
0.1 0.13 m 90 nm
65 nm
45 nm
32 nm 22 nm
0.01 10 nm
7 nm
5 nm
3 nm
0.001
1970 1980 1990 2000 2010 2020 2030
year
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Technology Scaling (cont.)
1971:
• Intel 4-bit processor in 10 m PMOS process
with 2300 transistors
• Initial clock speed of 108 kHz
• 10m pMOS technology

2020:
• AMD Epyc Rome 7 nm processor (64 cores, 256MB
L3, Zen 2 arch.) 40B transistors
• IBM z15 5.2 GHz clock freq., 12 cores in 14 nm
FinFET, 9.2B transistors
• Intel Xeon Platinum 8180 in 14nm CMOS (28
cores), 3.6 GHz, 205 W, 8B transistors
• nVIDIA Ampere, 7nm FinFET, 5 PFLOPS, 54B
transistors
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Technology Scaling (cont.)
10000
millions of transistors/die

1000
100
10 Moore’s
1 law
0.1
0.01
0.001
1970 1980 1990 2000 2010 2020
year
As more and more transistors can be integrated on a single chip,
- functionality is increased
- for the same functionality: lower chip area, lower cost per transistor
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 Technology Scaling (cont.)
10000 100000
2.5-3.5 GHz

single-thread performance (MIPS)

clock frequency (MHz)

10000
1000
1000
100 100
107
10
10
104 1
1
0.1
0.1 0.01
1970 1980 1990 2000 2010 2020 1970 1980 1990 2000 2010 2020
year year

1000 20

# of microprocessor cores
power consumption (W)

100
power limited regime 15

10 10 <102
102
1 5

0.1 0
1970 1980 1990 2000 2010 2020 1970 1980 1990 2000 2010 2020
year year

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 Digital Revolution & Information Age
1947 – Invention of transistor
1971 – First microprocessor
*Rapid development of digital computing and communication technology
brought about the digital revolution and information age
1980s – Personal computers
1990s – World Wide Web, digital cameras
2000s – Mobile phones, digital TVs, ipod
2010 – Smart phones, xPad, cloud computing (accessible
everywhere), social networking (constantly connected)
2020 – Cloud computing, Internet of things, ultra-low
power high-performance mobile computing, ubiquitous
computing, immersive computing/augmented reality,
gesture recognition...

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 Example in Your Pocket (Today)
Application Processor (AP) Image sensor + pre-processing
(microprocessor cores, GPU, LTE modem
memory, video processing…)

Touchscreen
controller

Image sensor +
pre-processing

smart battery GPS, WiFi, DRAM, Flash, RF transceiver, Power

(charge, wearing, genuineness) Management, NFC, audio, display power management,
FPGA, battery charger, compass, other sensors 23
 Example Available Everywhere
(Tomorrow) from GREEN IC Group

energy
1.2 V
http://www.green-ic.org
0.3 V

tiny sensing platforms

Ultra-low Energy-
CORE voltage scalable
TECHNOLOGIES ckts/systems ckts/systems

CONNECTING data-driven HW-level

ckts/systems security
THE DOTS
emerging technologies
LEVERAGING NEW POSSIBILITIES
- MEMS, STT-MRAMs, TFETs, ...

computer vision in IoT most (cyber)secure AES in 100 nW 1st lunar-powered

for 1st time (55 W) “silicon fingerprint” (0.1mx0.1m solar cell) chip (power
1nW)
3.08mm

IMEM

bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
testing harness
clk. gen.
MCU core

3.08mm

bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
DMEM
ripple self-startup & headers

solar cell

sub-W machine 1st mm-scale CO2 sensor PRESS

1st book
learning (perpetual operation)
ADC
resolution
# of
features
on chip
MEMS TinyCO2 MEMS
E-Q SCALING
speech
heater Integrated System thermop
ile
design
feature speech
analog FFT classifier
activity?
...
for IoT
+

extractor recognition
Voice Activity Detector (VAD)
voice controlled device
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Heaters array Thermopiles array