EECE

578:     INTEGRATED CIRCUIT DESIGN-FOR-

TEST                       
Winter 2008
                        UBC Department of Electrical and Computer Engineering
  

Credits: 3

Session TU 14:00 – 17:00 FSC 1221

Times/Location:
 

Lab: MCLD 332 (SoC Lab.)

Web Page: www.ece.ubc.ca/~eece578

Instructor: Dr. André Ivanov

   

Office: Kaiser 4030

Tel: 604-822-6936

Email: ivanovATece.ubc.ca

Lab Dr. Roberto Rosales

Engineer:

   

Office: MCLD 332 (SoC Lab.)

   

Email: robertor@ece.ubc.ca

Prerequisites: EECE 479 or the equivalent. Students are expected to

have a basic knowledge of the design and fabrication of
  digital CMOS integrated circuits and preferably some
prior experience with CAD (e.g., Cadence, Synopsys)
  tools for IC design.
Additional Assumed  
Background:
Boolean algebra, combinational logic design, sequential
circuit design, electrical network theory, C and C++
language programming, elements of computer
architecture

Text: VLSI Test Principles and Architectures, L.-T. Wang, C.-W.

Wu, and X.Wen, Eds., Elsevier, 2006, ISBN-13: 978-12-
  370597-6, ISBN-10: 0-12-370597-5  
Ref: Essentials of Electronic Testing for Digital, Memory, &
Mixed-Signal VLSI Circuits M. L. Bushnell and V. D.
 Agrawal, Kluwer Academic Press, 2000, ISBN: 0-7923-
7991-8

Course Motivation and Description:

With ever increasing demands on quality and narrower windows of market opportunity, combined with the
deployment of very deep submicron technology, the cost of testing remains a major component of the
development and manufacturing cost of new ICs and SoCs. In view of the importance of testing and its limited
attention in traditional courses on IC design, this course emphasizes test and design for testability (DFT). With
ICs contains 100s of millions of transistors, testing is a major technical and economic bottleneck.    Testing
determines whether a manufactured VLSI or SoC contains any “broken” wires or transistors, or components
that are out of the tolerance range for a specification.  Design for testability is a must since testing has become
so difficult that circuits need to be explicitly synthesized to be testable, i.e. designed for testability. Testing must
now be considered in early stages and throughout the full design process.  Testing is also recently becoming
increasingly important for yield learning and system ramp-up and debug.

This course introduces the participants to the fundamentals of integrated circuit testing and design for
testability (DFT), and also addresses several recent developments in this rapidly changing field. Topics range
from basic test fundamentals like fault modeling, fault simulation, test generation, and DFT, to recent
developments in, for example, power supply current monitoring, scan design, boundary scan, and built-in self-
test (BIST). Students will have the opportunity to gain deeper understanding and experience in test algorithms,
methodologies and/or design for testability topics through a major course project. Emphasis will be placed on
the testing of digital circuits.  However, elements of analog circuit and MEMs testing will also be addressed
depending on student interest.

The level of the course is appropriate for a senior level undergraduate or graduate student with knowledge of
digital IC design.

Course Objectives:

In EECE 578, participants will gain further knowledge and skills related to VLSI/SoC test and design for
testability. Specifically, they will:

·         acquire
knowledge of basics and fundamentals of testing, i.e., become familiar with fault modeling,
simulation, test pattern generation, test economics

·         acquire knowledge of the basics of design for testability, in particular scan-design and built-in self-test

·         review
current practice, emerging techniques and methodologies, as well as trends in the field of IC test
engineering

·         explore
IC design and test issues, with particular emphasis on post-manufacturing testing problems and
solutions associated with integrated digital and digital/analog (mixed) systems (SoCs)

·         develop further knowledge and skills in modern design for testability techniques and CAD tools

·         apply newly learned techniques for designing fully testable circuits.

 Course Outline & Schedule:

Week  1 Session 1 ·         Administrative issues ·         Homework 1 posted

8 January
·         Introduction to Testing
 
·         Fault Models, ATPG

 
Week 2 Session 2 ·         Design for Testability (DFT) ·         Homework 1 due (end
15
·         Testability Analysis ·         Homework 2 posted
January

·         Scan Design  

 
Week  3 Session 3 ·         Logic Simulation ·         Homework 2 due (end
22 ·         Fault Simulation ·         Homework 3 posted
January
   

Week 4 Session 4 ·         Automatic Test Pattern Generation ·         Homework 3 due  (end
29
January
  ·         Homework 4 posted

Week  5 Session 5 ·         Logic Built-In Self-Test ·         Homework 4 due (end
5
February
  ·         Homework 5 posted

 
Week 6 Session 6 ·         Test Compression ·         Homework 5 due (end
12
February
  ·         Homework 6 posted

·         Research topic selectio

 
Week     ·         Reading Week
18 – 22
·         Classes cancelled
February

Week 7 Session 7 ·         “Selected Topics” (guest lecturer(s)) ·         Homework 6 due (end
26 
February
  ·         Final project proposal

   
Week 8 Session 8 ·         Logic Diagnosis ·         Homework 7 posted
4 March
·         Student presentations

Week 9 Session 9 ·         Memory Test ·         Homework 7 due (end

11 March
·         Memory Built-In Self-Test ·         Homework 8 posted

·         Student presentations

Week 10 Session 10 ·         Boundary Scan ·         Homework 8 due
18 March
·         Core-Based Testing ·         Homework 9 posted

·         Student presentations

Week 11 Session 11 ·         Analog Test ·         Homework 9 due
25 March
·         Mixed-Signal Testing ·         Homework 10 posted

·         Student Presentations

Week 12 Session 12 ·         Test Technology Trends ·         Homework 10 due
1 April
·         Special Topics ·         Student Presentations
Week 13 Session 13 ·         Student Presentations ·         Student presentations
8 April
·         Project reports due (en

·         Research papers due

Course Requirements:

1.      Students are expected to attend class meetings, scheduled weekly, for 3 hours. A large proportion
of these meetings will be in the form of lectures. However, group discussions will form part of
these meetings also.  Attendance is mandatory.
 2.      Weekly reading assignments, primarily from the text and occasionally from additional hand-out
materials.

3.      Completion of a series of 10 homework assignments based on the reading material and topics
discussed in class.

4.      A research paper (of at most 6 pages) describing a current test topic in greater detail than that
discussed in class and covered in the text.  Students are expected to provide a
perspective/analysis that supplements material presented in class and in the text, and not simply
reiterate. 

5.      A 25-minute presentation by each student based on his/her research project in 4).

6.      Completion of an individual or group (2 students) programming or design project focusing on

some aspects of test or design for testability.  The project may involve CAD program/algorithm for
test generation/fault simulation, or involve the design of the design for testability elements of an
exemplary circuit.  A formal report will be expected as well as a project demonstration.

7.      Completion of a final examination.

Grading:

Homework Assignments (10)                20%

Project Oral Presentation                      10%

Research Paper                                    20%

Course Project                         30%

Final Examination                                  20%

Total                                                    100%