M98 Card

5 4 3 2 1
U1A U1J
PCIE_RXP0 AM48 AK45 PCIE_TXP0 BK49 BH48

PCIE_RXN0 PCIE_RX0P PCIE_TX0P PCIE_TXN0 SP_RX0P SP_TX0P
AL49 PCIE_RX0N PCIE_TX0N AK44 BL51 SP_RX0N SP_TX0N BH46
PCIE_RXP1 AL51 AK42 PCIE_TXP1 BJ50 BC45

AK52 PCIE_RX1N PCIE_TX1N AK41 BG52 SP_RX1N SP_TX1N BC44
PCIE_RXP2 AK48 AJ45 PCIE_TXP2 BF48 BB45

AJ49 PCIE_RX2N PCIE_TX2N AJ44 BE49 SP_RX2N SP_TX2N BB44
PCIE_REFCLKP
(10) PCIE_REFCLKP
PCIE_REFCLKN PCIE_RXP3 AJ51 AJ42 PCIE_TXP3 BE51 AY42
(10) PCIE_REFCLKN PCIE_RX3P PCIE_TX3P SP_RX3P SP_TX3P
PCIE_RXN3 AH52 AJ41 PCIE_TXN3 BD52 AY41
PCIE_RX3N PCIE_TX3N SP_RX3N SP_TX3N
PCIE_RXP4 AH48 AH45 PCIE_TXP4 BD48 AY45
PCIE_RXP[15..0] PCIE_RXN4 PCIE_RX4P PCIE_TX4P PCIE_TXN4 SP_RX4P SP_TX4P
D (10) PCIE_RXP[15..0] AG49 PCIE_RX4N PCIE_TX4N AH44 BC49 SP_RX4N SP_TX4N AY44 D
PCIE_RXN[15..0] PCIE_RXP5 AG51 AH42 PCIE_TXP5 BC51 AW42
(10) PCIE_RXN[15..0] PCIE_RX5P PCIE_TX5P SP_RX5P SP_TX5P
PCIE_RXN5 AF52 AH41 PCIE_TXN5 BB52 AW41
PCIE_TXP[15..0] PCIE_RX5N PCIE_TX5N SP_RX5N SP_TX5N
(10) PCIE_TXP[15..0]
PCIE_RXP6 AF48 AF45 PCIE_TXP6 BB48 AW45
PCIE_TXN[15..0] PCIE_RXN6 PCIE_RX6P PCIE_TX6P PCIE_TXN6 SP_RX6P SP_TX6P
(10) PCIE_TXN[15..0] AE49 PCIE_RX6N PCIE_TX6N AF44 BA49 SP_RX6N SP_TX6N AW44
PCIE_RXP7 AE51 AF42 PCIE_TXP7 BA51 AU42

AD52 PCIE_RX7N PCIE_TX7N AF41 AY52 SP_RX7N SP_TX7N AU41
PCIE_RXP8 AD48 AE45 PCIE_TXP8 AY48 AU45

AC49 PCIE_RX8N PCIE_TX8N AE44 AW49 SP_RX8N SP_TX8N AU44
PCIE_RXP9 AC51 AE42 PCIE_TXP9 AW51 AT42

AB52 PCIE_RX9N PCIE_TX9N AE41 AV52 SP_RX9N SP_TX9N AT41
PCIE_RXP10 AB48 AD45 PCIE_TXP10 AV48 AT45

AA49 PCIE_RX10N PCIE_TX10N AD44 AU49 SP_RX10N SP_TX10N AT44
PCIE_RXP11 AA51 AD42 PCIE_TXP11 AU51 AR42

Y52 PCIE_RX11N PCIE_TX11N AD41 AT52 SP_RX11N SP_TX11N AR41
PCIE_RXP12 Y48 AB45 PCIE_TXP12 AT48 AR45

W49 PCIE_RX12N PCIE_TX12N AB44 AR49 SP_RX12N SP_TX12N AR44
PCIE_RXP13 W51 AB42 PCIE_TXP13 AR51 AN42

V52 PCIE_RX13N PCIE_TX13N AB41 AP52 SP_RX13N SP_TX13N AN41
PCIE_RXP14 V48 AA45 PCIE_TXP14 AP48 AN45

U49 PCIE_RX14N PCIE_TX14N AA44 AN49 SP_RX14N SP_TX14N AN44
PCIE_RXP15 U51 AA42 PCIE_TXP15 AN51 AM42

T52 PCIE_RX15N PCIE_TX15N AA41 AM52 SP_RX15N SP_TX15N AM41
PCIE_REFCLKP AM45 AT39

PCIE_REFCLKP PERSTB PCIE_RST# (10,12)
PCIE_REFCLKN AM44 PCIE_REFCLKN
C
PCIE_PVDD AR37 PCIE_PVDD BM47 SP_REFCLKP SP_CALRP AH39 C
PCIE_PVDD: 1.8V,+-3%, 40mA BK46 SP_REFCLKN SP_CALRN AH38
1.27K R2 AF39
2.0K R1 PCIE_CALRP
AF38 PCIE_CALRN
SP_PVDD AR38 PCIE_PVDD
+1.1V_REG SP_PVDD: 1.8V,+-5%, 35mA
+1.1V_REG AF37 PCIE_VDDC#1
PCIE_VDDC: 1.0V-1.1V,+-5%, 2.5A AA38 PCIE_VDDC#2
AA39 PCIE_VDDC#3 PCIE_VSS#21 AH50
AB37 PCIE_VDDC#4 PCIE_VSS#22 AH40
AB38 AH43 M98 16P A12 MVD SLT BIN1
PCIE_VDDC#5 PCIE_VSS#23
AB39 PCIE_VDDC#6 PCIE_VSS#24 AJ53
AD37 PCIE_VDDC#7 PCIE_VSS#25 AJ40
AE37 PCIE_VDDC#10 PCIE_VSS#28 AK50
W38 PCIE_VDDC#13 PCIE_VSS#31 AL53
W39 PCIE_VDDC#14 PCIE_VSS#32 AL47
W40 PCIE_VDDC#15 PCIE_VSS#33 AM50
W41 PCIE_VDDC#16 PCIE_VSS#34 AA53
W42 PCIE_VDDC#17 PCIE_VSS#35 AM43
W43 PCIE_VDDC#18 PCIE_VSS#36 AN53
PCIE_VSS#39 AN47
PCIE_VDDR AM40 PCIE_VDDR#1 PCIE_VSS#40 AP50
PCIE_VDDR: 1.8V,+-5%, 700mA AJ38 PCIE_VDDR#2 PCIE_VSS#41 AR53
AJ39 PCIE_VDDR#3 PCIE_VSS#42 Y50
AH37 PCIE_VDDR#4 PCIE_VSS#43 AR43
AK38 PCIE_VDDR#5 PCIE_VSS#44 AR47
AK39 PCIE_VDDR#6 PCIE_VSS#45 AT50
AJ37 PCIE_VDDR#7 PCIE_VSS#46 AT40
AK37 PCIE_VDDR#8 PCIE_VSS#47 AT43
AM37 PCIE_VDDR#9 PCIE_VSS#48 AU53
AM38 PCIE_VDDR#10 PCIE_VSS#49 AU40
B
AM39 PCIE_VDDR#11 PCIE_VSS#50 AU43 B
AN37 PCIE_VDDR#12 PCIE_VSS#51 AU47
AN38 PCIE_VDDR#13 PCIE_VSS#52 AV50
AN39 PCIE_VDDR#14 PCIE_VSS#53 AW53
AR39 PCIE_VDDR#15 PCIE_VSS#54 AW40
AR40 PCIE_VDDR#16 PCIE_VSS#55 AW43
PCIE_VSS#56 AW47
PCIE_VSS#57 AY50
AA40 PCIE_VSS#1 PCIE_VSS#58 AY40
AA43 PCIE_VSS#2 PCIE_VSS#59 AY43
AA47 PCIE_VSS#3 PCIE_VSS#60 BA53
AB50 PCIE_VSS#4 PCIE_VSS#61 BA47
AB40 PCIE_VSS#5 PCIE_VSS#62 BB50
AB43 PCIE_VSS#6 PCIE_VSS#63 BB43
AC53 PCIE_VSS#7 PCIE_VSS#64 BC53
AC47 PCIE_VSS#8 PCIE_VSS#65 BB42
AD50 PCIE_VSS#9 PCIE_VSS#66 BC47
AD40 PCIE_VSS#10 PCIE_VSS#67 BD50
AD43 PCIE_VSS#11 PCIE_VSS#68 BD44
AE53 PCIE_VSS#12 PCIE_VSS#69 BD45
AE40 PCIE_VSS#13 PCIE_VSS#70 BF53
AE43 PCIE_VSS#14 PCIE_VSS#71 BE47
AE47 PCIE_VSS#15 PCIE_VSS#72 BF50
AF50 PCIE_VSS#16 PCIE_VSS#73 BJ53
AF40 PCIE_VSS#17 PCIE_VSS#74 BL45
AF43 PCIE_VSS#18 PCIE_VSS#75 BN46
AG53 PCIE_VSS#19 PCIE_VSS#76 W47
AG47 PCIE_VSS#20 PCIE_VSS#77 BN49
PCIE_VSS#78 T50
PCIE_VSS#79 U53
PCIE_VSS#80 U47
PCIE_VSS#81 V50
PCIE_VSS#82 W53
A M98 16P A12 MVD SLT BIN1 A
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Wednesday, May 27, 2009 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 1 of 19
from use of the information included herein.
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
DPAVDDR U1B U1K

DPAVDDR: 1.1V,+-3%, 200mA
BD29 BM26 +1.8V_REG BH20
DPAVDDR#1 TX0P_DPA2P DPA2P (10) DVPDATA_0
BE29 DPAVDDR#2 TX0M_DPA2N BL25 DPA2N (10) DVPDATA_1 BK20
R11 221R VREFG BG21 BM20
VREFG DVPDATA_2
BG25 DPAVSSR#1 TX1P_DPA1P BJ27 DPA1P (10) DVPDATA_3 BJ21
BN27 BH26 DPA1N (10) R21 110R BL21
DPAVSSR#2 TX1M_DPA1N C12 100nF_6.3V DVPDATA_4
D
BN25 DPAVSSR#3 DVPDATA_5 BN21 D
BG27 BM28 DPA0P (10) VDDR3 BH22
DPAVSSR#4 TX2P_DPA0P DVPDATA_6
BK26 DPAVSSR#5 TX2M_DPA0N BL27 DPA0N (10) DVPDATA_7 BK22
BK28 DPAVSSR#6 AU29 VDDR3#1 DVPDATA_8 BG23
DPBVDDR
DPBVDDR: 1.1V,+-3%, 200mA BM24 DPAVSSR#7 TXCAP_DPA3P BJ25 DPA3P (10) AU30 VDDR3#2 DVPDATA_9 BJ23
TXCAM_DPA3N BK24 DPA3N (10) AU32 VDDR3#3 DVPDATA_10 BN23
BD30 DPBVDDR#1 AU33 VDDR3#4 DVPDATA_11 BL23
BE30 DPBVDDR#2 TX3P_DPB2P BM30 DPB2P (10)
TX3M_DPB2N BL29 DPB2N (10) DVPCLK BK18
BK32 DPBVSSR#1
BG31 DPBVSSR#2 TX4P_DPB1P BJ31 DPB1P (10) DVPCNTL_0 BM18
BN29 BH30 VDDR4_5 BJ19
DPBVSSR#3 TX4M_DPB1N DPB1N (10) DVPCNTL_1
BN31 DPBVSSR#4 DVPCNTL_2 BL19
BH32 DPBVSSR#5 TX5P_DPB0P BM32 DPB0P (10) BB24 VDDR5#1
BK30 DPBVSSR#6 TX5M_DPB0N BL31 DPB0N (10) BE24 VDDR5#2 DVPDATA_12 AW25
LVDDC
LVDDC: 1.8V,+-3%, 400mA BG29 DPBVSSR#7 BC24 VDDR5#3 DVPDATA_13 AY24
TXCBP_DPB3P BJ29 DPB3P (10) BD24 VDDR5#4 DVPDATA_14 AV25
BG37 T2XVDDC#1 TXCBM_DPB3N BH28 DPB3N (10) DVPDATA_15 AY25
BK38 T2XVDDC#2 BE25 VDDR4#1 DVPDATA_16 AY26
BK44 T2VXDDC#3 BD25 VDDR4#2 DVPDATA_17 AW26
BM44 T2XVDDC#4 TXOUT_L0P BJ35 TXOUT_L0+ (10) BB25 VDDR4#3 DVPDATA_18 BA28
TXOUT_L0N BH34 TXOUT_L0- (10) BC25 VDDR4#4 DVPDATA_19 AV26
BG35 T2XVSSR#1 DVPDATA_20 AY28
BN41 T2XVSSR#2 TXOUT_L1P BM36 TXOUT_L1+ (10) DVPDATA_21 AW28
BM34 T2XVSSR#3 TXOUT_L1N BL35 TXOUT_L1- (10) DVPDATA_22 AY29
BG39 T2XVSSR#4 DVPDATA_23 AW29
BK36 BJ37 AV36 VDDR3
T2XVSSR#5 TXOUT_L2P TXOUT_L2+ (10) (11) TS_FDO TS_FDO
BJ43 T2XVSSR#6 TXOUT_L2N BH36 TXOUT_L2- (10) DVPCNTL_MVP_0 AW24
BN43 AV24 R196 100K
T2XVSSR#7 DVPCNTL_MVP_1
BK40 T2XVSSR#8 TXOUT_L3P BM38 TXOUT_L3+ (10)
BN35 T2XVSSR#9 TXOUT_L3N BL37 TXOUT_L3- (10) (11) GPU_DPLUS AV30 DPLUS
BN37 T2XVSSR#10 (11) GPU_DMINUS AW30 DMINUS GPIO_0 BA24 GPIO0 (11)
BN39 T2XVSSR#11 TXCLK_LP BK34 TXCLK_L+ (10) GPIO_1 AV29 GPIO1 (11)
BG41 T2XVSSR#12 TXCLK_LN BJ33 TXCLK_L- (10) GPIO_2 BH24 GPIO2 (11)
BH42 TSVDD BD22
T2XVSSR#13 GPIO_3_SMBDAT GPIO3_SMBDAT (10)
TXOUT_U0P BM40 TXOUT_U0+ (10) GPIO_4_SMBCLK BA25 GPIO4_SMBCLK (10)
DPA_PVDD BE26 DPA_PVDD TXOUT_U0N BL39 TXOUT_U0- (10) AU24 TSVDD GPIO_5 BE22 PWR_LEVEL (10)
DPA_PVDD: 1.8V,+-3%, 20mA GPIO_6_TACH AY22 GPIO6 (12)
C BD26 DPA_PVSS TXOUT_U1P BJ41 TXOUT_U1+ (10) GPIO_7 BC22 OPT_BL_ENA (10) C
GND_DPA_PVSS BH40 TXOUT_U1- (10) TSVSS AU25 BB22 33R 3 6 RP1C
TXOUT_U1N TSVSS GPIO_8_ROMSO GPIO8 (11,12)
BE28 BA21 33R 1 8 RP1A
DPB_PVDD DPB_PVDD GPIO_9_ROMSI GPIO9 (11,12)
DPB_PVDD: 1.8V,+-3%, 20mA BM42 TXOUT_U2+ (10) BB21 33R 2 7 RP1B
TXOUT_U2P GPIO_10_ROMSCK GPIO10 (12)
BD28 DPB_PVSS TXOUT_U2N BL41 TXOUT_U2- (10) (10) BLON_PWM BA30 VARY_BL GPIO_11 AW22 GPIO11 (11)
GND_DPB_PVSS BB30 BE21
(10) FPVCC DIGON GPIO_12 GPIO12 (11)
R22 150R DP_CALR BC29 BL43 TXOUT_U3+ (10) BD21
DP_CALR TXOUT_U3P GPIO_13 GPIO13 (11)
TXOUT_U3N BK42 TXOUT_U3- (10) AU39 JMODE GPIO_14_HPD2 BD19 HPD2 (10)
R19 R20 BB19
GPIO_15_PWRCNTL_0 GPIO15 (12)
BN33 BJ39 TXCLK_U+ (10) 10K 10K BC19
LPVDD T2PVDD TXCLK_UP GPIO_16_SSIN GPIO16_SS (11) VDDR3
LPVDD: 1.8V,+-3%, 40mA BH38 TXCLK_U- (10) R23 BE19 GPIO17_THERMAL_INT (10,11)
TXCLK_UN 1K GPIO_17_THERMAL_INT
GPIO_18_HPD3 AY21 HPD3 (10)
GPIO_19_CTF BH18 GPIO19_CTF (12)
BL33 AW39 BN17 10K
T2PVSS HPD1 HPD1 (10) GPIO_20_PWRCNTL_1 GPIO20 (12)
GND_LPVSS PLACE RGB TERMINATION VDDR3 BG17 R25
RESISTORS CLOSE TO ASIC GPIO_21 GPIO21 (11)
BC40 BC42 VGA_RED BC21 33R 4 5 RP1D
DAC1_AVDD AVDD R VGA_RED (10) FOR JTAG SCAN, POPULATE GPIO_22_ROMCSB GPIO22 (12)
AVDD: 1.8V,+-5%, 70mA Rb BC43
R465 AND REMOVE R23 GPIO_23_CLKREQB AW21 CLKREQB (10) VDDR3
BG19 VSSD#1 GPIO_24_TRSTB BL17 JTAG1 22mil
BD42 VGA_GRN BA22 BM16 JTAG2 22mil
G VGA_GRN (10) VSSD#2 GPIO_25_TDI
BB40 AVSSQ Gb BE42 AV28 VSSD#3 GPIO_26_TCK BH16 JTAG3 22mil
BA29 VSSD#4 GPIO_27_TMS BK16 JTAG4 22mil
GND_AVSSQ BE40 VGA_BLU BA35 BJ17 JTAG5 22mil
B VGA_BLU (10) VSSD#5 GPIO_28_TDO
VDD1DI BG45 VDD1DI Bb BD40 AW36 VSSD#6
VDD1DI: 1.8V,+-5%, 50mA BA26 VSSD#7
AY39 R26 R27 R28 AY30
HSYNC HSYNC (10,11) VSSD#8
BA39 150R 150R 150R BM22 BC35 GENERICA (10)
VSYNC VSYNC (10,11) VSSD#9 GENERICA
BE44 VSS1DI BN19 VSSD#10 GENERICB BE32 GENERICB (10)
AU22 VSSD#11 GENERICC BC33 GENERICC (11)
GND_VSS1DI BC37 BG43 BA33 GENERICD (10)
R29 499R RSET BA40 R2 VSSD#12 GENERICD
RSET R2b BC36 AU28 VSSD#13 GENERICE BC30
AU26 VSSD#14 GENERICF BD35
G2 BD37 GENERICG BB29
A2VDD: 3.3V,+-5%, 135mA A2VDD BD39 A2VDD G2b BE37 GENERICH BD32
BC39 A2VSSQ B2 BE36 VIP_0 AV35 VID_0 (11)

GND_A2VSSQ BD36 AR19 AW35
B2b NC_GPIO_31 VIP_1 VID_1 (11)
AP19 NC_GPIO_32 VIP_2 AY35 VID_2 (11)
B H2SYNC AY37 H2SYNC (11) VIP_3 AV33 VID_3 (11) B
VDDR3
VDD2DI: 1.8V,+-5%, 40mA VDD2DI BD43 VDD2DI V2SYNC AW37 V2SYNC (11) VIP_4 AW33 MEM_ID0 (11)
VIP_5 AY33 MEM_ID1 (11)
AV32 VIP[7,5,4] = 0x0 for Hynix 23C21287ST11
VIP_6 VID_6 (11) VIP[7,5,4] = 0x1 for Samsung 23C41287QH1A
BE43 VSS2DI COMP BB36 BA19 TEST_YCLK VIP_7 AW32 MEM_ID2 (11)
GND_VSS2DI BA37 AY19
Y R37 R33 TEST_MCLK
C BB37 VPCLK0 AY32
R30 715R R2SET BB39 4.7K 4.7K R31 R32 BB33
R2SET DVALID DVALID (11)
1K 1K BE35
PSYNC PSYNC (11)
A2VDDQ BE39 A2VDDQ SCL BC32 I2C_CLK (10) VHAD_0 AU36 VHAD0 (11)
A2VDDQ: 1.8V,+-5%, 1mA SDA BB32 I2C_DAT (10) VHAD_1 AU35
VPHCTL BB35
DPLL_VDDC BD33 DPLL_VDDC DDC1CLK AU37 DDC1CLK (10) VIPCLK BA32
DPLL_VDDC: 1.1V,+-5%, 100mA DPLL_PVDD BG33 DPLL_PVDD DDC1DATA AU38 DDC1DAT (10)
DPLL_PVDD: 1.8V,+-3%, 40mA
AY36 DDC2CLK (11) M98 16P A12 MVD SLT BIN1
DDC2CLK
BE33 DPLL_PVSS DDC2DATA BA36 DDC2DAT (11)
GND_PVSS
TP7 AV37 PLLTEST DDC3DATA_DP3_AUXN BB28 DPA_AUXN (10)
DDC3CLK_DP3_AUXP BC28 DPA_AUXP (10)
XTALIN BH44
(11) XTALIN XTALIN
DDC4CLK_DP4_AUXP BB26 DPB_AUXP (10)
DDC4DATA_DP4_AUXN BC26 DPB_AUXN (10)
22mil TP9 BJ45 VDDR3

XTALOUT
M98 16P A12 MVD SLT BIN1
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
RASB0# U1D
(7) RASB0#
RASA0# U1C RASB1#
(6) RASA0# (7) RASB1#
RASA1# MDB0 P35 C3 MDB32
(6) RASA1# DQB0_0 DQB1_0
MDA0 V40 D30 MDA32 CASB0# MDB1 P32 D5 MDB33
DQA0_0 DQA1_0 (7) CASB0# DQB0_1 DQB1_1
CASA0# MDA1 R42 A31 MDA33 CASB1# MDB2 T35 B7 MDB34
(6) CASA0# DQA0_1 DQA1_1 (7) CASB1# DQB0_2 DQB1_2
CASA1# MDA2 V41 F30 MDA34 MDB3 P33 D8 MDB35
(6) CASA1# DQA0_2 DQA1_2 DQB0_3 DQB1_3
MDA3 R41 E29 MDA35 WEB0# MDB4 N30 E9 MDB36
DQA0_3 DQA1_3 (7) WEB0# DQB0_4 DQB1_4
WEA0# MDA4 V42 D32 MDA36 WEB1# MDB5 P30 F10 MDB37
(6) WEA0# DQA0_4 DQA1_4 (7) WEB1# DQB0_5 DQB1_5
WEA1# MDA5 V43 C33 MDA37 MDB6 R32 D10 MDB38
(6) WEA1# DQA0_5 DQA1_5 DQB0_6 DQB1_6
MDA6 U45 E33 MDA38 CKEB0 MDB7 R35 A11 MDB39
D DQA0_6 DQA1_6 (7) CKEB0 DQB0_7 DQB1_7 D
CKEA0 MDA7 P44 F32 MDA39 CKEB1 MDB8 M25 K18 MDB40
(6) CKEA0 DQA0_7 DQA1_7 (7) CKEB1 DQB0_8 DQB1_8
CKEA1 MDA8 M48 J35 MDA40 MDB9 M28 L18 MDB41
(6) CKEA1 DQA0_8 DQA1_8 DQB0_9 DQB1_9
MDA9 M50 L32 MDA41 CSB0_0# MDB10 N25 L17 MDB42
DQA0_9 DQA1_9 (7) CSB0_0# DQB0_10 DQB1_10
CSA0_0# MDA10 L53 L35 MDA42 CSB1_0# MDB11 T26 M17 MDB43
(6) CSA0_0# DQA0_10 DQA1_10 (7) CSB1_0# DQB0_11 DQB1_11
CSA1_0# MDA11 L51 K35 MDA43 CSB0_1# MDB12 K26 M12 MDB44
CSA0_1# MDA12 P48 M30 MDA44 CSB1_1# MDB13 J26 L12 MDB45
CSA1_1# MDA13 P50 L33 MDA45 MDB14 R29 K12 MDB46
(6) CSA1_1# DQA0_13 DQA1_13 DQB0_14 DQB1_14
MDA14 P52 L30 MDA46 CLKB0 MDB15 N28 J12 MDB47
DQA0_14 DQA1_14 (7) CLKB0 DQB0_15 DQB1_15
CLKA0 MDA15 N53 J29 MDA47 CLKB0# MDB16 A29 F12 MDB48
(6) CLKA0 DQA0_15 DQA1_15 (7) CLKB0# DQB0_16 DQB1_16
CLKA0# MDA16 L49 F34 MDA48 MDB17 C29 D12 MDB49
(6) CLKA0# DQA0_16 DQA1_16 DQB0_17 DQB1_17
MDA17 J51 A35 MDA49 CLKB1 MDB18 F28 C13 MDB50
DQA0_17 DQA1_17 (7) CLKB1 DQB0_18 DQB1_18
CLKA1 MDA18 K50 E35 MDA50 CLKB1# MDB19 D28 A13 MDB51
(6) CLKA1 DQA0_18 DQA1_18 (7) CLKB1# DQB0_19 DQB1_19
CLKA1# MDA19 K48 C35 MDA51 MDB20 A27 F14 MDB52
(6) CLKA1# DQA0_19 DQA1_19 WDQSB[7..0] DQB0_20 DQB1_20
MDA20 G52 E37 MDA52 MDB21 D26 C15 MDB53
WDQSA[7..0] DQA0_20 DQA1_20 (7) WDQSB[7..0] DQB0_21 DQB1_21
MDA21 H48 C37 MDA53 MDB22 E25 A15 MDB54
(6) WDQSA[7..0] DQA0_21 DQA1_21 RDQSB[7..0] DQB0_22 DQB1_22
MDA22 F48 B38 MDA54 MDB23 F26 E15 MDB55
RDQSA[7..0] DQA0_22 DQA1_22 (7) RDQSB[7..0] DQB0_23 DQB1_23
MDA23 C51 A37 MDA55 MDB24 E21 F20 MDB59
(6) RDQSA[7..0] DQA0_23 DQA1_23 DQMB#[7..0] DQB0_24 DQB1_24
MDA24 C43 F42 MDA56 MDB25 D22 C17 MDB57
DQMA#[7..0] DQA0_24 DQA1_24 (7) DQMB#[7..0] DQB0_25 DQB1_25
MDA25 F44 E41 MDA57 MDB26 C21 D20 MDB58
(6) DQMA#[7..0] DQA0_25 DQA1_25 MDB[63..0] DQB0_26 DQB1_26
MDA26 E43 A43 MDA58 MDB27 A21 C19 MDB56
MDA[63..0] DQA0_26 DQA1_26 (7) MDB[63..0] DQB0_27 DQB1_27
MDA27 D44 D42 MDA59 MDB28 C23 E19 MDB60
(6) MDA[63..0] DQA0_27 DQA1_27 MAB[11..0] DQB0_28 DQB1_28
MDA28 A46 D40 MDA60 MDB29 E23 D18 MDB61
MAA[11..0] DQA0_28 DQA1_28 (7) MAB[11..0] DQB0_29 DQB1_29
MDA29 D46 E39 MDA61 MDB30 F24 E17 MDB62
(6) MAA[11..0] DQA0_29 DQA1_29 DQB0_30 DQB1_30
MDA30 F46 C39 MDA62 B_BA0 MDB31 D24 A17 MDB63
DQA0_30 DQA1_30 (7) B_BA0 DQB0_31 DQB1_31
A_BA0 MDA31 B47 F40 MDA63 B_BA1
(6) A_BA0 DQA0_31 DQA1_31 (7) B_BA1
A_BA1 B_BA2
(6) A_BA1 (7) B_BA2
A_BA2 MAB0 J24 J18 MAB8
(6) A_BA2 MAB0_0 MAB1_0
MAA0 L44 J42 MAA8 MAB1 L24 M19 MAB9
MAA1 MAA0_0 MAA1_0 MAA9 MAB2 MAB0_1 MAB1_1 MAB10
M45 MAA0_1 MAA1_1 K40 L25 MAB0_2 MAB1_2 P18
MAA2 P40 L37 MAA10 MAB3 P24 T18 MAB11
MAA3 MAA0_2 MAA1_2 MAA11 MAB4 MAB0_3 MAB1_3
M44 MAA0_3 MAA1_3 J40 L28 MAB0_4 MAB1_4 N17
MAA4 R43 J37 MAB5 P25 R18 B_BA2
MAA5 MAA0_4 MAA1_4 A_BA2 MAB6 MAB0_5 MAB1_5 B_BA0
P43 MAA0_5 MAA1_5 K37 N22 MAB0_6 MAB1_6 N19
MAA6 J43 M39 A_BA0 MAB7 P22 P21 B_BA1
MAA7 MAA0_6 MAA1_6 A_BA1 MAB0_7 MAB1_7
K44 MAA0_7 MAA1_7 M40 L22 MAB0_8 MAB1_8 L19
M42 MAA0_8 MAA1_8 K42
M22 ADBIB0 ADBIB1 J21
C K45 ADBIA0 ADBIA1 L42 C
DQMB#0 K29 C11 DQMB#4
DQMA#0 DQMA#4 DQMB#1 WCKB0_0 WCKB1_0 DQMB#5
R51 WCKA0_0 WCKA1_0 B34 L29 WCKB0B_0 WCKB1B_0 E11
DQMA#1 R49 D34 DQMA#5 DQMB#2 C25 D16 DQMB#6
DQMA#2 WCKA0B_0 WCKA1B_0 DQMA#6 DQMB#3 WCKB0_1 WCKB1_1 DQMB#7
E50 WCKA0_1 WCKA1_1 D38 A25 WCKB0B_1 WCKB1B_1 F16
DQMA#3 D49 F38 DQMA#7
WCKA0B_1 WCKA1B_1 RDQSB0 RDQSB4
N33 EDCB0_0 EDCB1_0 F8
RDQSB1 L26 K15 RDQSB5
RDQSA0 RDQSA4 RDQSB2 EDCB0_1 EDCB1_1 RDQSB6
U44 EDCA0_0 EDCA1_0 C31 E27 EDCB0_2 EDCB1_2 E13
RDQSA1 N49 J32 RDQSA5 RDQSB3 F22 A19 RDQSB7
RDQSA2 EDCA0_1 EDCA1_1 RDQSA6 EDCB0_3 EDCB1_3
J49 EDCA0_2 EDCA1_2 D36
RDQSA3 C45 C41 RDQSA7 WDQSB0 M33 C9 WDQSB4
EDCA0_3 EDCA1_3 WDQSB1 DDBIB0_0 DDBIB1_0 WDQSB5
M26 DDBIB0_1 DDBIB1_1 J15
WDQSA0 U43 E31 WDQSA4 WDQSB2 C27 D14 WDQSB6
WDQSA1 DDBIA0_0 DDBIA1_0 WDQSA5 WDQSB3 DDBIB0_2 DDBIB1_2 WDQSB7
N51 DDBIA0_1 DDBIA1_1 K32 A23 DDBIB0_3 DDBIB1_3 F18
WDQSA2 H50 F36 WDQSA6
WDQSA3 DDBIA0_2 DDBIA1_2 WDQSA7 WEB0# WEB1#
E45 DDBIA0_3 DDBIA1_3 A41 T29 WEB0B WEB1B P15
CSB0_0# P26 N15 CSB1_0#
WEA0# WEA1# CSB0_1# CSB0B_0 CSB1B_0 CSB1_1#
U38 WEA0B WEA1B N36 R26 CSB0B_1 CSB1B_1 L14
CSA0_0# R39 P37 CSA1_0# CASB0# R24 K21 CASB1#
CSA0_1# CSA0B_0 CSA1B_0 CSA1_1# +MVDD RASB0# CASB0B CASB1B RASB1#
R40 CSA0B_1 CSA1B_1 R37 K24 RASB0B RASB1B P19
CASA0# J44 N39 CASA1#
RASA0# CASA0B CASA1B RASA1# CKEB0 CKEB1
P45 RASA0B RASA1B L39 T24 CKEB0 CKEB1 L21
+MVDD CLKB0 P29 N14 CLKB1
R39 CLKB0# CLKB0 CLKB1 CLKB1#
P28 CLKB0B CLKB1B M14
CKEA0 L43 T37 CKEA1 40.2R
CLKA0 CKEA0 CKEA1 CLKA1 1%
U40 CLKA0 CLKA1 M36
R38 CLKA0# U39 L36 CLKA1# T17
40.2R CLKA0B CLKA1B MVREFBS
U18 MVREFBD
1%
U33 R42 C19 +MVDD R43 243R T21
MVREFAS 100R 100nF_6.3V R44 243R MEM_CALRPB
U32 MVREFAD R21 MEM_CALRNB
J10 1%
+MVDD MPVDD#0 MEM_PLL
R40 C18 R41 243R T32 K10
100R 100nF_6.3V R45 243R MEM_CALRPA MPVDD#1
P36 MEM_CALRNA MPVDD#2 K9
1% +MVDD
R46 10K AW19 M98 16P A12 MVD SLT BIN1

B +MVDD DRAM_RST B
R48
M98 16P A12 MVD SLT BIN1 40.2R
1%
R47 (6,7,8,9) MEM_RST R1000 681R
40.2R
1% C1000
68pF_50V R49 C21
100R 100nF_6.3V
1%
R50 C20
100R 100nF_6.3V
1% PLACE MVREF CAPS PLACE MVREF CAPS
AS CLOSE TO ASIC AS POSSIBLE AS CLOSE TO ASIC AS POSSIBLE
A A

is strictly prohibited. Use of this schematic and design for any purpose Markhaml, Ontario
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U1E U1F
RASC0#
(8) RASC0#
RASC1# MDC0 E4 AR16 MDC32 RASD0# MDD0 AJ5 BC18 MDD32
(8) RASC1# DQC0_0 DQC1_0 (9) RASD0# DQD0_0 DQD1_0
MDC1 H4 AN14 MDC33 RASD1# MDD1 AK6 BB18 MDD33
DQC0_1 DQC1_1 (9) RASD1# DQD0_1 DQD1_1
CASC0# MDC2 G2 AR14 MDC34 MDD2 AK4 BA18 MDD34
(8) CASC0# DQC0_2 DQC1_2 DQD0_2 DQD1_2
CASC1# MDC3 F6 AR15 MDC35 CASD0# MDD3 AL1 AY18 MDD35
(8) CASC1# DQC0_3 DQC1_3 (9) CASD0# DQD0_3 DQD1_3
MDC4 J5 AM15 MDC36 CASD1# MDD4 AM6 BE17 MDD36
DQC0_4 DQC1_4 (9) CASD1# DQD0_4 DQD1_4
WEC0# MDC5 K6 AM14 MDC37 MDD5 AM4 BA15 MDD37
(8) WEC0# DQC0_5 DQC1_5 DQD0_5 DQD1_5
WEC1# MDC6 K4 AK13 MDC38 WED0# MDD6 AN5 BB15 MDD38
D (8) WEC1# DQC0_6 DQC1_6 (9) WED0# DQD0_6 DQD1_6 D
MDC7 L1 AK14 MDC39 WED1# MDD7 AN3 BD14 MDD39
DQC0_7 DQC1_7 (9) WED1# DQD0_7 DQD1_7
CKEC0 MDC8 V10 AJ15 MDC40 MDD8 AR11 BH12 MDD40
(8) CKEC0 DQC0_8 DQC1_8 DQD0_8 DQD1_8
CKEC1 MDC9 V11 AH12 MDC41 CKED0 MDD9 AK12 BK12 MDD41
(8) CKEC1 DQC0_9 DQC1_9 (9) CKED0 DQD0_9 DQD1_9
MDC10 U11 AH13 MDC42 CKED1 MDD10 AR10 BN11 MDD42
DQC0_10 DQC1_10 (9) CKED1 DQD0_10 DQD1_10
CSC0_0# MDC11 U12 AF10 MDC43 MDD11 AR9 BL11 MDD43
(8) CSC0_0# DQC0_11 DQC1_11 DQD0_11 DQD1_11
CSC1_0# MDC12 L11 AF9 MDC44 CSD0_0# MDD12 AN11 BH14 MDD44
(8) CSC1_0# DQC0_12 DQC1_12 (9) CSD0_0# DQD0_12 DQD1_12
CSC0_1# MDC13 M11 AF16 MDC45 CSD1_0# MDD13 AK11 BK14 MDD45
CSC1_1# MDC14 M10 AE13 MDC46 CSD0_1# MDD14 AJ9 BM14 MDD46
MDC15 M9 AE12 MDC47 CSD1_1# MDD15 AM11 BN13 MDD47
DQC0_15 DQC1_15 (9) CSD1_1# DQD0_15 DQD1_15
CLKC0 MDC16 M6 AJ3 MDC48 MDD16 AR3 BJ11 MDD48
(8) CLKC0 DQC0_16 DQC1_16 DQD0_16 DQD1_16
CLKC0# MDC17 M4 AJ1 MDC49 CLKD0 MDD17 AR1 BK10 MDD49
(8) CLKC0# DQC0_17 DQC1_17 (9) CLKD0 DQD0_17 DQD1_17
MDC18 N3 AH4 MDC50 CLKD0# MDD18 AP6 BM7 MDD55
DQC0_18 DQC1_18 (9) CLKD0# DQD0_18 DQD1_18
CLKC1 MDC19 N1 AH6 MDC51 MDD19 AR5 BL9 MDD51
(8) CLKC1 DQC0_19 DQC1_19 DQD0_19 DQD1_19
CLKC1# MDC20 P6 AG1 MDC52 CLKD1 MDD20 AU1 BH10 MDD52
(8) CLKC1# DQC0_20 DQC1_20 (9) CLKD1 DQD0_20 DQD1_20
MDC21 R3 AF4 MDC53 CLKD1# MDD21 AU3 BH8 MDD53
WDQSC[7..0] DQC0_21 DQC1_21 (9) CLKD1# DQD0_21 DQD1_21
MDC22 R1 AE5 MDC54 MDD22 AU5 BH6 MDD50
(8) WDQSC[7..0] DQC0_22 DQC1_22 WDQSD[7..0] DQD0_22 DQD1_22
MDC23 R5 AF6 MDC55 MDD23 AV2 BL3 MDD54
RDQSC[7..0] DQC0_23 DQC1_23 (9) WDQSD[7..0] DQD0_23 DQD1_23
MDC24 Y6 AA5 MDC56 MDD24 BB6 BC5 MDD56
(8) RDQSC[7..0] DQC0_24 DQC1_24 RDQSD[7..0] DQD0_24 DQD1_24
MDC25 W3 AB4 MDC57 MDD25 BA5 BD4 MDD57
DQMC#[7..0] DQC0_25 DQC1_25 (9) RDQSD[7..0] DQD0_25 DQD1_25
MDC26 Y4 AA3 MDC58 MDD26 BC1 BC3 MDD58
(8) DQMC#[7..0] DQC0_26 DQC1_26 DQMD#[7..0] DQD0_26 DQD1_26
MDC27 W5 AA1 MDC59 MDD27 BB4 BF1 MDD59
MDC[63..0] DQC0_27 DQC1_27 (9) DQMD#[7..0] DQD0_27 DQD1_27
MDC28 V4 AC5 MDC60 MDD28 AY6 BD6 MDD60
(8) MDC[63..0] DQC0_28 DQC1_28 MDD[63..0] DQD0_28 DQD1_28
MDC29 U3 AD6 MDC61 MDD29 AW5 BF6 MDD61
MAC[11..0] DQC0_29 DQC1_29 (9) MDD[63..0] DQD0_29 DQD1_29
MDC30 U5 AD4 MDC62 MDD30 AW3 BF4 MDD62
(8) MAC[11..0] DQC0_30 DQC1_30 MAD[11..0] DQD0_30 DQD1_30
MDC31 U1 AC3 MDC63 MDD31 AY4 BG2 MDD63
DQC0_31 DQC1_31 (9) MAD[11..0] DQD0_31 DQD1_31
C_BA0
(8) C_BA0
C_BA1 D_BA0
(8) C_BA1 (9) D_BA0
C_BA2 MAC0 V9 AD9 MAC8 D_BA1 MAD0 BB9 BD11 MAD8
(8) C_BA2 MAC0_0 MAC1_0 (9) D_BA1 MAD0_0 MAD1_0
MAC1 W12 AD11 MAC9 D_BA2 MAD1 AY10 BE12 MAD9
MAC0_1 MAC1_1 (9) D_BA2 MAD0_1 MAD1_1
MAC2 V14 AE11 MAC10 MAD2 AU11 AY14 MAD10
MAC3 MAC0_2 MAC1_2 MAC11 MAD3 MAD0_2 MAD1_2 MAD11
V16 MAC0_3 MAC1_3 AD14 AY9 MAD0_3 MAD1_3 BD12
MAC4 U13 AH11 MAD4 AU9 BC15
MAC5 MAC0_4 MAC1_4 C_BA2 MAD5 MAD0_4 MAD1_4 D_BA2
V15 MAC0_5 MAC1_5 AE14 AU10 MAD0_5 MAD1_5 BC14
MAC6 W13 AB13 C_BA0 MAD6 AW12 BC9 D_BA0
MAC7 MAC0_6 MAC1_6 C_BA1 MAD7 MAD0_6 MAD1_6 D_BA1
AA14 MAC0_7 MAC1_7 AB14 AY12 MAD0_7 MAD1_7 BD10
W11 MAC0_8 MAC1_8 AB11 BB10 MAD0_8 MAD1_8 BC11
C AA9 ADBIC0 ADBIC1 AB12 BB11 ADBID0 ADBID1 BE10 C
DQMC#0 L3 AJ10 DQMC#4 DQMD#0 AP2 BL15 DQMD#4

DQMC#1 WCKC0_0 WCKC1_0 DQMC#5 DQMD#1 WCKD0_0 WCKD1_0 DQMD#5
L5 WCKC0B_0 WCKC1B_0 AJ11 AP4 WCKD0B_0 WCKD1B_0 BJ15
DQMC#2 T4 AE3 DQMC#6 DQMD#2 AV4 BK5 DQMD#6
DQMC#3 WCKC0_1 WCKC1_1 DQMC#7 DQMD#3 WCKD0_1 WCKD1_1 DQMD#7
T6 WCKC0B_1 WCKC1B_1 AE1 AV6 WCKD0B_1 WCKD1B_1 BJ4
RDQSC0 H6 AN13 RDQSC4 RDQSD0 AL3 BD17 RDQSD4

RDQSC1 EDCC0_0 EDCC1_0 RDQSC5 RDQSD1 EDCD0_0 EDCD1_0 RDQSD5
R10 EDCC0_1 EDCC1_1 AF11 AM9 EDCD0_1 EDCD1_1 BJ13
RDQSC2 N5 AG5 RDQSC6 RDQSD2 AT4 BJ9 RDQSD6
RDQSC3 EDCC0_2 EDCC1_2 RDQSC7 RDQSD3 EDCD0_2 EDCD1_2 RDQSD7
W1 EDCC0_3 EDCC1_3 AB6 BA3 EDCD0_3 EDCD1_3 BE3
WDQSC0 J3 AN12 WDQSC4 WDQSD0 AL5 BC17 WDQSD4

WDQSC1 DDBIC0_0 DDBIC1_0 WDQSC5 WDQSD1 DDBID0_0 DDBID1_0 WDQSD5
R9 DDBIC0_1 DDBIC1_1 AF12 AM10 DDBID0_1 DDBID1_1 BL13
WDQSC2 P4 AG3 WDQSC6 WDQSD2 AT6 BK8 WDQSD6
WDQSC3 DDBIC0_2 DDBIC1_2 WDQSC7 WDQSD3 DDBID0_2 DDBID1_2 WDQSD7
V6 DDBIC0_3 DDBIC1_3 AC1 BA1 DDBID0_3 DDBID1_3 BE5
WEC0# R14 AJ16 WEC1# WED0# AT13 AV17 WED1#

CSC0_0# WEC0B WEC1B CSC1_0# CSD0_0# WED0B WED1B CSD1_0#
R13 CSC0B_0 CSC1B_0 AF14 AU14 CSD0B_0 CSD1B_0 AW15
CSC0_1# P11 AF15 CSC1_1# CSD0_1# AU15 AY15 CSD1_1#
CASC0# CSC0B_1 CSC1B_1 CASC1# CASD0# CSD0B_1 CSD1B_1 CASD1#
AA10 CASC0B CASC1B AD15 AW13 CASD0B CASD1B BD9
RASC0# W14 AD10 RASC1# +MVDD RASD0# AW11 BE14 RASD1#
+MVDD RASC0B RASC1B RASD0B RASD1B
CKED0 AU16 BB12 CKED1
CKEC0 CKEC1 CLKD0 CKED0 CKED1 CLKD1
AA11 CKEC0 CKEC1 AD16 AT12 CLKD0 CLKD1 AY17
CLKC0 P13 AJ14 CLKC1 R52 CLKD0# AT11 AW17 CLKD1#
R51 CLKC0# CLKC0 CLKC1 CLKC1# 40.2R CLKD0B CLKD1B
P12 CLKC0B CLKC1B AH14
40.2R
AM17 MVREFDS
U16 MVREFCS AN17 MVREFDD
V17 MVREFCD R56 C23 +MVDD R58 243R AM16
R53 C22 +MVDD R55 243R 100R 100nF_6.3V R57 243R AT14 MEM_CALRPD
AA16 MEM_CALRPC MEM_CALRND
100R 100nF_6.3V R54 243R AA15 1%
1% MEM_CALRNC
+MVDD
+MVDD
B B
PLACE MVREF CAPS R60
R59 AS CLOSE TO ASIC AS POSSIBLE 40.2R
40.2R 1%
1%
R62
R61 C24 100R C25
100R 100nF_6.3V 1% 100nF_6.3V
1%
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U1H U1I
U1G
AA19 VDDC#1 VSSC#1 AA20 B14 VSSM#1 VSSM#101 G39
AA12 VDDR1#1 AA21 VDDC#2 VSSC#2 AA23 B18 VSSM#2 VSSM#102 G41
+MVDD AB9 AA24 AA25 B22 G43
VDDR1#2 VDDC#3 VSSC#3 VSSM#3 VSSM#103
AD12 VDDR1#3 AA26 VDDC#4 VSSC#4 AA28 A39 VSSM#4 VSSM#104 G45
AE9 VDDR1#4 AA29 VDDC#5 VSSC#5 AA30 A49 VSSM#5 VSSM#105 G9
AE15 VDDR1#5 AA31 VDDC#6 VSSC#6 AA33 A5 VSSM#6 VSSM#106 H1
AB15 VDDR1#6 AA34 VDDC#7 VSSC#7 AA35 AA13 VSSM#7 VSSM#107 J47
C56 C57 C33 C26 C58 C59 AH9 AC20 AC19 AA7 H53
D
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V VDDR1#7 VDDC#8 VSSC#8 VSSM#8 VSSM#108 D
AH15 VDDR1#8 AC23 VDDC#9 VSSC#9 AC21 AB10 VSSM#9 VSSM#109 J7
AJ12 +VDDC AC25 AC24 AB16 J11
AK15 VDDR1#10 AC28 VDDC#11 VSSC#11 AC26 AB2 VSSM#11 VSSM#111 K2
AK9 VDDR1#11 AC30 VDDC#12 VSSC#12 AC29 AC7 VSSM#12 VSSM#112 L40
AM12 VDDR1#12 AC33 VDDC#13 VSSC#13 AC31 AD13 VSSM#13 VSSM#113 K14
C60 C61 C62 C34 C35 C63 AN15 C27 C64 C65 C66 C28 C36 AC35 AC34 AD2 K17
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V VDDR1#13 1uF_6.3V 100nF_6.3V 2.2UF_2.5V 2.2UF_2.5V 100nF_6.3V 10uF_2.5V VDDC#14 VSSC#14 VSSM#14 VSSM#114
AN9 VDDR1#14 AD19 VDDC#15 VSSC#15 AD20 AE10 VSSM#15 VSSM#115 K19
AR12 +VDDC AD21 AD23 AE16 K22
AT15 VDDR1#16 AD24 VDDC#17 VSSC#17 AD25 AE7 VSSM#17 VSSM#117 K25
AT9 VDDR1#17 AD26 VDDC#18 VSSC#18 AD28 AF13 VSSM#18 VSSM#118 K28
AU12 VDDR1#18 VDDCI#1 AA17 AD29 VDDC#19 VSSC#19 AD30 AF2 VSSM#19 VSSM#119 K30
C37 C67 C38 C55 C68 C69 AW9 AB17 C70 C71 C72 C73 C29 C74 C75 C76 C77 C78 AD31 AD33 AG7 K33
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V VDDR1#19 VDDCI#2 2.2UF_2.5V 2.2UF_2.5V 1uF_6.3V 10uF_2.5V 1uF_6.3V 1uF_6.3V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 10uF_2.5V VDDC#20 VSSC#20 VSSM#20 VSSM#120
AW14 VDDR1#20 VDDCI#3 AD17 AD34 VDDC#21 VSSC#21 AD35 AH10 VSSM#21 VSSM#121 K36
BB14 VDDR1#21 VDDCI#4 AE17 AE20 VDDC#22 VSSC#22 AE19 AH16 VSSM#22 VSSM#122 K39
BE18 VDDR1#22 VDDCI#5 AF17 AE23 VDDC#23 VSSC#23 AE21 AH2 VSSM#23 VSSM#123 L47
BC10 VDDR1#23 VDDCI#6 AH17 AE25 VDDC#24 VSSC#24 AE24 AJ13 VSSM#24 VSSM#124 K52
AW18 VDDR1#24 VDDCI#7 AJ17 AE28 VDDC#25 VSSC#25 AE26 AJ7 VSSM#25 VSSM#125 L7
C79 C80 C39 C81 C40 C82 BE11 AK17 C83 C84 C85 C41 C86 C87 C88 C42 C89 AE30 AE29 AK10 P2
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V VDDR1#25 VDDCI#8 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 10uF_2.5V VDDC#26 VSSC#26 VSSM#26 VSSM#126
BE15 VDDR1#26 VDDCI#9 AR17 AE33 VDDC#27 VSSC#27 AE31 AK16 VSSM#27 VSSM#127 M2
BB17 VDDR1#27 VDDCI#10 AT17 AE35 VDDC#28 VSSC#28 AE34 AK2 VSSM#28 VSSM#128 M43
K11 VDDR1#28 VDDCI#11 AU17 AF19 VDDC#29 VSSC#29 AF20 AL7 VSSM#29 VSSM#129 M52
J14 VDDR1#29 VDDCI#12 AU18 AF21 VDDC#30 VSSC#30 AF23 AM13 VSSM#30 VSSM#130 L9
J17 VDDR1#30 VDDCI#13 AU19 AF24 VDDC#31 VSSC#31 AF25 AM2 VSSM#31 VSSM#131 R15
C90 C91 C92 C30 C43 C93 J30 U17 C44 C94 C45 C95 C46 C96 AF26 AF28 AN1 N18
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V VDDR1#31 VDDCI#14 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 10uF_2.5V VDDC#32 VSSC#32 VSSM#32 VSSM#132
J33 VDDR1#32 VDDCI#15 U19 AF29 VDDC#33 VSSC#33 AF30 AN10 VSSM#33 VSSM#133 N21
J22 U24 C47 C97 C98 C99 AH20 AH19 AR13 N29
VDDR1#35 VDDCI#18 2.2UF_2.5V 2.2UF_2.5V 1uF_6.3V 10uF_2.5V VDDC#36 VSSC#36 VSSM#36 VSSM#136
J25 VDDR1#36 VDDCI#19 U25 AH23 VDDC#37 VSSC#37 AH21 AR7 VSSM#37 VSSM#137 N32
J28 U26 C101 C102 C103 C104 C108 C109 AH25 AH24 AT10 N35
C100 C105 C48 C106 C107 C49 VDDR1#37 VDDCI#20 2.2UF_2.5V 2.2UF_2.5V 1uF_6.3V 100nF_6.3V 1uF_6.3V 10uF_2.5V VDDC#38 VSSC#38 VSSM#38 VSSM#138
J39 VDDR1#38 VDDCI#21 U28 AH28 VDDC#39 VSSC#39 AH26 AT16 VSSM#39 VSSM#139 N37
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V K43 U29 AH30 AH29 AT2 N40
VDDR1#39 VDDCI#22 VDDC#40 VSSC#40 VSSM#40 VSSM#140
L45 VDDR1#40 VDDCI#23 U30 AH33 VDDC#41 VSSC#41 AH31 AU13 VSSM#41 VSSM#141 N47
L10 U35 C110 C111 C50 AH35 AH34 AU7 N7
VDDR1#41 VDDCI#24 100nF_6.3V 100nF_6.3V 1uF_6.3V VDDC#42 VSSC#42 VSSM#42 VSSM#142
L15 VDDR1#42 VDDCI#25 U36 AJ19 VDDC#43 VSSC#43 AJ20 AW1 VSSM#43 VSSM#143 P10
M18 U37 C51 C52 C31 C112 C113 C53 AJ21 AJ23 AW10 P41
C114 C54 C115 C116 C32 C117 VDDR1#43 VDDCI#26 100nF_6.3V 1uF_6.3V 2.2UF_2.5V 2.2UF_2.5V 100nF_6.3V 10uF_2.5V VDDC#44 VSSC#44 VSSM#44 VSSM#144
M21 VDDR1#44 VDDCI#27 V37 AJ24 VDDC#45 VSSC#45 AJ25 AW7 VSSM#45 VSSM#145 R53
C 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V M24 W37 AJ26 AJ28 AY13 R12 C
VDDR1#45 VDDCI#28 VDDC#46 VSSC#46 VSSM#46 VSSM#146
R22 VDDR1#46 VDDCI#29 W17 AJ29 VDDC#47 VSSC#47 AJ30 AY2 VSSM#47 VSSM#147 M15
M29 VDDR1#47 VDDCI#30 AA37 AJ31 VDDC#48 VSSC#48 AJ33 B10 VSSM#48 VSSM#148 R17
M32 VDDR1#48 AJ34 VDDC#49 VSSC#49 AJ35 B16 VSSM#49 VSSM#149 T19
M35 C118 C119 C120 C121 C122 C467 AK20 AK19 B26 T22
C123 C124 C125 C126 C127 C128 VDDR1#49 1uF_6.3V 1uF_6.3V 1uF_6.3V 2.2UF_2.5V 2.2UF_2.5V 100nF_6.3V VDDC#50 VSSC#50 VSSM#50 VSSM#150
M37 VDDR1#50 AK23 VDDC#51 VSSC#51 AK21 B30 VSSM#51 VSSM#151 T25
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V P14 AK25 AK24 A33 T28
P17 VDDR1#52 AK28 VDDC#53 VSSC#53 AK26 B42 VSSM#53 VSSM#153 T30
R19 VDDR1#53 AK30 VDDC#54 VSSC#54 AK29 BA14 VSSM#54 VSSM#154 T33
R25 VDDR1#54 AK33 VDDC#55 VSSC#55 AK31 BA17 VSSM#55 VSSM#155 T36
R28 C129 C130 C131 C132 C133 AK35 AK34 BA7 R44
C134 C135 C136 C137 C138 C139 VDDR1#55 1uF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V VDDC#56 VSSC#56 VSSM#56 VSSM#156
R30 VDDR1#56 VDDCT#1 AV22 VDD_CT AL19 VDDC#57 VSSC#57 AL20 AY11 VSSM#57 VSSM#157 R47
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V R33 AU21 AL21 AL23 AV18 R7
VDDR1#57 VDDCT#2 VDDC#58 VSSC#58 VSSM#58 VSSM#158
R36 VDDR1#58 VDDCT#3 AV21 AL24 VDDC#59 VSSC#59 AL25 BB2 VSSM#59 VSSM#159 T2
P39 VDDR1#59 VDDCT#4 AV19 AL26 VDDC#60 VSSC#60 AL28 BD15 VSSM#60 VSSM#160 T48
P42 VDDR1#60 AL29 VDDC#61 VSSC#61 AL30 BD18 VSSM#61 VSSM#161 U10
P9 VDDR1#61 AL31 VDDC#62 VSSC#62 AL33 BC7 VSSM#62 VSSM#162 U15
C140 C141 C142 C143 C144 C145 R11 AL34 AL35 BC12 U41
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V VDDR1#62 C146 C147 C148 C149 C150 VDDC#63 VSSC#63 VSSM#63 VSSM#163
R45 VDDR1#63 AN20 VDDC#64 VSSC#64 AN19 BD2 VSSM#64 VSSM#164 U7
U14 AT37 10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V AN23 AN21 BE7 V13
VDDR1#64 SPVDD SPVDD VDDC#65 VSSC#65 VSSM#65 VSSM#165
U42 VDDR1#65 SPVSS AT38 AN25 VDDC#66 VSSC#66 AN24 BG11 VSSM#66 VSSM#166 V38
U9 VDDR1#66 AN28 VDDC#67 VSSC#67 AN26 BG13 VSSM#67 VSSM#167 V44
V12 GND_SPVSS AN30 AN29 BG15 V2
V39 VDDR1#68 AN33 VDDC#69 VSSC#69 AN31 BG9 VSSM#69 VSSM#169 W10
V45 VDDR1#69 AN35 VDDC#70 VSSC#70 AN34 BJ1 VSSM#70 VSSM#170 W16
W9 C151 C152 C153 C154 AP21 AP20 BM12 W7
VDDR1#70 10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V VDDC#71 VSSC#71 VSSM#71 VSSM#171
W15 VDDR1#71 AP24 VDDC#72 VSSC#72 AP23 BN8 VSSM#72 VSSM#172 Y2
AP26 VDDC#73 VSSC#73 AP25 BN15 VSSM#73
AP29 VDDC#74 VSSC#74 AP28 BM10 VSSM#74
M98 16P A12 MVD SLT BIN1 AP31 AP30 BN5
VDDC#75 VSSC#75 VSSM#75
AP34 VDDC#76 VSSC#76 AP33 B12 VSSM#76
AR20 VDDC#77 VSSC#77 AR21 B20 VSSM#77
B
W19 VDDC#83 VSSC#83 W20 B44 VSSM#83 B
W21 VDDC#84 VSSC#84 W23 A8 VSSM#84
W24 VDDC#85 VSSC#85 W25 E1 VSSM#85
W26 VDDC#86 VSSC#86 W28 E53 VSSM#86
W29 VDDC#87 VSSC#87 W30 G11 VSSM#87
Y20 VDDC#90 VSSC#90 Y19 G17 VSSM#90
AR35 VDDC#97 VSSC#97 AP35 G31 VSSM#97
G33 VSSM#98
G35 VSSM#99
M98 16P A12 MVD SLT BIN1 G37 VSSM#100
+VDDC
C1011 C1013 C1014 C1015 C1016 C1017 C1018

4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V
A A

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Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U2 U3
MDA20 T3 A1 MDA58 T3 A1
MDA22 DQ31 | DQ23 VDDQ MDA56 DQ31 | DQ23 VDDQ
T2 DQ30 | DQ22 VDDQ#A12 A12 T2 DQ30 | DQ22 VDDQ#A12 A12
MDA23 R3 C1 MDA57 R3 C1
MDA21 DQ29 | DQ21 VDDQ#C1 MDA59 DQ29 | DQ21 VDDQ#C1
R2 DQ28 | DQ20 VDDQ#C4 C4 R2 DQ28 | DQ20 VDDQ#C4 C4
MDA17 M3 C9 MDA62 M3 C9
MDA19 DQ27 | DQ19 VDDQ#C9 MDA61 DQ27 | DQ19 VDDQ#C9
N2 DQ26 | DQ18 VDDQ#C12 C12 N2 DQ26 | DQ18 VDDQ#C12 C12
MDA18 L3 E1 MDA60 L3 E1
MDA16 DQ25 | DQ17 VDDQ#E1 MDA63 DQ25 | DQ17 VDDQ#E1
M2 DQ24 | DQ16 VDDQ#E4 E4 M2 DQ24 | DQ16 VDDQ#E4 E4
MDA9 T10 E9 MDA35 T10 E9
MDA10 DQ23 | DQ31 VDDQ#E9 MDA34 DQ23 | DQ31 VDDQ#E9
T11 DQ22 | DQ30 VDDQ#E12 E12 T11 DQ22 | DQ30 VDDQ#E12 E12
MDA8 R10 J4 MDA32 R10 J4
MDA12 DQ21 | DQ29 VDDQ#J4 MDA33 DQ21 | DQ29 VDDQ#J4
R11 DQ20 | DQ28 VDDQ#J9 J9 R11 DQ20 | DQ28 VDDQ#J9 J9
MDA11 M10 N1 MDA36 M10 N1
MDA15 DQ19 | DQ27 VDDQ#N1 MDA39 DQ19 | DQ27 VDDQ#N1
N11 DQ18 | DQ26 VDDQ#N4 N4 N11 DQ18 | DQ26 VDDQ#N4 N4
MDA13 L10 N9 +MVDD MDA38 L10 N9 +MVDD MAA[11..0]
DQ17 | DQ25 VDDQ#N9 DQ17 | DQ25 VDDQ#N9 (3) MAA[11..0]
MDA14 M11 N12 MDA37 M11 N12
D
MDA25 DQ16 | DQ24 VDDQ#N12 MDA48 DQ16 | DQ24 VDDQ#N12 A_BA0 D
G10 DQ15 | DQ7 VDDQ#R1 R1 G10 DQ15 | DQ7 VDDQ#R1 R1 (3) A_BA0
MDA27 F11 R4 MDA49 F11 R4 A_BA1
DQ14 | DQ6 VDDQ#R4 DQ14 | DQ6 VDDQ#R4 (3) A_BA1
MDA24 F10 R9 MDA51 F10 R9 A_BA2
DQ13 | DQ5 VDDQ#R9 DQ13 | DQ5 VDDQ#R9 (3) A_BA2
MDA26 E11 R12 MDA50 E11 R12
MDA30 DQ12 | DQ4 VDDQ#R12 MDA54 DQ12 | DQ4 VDDQ#R12 WDQSA[7..0]
C10 DQ11 | DQ3 VDDQ#V1 V1 C10 DQ11 | DQ3 VDDQ#V1 V1 (3) WDQSA[7..0]
MDA29 C11 V12 MDA52 C11 V12
MDA31 DQ10 | DQ2 VDDQ#V12 MDA53 DQ10 | DQ2 VDDQ#V12 RDQSA[7..0]
B10 DQ9 | DQ1 B10 DQ9 | DQ1 (3) RDQSA[7..0]
MDA28 B11 A2 MDA55 B11 A2
MDA3 DQ8 | DQ0 VDD MDA47 DQ8 | DQ0 VDD DQMA#[7..0]
G3 DQ7 | DQ15 VDD#A11 A11 G3 DQ7 | DQ15 VDD#A11 A11 (3) DQMA#[7..0]
MDA4 F2 F1 MDA46 F2 F1
MDA7 DQ6 | DQ14 VDD#F1 MDA44 DQ6 | DQ14 VDD#F1 MDA[63..0]
F3 DQ5 | DQ13 VDD#F12 F12 F3 DQ5 | DQ13 VDD#F12 F12 (3) MDA[63..0]
MDA1 E2 M1 MDA41 E2 M1
MDA6 DQ4 | DQ12 VDD#M1 MDA43 DQ4 | DQ12 VDD#M1
C3 DQ3 | DQ11 VDD#M12 M12 C3 DQ3 | DQ11 VDD#M12 M12
MDA2 C2 V2 MDA42 C2 V2
MDA5 DQ2 | DQ10 VDD#V2 MDA45 DQ2 | DQ10 VDD#V2 MEM_RST
B3 DQ1 | DQ9 VDD#V11 V11 B3 DQ1 | DQ9 VDD#V11 V11 (3,7,8,9) MEM_RST
MDA0 B2 MDA40 B2
DQ0 | DQ8 DQ0 | DQ8
VSSQ B1 VSSQ B1
B4 B4 RASA0# R63 121R
VSSQ#B4 VSSQ#B4 (3) RASA0#
A_BA2 H10 B9 A_BA2 H10 B9 RASA1# R64 121R
BA2 | RAS VSSQ#B9 BA2 | RAS VSSQ#B9 (3) RASA1#
A_BA1 G9 B12 A_BA1 G9 B12
A_BA0 BA1 | BA0 VSSQ#B12 A_BA0 BA1 | BA0 VSSQ#B12 CASA0# R66 121R
G4 BA0 | BA1 VSSQ#D1 D1 G4 BA0 | BA1 VSSQ#D1 D1 (3) CASA0#
D4 D4 CASA1# R65 121R
VSSQ#D4 VSSQ#D4 (3) CASA1#
MAA11 L4 D9 MAA11 L4 D9
MAA10 A11 | A7 VSSQ#D9 MAA10 A11 | A7 VSSQ#D9 WEA0# R68 121R
K2 A10 | A8 VSSQ#D12 D12 K2 A10 | A8 VSSQ#D12 D12 (3) WEA0#
MAA9 M9 G2 MAA9 M9 G2 WEA1# R67 121R
A9 | A3 VSSQ#G2 A9 | A3 VSSQ#G2 (3) WEA1#
MAA8 K11 G11 MAA8 K11 G11
MAA7 A8/AP | A10 VSSQ#G11 MAA7 A8/AP | A10 VSSQ#G11 CSA0_0# R70 121R
L9 A7 | A11 VSSQ#L2 L2 L9 A7 | A11 VSSQ#L2 L2 (3) CSA0_0#
MAA6 K10 L11 MAA6 K10 L11 CSA1_0# R69 121R
A6 | A2 VSSQ#L11 A6 | A2 VSSQ#L11 (3) CSA1_0#
MAA5 H11 P1 MAA5 H11 P1
MAA4 A5 | A1 VSSQ#P1 MAA4 A5 | A1 VSSQ#P1 CSA0_1# R71 121R
K9 A4 | A0 VSSQ#P4 P4 K9 A4 | A0 VSSQ#P4 P4 (3) CSA0_1#
MAA3 M4 P9 MAA3 M4 P9 CSA1_1# R72 121R
A3 | A9 VSSQ#P9 A3 | A9 VSSQ#P9 (3) CSA1_1#
MAA2 K3 P12 MAA2 K3 P12
MAA1 A2 | A6 VSSQ#P12 MAA1 A2 | A6 VSSQ#P12 CKEA0 R74 121R
H2 A1 | A5 VSSQ#T1 T1 H2 A1 | A5 VSSQ#T1 T1 (3) CKEA0
MAA0 K4 T4 MAA0 K4 T4 CKEA1 R73 121R
A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4 (3) CKEA1
VSSQ#T9 T9 VSSQ#T9 T9
CSA0_0# F9 T12 CSA1_0# F9 T12
CS | CAS VSSQ#T12 CS | CAS VSSQ#T12 CLKA0 R75
VSS A3 VSS A3 (3) CLKA0
C WEA0# H9 A10 WEA1# H9 A10 60.4R C
WE | CKE VSS#A10 WE | CKE VSS#A10 CLKA0# R76
VSS#G1 G1 VSS#G1 G1 (3) CLKA0#
RASA0# H3 G12 RASA1# H3 G12 60.4R
RAS | BA2 VSS#G12 RAS | BA2 VSS#G12
VSS#L1 L1 VSS#L1 L1
CASA0# F4 L12 CASA1# F4 L12 CLKA1 R77
CAS | CS VSS#L12 CAS | CS VSS#L12 (3) CLKA1
V3 V3 60.4R
CKEA0 VSS#V3 CKEA1 VSS#V3 CLKA1# R78
H4 CKE | WE VSS#V10 V10 H4 CKE | WE VSS#V10 V10 (3) CLKA1#
60.4R
CLKA0# J10 B1 CLKA1# J10 B2
CLKA0 CK BLM15BD121SN1 CLKA1 CK BLM15BD121SN1
J11 CK VDDA K1 J11 CK VDDA K1
K12 BLM15BD121SN1 K12 BLM15BD121SN1 +MVDD
RDQSA2 VDDA#K12 B30 RDQSA7 VDDA#K12 B31
P3 RDQS3 | RDQS2 P3 RDQS3 | RDQS2
RDQSA1 P10 RDQSA4 P10
RDQSA3 RDQS2 | RDQS3 C156 RDQSA6 RDQS2 | RDQS3 C155
D10 RDQS1 | RDQS0 D10 RDQS1 | RDQS0
RDQSA0 D3 C293 1uF_6.3V RDQSA5 D3 C292 1uF_6.3V
RDQS0 | RDQS1 1uF_6.3V RDQS0 | RDQS1 1uF_6.3V
WDQSA2 P2 WDQSA7 P2
WDQSA1 WDQS3 | WDQS2 WDQSA4 WDQS3 | WDQS2
P11 WDQS2 | WDQS3 VSSA#J12 J12 P11 WDQS2 | WDQS3 VSSA#J12 J12
WDQSA3 D11 J1 WDQSA6 D11 J1
WDQSA0 WDQS1 | WDQS0 VSSA WDQSA5 WDQS1 | WDQS0 VSSA
D2 WDQS0 | WDQS1 D2 WDQS0 | WDQS1
DQMA#2 N3 J3 CSA0_1# DQMA#7 N3 J3 CSA1_1#
DQMA#1 DM3 | DM2 RFU2 DQMA#4 DM3 | DM2 RFU2
N10 DM2 | DM3 N10 DM2 | DM3
DQMA#3 E10 J2 DQMA#6 E10 J2
DQMA#0 DM1 | DM0 RFU1 DQMA#5 DM1 | DM0 RFU1
E3 DM0 | DM1 E3 DM0 | DM1
+MVDD V4 +MVDD V4
MEM_RST RFU0 MEM_RST RFU0
V9 RESET V9 RESET
R79 R80 A4 R81 R82 A4
2.37K 243R ZQ 2.37K 243R ZQ
VREF = .7*VDDQ H1 VREF = .7*VDDQ H1

VREF VREF
MF A9 MF A9
H12 VREF#H12 H12 VREF#H12
R83 C157 +MVDD GND | VDD R84 C158 +MVDD GND | VDD
5.49K 100nF_6.3V 5.49K 100nF_6.3V
R85 136 FBGA R86 136 FBGA(MIRROR)

B B
2.37K 23C21287ST11 2.37K 23C21287ST11
VREF = .7*VDDQ VREF = .7*VDDQ +MVDD

PLACE VREF DIVIDER COMPONENTS
AS CLOSE TO MEMORY AS POSSIBLE
R87 C170 R88 C173
5.49K 100nF_6.3V 5.49K 100nF_6.3V
C159 C160 C161 C162 C163 C164 C165 C166 C167 C168 C169 C171 C172
1uF_6.3V 1uF_6.3V 10uF_2.5V 10uF_2.5V 10uF_2.5V 10nF 10nF 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
+MVDD
C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 CHAN A GDDR3 136FBGA MEMORY
A A

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Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U5
U4 MDB59 T3 A1
MDB7 MDB58 DQ31 | DQ23 VDDQ
T3 DQ31 | DQ23 VDDQ A1 T2 DQ30 | DQ22 VDDQ#A12 A12
MDB0 T2 A12 MDB56 R3 C1
MDB2 DQ30 | DQ22 VDDQ#A12 MDB60 DQ29 | DQ21 VDDQ#C1
MDB3 R2 C4 MDB63 M3 C9
MDB1 DQ28 | DQ20 VDDQ#C4 MDB62 DQ27 | DQ19 VDDQ#C9
M3 DQ27 | DQ19 VDDQ#C9 C9 N2 DQ26 | DQ18 VDDQ#C12 C12
MDB6 N2 C12 MDB57 L3 E1
MDB5 DQ26 | DQ18 VDDQ#C12 MDB61 DQ25 | DQ17 VDDQ#E1
L3 DQ25 | DQ17 VDDQ#E1 E1 M2 DQ24 | DQ16 VDDQ#E4 E4
MDB4 M2 E4 MDB38 T10 E9
MDB30 DQ24 | DQ16 VDDQ#E4 MDB39 DQ23 | DQ31 VDDQ#E9
MDB28 T11 E12 MDB37 R10 J4
MDB31 DQ22 | DQ30 VDDQ#E12 MDB36 DQ21 | DQ29 VDDQ#J4
MDB27 R11 J9 MDB34 M10 N1
MDB29 DQ20 | DQ28 VDDQ#J9 MDB35 DQ19 | DQ27 VDDQ#N1
M10 DQ19 | DQ27 VDDQ#N1 N1 N11 DQ18 | DQ26 VDDQ#N4 N4
MDB26 N11 N4 MDB32 L10 N9 +MVDD MAB[11..0]
DQ18 | DQ26 VDDQ#N4 +MVDD DQ17 | DQ25 VDDQ#N9 (3) MAB[11..0]
MDB25 L10 N9 MDB33 M11 N12
MDB24 DQ17 | DQ25 VDDQ#N9 MDB49 DQ16 | DQ24 VDDQ#N12 B_BA0
D
M11 DQ16 | DQ24 VDDQ#N12 N12 G10 DQ15 | DQ7 VDDQ#R1 R1 (3) B_BA0 D
MDB21 G10 R1 MDB48 F11 R4 B_BA1
DQ15 | DQ7 VDDQ#R1 DQ14 | DQ6 VDDQ#R4 (3) B_BA1
MDB22 F11 R4 MDB51 F10 R9 B_BA2
DQ14 | DQ6 VDDQ#R4 DQ13 | DQ5 VDDQ#R9 (3) B_BA2
MDB23 F10 R9 MDB50 E11 R12
MDB20 DQ13 | DQ5 VDDQ#R9 MDB55 DQ12 | DQ4 VDDQ#R12 WDQSB[7..0]
E11 DQ12 | DQ4 VDDQ#R12 R12 C10 DQ11 | DQ3 VDDQ#V1 V1 (3) WDQSB[7..0]
MDB19 C10 V1 MDB53 C11 V12
MDB17 DQ11 | DQ3 VDDQ#V1 MDB54 DQ10 | DQ2 VDDQ#V12 RDQSB[7..0]
C11 DQ10 | DQ2 VDDQ#V12 V12 B10 DQ9 | DQ1 (3) RDQSB[7..0]
MDB18 B10 MDB52 B11 A2
MDB16 DQ9 | DQ1 MDB45 DQ8 | DQ0 VDD DQMB#[7..0]
B11 DQ8 | DQ0 VDD A2 G3 DQ7 | DQ15 VDD#A11 A11 (3) DQMB#[7..0]
MDB11 G3 A11 MDB47 F2 F1
MDB10 DQ7 | DQ15 VDD#A11 MDB44 DQ6 | DQ14 VDD#F1 MDB[63..0]
F2 DQ6 | DQ14 VDD#F1 F1 F3 DQ5 | DQ13 VDD#F12 F12 (3) MDB[63..0]
MDB8 F3 F12 MDB46 E2 M1
MDB13 DQ5 | DQ13 VDD#F12 MDB41 DQ4 | DQ12 VDD#M1
E2 DQ4 | DQ12 VDD#M1 M1 C3 DQ3 | DQ11 VDD#M12 M12
MDB12 C3 M12 MDB40 C2 V2
MDB14 DQ3 | DQ11 VDD#M12 MDB43 DQ2 | DQ10 VDD#V2 MEM_RST
C2 DQ2 | DQ10 VDD#V2 V2 B3 DQ1 | DQ9 VDD#V11 V11 (3,6,8,9) MEM_RST
MDB15 B3 V11 MDB42 B2
MDB9 DQ1 | DQ9 VDD#V11 DQ0 | DQ8
B2 DQ0 | DQ8 VSSQ B1
B1 B4 RASB0# R90 121R
VSSQ VSSQ#B4 (3) RASB0#
B4 B_BA2 H10 B9 RASB1# R89 121R
VSSQ#B4 BA2 | RAS VSSQ#B9 (3) RASB1#
B_BA2 H10 B9 B_BA1 G9 B12
B_BA1 BA2 | RAS VSSQ#B9 B_BA0 BA1 | BA0 VSSQ#B12 CASB0# R92 121R
G9 BA1 | BA0 VSSQ#B12 B12 G4 BA0 | BA1 VSSQ#D1 D1 (3) CASB0#
B_BA0 G4 D1 D4 CASB1# R91 121R
BA0 | BA1 VSSQ#D1 VSSQ#D4 (3) CASB1#
D4 MAB11 L4 D9
MAB11 VSSQ#D4 MAB10 A11 | A7 VSSQ#D9 WEB0# R94 121R
L4 A11 | A7 VSSQ#D9 D9 K2 A10 | A8 VSSQ#D12 D12 (3) WEB0#
MAB10 K2 D12 MAB9 M9 G2 WEB1# R93 121R
A10 | A8 VSSQ#D12 A9 | A3 VSSQ#G2 (3) WEB1#
MAB9 M9 G2 MAB8 K11 G11
MAB8 A9 | A3 VSSQ#G2 MAB7 A8/AP | A10 VSSQ#G11 CSB0_0# R95 121R
K11 A8/AP | A10 VSSQ#G11 G11 L9 A7 | A11 VSSQ#L2 L2 (3) CSB0_0#
MAB7 L9 L2 MAB6 K10 L11 CSB1_0# R97 121R
A7 | A11 VSSQ#L2 A6 | A2 VSSQ#L11 (3) CSB1_0#
MAB6 K10 L11 MAB5 H11 P1 CSB0_1# R96 121R
A6 | A2 VSSQ#L11 A5 | A1 VSSQ#P1 (3) CSB0_1#
MAB5 H11 P1 MAB4 K9 P4 CSB1_1# R98 121R
A5 | A1 VSSQ#P1 A4 | A0 VSSQ#P4 (3) CSB1_1#
MAB4 K9 P4 MAB3 M4 P9
MAB3 A4 | A0 VSSQ#P4 MAB2 A3 | A9 VSSQ#P9
M4 A3 | A9 VSSQ#P9 P9 K3 A2 | A6 VSSQ#P12 P12
MAB2 K3 P12 MAB1 H2 T1 CKEB0 R100 121R
A2 | A6 VSSQ#P12 A1 | A5 VSSQ#T1 (3) CKEB0
MAB1 H2 T1 MAB0 K4 T4 CKEB1 R99 121R
A1 | A5 VSSQ#T1 A0 | A4 VSSQ#T4 (3) CKEB1
MAB0 K4 T4 T9
A0 | A4 VSSQ#T4 CSB1_0# VSSQ#T9
VSSQ#T9 T9 F9 CS | CAS VSSQ#T12 T12
CSB0_0# F9 T12 A3 CLKB0 R101
CS | CAS VSSQ#T12 VSS (3) CLKB0
A3 WEB1# H9 A10 60.4R
WEB0# VSS WE | CKE VSS#A10 CLKB0# R102
C H9 WE | CKE VSS#A10 A10 VSS#G1 G1 (3) CLKB0# C
G1 RASB1# H3 G12 60.4R
RASB0# VSS#G1 RAS | BA2 VSS#G12
H3 RAS | BA2 VSS#G12 G12 VSS#L1 L1
L1 CASB1# F4 L12 CLKB1 R103
VSS#L1 CAS | CS VSS#L12 (3) CLKB1
CASB0# F4 L12 V3 60.4R
CAS | CS VSS#L12 CKEB1 VSS#V3 CLKB1# R104
VSS#V3 V3 H4 CKE | WE VSS#V10 V10 (3) CLKB1#
CKEB0 H4 V10 60.4R
CKE | WE VSS#V10 CLKB1# B4
J10 CK
CLKB0# J10 B3 CLKB1 J11 K1 BLM15BD121SN1
CLKB0 CK BLM15BD121SN1 CK VDDA BLM15BD121SN1 +MVDD
J11 CK VDDA K1 VDDA#K12 K12
K12 BLM15BD121SN1 RDQSB7 P3 B33
RDQSB0 VDDA#K12 B32 RDQSB4 RDQS3 | RDQS2
P3 RDQS3 | RDQS2 P10 RDQS2 | RDQS3
RDQSB3 P10 RDQSB6 D10 C295 C187
RDQSB2 RDQS2 | RDQS3 RDQSB5 RDQS1 | RDQS0 1uF_6.3V 1uF_6.3V
RDQSB1 D3 RDQS0 | RDQS1 C294 C188 WDQSB7 P2 WDQS3 | WDQS2
WDQSB0 P2 1uF_6.3V 1uF_6.3V WDQSB4 P11 J12
WDQSB3 WDQS3 | WDQS2 WDQSB6 WDQS2 | WDQS3 VSSA#J12
P11 WDQS2 | WDQS3 VSSA#J12 J12 D11 WDQS1 | WDQS0 VSSA J1
WDQSB2 D11 J1 WDQSB5 D2
WDQSB1 WDQS1 | WDQS0 VSSA WDQS0 | WDQS1
D2 WDQS0 | WDQS1 DQMB#7 N3 J3 CSB1_1#
DQMB#0 CSB0_1# DQMB#4 DM3 | DM2 RFU2
N3 DM3 | DM2 RFU2 J3 N10 DM2 | DM3
DQMB#3 N10 DQMB#6 E10 J2
DQMB#2 DM2 | DM3 DQMB#5 DM1 | DM0 RFU1
E10 DM1 | DM0 RFU1 J2 E3 DM0 | DM1
DQMB#1 E3 +MVDD V4
+MVDD DM0 | DM1 MEM_RST RFU0
RFU0 V4 V9 RESET
MEM_RST V9 RESET R107 R108 A4 ZQ
R105 R106 A4 2.37K 243R
2.37K 243R ZQ
VREF = .7*VDDQ H1
VREF = .7*VDDQ VREF
H1 VREF MF A9
MF A9 H12 VREF#H12
H12 C190 +MVDD GND | VDD
R109 C189 +MVDD VREF#H12 GND | VDD R110 100nF_6.3V
5.49K 100nF_6.3V 5.49K
R112 136 FBGA(MIRROR)
R111 136 FBGA 2.37K 23C21287ST11
B B
2.37K 23C21287ST11
VREF = .7*VDDQ
VREF = .7*VDDQ +MVDD
AS CLOSE TO MEMORY AS POSSIBLE R114 C192
R113 C191 5.49K 100nF_6.3V
5.49K 100nF_6.3V
C193 C194 C195 C196 C197 C198 C199 C200 C201 C202 C203 C204 C205
+MVDD
CHAN B GDDR3 136FBGA MEMORY

C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U6 U7
MDC7 T3 A1 MDC59 T3 A1
MDC6 DQ31 | DQ23 VDDQ MDC58 DQ31 | DQ23 VDDQ
MDC4 R3 C1 MDC57 R3 C1
MDC5 DQ29 | DQ21 VDDQ#C1 MDC56 DQ29 | DQ21 VDDQ#C1
MDC1 M3 C9 MDC63 M3 C9
MDC3 DQ27 | DQ19 VDDQ#C9 MDC62 DQ27 | DQ19 VDDQ#C9
MDC2 L3 E1 MDC60 L3 E1
MDC0 DQ25 | DQ17 VDDQ#E1 MDC61 DQ25 | DQ17 VDDQ#E1
MDC18 T10 E9 MDC32 T10 E9
MDC17 DQ23 | DQ31 VDDQ#E9 MDC34 DQ23 | DQ31 VDDQ#E9
MDC16 R10 J4 MDC35 R10 J4
MDC23 DQ21 | DQ29 VDDQ#J4 MDC33 DQ21 | DQ29 VDDQ#J4
MDC19 M10 N1 MDC36 M10 N1
MDC21 DQ19 | DQ27 VDDQ#N1 MDC37 DQ19 | DQ27 VDDQ#N1
MDC20 L10 N9 +MVDD MDC38 L10 N9 +MVDD MAC[11..0]
DQ17 | DQ25 VDDQ#N9 DQ17 | DQ25 VDDQ#N9 (4) MAC[11..0]
MDC22 M11 N12 MDC39 M11 N12
MDC24 DQ16 | DQ24 VDDQ#N12 MDC48 DQ16 | DQ24 VDDQ#N12 C_BA0
D
G10 DQ15 | DQ7 VDDQ#R1 R1 G10 DQ15 | DQ7 VDDQ#R1 R1 (4) C_BA0 D
MDC26 F11 R4 MDC49 F11 R4 C_BA1
DQ14 | DQ6 VDDQ#R4 DQ14 | DQ6 VDDQ#R4 (4) C_BA1
MDC27 F10 R9 MDC51 F10 R9 C_BA2
DQ13 | DQ5 VDDQ#R9 DQ13 | DQ5 VDDQ#R9 (4) C_BA2
MDC25 E11 R12 MDC50 E11 R12
MDC31 DQ12 | DQ4 VDDQ#R12 MDC54 DQ12 | DQ4 VDDQ#R12 WDQSC[7..0]
C10 DQ11 | DQ3 VDDQ#V1 V1 C10 DQ11 | DQ3 VDDQ#V1 V1 (4) WDQSC[7..0]
MDC28 C11 V12 MDC53 C11 V12
MDC29 DQ10 | DQ2 VDDQ#V12 MDC55 DQ10 | DQ2 VDDQ#V12 RDQSC[7..0]
B10 DQ9 | DQ1 B10 DQ9 | DQ1 (4) RDQSC[7..0]
MDC30 B11 A2 MDC52 B11 A2
MDC12 DQ8 | DQ0 VDD MDC40 DQ8 | DQ0 VDD DQMC#[7..0]
G3 DQ7 | DQ15 VDD#A11 A11 G3 DQ7 | DQ15 VDD#A11 A11 (4) DQMC#[7..0]
MDC13 F2 F1 MDC42 F2 F1
MDC14 DQ6 | DQ14 VDD#F1 MDC41 DQ6 | DQ14 VDD#F1 MDC[63..0]
F3 DQ5 | DQ13 VDD#F12 F12 F3 DQ5 | DQ13 VDD#F12 F12 (4) MDC[63..0]
MDC15 E2 M1 MDC43 E2 M1
MDC8 DQ4 | DQ12 VDD#M1 MDC47 DQ4 | DQ12 VDD#M1
MDC9 C2 V2 MDC45 C2 V2
MDC10 DQ2 | DQ10 VDD#V2 MDC44 DQ2 | DQ10 VDD#V2 MEM_RST
MDC11 B2 MDC46 B2
DQ0 | DQ8 DQ0 | DQ8
VSSQ B1 VSSQ B1
B4 B4 RASC0# R116 121R
VSSQ#B4 VSSQ#B4 (4) RASC0#
C_BA2 H10 B9 C_BA2 H10 B9 RASC1# R115 121R
BA2 | RAS VSSQ#B9 BA2 | RAS VSSQ#B9 (4) RASC1#
C_BA1 G9 B12 C_BA1 G9 B12
C_BA0 BA1 | BA0 VSSQ#B12 C_BA0 BA1 | BA0 VSSQ#B12 CASC0# R118 121R
G4 BA0 | BA1 VSSQ#D1 D1 G4 BA0 | BA1 VSSQ#D1 D1 (4) CASC0#
D4 D4 CASC1# R117 121R
VSSQ#D4 VSSQ#D4 (4) CASC1#
MAC11 L4 D9 MAC11 L4 D9
MAC10 A11 | A7 VSSQ#D9 MAC10 A11 | A7 VSSQ#D9 WEC0# R120 121R
K2 A10 | A8 VSSQ#D12 D12 K2 A10 | A8 VSSQ#D12 D12 (4) WEC0#
MAC9 M9 G2 MAC9 M9 G2 WEC1# R119 121R
A9 | A3 VSSQ#G2 A9 | A3 VSSQ#G2 (4) WEC1#
MAC8 K11 G11 MAC8 K11 G11
MAC7 A8/AP | A10 VSSQ#G11 MAC7 A8/AP | A10 VSSQ#G11 CSC0_0# R121 121R
L9 A7 | A11 VSSQ#L2 L2 L9 A7 | A11 VSSQ#L2 L2 (4) CSC0_0#
MAC6 K10 L11 MAC6 K10 L11 CSC1_0# R123 121R
A6 | A2 VSSQ#L11 A6 | A2 VSSQ#L11 (4) CSC1_0#
MAC5 H11 P1 MAC5 H11 P1 CSC0_1# R122 121R
A5 | A1 VSSQ#P1 A5 | A1 VSSQ#P1 (4) CSC0_1#
MAC4 K9 P4 MAC4 K9 P4 CSC1_1# R124 121R
A4 | A0 VSSQ#P4 A4 | A0 VSSQ#P4 (4) CSC1_1#
MAC3 M4 P9 MAC3 M4 P9
MAC2 A3 | A9 VSSQ#P9 MAC2 A3 | A9 VSSQ#P9
K3 A2 | A6 VSSQ#P12 P12 K3 A2 | A6 VSSQ#P12 P12
MAC1 H2 T1 MAC1 H2 T1 CKEC0 R126 121R
A1 | A5 VSSQ#T1 A1 | A5 VSSQ#T1 (4) CKEC0
MAC0 K4 T4 MAC0 K4 T4 CKEC1 R125 121R
A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4 (4) CKEC1
CSC0_0# F9 T12 CSC1_0# F9 T12
CS | CAS VSSQ#T12 CS | CAS VSSQ#T12 CLKC0 R127
VSS A3 VSS A3 (4) CLKC0
WEC0# H9 A10 WEC1# H9 A10 60.4R
WE | CKE VSS#A10 WE | CKE VSS#A10 CLKC0# R128
C
VSS#G1 G1 VSS#G1 G1 (4) CLKC0# C
RASC0# H3 G12 RASC1# H3 G12 60.4R
VSS#L1 L1 VSS#L1 L1
CASC0# F4 L12 CASC1# F4 L12 CLKC1 R129
CAS | CS VSS#L12 CAS | CS VSS#L12 (4) CLKC1
V3 V3 60.4R
CKEC0 VSS#V3 CKEC1 VSS#V3 CLKC1# R130
H4 CKE | WE VSS#V10 V10 H4 CKE | WE VSS#V10 V10 (4) CLKC1#
60.4R
CLKC0# J10 B5 CLKC1# J10 B6
CLKC0 CK BLM15BD121SN1 CLKC1 CK BLM15BD121SN1
RDQSC0 VDDA#K12 B34 RDQSC7 VDDA#K12
P3 RDQS3 | RDQS2 P3 RDQS3 | RDQS2 B35
RDQSC2 P10 RDQSC4 P10
RDQSC3 RDQS2 | RDQS3 C296 RDQSC6 RDQS2 | RDQS3 C297 C219
RDQSC1 D3 1uF_6.3V C220 RDQSC5 D3 1uF_6.3V 1uF_6.3V
RDQS0 | RDQS1 1uF_6.3V RDQS0 | RDQS1
WDQSC0 P2 WDQSC7 P2
WDQSC2 WDQS3 | WDQS2 WDQSC4 WDQS3 | WDQS2
WDQSC3 D11 J1 WDQSC6 D11 J1
WDQSC1 WDQS1 | WDQS0 VSSA WDQSC5 WDQS1 | WDQS0 VSSA
DQMC#0 N3 J3 CSC0_1# DQMC#7 N3 J3 CSC1_1#
DQMC#2 DM3 | DM2 RFU2 DQMC#4 DM3 | DM2 RFU2
N10 DM2 | DM3 N10 DM2 | DM3
DQMC#3 E10 J2 DQMC#6 E10 J2
DQMC#1 DM1 | DM0 RFU1 DQMC#5 DM1 | DM0 RFU1
+MVDD V4 +MVDD V4
V9 RESET V9 RESET
R131 R132 A4 R133 R134 A4
2.37K 243R ZQ 2.37K 243R ZQ

VREF VREF
MF A9 MF A9
R135 +MVDD GND | VDD R136 C222 +MVDD GND | VDD
5.49K C221 5.49K 100nF_6.3V
100nF_6.3V
2.37K 23C21287ST11 2.37K 23C21287ST11
B B
VREF = .7*VDDQ VREF = .7*VDDQ
AS CLOSE TO MEMORY AS POSSIBLE +MVDD
R139 C223 R140 C224
5.49K 100nF_6.3V 5.49K 100nF_6.3V
C225 C226 C227 C228 C229 C230 C231 C232 C233 C234 C235 C236 C237
+MVDD
CHAN C GDDR3 136FBGA MEMORY

C238 C239 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249 C250
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
U8 U9
MDD19 T3 A1 MDD49 T3 A1
MDD16 DQ31 | DQ23 VDDQ MDD48 DQ31 | DQ23 VDDQ
MDD17 R3 C1 MDD54 R3 C1
MDD18 DQ29 | DQ21 VDDQ#C1 MDD50 DQ29 | DQ21 VDDQ#C1
MDD20 M3 C9 MDD52 M3 C9
MDD22 DQ27 | DQ19 VDDQ#C9 MDD53 DQ27 | DQ19 VDDQ#C9
MDD21 L3 E1 MDD51 L3 E1
MDD23 DQ25 | DQ17 VDDQ#E1 MDD55 DQ25 | DQ17 VDDQ#E1
MDD31 T10 E9 MDD41 T10 E9
MDD24 DQ23 | DQ31 VDDQ#E9 MDD42 DQ23 | DQ31 VDDQ#E9
MDD27 R10 J4 MDD40 R10 J4
MDD26 DQ21 | DQ29 VDDQ#J4 MDD43 DQ21 | DQ29 VDDQ#J4
MDD28 M10 N1 MDD47 M10 N1
MDD25 DQ19 | DQ27 VDDQ#N1 MDD44 DQ19 | DQ27 VDDQ#N1
MDD29 L10 N9 +MVDD MDD45 L10 N9 +MVDD MAD[11..0]
DQ17 | DQ25 VDDQ#N9 DQ17 | DQ25 VDDQ#N9 (4) MAD[11..0]
MDD30 M11 N12 MDD46 M11 N12
MDD7 DQ16 | DQ24 VDDQ#N12 MDD58 DQ16 | DQ24 VDDQ#N12 D_BA0
D
G10 DQ15 | DQ7 VDDQ#R1 R1 G10 DQ15 | DQ7 VDDQ#R1 R1 (4) D_BA0 D
MDD6 F11 R4 MDD56 F11 R4 D_BA1
DQ14 | DQ6 VDDQ#R4 DQ14 | DQ6 VDDQ#R4 (4) D_BA1
MDD5 F10 R9 MDD57 F10 R9 D_BA2
DQ13 | DQ5 VDDQ#R9 DQ13 | DQ5 VDDQ#R9 (4) D_BA2
MDD4 E11 R12 MDD60 E11 R12
MDD0 DQ12 | DQ4 VDDQ#R12 MDD63 DQ12 | DQ4 VDDQ#R12 WDQSD[7..0]
C10 DQ11 | DQ3 VDDQ#V1 V1 C10 DQ11 | DQ3 VDDQ#V1 V1 (4) WDQSD[7..0]
MDD3 C11 V12 MDD61 C11 V12
MDD2 DQ10 | DQ2 VDDQ#V12 MDD59 DQ10 | DQ2 VDDQ#V12 RDQSD[7..0]
B10 DQ9 | DQ1 B10 DQ9 | DQ1 (4) RDQSD[7..0]
MDD1 B11 A2 MDD62 B11 A2
MDD8 DQ8 | DQ0 VDD MDD34 DQ8 | DQ0 VDD DQMD#[7..0]
G3 DQ7 | DQ15 VDD#A11 A11 G3 DQ7 | DQ15 VDD#A11 A11 (4) DQMD#[7..0]
MDD11 F2 F1 MDD32 F2 F1
MDD10 DQ6 | DQ14 VDD#F1 MDD33 DQ6 | DQ14 VDD#F1 MDD[63..0]
F3 DQ5 | DQ13 VDD#F12 F12 F3 DQ5 | DQ13 VDD#F12 F12 (4) MDD[63..0]
MDD12 E2 M1 MDD36 E2 M1
MDD15 DQ4 | DQ12 VDD#M1 MDD39 DQ4 | DQ12 VDD#M1
MDD14 C2 V2 MDD35 C2 V2
MDD13 DQ2 | DQ10 VDD#V2 MDD38 DQ2 | DQ10 VDD#V2 MEM_RST
MDD9 B2 MDD37 B2
DQ0 | DQ8 DQ0 | DQ8
VSSQ B1 VSSQ B1
B4 B4 RASD0# R142 121R
VSSQ#B4 VSSQ#B4 (4) RASD0#
D_BA2 H10 B9 D_BA2 H10 B9 RASD1# R141 121R
BA2 | RAS VSSQ#B9 BA2 | RAS VSSQ#B9 (4) RASD1#
D_BA1 G9 B12 D_BA1 G9 B12
D_BA0 BA1 | BA0 VSSQ#B12 D_BA0 BA1 | BA0 VSSQ#B12 CASD0# R144 121R
G4 BA0 | BA1 VSSQ#D1 D1 G4 BA0 | BA1 VSSQ#D1 D1 (4) CASD0#
D4 D4 CASD1# R143 121R
VSSQ#D4 VSSQ#D4 (4) CASD1#
MAD11 L4 D9 MAD11 L4 D9
MAD10 A11 | A7 VSSQ#D9 MAD10 A11 | A7 VSSQ#D9 WED0# R145 121R
K2 A10 | A8 VSSQ#D12 D12 K2 A10 | A8 VSSQ#D12 D12 (4) WED0#
MAD9 M9 G2 MAD9 M9 G2 WED1# R146 121R
A9 | A3 VSSQ#G2 A9 | A3 VSSQ#G2 (4) WED1#
MAD8 K11 G11 MAD8 K11 G11
MAD7 A8/AP | A10 VSSQ#G11 MAD7 A8/AP | A10 VSSQ#G11 CSD0_0# R147 121R
L9 A7 | A11 VSSQ#L2 L2 L9 A7 | A11 VSSQ#L2 L2 (4) CSD0_0#
MAD6 K10 L11 MAD6 K10 L11 CSD1_0# R148 121R
A6 | A2 VSSQ#L11 A6 | A2 VSSQ#L11 (4) CSD1_0#
MAD5 H11 P1 MAD5 H11 P1 CSD0_1# R149 121R
A5 | A1 VSSQ#P1 A5 | A1 VSSQ#P1 (4) CSD0_1#
MAD4 K9 P4 MAD4 K9 P4 CSD1_1# R150 121R
A4 | A0 VSSQ#P4 A4 | A0 VSSQ#P4 (4) CSD1_1#
MAD3 M4 P9 MAD3 M4 P9
MAD2 A3 | A9 VSSQ#P9 MAD2 A3 | A9 VSSQ#P9
K3 A2 | A6 VSSQ#P12 P12 K3 A2 | A6 VSSQ#P12 P12
MAD1 H2 T1 MAD1 H2 T1 CKED0 R152 121R
A1 | A5 VSSQ#T1 A1 | A5 VSSQ#T1 (4) CKED0
MAD0 K4 T4 MAD0 K4 T4 CKED1 R151 121R
A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4 (4) CKED1
CSD0_0# F9 T12 CSD1_0# F9 T12
CS | CAS VSSQ#T12 CS | CAS VSSQ#T12 CLKD0 R153
VSS A3 VSS A3 (4) CLKD0
WED0# H9 A10 WED1# H9 A10 60.4R
WE | CKE VSS#A10 WE | CKE VSS#A10 CLKD0# R154
C
VSS#G1 G1 VSS#G1 G1 (4) CLKD0# C
RASD0# H3 G12 RASD1# H3 G12 60.4R
VSS#L1 L1 VSS#L1 L1
CASD0# F4 L12 CASD1# F4 L12 CLKD1 R155
CAS | CS VSS#L12 CAS | CS VSS#L12 (4) CLKD1
V3 V3 60.4R
CKED0 VSS#V3 CKED1 VSS#V3 CLKD1# R156
H4 CKE | WE VSS#V10 V10 H4 CKE | WE VSS#V10 V10 (4) CLKD1#
60.4R
CLKD0# J10 B8 CLKD1# J10 B7
CLKD0 CK BLM15BD121SN1 CLKD1 CK BLM15BD121SN1
RDQSD2 VDDA#K12 B36 RDQSD6 VDDA#K12
P3 RDQS3 | RDQS2 P3 RDQS3 | RDQS2 B37
RDQSD3 P10 RDQSD5 P10
RDQSD0 RDQS2 | RDQS3 C298 C252 RDQSD7 RDQS2 | RDQS3 C299 C251
RDQSD1 D3 1uF_6.3V 1uF_6.3V RDQSD4 D3 1uF_6.3V 1uF_6.3V
RDQS0 | RDQS1 RDQS0 | RDQS1
WDQSD2 P2 WDQSD6 P2
WDQSD3 WDQS3 | WDQS2 WDQSD5 WDQS3 | WDQS2
WDQSD0 D11 J1 WDQSD7 D11 J1
WDQSD1 WDQS1 | WDQS0 VSSA WDQSD4 WDQS1 | WDQS0 VSSA
DQMD#2 N3 J3 CSD0_1# DQMD#6 N3 J3 CSD1_1#
DQMD#3 DM3 | DM2 RFU2 DQMD#5 DM3 | DM2 RFU2
N10 DM2 | DM3 N10 DM2 | DM3
DQMD#0 E10 J2 DQMD#7 E10 J2
DQMD#1 DM1 | DM0 RFU1 DQMD#4 DM1 | DM0 RFU1
+MVDD V4 +MVDD V4
V9 RESET V9 RESET
R157 R158 A4 R159 R160 A4
2.37K 243R ZQ 2.37K 243R ZQ

VREF VREF
MF A9 MF A9
R161 C253 +MVDD GND | VDD R162 C254 +MVDD GND | VDD
5.49K 100nF_6.3V 5.49K 100nF_6.3V

2.37K 23C21287ST11 2.37K 23C21287ST11
B B
VREF = .7*VDDQ VREF = .7*VDDQ
AS CLOSE TO MEMORY AS POSSIBLE +MVDD
R165 C255 R166 C256
5.49K 100nF_6.3V 5.49K 100nF_6.3V
C257 C258 C259 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269
+MVDD
C270 C271 C272 C273 C274 C275 C276 C277 C278 C279 C280 C281 C282
CHAN D GDDR3 BGA MEMORY
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
+3VRUN +3VRUN
J1A +3VRUN
G_PWR_SRC E1 E2 C939 100nF_6.3V
PWR_SRC_E1 PWR_SRC_E2 R6095
E3 GND_E3 GND_E4 E4
C283 C288 C289 Part 1 of 2 R195 100K NC7SZ08P5X_NL
5
100nF_50V 100nF_50V 1nF 1 2 R194 0R 100K
5V_1 PRSNT_R#_2
3 5V_3 WAKE#_4 4 (12) CTFb 1
5 5V_5 PWR_GOOD_6 6 PWRGOOD (11) 4 RUNPWROK (11)
7 5V_7 PWR_EN_8 8 2
9 10 R488 0R U34
+5VRUN 5V_9 RSVD_10
11 12
3
C291 C290 GND_11 RSVD_12
13 GND_13 RSVD_14 14
1uF_6.3V 100nF_6.3V 15 16
GND_15 RSVD_16 R171 0R
17 GND_17 PWR_LEVEL_18 18 PWR_LEVEL (2) CTFb (12)
19 20 TH_OVERT#
(11) PEX_STD_SW# PEX_STD_SW#_19 TH_OVERT#_20 MB_THERMB (11)
21 22 TH_ALERT#
(11) VGA_DISABLE# VGA_DISABLE#_21 TH_ALERT#_22 GPIO17_THERMAL_INT (2,11)
FPVCC_MB 23 24 TH_PWM
PNL_PWR_EN_23 TH_PWM_24 TH_PWM (11)
BL_ENA 25 26 MB_GPIO0 GENERICA (2)
D
BL_BRIGHT_MB PNL_BL_EN_25 GPIO0_26 MB_GPIO1 D
27 PNL_PWM_27 GPIO1_28 28 GENERICB (2)
29 30 MB_GPIO2 GENERICD (2) R169
HPD_DVI HDMI_CEC_29 GPIO2_30 SMB_DAT 100K
31 DVI_HPD_31 SMB_DAT_32 32
LVDS_DDC_DAT 33 34 SMB_CLK
LVDS_DDC_CLK LVDS_DDC_DAT_33 SMB_CLK_34
35 LVDS_DDC_CLK_35 GND_36 36
37 GND_37 OEM_38 38
39 40 VDDR3 VDDR3 VDDR3
OEM_39 OEM_40
41 OEM_41 OEM_42 42
43 OEM_43 OEM_44 44
45 OEM_45 GND_46 46
47 48 PCIE_RXN15
PCIE_TXN15 GND_47 PEX_TX15#_48 PCIE_RXP15
49 PEX_RX15#_49 PEX_TX15_50 50
VGA_RED PCIE_TXP15 51 52
(2) VGA_RED PEX_RX15_51 GND_52
VGA_GRN 53 54 PCIE_RXN14
(2) VGA_GRN GND_53 PEX_TX14#_54
VGA_BLU PCIE_TXN14 55 56 PCIE_RXP14
(2) VGA_BLU PEX_RX14#_55 PEX_TX14_56
PCIE_TXP14 57 58
PEX_RX14_57 GND_58 PCIE_RXN13
59 GND_59 PEX_TX13#_60 60
PCIE_REFCLKP PCIE_TXN13 61 62 PCIE_RXP13
(1) PCIE_REFCLKP PEX_RX13#_61 PEX_TX13_62
PCIE_REFCLKN PCIE_TXP13 63 64
(1) PCIE_REFCLKN PEX_RX13_63 GND_64
65 66 PCIE_RXN12
PCIE_TXN12 GND_65 PEX_TX12#_66 PCIE_RXP12
67 PEX_RX12#_67 PEX_TX12_68 68
PCIE_TXP12 69 70
PCIE_RXP[15..0] PEX_RX12_69 GND_70 PCIE_RXN11
(1) PCIE_RXP[15..0] 71 GND_71 PEX_TX11#_72 72
PCIE_TXN11 73 74 PCIE_RXP11 R172 0R
PCIE_RXN[15..0] PCIE_TXP11 PEX_RX11#_73 PEX_TX11_74
(1) PCIE_RXN[15..0] 75 PEX_RX11_75 GND_76 76
77 78 PCIE_RXN10 BL_ENA
PCIE_TXP[15..0] GND_77 PEX_TX10#_78 BLON_PWM (2)
PCIE_TXN10 79 80 PCIE_RXP10
(1) PCIE_TXP[15..0] PEX_RX10#_79 PEX_TX10_80
PCIE_TXP10 81 82 R174 0R
PCIE_TXN[15..0] PEX_RX10_81 GND_82 OPT_BL_ENA (2)
83 84 PCIE_RXN9
(1) PCIE_TXN[15..0] GND_83 PEX_TX9#_84
PCIE_TXN9 85 86 PCIE_RXP9
PCIE_TXP9 PEX_RX9#_85 PEX_TX9_86
87 PEX_RX9_87 GND_88 88
89 90 PCIE_RXN8 The circuit is an option to prevent the leakage from LCD
RUNPWROK PCIE_TXN8 GND_89 PEX_TX8#_90 PCIE_RXP8
(11) RUNPWROK 91 PEX_RX8#_91 PEX_TX8_92 92
PCIE_TXP8 93 94
PEX_RX8_93 GND_94 PCIE_RXN7
95 GND_95 PEX_TX7#_96 96
TXOUT_L0- PCIE_TXN7 97 98 PCIE_RXP7
(2) TXOUT_L0- PEX_RX7#_97 PEX_TX7_98 U12
TXOUT_L0+ PCIE_TXP7 99 100
(2) TXOUT_L0+ PEX_RX7_99 GND_100
C TXOUT_L1- 101 102 PCIE_RXN6 BL_BRIGHT_MB 6 2 BL_BRIGHT C
(2) TXOUT_L1- GND_101 PEX_TX6#_102 1Y 1A
TXOUT_L1+ PCIE_TXN6 103 104 PCIE_RXP6 FPVCC_MB 3 5
(2) TXOUT_L1+ PEX_RX6#_103 PEX_TX6_104 2Y 2A FPVCC (2)
TXOUT_L2- PCIE_TXP6 105 106
(2) TXOUT_L2- PEX_RX6_105 GND_106 +3VRUN
TXOUT_L2+ 107 108 PCIE_RXN5 8 1 R175 0R
(2) TXOUT_L2+ GND_107 PEX_TX5#_108 VCC 1OE PWRGOOD (11)
TXOUT_L3- PCIE_TXN5 109 110 PCIE_RXP5 R168 4 7
(2) TXOUT_L3- PEX_RX5#_109 PEX_TX5_110 GND 2OE
TXOUT_L3+ PCIE_TXP5 111 112 10K
(2) TXOUT_L3+ PEX_RX5_111 GND_112
TXCLK_L- 113 114 PCIE_RXN4 C304 74LVC2G126 C305
(2) TXCLK_L- GND_113 PEX_TX4#_114
TXCLK_L+ PCIE_TXN4 115 116 PCIE_RXP4 100nF_6.3V 100nF_6.3V
(2) TXCLK_L+ PEX_RX4#_115 PEX_TX4_116
PCIE_TXP4 117 118
TXOUT_U0- PEX_RX4_117 GND_118 PCIE_RXN3
(2) TXOUT_U0- 119 GND_119 PEX_TX3#_120 120
TXOUT_U0+ PCIE_TXN3 121 122 PCIE_RXP3
(2) TXOUT_U0+ PEX_RX3#_121 PEX_TX3_122
TXOUT_U1- PCIE_TXP3 123 124
(2) TXOUT_U1- PEX_RX3_123 GND_124
TXOUT_U1+ 125
(2) TXOUT_U1+ GND_125
TXOUT_U2- Mechanical Key
(2) TXOUT_U2-
TXOUT_U2+ 133 134
(2) TXOUT_U2+ GND_133 GND_134
TXOUT_U3- PCIE_TXN2 135 136 PCIE_RXN2 BL_BRIGHT_MB BL_BRIGHT
(2) TXOUT_U3- PEX_RX2#_135 PEX_TX2#_136
TXOUT_U3+ PCIE_TXP2 137 138 PCIE_RXP2
(2) TXOUT_U3+ PEX_RX2_137 PEX_TX2_138
TXCLK_U- 139 140 FPVCC_MB
(2) TXCLK_U- GND_139 GND_140 FPVCC (2)
TXCLK_U+ PCIE_TXN1 141 142 PCIE_RXN1
(2) TXCLK_U+ PEX_RX1#_141 PEX_TX1#_142
PCIE_TXP1 143 144 PCIE_RXP1
LVDS_DDC_CLK PEX_RX1_143 PEX_TX1_144
(2) I2C_CLK 145 GND_145 GND_146 146
LVDS_DDC_DAT PCIE_TXN0 147 148 PCIE_RXN0
(2) I2C_DAT PEX_RX0#_147 PEX_TX0#_148
PCIE_TXP0 149 150 PCIE_RXP0
FPVCC PEX_RX0_149 PEX_TX0_150
(2) FPVCC 151 GND_151 GND_152 152
PCIE_REFCLKN 153 154
PCIE_REFCLKP PEX_REFCLK#_153 CLK_REQ#_154 CLKREQB (2)
155 PEX_REFCLK_155 PEX_RST#_156 156 PCIE_RST# (1,12)
157 GND_157 VGA_DDC_DAT_158 158
159 RSVD_159 VGA_DDC_CLK_160 160
161 RSVD_161 VGA_VSYC_162 162 VSYNC (2,11)
163 RSVD_163 VGA_HSYC_164 164 HSYNC (2,11)
165 RSVD_165 GND_166 166
167 168 VGA_RED
TXCLK_U- RSVD_167 VGA_RED_168 VGA_GRN
169 LVDS_UCLK#_169 VGA_GREEN_170 170
TXCLK_U+ 171 172 VGA_BLU
LVDS_UCLK_171 VGA_BLUE_172
173 GND_173 GND_174 174 DDC1CLK (2)
TXOUT_U3- 175 176 TXCLK_L- +3VRUN
LVDS_UTX3#_175 LVDS_LCLK#_176 DDC1DAT (2)
TXOUT_U3+ 177 178 TXCLK_L+
LVDS_UTX3_177 LVDS_LCLK_178 VDDR3
B
179 GND_179 GND_180 180 B
TXOUT_U2- 181 182 TXOUT_L3- R189 R188
TXOUT_U2+ LVDS_UTX2#_181 LVDS_LTX3#_182 TXOUT_L3+ 4.7K 4.7K PBATB_SMBCLK
183 LVDS_UTX2_183 LVDS_LTX3_184 184
185 186 SMB_CLK PBATB_SMBDAT
TXOUT_U1- GND_185 GND_186 TXOUT_L2- SMB_DAT
187 LVDS_UTX1#_187 LVDS_LTX2#_188 188
TXOUT_U1+ 189 190 TXOUT_L2+
LVDS_UTX1_189 LVDS_LTX2_190
191 GND_191 GND_192 192
TXOUT_U0- 193 194 TXOUT_L1- VDDR3
TXOUT_U0+ LVDS_UTX0#_193 LVDS_LTX1#_194 TXOUT_L1+
195 LVDS_UTX0_195 LVDS_LTX1_196 196
197 198 0R R7
DPB0N GND_197 GND_198 TXOUT_L0- 0R R8
(2) DPB0N 199 DP_C_L0#_199 LVDS_LTX0#_200 200
(2) DPB0P DPB0P 201 202 TXOUT_L0+
DP_C_L0_201 LVDS_LTX0_202 To Bypass U12
203 GND_203 GND_204 204
(2) DPB1N DPB1N 205 206
DPB1P DP_C_L1#_205 DP_D_L0#_206
(2) DPB1P 207 DP_C_L1_207 DP_D_L0_208 208
209 GND_209 GND_210 210
(2) HPD3 HPD_DPB (2) DPB2N DPB2N 211 212
DPB2P DP_C_L2#_211 DP_D_L1#_212
(2) DPB2P 213 DP_C_L2_213 DP_D_L1_214 214
R180 215 216
100K DPB3N GND_215 GND_216
(2) DPB3N 217 DP_C_L3#_217 DP_D_L2#_218 218
(2) DPB3P DBP3P 219 220
DP_C_L3_219 DP_D_L2_220
221 GND_221 GND_222 222
(2) DPB_AUXN 223 DP_C_AUX#_223 DP_D_L3#_224 224
(2) DPB_AUXP 225 DP_C_AUX_225 DP_D_L3_226 226
227 RSVD_227 GND_228 228
229 RSVD_229 DP_D_AUX#_230 230
HPD_DPA 231 232
(2) HPD2 RSVD_231 DP_D_AUX_232
233 234 HPD_DPB
R181 RSVD_233 DP_C_HPD_234 VDDR3 VDDR3
235 RSVD_235 DP_D_HPD_236 236
100K 237 238
RSVD_237 RSVD_238
239 RSVD_239 RSVD_240 240
241 RSVD_241 RSVD_242 242
243 244 R248 R249
RSVD_243 GND_244 100K 100K
245 RSVD_245 DP_B_L0#_246 246
247 RSVD_247 DP_B_L0_248 248
HPD_DVI 249 250 PBATB_SMBCLK R250 0R
(2) HPD1 RSVD_249 GND_250 PBAT_SMBCLK (11)
251 252 PBATB_SMBDAT R251 0R
GND_251 DP_B_L1#_252 PBAT_SMBDAT (11)
R201 (2) DPA0N DPA0N 253 254
100K DPA0P DP_A_L0#_253 DP_B_L1_254
A (2) DPA0P 255 DP_A_L0_255 GND_256 256 GPIO4_SMBCLK (2) A
257 GND_257 DP_B_L2#_258 258 GPIO3_SMBDAT (2)
(2) DPA1N DPA1N 259 260
DPA1P DP_A_L1#_259 DP_B_L2_260
(2) DPA1P 261 DP_A_L1_261 GND_262 262
263 GND_263 DP_B_L3#_264 264
(2) DPA2N DPA2N 265 266
DPA2P DP_A_L2#_265 DP_B_L3_266 J1B
(2) DPA2P 267 DP_A_L2_267 GND_268 268
269 270 Part 2 of 2 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
DPA3N GND_269 DP_B_AUX#_270 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
(2) DPA3N 271 DP_A_L3#_271 DP_B_AUX_272 272 MTG1 MTG1 This AMD Board schematic and design is the exclusive property of AMD,
(2) DPA3P DPA3P 273 274 MTG2 and is provided only to entities under a non-disclosure agreement
DP_A_L3_273 DP_B_HPD_274 HPD_DPA MTG2 1 Commerce Valley Drive East
275 GND_275 DP_A_HPD_276 276 MTG3 MTG3 with AMD for evaluation purposes. Further distribution or disclosure
277 278 3V3RUN +3VRUN MTG4 is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
(2) DPA_AUXN DP_A_AUX#_277 3V3_278 MTG4 other than evaluation requires a Board Technology License Agreement
(2) DPA_AUXP 279 DP_A_AUX_279 3V3_280 280 MTG5 MTG5 with AMD. AMD makes no representations or warranties of any kind
R186 0R 281 C324 C325 C326 MTG6 Date: Rev
PRSNT_L#_281 MTG6 regarding this schematic and design, including, not limited to, Wednesday, May 27, 2009 0
10uF_4V 1uF_6.3V 1uF_6.3V any implied warranty of merchantibility or fitness for a particular
MXM 3 MXM 3 purpose, and disclaims responsibility forany consequences resulting Sheet 10
from use of the information included herein. of 19
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
VDDR3
Strap Name Pin Straps description Default Value
VDDR3
External Thermal Sensor TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable 0
0: 50% Tx output swing for mobile mode GPIO0 and GPIO1 pulls
R261 10K 1: full Tx output swing (Default setting for Desktop) ups need to be stuffed
(2) GPIO2 with Q51 if system board
R260
R263 10K is controlling the PCIE
10K (2,12) GPIO8 swing.
(2,12) GPIO9 TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable 0
R230 R264 10K 0: Tx de-emphasis disabled for mobile mode
GPIO0 (2) (2) GPIO11 1: Tx de-emphasis enabled (Default setting for Desktop)
100K
(2) GPIO12
6
R266 10K
(2) GPIO13
Q51A
BIF_GEN2_EN GPIO2 0 = Advertises the PCI-E device as 2.5 GT/s capable at power-on. 1
C301 2 1 = Advertises the PCI-E device as 5.0 GT/s capable at power-on.
(2,10) VSYNC
100nF_6.3V 2N7002 5.0 GT/s capability will be controlled by software.
VDDR3 (2,10) HSYNC
I2C option
1
D D
DEBUG_I2C_ENABLE GPIO6 Internal use only. THIS PAD HAS AN INTERNALPULL-DOWN AND MUST BE 0 V 0
(2) DDC2CLK AT RESET. The pad may be left unconnected, however, if it is connected to additional
(2) V2SYNC logic on the board, the logic must not allow this signal to be driven or pulled to any
(2) DDC2DAT VDDR3 (2) H2SYNC value except GND at reset.
(2) GPIO21
U14 C302 2.2nF_50V
(2) VID_0
(10) PBAT_SMBCLK 8 SCLK VDD 1 (2) VID_1
R262 MSI_DIS VID_1 Disable Message Signaled Interrupt is both a ROM strap and a pin strap. The pin 0
(2) VID_2 strap is only applicable if a BIOS ROM is not present.
(10) PBAT_SMBDAT 7 SDATA D+ 2 GPU_DPLUS (2) 10K (2) VID_3
(2) VID_6
6 ALERT D- 3 GPU_DMINUS (2) GPIO1 (2) (2) DVALID
AUDIO_EN GPIO8 Enable HD Audio function in the PCI configuration space. 1
(10) PEX_STD_SW#
3
5 4 0 - Disable HD Audio
GND THERM MB_THERMB (10) (2) VHAD0 1 - Enable HD Audio
Q51B (2) GENERICC
EMC1402-1-ACZL R305 0R
(2) MEM_ID0
GPIO17_THERMAL_INT (2,10) 5 (2) MEM_ID1
2N7002
(2) MEM_ID2 GPIO9,13,12,11 (config 3,2,1,0):
TH_PWM (10) CONFIG[3] GPIO9 0101
4
a> If BIOS_ROM_EN = 1, then Config[3:0] defines the ROM Type:
(2) TS_FDO b> If BIOS_ROM_EN = 0, then Config[3:0] defines the Aperture size:Size of the
CONFIG[2] GPIO13 primary memory apertures claimed in PCI configuration space
000 = 128MB
VDDR3
CONFIG[1] GPIO12 001 = 256MB
010 = 64MB
CONFIG[0] GPIO11 011 = 32MB
100 = 512MB
101 = 1GB
110 = 2GB
111 = 4GB
PSYNC (2)
BIF_CLK_PM_EN DVALID Enable CLKREQ# Power Management 0
Power Up Sequence 0 - CLKREQ# power management capability is disabled
1 - CLKREQ# power management capability is enabled
(10) VGA_DISABLE#
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device 1
C 0 - Disable external BIOS ROM device 1 - Enable C
external BIOS ROM device
VIP_DEVICE_STRAP_EN VSYNC VSYNC - VIP_DEVICE_STRAP_EN 0

G_PWR_SRC 0: Driver would ignore the value sampled on VHAD_0 during reset.
1: Driver would use the sampled value sampled at reset from VHAD_0 to determine whether
or not a VIP slave device (e.g. Theater chip) is connected (0 indicates yes, 1 indicates no)
10K VDDC_EN (14)
3
R848
R849 5.1K 1 Q845 VIP_DEVICE VHAD_0 If VIP_DEVICE_STRAP_EN is set to ‘1’, then this pin 0
MMBT3904 is used to sense whether a VIP slave device is connected to the VIP Host interface. If
VIP_DEVICE_STRAP_EN is set to ‘0’, then this pin is not used as a strap at all (i.e. its value
2
3
during reset is unimportant), and it can be used as a regular GPIO

R847 5.1K 1 Q844 VDDR3
(10) RUNPWROK MMBT3904 +3VRUN PSYNC pull up needs to be
Q5531
2 3 VGA_DIS PSYNC PSYNC - VGA DISABLE : 0 – VGA Controller capacity enabled 1 – The stuffed with Q5537 if system 0
2
device will not be recognized as the system’s VGA ontroller board is controlling the
Si2301BDS VGA capacity
1
HDMI_EN HSYNC HSYNC - HDMI_EN 1
HDMI connector presence. 0 – No HDMI connector is present on PCB 1
R6196 - HDMI connector is present on the PCB HDMI
100K RX_PLL_CALIB_BYPASS GPIO21 Internal use only. 0

+VDDC
G_PWR_SRC R6198
1.8V_REG_EN (16) 15K
3
Q5534 FORCE_COMPLIANCE_A VID_3 Internal use only. 0
3
+VDDC 1
MMBT3904 PWRGOOD (10)
R843 R844 5.1K1 Q841
5.1K MMBT3904 C6053
2
5% 1uF_6.3V
2
R841
1K
3
B +1.8V_REG B
1 Q840 MVDD_EN (15)
MMBT3904 B112 Install 0R for 1.8V
VDDR3 Enable Circuit
3
BLM15BD121SN1 Oscillators
2
C842 R846 5.1K1 Q842 VDDR3 Y1

1uF_6.3V MMBT3904 4 3 XIN 0R R446
VCC OUT XTALIN (2)
2
2 GND E/D 1 VDDR3

C464 C465
1uF_6.3V 100nF_6.3V 100MHZ_1.8V
Install B112 and DNI B111 for R448 10K +1.8V_REG
1.8V Oscillators
DNI for 1.8V
Install R448 and DNI R447 for Oscillators
1.8V Oscillators
LDO #2: Vin = +1.8V +/-5% Vout = +1.1V +/- 2% Iout = 1.7A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling VDDR3
XIN
U39
+1.8V_REG R478 XIN 1 6 R289 0R
XIN CKOUT GPIO16_SS (2)
10K
MR858 0.1R 2 XOUOT
LDO2_VIN 4 S1
R480 R482 5 VDDR3
10K 10K S0
+5VRUN +1.1V_REG 9 7
+1.1V_REG VDDR3 FR1 VDD 1uF_6.3V
TP851 TP850
Overlap 8 FR0 C555
footprints 10 3
Use 0.1R U851 R855 C855 C852 C851 C854 C/D/OFF VSS
A 1/2W <=5%
(10) PWRGOOD
PWR_GOOD 1
POK GND#8 8 3.92K R5 33pF_50V 10uF_4V 10uF_4V 100nF_6.3V AK8126B A
2 7 LDO2_FB
(10) RUNPWROK
3
EN
VIN
FB
VOUT 6 C3
4 CNTL REFIN 5
9 R854
C856 GND#9 10K R4
10uF_4V C858 uP7706U8
1uF_6.3V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
VOUT = Vref x (1 + R5/R4) This AMD Board schematic and design is the exclusive property of AMD,
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
Optional Critial Temperature Fault
G_PWR_SRC
+3VRUN
R4056 3.9R
3
R4055
20K 2N7002E
Q4014 C4013 C4014
1 1uF_6.3V 1uF_6.3V
2
D D
PCB1
R4054 1K 1 Q4013 1 Q4008
2
(1,10) PCIE_RST# MMBT3904 CTF_SET2 MMBT3906
PCB
3
3
R4043
1 R4060 5.1K 470K 109-B91157-00A
Q4016 R4045
2
MMBT3904 10K
CTFb (10)
3
CTF_VCNTL R4051 1K 1 Q4010
MMBT3904
3
+3VRUN
2
CTF_GATED2 R4044 1K CTF_SET3 1 Q4009 R4047
MMBT3904 100K
2
R4040
5.1K
3
3
R4038 2.2K CTF_TRIP 1 Q4006 Q4007 1 CTF_FB_CNTL R4046 5.1K
(2) GPIO19_CTF MMBT3904 MMBT3904
1%
2
2
CTF SHOULD BE ACTIVE HI. R4039
1K
1%
C C
Power Play
Optional VID for VDDC Setting

VDDR3 VDDR3 VDDR3 VDDR3 VDDR3
VID0_VDDC
VID1_VDDC
VID2_VDDC
(2) GPIO15
VID3_VDDC
(2) GPIO20
VID4_VDDC
VID_VREF
+5VRUN
402
10V
B X5R B
GPIO20 GPIO15 VDDC
VDDC_REFIN
(14) VDDC_REFIN
0 0 TBD R1689 & R1690 must External Reference is used when
REFIN is driven by voltage ranged VDDR3
be selected to limit from 0.4V to 3.3V Table 4 VDDC Vref Mode Selection FLASH ROM
0 1 TBD MAX ref voltage to MAX BIOS1
VDDC.
Vref Mode R636 R639/C659 Vref (V) BIOS
1 0 TBD R636 1K
5VCC (14)
See BOM for qualified Internal Populate NC 0.6
R636, R639 Internal Reference is used when
values. REFIN is pull-up to > 4.5V R491 C463 113-B91101-1xx
1 1 TBD share pad External NC Populate set by VID IC (U1604)
0R 100nF_6.3V VIDEO BIOS
TP2 U17 FIRMWARE
(2) GPIO22 1 CE# VCC 8
2 7 TP3
(2,11) GPIO8 SO HOLD#
3 WP# SCK 6 GPIO10 (2)
TP4 4 5
GND SI GPIO9 (2,11)
PM25LV010A-100SCE TP1
Optional MVDD Voltage Control
MVDD_FB (15) 1.8V_REG_FB (16) VDDC_FB (14)

Rb Rb
GPIO6 MVDD Rf1 Rb R810 R650 SERIAL EEPROM 512K/1M
R710 7.87K 13.0K Rb VDDC Lower Resistor PN 2280007900G for 1Mbit (PM25LV010A-100SCE)
0 TBD 7.87K 402
402 1%
1% R650 must be populated only if VID is
1 TBD DESIGN MUST KEEP TEST PONINTS AND
not used. This will set VDDC to a fixed TRACES OUT OF ASIC BALLS FOR DEBUG.
VDDR3 value
A A
Rb Resistors to set the output voltages Vout = Vref * (1+Rt/Rb)

(2) GPIO6 for VDDC, MVDD and 1.8V_REG Dual: Vref = 0.6V, Rt = 10k
Single: Vref = 0.8V, Rt = 10k
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
+1.8V_REG
L4 470R_1000mA
MEM_PLL
(600mA 1.8V MEM_PLL)
C387 C388 C389

10uF_2.5V 1uF_6.3V 100nF_6.3V
+1.8V_REG B9 +1.8V_REG
TSVDD B10
BLM15BD121SN1 DAC1_AVDD
BLM15BD121SN1 (20mA 1.8V TSVDD) (65mA 1.8V AVDD)
C390 C391 C392 C393 C394
D D
4.7uF_6.3V 1uF_6.3V NS1 4.7uF_6.3V 1uF_6.3V 100nF_6.3V NS2 NS_VIA
2 1 2 1
B11 +VDDC
TSVSS NS_VIA BLM15BD121SN1 VDD1DI GND_AVSSQ B12
(55 mA 1.8V VDD1DI) BLM15BD121SN1 SPVDD
C395 C396 C397 (35 mA 0.9V-1.1V SPVDD)
4.7uF_6.3V 1uF_6.3V 100nF_6.3V NS3 NS_VIA C466 C399 C400
2 1 1uF_6.3V 1uF_6.3V 100nF_6.3V
NS4 NS_VIA
2 1
GND_VSS1DI
GND_SPVSS
A2VDDQ
(2 mA 1.8V A2VDDQ)
C403 +1.1V_REG
0R NS5 NS_VIA
2 1
+1.8V_REG
B15 VDD2DI GND_A2VSSQ
BLM15BD121SN1 DPLL_PVDD (55 mA 1.8V VDD2DI)
(40mA 1.8V DPLL_PVDD) C406 C407 C408 C409 C410 C411 C412
NS7 0R NS6 NS_VIA 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V
C416 C417 C413 2 1 2 1
4.7uF_6.3V 1uF_6.3V 100nF_6.3V
GND_PVSS NS_VIA GND_VSS2DI
B18
LPVDD B16
(20MA 1.8V LPVDD) VDD_CT DPLL_VDDC
NS8 BLM15BD121SN1
(150mA 1.8V VDD_CT)
BLM15BD121SN1
C421 2 1 C422 C423 C424 (100mA 1.1V DPLL_VDDC)
0R NS_VIA 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
C414 C415 C418
GND_LPVSS 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
LVDDC
400 MA 1.8V LVDDR+LVDDC) GND_PVSS
C427
0R B20
+1.8V_REG
DPAVDDR
C L5 470R_1000mA VDDR4_5 C
BLM15BD121SN1
B21 C434 C435 C436 (200mA 1.1V DPAVDDR)
BLM15BD121SN1 DPA_PVDD (300mA 1.8V VDDR4_5) 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
(20 MA 1.8V DPA_PVDD)
C437 C438 C439 NS9 NS_VIA C428 C430
4.7uF_6.3V 1uF_6.3V 100nF_6.3V 2 1 100nF_6.3V 1uF_6.3V
GND_DPA_PVSS
B22
BLM15BD121SN1 DPB_PVDD L6 470R_1000mA B24
PCIE_VDDR
(20 MA 1.8V DPB_PVDD)
(700mA 1.8V PCIE_VDDR)
DPBVDDR
C450 C446 C451 NS10 NS_VIA
BLM15BD121SN1
4.7uF_6.3V 1uF_6.3V 100nF_6.3V 2 1 C452 C453 C454 (200mA 1.1V DPBVDDR)
C440 C441 C442 C443 C444 C445 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
GND_DPB_PVSS 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_2.5V
B23
PCIE_PVDD
BLM15BD121SN1
(60mA 1.8V PCIE_PVDD)
C447 C448 C449

4.7uF_6.3V 1uF_6.3V 100nF_6.3V NS11
2 1
NS_VIA
GND_PCIE_PVSS
VDDR3
(100mA 3.3V VDDR3)
C458 C459 C460

4.7uF_6.3V 1uF_6.3V 100nF_6.3V
B B
A2VDD
C457 (135mA 3.3V A2VDD)
0R
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
8 7 6 5 4 3 2 1
+VDDC
Input Cap
2
NS600
NS_VIA
1
Overlap Overlap VDDC_FB_TRACE
G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC R600

VDDC_SV 0R 603
VDDC_FB Reserve for
(12) VDDC_FB Loop Measurement
C673 C686
2.2uF_16V 10UF_16V VDDC_REFIN DNI
D X7R, 1206 16V, 16V, X7R, 1206 (12) VDDC_REFIN D
1.3mm Hi MLCC SP/POSCAP, SP/POSCAP, 1.3mm Hi MLCC Type III compensation
SMT 7343 1.5MM H SMT 7343 3.1MM H close to IC VDDC_SV
4236047600G 423B010700G COMP_GND
R653
Top Side Hmax=1.5mm Top Side Hmax=4mm RFB1 R3 0R Rj1
R651 402 R657
R611 0R C655 10K 0R
603 Css 15nF 402 C3 C653 402
G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC 402 2.2nF_50V
402 Rj2
SS_ICOMP
UGATE2 COMP_FB
C636 C666 C667 C668 C657 C641 C642 C664 402 R1
2.2uF_16V 10UF_16V 10UF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 10UF_16V 2.2uF_16V R652
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 C612 10K
1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1uF_25V 402 C2
U601 C651
18
17
16
15
14
13
uPI6201BQ 100pF_50V
C1 402
REFOUT/POK
SS/ICOMP
FB
UGATE2
BOOT2
REFIN/EN
Top Side Hmax=1.5mm C652
15nF
402
PHASE2 19 12
PHASE2 COMP/DROOP
LGATE2 5VCC
20 LGATE2 RT 11
G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC R655 33.2K
C637 C640 C639 C669 C671 C670 C665 C672 C674 C682 C683 C684 C685 Rdroop 21 10
1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V VCCDRV/DROOP IOUT/IMAX/DROOP
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi G_PWR_SRC Droop Option 402 10V
X5R
C VCC 22 9 C
VCC CSP2
CSP2
C694
1UF_16V CSN2
X7R LGATE1 23 8
G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC 603 LGATE1 CSN2
PHASE1 24 PHASE1
C678 C681 C679 C680 C677 C687 C688 C689 C691 C690 C693 C692 C623 25 7
1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V PGND CSN1
26 PGND26
UGATE1
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 27 CSN1
BUSEN
BOOT1
PGND27
AGND
5VCC
0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi
CSP1
C602 28
1uF_25V 29 PGND28 CSP1
PGND29
6
Bottom Side Hmax=1.2mm
UGATE1
C660 share pad

R601 0R 100nF_6.3V
603 402 6.3V MR606
R685 0R SS_ICOMP Y5V 0R
(11) VDDC_EN
VDDC_REFIN
share pad (12) 5VCC

PIN5 PH2_ENb:
VDDC PWM Whole CHip Enable - Hi , Ph 2 Disabled, Ph 1 Enabled,
- Lo, Ph 1 and Ph 2 Enabled,
G_PWR_SRC
B Output Cap B
9
5
6
7
8
9
5
6
7
8
8
7
6
5
9
8
7
6
5
9
+VDDC Top Side Hmax=2.2mm Top Side Hmax=4mm Bottom Side Hmax=1.2mm
Q601 Q602 Q611 Q612
BSC120N03LSG BSC120N03LSG BSC120N03LSG BSC120N03LSG
NC641 NC642 NC644 NC643
470uF 470uF 470uF 1000uF_5mR
2.5V, 2.5V, 2.5V, 2.5V, SP/POSCAP, SP/POSCAP,

+VDDC SP/POSCAP, SP/POSCAP, SP/POSCAP, SP/POSCAP, SMT 7343 SMT 7343
4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
SMT 7343 2MM H SMT 7343 2MM H SMT 7343 2MM H SMT 7343 4MM H Max 1.2mm_H Max 1.2mm_H
UGATE1 UGATE1 UGATE2 UGATE2
L601 L611
PHASE1 1 2 PCMC104T-R36MN PCMC104T-R36MN 1 2 PHASE2
4mm H 4mm H LOW PROFILE POSCAP
Bottom Side Hmax=1.2mm

9
5
6
7
8
9
5
6
7
8
8
7
6
5
9
8
7
6
5
9
+VDDC +VDDC
805 Q603 Q604 Q613 Q614 805
BSC030N03LS G BSC030N03LS G BSC030N03LS G BSC030N03LS G
Route like Route like C658 C661 C649 C650
differential pair differential pair C645 C646 C647 C648 C675 C676 100nF_6.3V 15nF 15nF 100nF_6.3V
2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V 402 402 402 402
603 603 603 603 603 603 603
4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
LGATE1 LGATE1 R604 R614 LGATE2 LGATE2

Place across 715R 715R Place across MLCC
Q613, Q614 1/10W 1/10W Q613, Q614
0603 C604 1UF_16V C614 1UF_16V 0603
RC snubber values shown X7R X7R RC snubber values shown
are for reference only, are for reference only,
tuning is required R605 C605 C615 R615 tuning is required
A 1.47K 100nF_6.3V 100nF_6.3V 1.47K A
CSN2
CSN1
CSP2
CSP1
+VDDC Place close to Controller Place close to Controller

805 with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Wednesday, May 27, 2009 Rev
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+PW_MVDDC_M
+MVDDC_B
MVDDC_CSP G_PWR_SRC
D MVDDC_CSN D
16
15
14
13
U703
BOOT
PHASE
IMAX
CSP
+PW_MVDDC_HGD 1 12
UG CSN C721 C722 C724
+MVDD_VCC 2 11 C723 2.2uF_16V 2.2uF_16V 2.2uF_16V
VCC DROOP 150nF_16V X7R, 1206 X7R, 1206 X7R, 1206
+PW_MVDDC_LGD 3 10 603 1.3mm Hi 1.3mm Hi 1.3mm Hi
LG SS
R734 4 9 MVDDC_COMP Top Side Hmax=1.5mm
10K POK COMP Bottom Side
9
5
6
7
8
17 18 MVDD_EN (11) Hmax=1.2mm
TH1 TH2
RT/EN
REFIN
VREF
Q701
BSC080N03LS G
FB
5
+MVDD_VCC
R717 0R
4
3
2
1
+PW_MVDDC_HGD
C C
MVDDC_FB
+MVDD
C714 R731
100nF 0R +PW_MVDDC_M L701 0.56uH
2
4mm H
MVDD_FB (12) NS701
NS_VIA
Sense Point
1
MC738 C741 C739
1000uF_5mR 15nF 1uF_25V
MVDD_FB_TRACE
402 X7R, 0805
SP/POSCAP, SP/POSCAP,
Rs 1210 Route like SMT 7343 SMT 7343
1% differential pair Max 1.2mm_H 4MM H
9
5
6
7
8
9
5
6
7
8
Q703 Q702 Bottom Side Hmax=1.2mm
BSC025N03LS G BSC025N03LS G Cs Bottom Side
402 Reserve for R701 Hmax=1.2mm Top Side MLCC
X7R Loop Measurement 0R Hmax=4mm
25V 603
1/10W MVDD_SV LOW PROFILE POSCAP
B Place Rs and 0603 B
4
3
2
1
4
3
2
1
Cs across QL
+PW_MVDDC_LGD RC snubber values shown C713

are for reference only, 2.2nF_50V
tuning is required RFB1 402
R711 X7R
X7R 10K
402
MVDDC_CSN
MVDDC_CSP
1% R713
1K
402
COMPENSATION CIRCUIT FILTERED SMPS VCC BOOT CIRCUIT MVDDC_FB
MVDDC_COMP
G_PWR_SRC +MVDDC_B Place close to Controller
C711
15nF
402
X7R C712 100pF_50V +MVDD_VCC R718
402 R707 0R
R712 X7R 2.2R 603
8.06K
A 402 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC. A
1% C705 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
MVDDC_FB 100nF and is provided only to entities under a non-disclosure agreement
X7R 1 Commerce Valley Drive East
603 C707 16V is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
R709 X7R 100nF 603 other than evaluation requires a Board Technology License Agreement
0R +PW_MVDDC_M regarding this schematic and design, including, not limited to, Date: Wednesday, May 27, 2009 Rev
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+5VRUN
+PW_1.8V_REG_M
D D
C821 C823 C822 C824
1uF_16V 10UF_16V 2.2uF_16V 2.2uF_16V
X5R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
0.95mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi
+1.8V_REG_B
+PW_1.8V_REG_CSP
16 +PW_1.8V_REG_CSN Bottom Side Top Side Hmax=1.5mm
15
14
13
U803 BOOT Hmax=1.2mm
PHASE
IMAX
CSP
+PW_1.8V_REG_HGD 1 12
UG CSN (R733)
1.8V_REG_VCC 2 11
VCC DROOP
+PW_1.8V_REG_LGD 3 10
LG SS
R834 4 9 1.8V_REG_COMP
10K POK COMP
17 TH1 TH2 18 1.8V_REG_EN (11)
RT/EN
REFIN
VREF
FB
SSO8 Dual-FET (FT1)

5
1.8V_REG_VCC QH
7
8
9
R817 0R Q801A
SM
+PW_1.8V_REG_HGD 2
C BSC072N03LD_G C
+1.8V_REG
1
1V8_REG_FB +PW_1.8V_REG_M L801 4.7uH_5.5A
2
10
5
6
Overlap NS801
C814 R831 Q801B NS_VIA
100nF 0R Sense Point
1
+PW_1.8V_REG_LGD 4
1.8V_REG_FB (12) BSC072N03LD_G C838 C841
QL Rs 1.8V_REG_FB_TRACE 330UF_2V C839 15nF
3
1uF_25V 402
805 Route like R801 2.5V, X7R, 0805
differential pair 0R SP/POSCAP,
Top Side H<1.5mm 603 Reserve for SMT 7343
Loop Measurement 1.5MM H
402
Overlap Q801 and MQ801 X7R
Cs
25V 1.8V_REG_SV Top Side Hmax=1.5mm Bottom Side Hmax=1.2mm
Place Rs and Cs across QL LOW PROFILE POSCAP MLCC

RC snubber values shown C813
are for reference only, 3.3nF_50V
tuning is required 0603 402
1/10W RFB1 X7R
R811
10K R813
402 1K
X7R 1% 402
1V8_REG_FB
B B
+PW_1.8V_REG_CSN
+PW_1.8V_REG_CSP
SO8 Dual-FET (FT1) +5VRUN
COMPENSATION CIRCUIT FILTERED SMPS VCC BOOT CIRCUIT Place close to Controller
+PW_1.8V_REG_HGD
G_PWR_SRC +1.8V_REG_B
1.8V_REG_COMP +PW_1.8V_REG_M
C811
10nF_25V C812 68pF_50V R807
402 402 2.2R
X7R X7R R818
0R +PW_1.8V_REG_LGD
R812 1.8V_REG_VCC
A 15K A
402 603
C807 X7R C805
1V8_REG_FB 100nF 5% 100nF CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
603 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
X7R 16V This AMD Board schematic and design is the exclusive property of AMD,
R809 Top Side H<1.5mm with AMD for evaluation purposes. Further distribution or disclosure
0R is strictly prohibited. Use of this schematic and design for any purpose Markhaml, Ontario
+PW_1.8V_REG_M other than evaluation requires a Board Technology License Agreement
0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
8 7 6 5 4 3 2 1
5 4 3 2 1
POWER UP SEQUENCE (not to scale)
D D
PWR_SRC
+5VRUN
+3VRUN
> 1ms
PWR_EN
VDDC, VDDCI, SPVDD

+VDDC
VDDR1, MVDDQ/C
+MVDD
C C
VDDR4/5, VDD_CT, TSVDD, PCIE_VDDR, PCIE_PVDD, DPLL_PVDD,

+1.8V_REG DPx_PVDD, LPVDD, LVDDC, MPVDD, AVDD, VDD1DI
PCIE_VDDC, DPLL_VDDC, DPxVDDR

+1.1V_REG
+1.1V_REG AND VDDR3 RAMP UP SEQUENCE CAN BE INTERCHANGED.
VDDR3
VDDR3
< 20ms
PWR_GODD
< 90ms
B B
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
MEMORY CHANNEL A & B MEMORY CHANNEL C & D
GDDR3 4pcs 16Mx32 GDDR3 4pcs 16Mx32
D D
CH A&B CH C&D
LVTMDP
DL LVDS LVDS
LVDS_LTXx/LTXx#
POWER REGULATORS DPE/F LVDS_UTXx/UTXx#
SCL/SDA LVDS_DDC_CLK/DAT
From G_PWR_SRC
+VDDC, +MVDD HPD1 DVI_HPD
From +5VRUN
+1.8V_REG TMDPAB
DP_A
From +3VRUN DPA DP_A_Lx/Lx#
VDDR3 GPIO
Straps DDCAUX3 DP_A_AUX/AUX#
C C
From +VDDC HPD2 DP_A_HPD
VDDC, VDDCI, SPVDD
BIOS ROM
From +MVDD DP_C
VDDR1, MVDDQ/C DPB DP_C_Lx/Lx#
DDCAUX4 DP_C_AUX/AUX#
From +1.8V_REG HPD3 DP_C_HPD
VDDR4/5, VDD_CT, TSVDD,
PCIE_VDDR, PCIE_PVDD, OSC/SS GPIO16_SSIN
DPLL_PVDD, DPx_PVDD, XTALIN/OUT
LPVDD, LVDDC, MPVDD,

AVDD, VDD1DI, +1.1V_REG
DAC1
CRT DAC1 VGA
From +1.1V_REG Dynamic MVDD GPIO6 VGA_RED/GREEN/BLUE
PCIE_VDDC, DPLL_VDDC, Dynamic VDDC GPIO15, GPIO20 DDC1
DPxVDDR VGA_DDC_CLK/DAT
V/HSync
VGA_VSYNC/HSYNC
POWER DELIVERY
MxM3.0 Source
3V3 5V PWR_SRC
B Thermal B
I2C SMB_CLK/DAT
M98 DDC2
Interrupt Temperature
GPIO17 TH_ALERT#/OVERT#
Temp. Sensing Sensor
3V3 delayed circuit D+/D-
Temperature Critical
GPIO19_CTF
PCIE
SMPS Enable
Circuit
3V3
5V MxM3.0 Connector RH MxM3.0 M98 GDDR3 512MB
PWR_SRC
DP DP DL-LVDS VGA REV 0
A A

0
Title Doc No.
M98 GDDR3 512MB MXM 3.0 105-B911xx-0A
5 4 3 2 1
5 4 3 2 1
Title Schematic No. Date:

M98 GDDR3 512MB MXM 3.0 105-B911xx-0A Wednesday, May 27, 2009
NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.
0
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A 09/04/15 Initial design based on B909-00; A series resistor (R1000) and a shunt cap (C1000) are added to mem_rst signal
C C
B B
A A
5 4 3 2 1

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5 4 3 2 1

PCIE_RXP0 AM48 AK45 PCIE_TXP0 BK49 BH48

PCIE_RXP1 AL51 AK42 PCIE_TXP1 BJ50 BC45

PCIE_RXP2 AK48 AJ45 PCIE_TXP2 BF48 BB45

PCIE_RXP7 AE51 AF42 PCIE_TXP7 BA51 AU42

PCIE_RXP8 AD48 AE45 PCIE_TXP8 AY48 AU45

PCIE_RXP9 AC51 AE42 PCIE_TXP9 AW51 AT42

PCIE_RXP10 AB48 AD45 PCIE_TXP10 AV48 AT45

PCIE_RXP11 AA51 AD42 PCIE_TXP11 AU51 AR42

PCIE_RXP12 Y48 AB45 PCIE_TXP12 AT48 AR45

PCIE_RXP13 W51 AB42 PCIE_TXP13 AR51 AN42

PCIE_RXP14 V48 AA45 PCIE_TXP14 AP48 AN45

PCIE_RXP15 U51 AA42 PCIE_TXP15 AN51 AM42

PCIE_REFCLKP AM45 AT39

A M98 16P A12 MVD SLT BIN1 A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

DPAVDDR U1B U1K

BC39 A2VSSQ B2 BE36 VIP_0 AV35 VID_0 (11)

22mil TP9 BJ45 VDDR3

M98 16P A12 MVD SLT BIN1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

R46 10K AW19 M98 16P A12 MVD SLT BIN1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

C AA9 ADBIC0 ADBIC1 AB12 BB11 ADBID0 ADBID1 BE10 C

DQMC#0 L3 AJ10 DQMC#4 DQMD#0 AP2 BL15 DQMD#4

RDQSC0 H6 AN13 RDQSC4 RDQSD0 AL3 BD17 RDQSD4

WDQSC0 J3 AN12 WDQSC4 WDQSD0 AL5 BC17 WDQSD4

WEC0# R14 AJ16 WEC1# WED0# AT13 AV17 WED1#

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

M98 16P A12 MVD SLT BIN1

C1011 C1013 C1014 C1015 C1016 C1017 C1018

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

VREF = .7*VDDQ H1 VREF = .7*VDDQ H1

R85 136 FBGA R86 136 FBGA(MIRROR)

VREF = .7*VDDQ VREF = .7*VDDQ +MVDD

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CHAN B GDDR3 136FBGA MEMORY

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

VREF = .7*VDDQ H1 VREF = .7*VDDQ H1

CHAN C GDDR3 136FBGA MEMORY

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

VREF = .7*VDDQ H1 VREF = .7*VDDQ H1

R163 136 FBGA R164 136 FBGA(MIRROR)

CHAN D GDDR3 BGA MEMORY

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

VIP_DEVICE_STRAP_EN VSYNC VSYNC - VIP_DEVICE_STRAP_EN 0

during reset is unimportant), and it can be used as a regular GPIO

100K RX_PLL_CALIB_BYPASS GPIO21 Internal use only. 0

C842 R846 5.1K1 Q842 VDDR3 Y1

2 GND E/D 1 VDDR3

Optional Critial Temperature Fault

Optional VID for VDDC Setting

Optional MVDD Voltage Control

MVDD_FB (15) 1.8V_REG_FB (16) VDDC_FB (14)

Rb Resistors to set the output voltages Vout = Vref * (1+Rt/Rb)

C387 C388 C389

C447 C448 C449

(100mA 3.3V VDDR3)

C458 C459 C460

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

G_PWR_SRC G_PWR_SRC G_PWR_SRC G_PWR_SRC R600

C660 share pad

share pad (12) 5VCC

VREF = .7VDDQ H1 VREF = .7VDDQ H1

VREF = .7VDDQ VREF = .7VDDQ +MVDD

VREF = .7VDDQ H1 VREF = .7VDDQ H1

VREF = .7VDDQ H1 VREF = .7VDDQ H1