CMPE 262 Digital Logic Design

Fall 2019 - Final Exam Question Sheet

120 minutes

Section: L52-11323
Name: ………….………………..………………………………………
University ID: ………….………………..………………………………………

Directions to be followed in exam:

 Within 24 hours from the exam, all students should check the exam grade
and model answer in the course web page in Blackboard.
 A meeting hour will be arranged the next morning from exam date between
10:00 and 11:00 AM in C07-122 to see your answer sheet.
 If the student fail to come, then the instructor holds no responsibility to
arrange a next meeting hour with the student.

Sign the box if you read this note if kindly possible.

If your answer in question sheet and the answer sheet is different then what I
should correct? Tick your selection

Correct the Question Sheet

Correct the Answer Sheet

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Empty scratch space:

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Q1. Complete the timing diagram for the given circuit. Assume that both gates have a
propagation delay of 5 ns. Remember that the question is solved from 0 ns – 20 ns.

Option Answer

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 4

Consider the three-level circuit corresponding to the expression

F(A,B,C,D) = (A+B)(B’C’ + BD’)

Q2. Find all static_1 hazard.

1- 1101 – 1001, 1000 – 1001

2- 0100 – 0011, 0000 – 0001
3- 1000 – 1010, 1101 – 1001
4- 0000 – 0010, 1000 – 1001
5- Others

Q3. Find all static_0 hazard

1- 1100 – 0100
2- 1011 – 1010
3- 1110 – 1010
4- 0001 – 0100
5- Others

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Q4. Which of the following will be the correct circuit design solving the static-0 hazard

Option Answer

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 4

5 Others

Q5. Finish the AND function for the 4-valued simulation. Remember that:
X = unknown 0,1 ?
Z = not connected = high impedance.

Option Answer

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 3

5 Others

Q6. Which one of those hazards is a static-0 hazard?

Option Answer

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 3

4 Others

Q7. Which one of those hazards is a dynamic hazard?

Option Answer

4 Others

Q8. What would be the value of H at end?

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Know that: X = unknown 0 or 1, Z = not connected = high impedance

Option Answer
1 0
2 1
3 X
4 Z
5 Others

Q9. Two kinds of 3-state buffers are presented. Their truth table is the 1st and the 4th rows are
filled. Choose one of the correct solutions.

Option Answer

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 4

5 Others

Q10. Given the next functions:

F1 = A’BD and F2 = AB’C’

Choose one of four different implementations to this 4-variable F1 and F2 using 4-10 inverted
output line decoder, which makes the implementation correct.

Option Answer

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 3

Q11. This is an internal architectural drawing of a PLA of 3-input, 5-product terms, and 4-
output. This PLA is implementing 4-output functions F0, F1, F2, and F3. Which of the next
Boolean function of F1 and F2, this PLA implements?

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 Option Answer
F1 = m0, m1, m2, m3
1
F2 = m4, m5, m6, m7
F1 = m3, m4, m5,
2
F2 = m0, m1, m2
F1 = m1, m6, m5, m7
3
F2 = m0, m5, m2, m3
F1 = m2, m3, m4, m6, m7
4
F2 = m0, m1, m2, m6
5 Others

Q12. The next is a D FF connected as shown below to measure the minimum frequency this FF
works on. If the FF delay is 7ns, the inverter delay is 3 ns, and the inverter setup time is 3 ns
and hold time is 2 ns. What is the minimum clock period should be such that the FF works at
its maximum frequency?

Hold and setup times must be known by the student as given in lectures before.

Option Answer
1 Others
2 12
3 13
4 14
5 15

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Q13. The next timing diagram is for a falling-edge triggered SR FF. the Q output is done for
you for CLK 1 and 2, but CLK 3 and 4 needs to be solved. Which of the following diagram
is correct?

Option Answer

5 Others

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Design a counter with the next count sequence: CBA = 000-100-111-010-011-000 (repeat)
using three SR FFs.

Q14. Which of the following excitation table for SCRC is correct? Remember that the first two
and last two rows are solved for you.

Option Answer

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 4

Q15. Which of the K map for next state of FFA is correct? First and fourth rows are solved for
you.

Option Answer

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 2

Q16. Which of the K map for SR of FFC is correct? First and fourth rows are solved for you.

Option Answer

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1

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 5

Q17. Which circuit drawing describes FFB full design?

Option Answer

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 3

5 Others

Look at next Figure as it shows a Mealy machine circuit. The student asked to do the
design for him/her self in the empty solution space to help in selecting the correct
answer.

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Q18. Select the state table that represent the circuit and the correct state equation. Remember
that the first row and the last row solved for you.

Option Answer

4 Others

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Empty scratch space:

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