2020 27th International Workshop on Electric Drives: MPEI Department of Electric Drives 90th Anniversary (IWED), Moscow, Russia.

Jan 27 – 30, 2020

An Improved SVPWM Strategy for Three-Level

Neutral Point Clamped Converter Capacitor Voltage
Balancing
Duy Hiep Do1, Alecksey Anuchin2
Department of Electric Drives
Moscow Power Engineering Institute
Moscow, Russia
1hiep.d.do@gmail.com, 2anuchin.alecksey@gmail.com

Abstract— DC link capacitor voltage balancing is a classical
issue of multilevel converters because it causes error in output
voltages or even damages the capacitors. Additional circuits or
proper uses of redundant states can be utilized to reduce the
deviation of neutral point voltage. This paper proposed an
improved method using modulating times of redundant states
as optimal parameters in capacitor voltage deviation
minimization problem of three-level neutral point clamped
converters. The procedure of formulating and minimizing the
capacitor voltage deviation is presented in detail. Test results
show the significant improvement of this method over previous
solutions.
Keywords—three-level NPC converter, redundant state, space
vector modulation, quadratic function
I. INTRODUCTION
Three-level converters are more and more interested in
research and industrial applications where high power and
medium voltage are required because they have many
advantages over classical inverter. They generate staircase
waveform of output voltage, hence improve its harmonic
characteristic; combine the working voltages of valves
connected in series, so reduce the required blocking voltage
of valves as compared to classical two-level inverter of the
same output voltage capability.
There are three main topologies of there-level converter,
which are neutral point clamped (or diode-clamped), flying
capacitor (or capacitor clamped), and cascaded H-bridge. In
this paper, the neutral-clamped topology (Fig. 1) is
considered. It was the first type of multilevel converter.
Despite having many advantages, three-level NPC
converter has a classical drawback which is to keep the
capacitor voltage balanced when using only one DC source.
Otherwise neutral point (O) voltage will not be equal to
Edc 2 and the exact required voltage cannot be generated,
especially when the modulation index is low. Moreover, this
leads to unsafe working of the capacitors.
This critical problem is of great concern since three-level
NPC converter was first used. Many researches were
conducted and many solutions were proposed.
On the one hand, researchers proposed using additional
hardware for balancing capacitor voltages. The authors of [1]
used a “back-to-back” rectifier/inverter configuration and
coordinated switching angles of rectifier and inverter to
achieve capacitor charge balance. In [4] auxiliary capacitor-
based circuits were used. In [5] and [6] inductors were
The research was performed with the support of the Russian Ministry
of Education and Science grant (Project № 8.8313.2017/BCh).
978-1-7281-4158-9/20/$31.00 ©2020 IEEE
inserted into the converter. These “hard” methods basically
increased the size and cost of the converter.
On the other hand, other researchers want to use soft
methods. They did not increase the hardware complexity of
the converter but required much more complicated
calculation executed in drive circuits. In [7] the authors
introduced an alternative space vector modulation technique
for three-level NPC converter in an aircraft starter generator
system. In the region of high modulation index, the medium
vectors were not used, but a small vector instead. This
doubles the step in the output phase voltages and takes away
the staircase waveform, hence, the advantage in harmonic
characteristics of the three-level converter. The authors of [2]
and [3] aimed to select the best switching states to generate
the required output voltage and at the same time drive the
voltage of DC link capacitors to balance value. The
disadvantage of this method is that only one redundant state
was used for one vector throughout the whole sample time
and this can very likely cause overshoot.
In this paper, the authors proposed a way to improve the
soft methods. Space vector is held unchanged to preserve the
principle of “three nearest vectors” but manipulated times of
redundant states are used as optimal parameters. Test results
show the validity of this method. The neutral point voltage is
stabilized and its deviation about balance point decreases
dramatically as compared to former methods. Although a lot
of calculation is required per sample time, intervening at
these optimal parameters has become increasingly simple
due to the recent development of digital signal processors.
Cup
Edc
2
ia
Edc ib
ic
0
Edc
2
Cdown
Fig. 1. Three-level NPC converter topology.

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 II. METHOD FOR CALCULATION AND MINIMIZING NEUTRAL
POINT VOLTAGE DEVIATION
To minimize neutral point voltage deviation using
manipulating times of redundant states as optimal
parameters, it is necessary to build its formula as a function
of manipulating times, then minimize this function and
design an appropriate sequence of states.
A. Calculation of neutral point voltage deviation
(type 1) (type 2)
The shift of neutral point voltage (or lower capacitor
voltage ΔVC ,low ) is caused by phase currents flowing to
neutral point. According to [3], if the sample time is
supposed to be short enough compared to output current
period, the phase currents change very little during one
sample time, then ΔVC ,low after one sample time is derived as
(1) for the case of three-level neutral point clamped
converter.
ta ia + tb ib + tc ic
ΔVC ,low = (1)
Cup + Clow
(type 3) (type 4)
where t a , t b , and t c are the connected times to neutral point
during one sample time of phases a, b, and c, respectively. Fig. 3. Four types of triangles in space vector.

The estimated deviation of neutral point voltage after this
sample time is:
Edc
ΔE = − VC ,low − ΔVC ,low (2)
2 derived from Sector 1 are shown in detail.
When the voltage vector Vs rotates in the space vector, (2)
will have specific forms.
The space vector of three-level NPC converter consists of
27 states, making 24 triangles as shown in Fig. 2.
For the sake of simplicity in calculation of duty cycles, Vs
and its three nearest vectors are rotated to Sector 1. The
feasible rotated vector will fall into one of the four triangles
as shown in Fig. 3. The three nearest vector used to
synthesize Vs will come to apices of triangles in Sector 1. The
modulation times required for vectors V1 , V2 , and V3 are
denoted as t1, t 2 , and t 3, respectively.
V11 (110) and V12 (221) . Following the same process as for
triangle 2, now the formula of neutral point voltage deviation
is:
Fig. 2. Space vector of three-level NPC converter
To have the specific formulae of (2), it is necessary to
determine which phases will be connected to neutral point
and how long they will connect. Moreover, the calculation is
analogous in any Sector, so in this paper only formulae
To our knowledge, the modulation times t1, t 2 , and t 3 were
used for only the “best states” of the required vector V1, V2 ,
and V3 . In this paper these times are allocated for every
redundant state to utilize compensating ability to neutral
point voltage of every phase as much as possible.
1) When voltage vector Vs rotates in triangle 2
Referring to Fig. 2 and Fig. 3, there are two possible
states for vector V1, which are V11 (100) and , and only one
state for each vector V2 or V3, which are V2 (200) and (210).
Both V11 and V21 are used with total period per sample time,
say T1 and T2. Phase a is connected to neutral point when V11 is
manipulated. Phase b is connected to neutral point when
manipulating V12 or V3 . And for phase c, when V12 is
manipulated. So the total change of the neutral point voltage
after one sample time is:
T1ia + ( t1 − T1 )( ib + ic ) + t3ib
ΔVC ,low = (3)
Cup + Clow
Substitution (3) to (2) leads to the formula of neutral
point voltage deviation:
Edc t (i + i ) + t3ib ia − ib − ic
ΔE = − VC ,low + 1 b c + T1 (4)
2 Cup + Clow Cup + Clow
2) When Vs rotates in triangle 4
There are two possible states for vector V1 which are
Edc (t i + t i ) i − i − i
ΔE = − VC ,low − 1 c 2 b + c a b T1 (5)
2 Cup + Clow Cup + Clow
where T1 is total time to manipulate V11 in one sample time.

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 3) When Vs rotates in triangle 3 To minimize the number of valves to be switched the
Now each of the vectors V1, V2 has two redundant states. sequence of states in one sample time and their
Let the two states V11 (110) , V12 (221) of V1 take total times T1 corresponding intervals are designed as follow:
and (t1 − T1 ) and the two states V21 (100) , V22 (211) of V2 take T  t  t   t −T 
total times T2 and (t2 − T2 ). In this triangle the formula of ΔE V11  1  → V2  2  → V3  3  → V12  1 1  →
after one sample time is as follow: 2 2 2  2 
t  t  T 
Edc t i + t (i + i ) + t3ib → V3  3  → V2  2  → V11  2 
ΔE = − VC ,low + 1 c 2 b c + 2
  2
  2
2 Cup + Clow If some state’s interval is zero, then it is not manipulated.
(6)
i +i −i i −i −i
+ a b c T1 + a b c T2 2) When Vs rotates in triangle 4
Cup + Clow Cup + Clow T1 is found by solving the optimal problem:
4) When Vs rotates in triangle 1 2

All the three nearest vectors have more than one

 Edc (t i + t i ) 
 − VC ,low − 1 c 2 b + 
corresponding state. Suppose the two states V11 (100) and 2 Cup + Clow 
(ΔE ) 2 =   ⎯⎯⎯→ min
V12 (211) take total times T1 and (t1 − T1 ); the two states V21 (110) i −i −i
0 ≤T1 ≤ t1

and V22 (221) take total times T2 and (t2 − T2 ) ; and the three  + c a b T1 
 Cup + Clow 
state V31 (111) , V32 (222) , and V33 (000) take total times T3 ,  
(t3 − T3 ) 2 , and (t3 − T3 ) 2 . Actually, when the load is Let
perfectly symmetrical there is no need to consider T3 because
 Edc 
the total effect of three phases to neutral point is cancelled.  2 − VC ,low  ( Cup + Clow ) − t1 (ib + ic ) − t3ib
The formula of ΔE in this triangle now becomes: T14* = −  
Edc t (i + i ) + t2 ic ia − ib − ic ic − ia − ib
ΔE = − VC ,low + 1 c b + T1 +
2 Cup + Clow Cup + Clow The solution of T1 is:
(7)
ia + ib − ic i +i +i T1 = t1 2 if ic − ia − ib = 0
+ T2 + a b c T3
Cup + Clow Cup + Clow T1 = 0 if T14* ≤ 0 and ic − ia − ib ≠ 0
B. Optimal times for redundant states and their sequence T1 = T14* if 0 < T14* ≤ t1 and ic − ia − ib ≠ 0
1) When Vs rotates in triangle 2 T1 = t1 if t1 < T14* and ic − ia − ib ≠ 0
T1 is found by solving the optimal problem:
Suitable sequence of states and their corresponding
( ΔE ) 2 ⎯⎯⎯→
0 ≤ T1 ≤ t1
min intervals:
Or
T  t  t   t −T 
2 V11  1  → V3  3  → V2  2  → V12  1 1  →
 Edc t1 (ib + ic ) + t3ib  2 2 2  2 
 2 − VC ,low + C + C +
t  t  T 
( ΔE ) =   ⎯⎯⎯→ min
2 up low
→ V2  2  → V3  3  → V11  1 
 (ia − ib − ic )  0 ≤ T1 ≤ t1
2 2 2
 + T1 
Cup + Clow 3) When Vs rotates in triangle 3
 
If the coefficient of T1 happens to be zero (i.e. T1 and T2 are found by solving the optimal problem:
ia − ib − ic = 0), then ( ΔE ) 2 does not depend on T1, that means  Edc t1ic + t2 (ib + ic ) + t3ib 
2

any value of T1 in the interval [0; t1] can be a solution to  2 − VC ,low + Cup + Clow
+
minimize ( ΔE ) 2 , and T1 = t1 2 is chosen for a smooth 2
( ΔE ) =   ⎯⎯⎯⎯ → min
switching pattern.  ia + ib − ic ia − ib − ic  0 ≤T1 ≤ t1
0 ≤T2 ≤ t2
 + T1 + T2 
Cup + Clow Cup + Clow 
If T1’s coefficient is not zero, then ( ΔE ) 2 is a quadratic  
function of T1 .
Let Let
 Edc 
 2 − VC ,low  ( Cup + Clow ) + t1ic + t2 (ib + ic ) + t3ib
 Edc 
 2 − VC ,low  ( Cup + Clow ) + t1 (ib + ic ) + t3ib
T12* = −   T13* = −  
ia − ib − ic ia + ib − ic
 Edc 
(The index “2” in T12* denote triangle 2)  2 − VC ,low  ( Cup + Clow ) − t1 (ib + ic ) − t3ib
The optimal solution of T1 is: T23* = −  
ia − ib − ic
T1 = 0 if T12* ≤ 0 The solution of T1 is:
T1 = T12* if 0 < T12* ≤ t1
T1 = t1 if t1 < T12*

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 T1 = t1 2 if ia + ib − ic = 0 T3 = t3 3 if ia + ib + ic = 0
T1 = 0 if T13* ≤ 0 and ia + ib − ic ≠ 0 T3 = 0 if T31* ≤ 0 and ia + ib + ic ≠ 0
T1 = T13* if 0 < T13* ≤ t1 and ia + ib − ic ≠ 0 T3 = T31* if 0 < T31* ≤ t3 and ia + ib + ic ≠ 0
T1 = t1 if t1 < T13* and ia + ib − ic ≠ 0 T3 = t3 if t3 < T31* and ia + ib + ic ≠ 0
The solution of T2 is: Suitable sequence of states and their corresponding
intervals:
T2 = t2 2 if ia − ib − ic = 0
 t −T  T  T  T 
T2 = 0 if T23* ≤ 0 and ia − ib − ic ≠ 0 V33  3 3  → V11  1  → V21  2  → V31  3  →
 2  2 2 2
T2 = T2* if 0 < T23* ≤ t2 and ia − ib − ic ≠ 0
 t −T   t −T   t −T 
T2 = t2 if t2 < T23* and ia − ib − ic ≠ 0 → V12  1 1  → V22  2 2  → V32  3 3  →
 2   2   2 
Suitable sequence of states and their corresponding  t −T   t −T  T 
intervals: → V22  2 2  → V12  1 1  → V31  3  →
 2   2  2
T  T  t  T  T   t −T 
V21  2  → V11  1  → V3  3  → → V21  2  → V11  1  → V33  3 3 
2
  2
  2 2 2  2 
 t −T   t −T   t −T 
→ V22  2 2  → V12  1 1  → V22  2 2 → III. SIMULATION RESULTS
 2   2   2 
To test the validity of this SVPWM strategy, the three-
t  T  T  level NPC converter is used to feed a three-phase RL wye-
→ V3  2  → V11  1  → V21  2 
2 2 2 connected load. The tests are conducted under the purposely
4) When Vs rotates in triangle 1 unbalanced condition of all DC link capacitors and three
T1, T2, and T3 are found by solving the optimal problem: phase loads. All system parameters are shown is table 1.
2
 Edc t (i + i ) + t2 ic  TABLE I. SYSTEM PARAMETERS
 − VC ,low + 1 c b +
 2 Cup + Clow  Parameter Symbol Value
 i −i −i i +i −i  DC link voltage E dc 1200 V
(ΔE )2 =  a b c T1 + a b c T2 +  ⎯⎯⎯⎯ → min Output voltage and frequency Vs 600 V
 Cup + Clow Cup + Clow  0 ≤T1 ≤ t1
0 ≤T2 ≤ t2
Output voltage frequency 50 Hz
  0 ≤ T ≤
3 3t fs
 i +i +i  Sampling frequency f svm 16 kHz
+ a b c T3
 Cup + Clow  Upper capacitor Cup 90 μF
 
Let Lower capacitor C low 110 μF
Inductance of phase a and c loads La , L c 10 mH
 Edc 
 2 − VC ,low  ( Cup + Clow ) + t1 (ic + ib ) + t2ic Inductance of phase b load Lb 11 mH
T11* = −   Resistance of phase a and c loads R a, R c 10 Ω
ia − ib − ic Resistance of phase b load Rb 11 Ω
 dc
E 
 2 − VC ,low  ( Cup + Clow ) + t1 (ic + ib ) + t2ic
Output voltage of phase a and three phase currents are
*   completely in accordance with the theory of three-level NPC
T21 = − converter as shown in Fig. 4 and Fig. 5.
ia + ib − ic
 Edc 
 2 − VC ,low  ( Cup + Clow ) + t1 (ic + ib ) + t2ic
T31 = − 
* 
ia + ib + ic
The solution of T1 is:
Phase a voltage (V)

T1 = t1 2 if ia − ib − ic = 0
T1 = 0 if T11* ≤ 0 and ia − ib − ic ≠ 0
T1 = T11* if 0 < T11* ≤ t1 and ia − ib − ic ≠ 0
T1 = t1 if t1 < T11* and ia − ib − ic ≠ 0
The solution of T2 is:
T2 = t2 2 if ia + ib − ic = 0
T2 = 0 if T21* ≤ 0 and ia + ib − ic ≠ 0
T2 = T21* if 0 < T21* ≤ t2 and ia + ib − ic ≠ 0
T2 = t2 if t2 < T21* and ia + ib − ic ≠ 0
The solution of T3 is: Fig. 4. Phase a voltage of converter

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 Neutral point voltage of method i
(a) method i

Fig. 5. Three phase output currents of the converter

Neutral point voltage of method ii

For easily witness the advantage of the proposed method,
neutral point voltages are shown in Fig. 6 for three cases: i.
Proposed method, ii. Using only one best state for one
vector, and iii. Not using any balancing method, time for
each vector is divided evenly for all its redundant states.
As predicted, Fig. 6 showed that method iii cannot (b) method ii
stabilize neutral point voltage, both methods i and ii can
balance capacitors voltages but the former hold it much
closer to Edc 2 than the latter. The rising time of methods i
and ii are quite similar because during this period both of
them chose the same states for one required vector. The
steady characteristic of method i is obviously better because
it chose the states to manipulate more effectively.
IV. CONCLUSION
This paper proposes an upgraded way to design the series
of states using in three-level NPC converters. In this research
the shared times between the redundant states of one vector
were used as optimizing parameters, which were not paid
attention in former researches. This method does not require
Neutral point voltage of method iii

any additional hardware, hence does not augment the

converter size and manufacturing cost. Moreover, it always
uses three nearest vectors to synthesize the required voltage
vector, which maintains the nature of having multi-level
output phase voltages of the converter. The simulation results
showed the evident advantage of this method.
The methodology here can be widened to apply for any
higher level converters, yet more complex because of the
higher number of redundant states for each vector. (c) method iii
However, this method is slightly sensitive to currents
measurement. Especially when the output voltage frequency
is high and the sample frequency doesn’t accordingly
increase, because the assumption that phase currents change
very little in (1) will not be satisfied.
Future research will focus on finding a new method to
Fig. 6. Neutral point voltage characteristics of: a. Method i; b. Method ii;
estimate neutral point voltage deviation which is related c. Method iii
more to the required output voltage and less to converter’s
load variables.

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 REFERENCES
[1] Z. Pan, F. Z. Peng, Keith A. Corzine, Victor R. Stefanovic, John M.
Leuthen, Slobodan Gataric, “Voltage Balancing Control of Diode
Clamped Multilevel Rectifier/Inverter Systems”, IEEE transactions
on industry applications, vol. 41, no. 6, November/December 2005.
[2] M. Narimani, V. Yaramasu, B. Wu, N. Zargari, G. Cheng, G.
Moschopoulos, “A Simple Method for Capacitor Voltages Balancing
of Diode-Clamped Multilevel Converters Using Space Vector
Modulation” IECON 2013 - 39th Annual Conference of the IEEE
Industrial Electronics Society.
[3] S. A. González, S. A. Verne, M. I. Valla, “Multilevel Converters for
Industrial applications”, CRC Press, 2013
[4] Z. Shu, X. He, Z. Wang, D. Qiu, Y. Jing, “Voltage Balancing
Approaches for Diode-Clamped Multilevel Converters Using
Auxiliary Capacitor-Based Circuits”, IEEE Transactions on Power
Electronics, vol. 28, is. 5, May 2013
[5] S. Shi, X. Wang, S. Zheng, F. Xia, “A New Diode-Clamped
Multilevel Inverter for Capacitor Voltage Balancing”, Progress In
Electromagnetics Research M, January 2016
[6] S. Shi, X. Wang, S. Zheng, Y. Zhang, D. Lu, “A New Diode-Clamped
Multilevel Inverter With Balance Voltages of DC Capacitors”, IEEE
Transactions on Energy Conversion, vol.33, is. 4, December 2018
[7] C. Li, T. Yang, P. Kulsangcharoen, G. L. Calzo, S. Bozhko, C.
Gerada, P. Wheeler, “A Modified Neutral Point Balancing Space
Vector Modulation for Three-Level Neutral Point Clamped
Converters in High-Speed Drives”, IEEE Transactions on Industrial
Electronics, vol. 66, is. 2 , February 2019

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