Acer Nitro 5 AN515!55!53E5 GH51M LA-K861P Rev 1A Schematic Diagram

A B C D E
1 1
2
Compal LA-K861P 2
MB Schematic Document
GH51M
3
Rev:1.A 3
2020.11.19
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom GH51M M/B LA-K861P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 01, 2020 Sheet 1 of 112
A B C D E
A B C D E
mDP - JDP1 HDMI - JHDMI1 eDP - JEDP1 Interleaved (DDR4 2666/2933)

DDI Memory BUS
- VGA Port E - VGA Port C - CPU eDP Comet Lake H-Refresh Processor - DDR4 So-DIMM 260 pin
BGA1440 (42X28) - Channel A
N18P-G61-A - BANK 0,1,2,3
- Address : 0XA0/1 P.23
1
P.39 P.40 GN20-P0/P1 P.38
1
- DDR4 So-DIMM 260 pin

- GDDR6 4G PEG x16 - Channel B
8GT/s - BANK 4,5,6,7
- Address : 0XA3/4 P.24
VBIOS ROM
P.27-37 P.6-13
- SOP8
- Size : 1M/2M
P.29 X4 DMI
LAN(GbE) JRJ45 USB3.1 - JUSB 3 USB3.1 - JUSB 2 USB3.1 - JUSB 1 Type C - JUSBC1
- PCIE 1.0 2.5GT/s - GEN2 - USB3.1 GEN2
- Port 14 - On M/B - USB3.1 Port3&4 Comet Lake PCH-H SPI ROM 16M
- Port 1 SPI
- E2600 - GEN1
- USB3.1 Port 2
- GEN1
- USB3.1 Port 5 - W/USB Charger
- RTS5441E FCBGA874 (25X24) - SOP8
- Size : 16M
- USB2.0 Port 2 - USB2.0 Port 3 (SLGC55544) P.16
P.71 P.42-43
CML-H : HM470
2
USB3 Re-driver USB3 Re-driver 2
- PS8713 - PS8713
IO_B
P.73 LPC/eSPI BUS
P.14-21
HDD - JHDD1 SSD - JSSD3 (PCIE/SATA) SSD - JSSD2 (PCIE/SATA) SSD - JSSD1 (PCIE) TPM
HD Audio I2C - NPCT750
- SATA 3.0 P.66
- Port 13
(SATA 0B)
- PCIE 2.0 5GT/s - PCIE 2.0 5GT/s - PCIE 2.0 5GT/s
- PCIE Port 17-20 - PCIE Port 9-12 - PCIE Port 21-24 EMR - JEMR1 Touch Pad
P.67
- SATA @ Port 17
P.69
- SATA @ Port 12
P.68 P.68
EC KB9022
- PCH I2C0
P.64
- EC PS2 P.58
- PCH I2C1 P.63
3
I2C/PS2 3
WIFI - JNGFF1 DDC Camera Finger print Tuch Screen Fan Control*2
page 77
- Port 5 - USB2 Port 8 - USB2 Port 6
- PCH I2C2
P.38 P.66 P.38
- PCIE1.0 2.5GT/s - USB2 Port 4

- PCIE Port 15 P.52 Extend IC Int.KBD
HDA Codec
- I2C
- ALC295 - KC3810 P.59
Sub Board
P.56
IO/B (JIO1/JIO2) P.73 - KSI/KSO
HS/B (JHS1) P.66
- W/BL or 4 Zone RGB
P.63
TURBO/B (JTRB1) P.77 Int. Speaker Int. DMIC Audio Jack
RTC CKT. (JRTC1)

4 P.20 4
Power On/Of f CKT. - ON IO/B > L - On CCD Module - On IO/B

P.63
- ON M/B > R
HW Circuit DC/DC Security Classification Compal Secret Data Compal Electronics, Inc.
P.78
2019/09/20 2020/09/20 Title
Issued Date Deciphered Date Block Diagrams
Power Circuit DC/DC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number
Custom
R ev
1A
P.82-111 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. GH51M M/B LA-K861P
A B C D E
A B C D E
Vcc 3.3V +/- 5% *PCB Version SIGNAL

STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS
Ra 100K +/- 1% EC Board ID Table for AD channel *Key board type
S0 (Full ON) HIGH HIGH HIGH ON ON ON
Board ID Vmin Vtyp Vmax EC AD Board ID PCB Revision
Rb S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF
0 0 0.000 V 0.300 V 0x00 - 0x13 0 50 Rev0.1
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E SD034120280 1 50 Rev0.2
S5 (Soft OFF) LOW LOW LOW ON OFF OFF
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 SD034150280 2 50 Rev1.0
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 SD034200280 3 Power Plane Description S0 S3 S4 S5
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A SD034270280 4 50 Rev0.1+RGB +RTCVCC RTC Battery Power ON ON ON ON
1 5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 SD034330280 5 50 Rev1.0+RGB +19V_VIN Adapter power supply N/A N/A N/A N/A 1
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54 SD034430280 6 +12.6V_BATT Battery power supply N/A N/A N/A N/A
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64 SD034560280 7 +19VB AC or battery power rail for power circuit. N/A N/A N/A N/A
8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 SD034750280 8 +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON
9 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 SD034100380 9 +5VALW +5V Always power rail ON ON ON ON
10 130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 SD034130380 10 +3VALW System +3VALW always on power rail ON ON ON ON*
11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 SD034160380 11 +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON
12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF SD034200380 12

13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 SD000001B80 13
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF SD00000G280 14 +1.05VALW +1.05V Always power rail ON ON ON ON
330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 SD034330380 15 +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF
15
430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 SD00000WM80 16 +1.05V_VCCST Sustain voltage for processor in Standby modes ON ON OFF OFF
16
560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD SD034560380 17 +5VS System +5V power rail ON OFF OFF OFF
17
750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0 SD00000AL80 18 +3VS System +3V power rail ON OFF OFF OFF
18
NC 3.000 V 3.000 V 0xF1 - 0xFF 19 +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF
19
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF OFF
Address(8bit)
+VCC_CORE Core voltage for CPU ON OFF OFF OFF
BUS Device Address(7 bit) Write Read
+VCC_GT Sliced graphics power rail ON OFF OFF OFF
2 I2C_0 (+3VS) XXXXXX (EMR) +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF 2
I2C_1 (+3VS) TM-P3393-003 (Touch Pad) +VCC_SA System Agent power rail ON OFF OFF OFF
DIMM1 +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
PCH_SMBCLK
(+3VS) DIMM2 +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF
+NVVDD1 Core voltage for VGA (merge core & core_s) ON OFF OFF OFF
+FBVDDQ +1.35VS power rail for GPU ON OFF OFF OFF

N18P-G61-A/GN20P (VGA) 0x9E +PEXVDD +1.0VS power rail for GPU ON OFF OFF OFF
PCH_SML1CLK
(+3VALW) Thermal Sensor (NCT7718W) 1001_100xb 1001_1001b 1001_1000b +1.8VALW System +1.8VALW always on power rail ON ON ON ON*
EC_SMB_CK2 Thermal Sensor (G781) 1001_101xb 1001_1011b 1001_1010b
(+3VS) PCH 0x90
BQ24780 (Charger IC) 0x12
EC_SMB_CK1
(+3VLP) BATTERY PACK 0x16 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC_SMB_CK3 LED driver 0xC0

(+3VALW)
Reserved KC3810 Reserved
3 3
Item (X43 / X76) BOM Structure Item (X43 / X76) BOM Structure 43 Level Descript i on BOM Structure
Unpop @ eDP-TS USB TS_USB@
Connector CONN@ eDP-TS USB NONTS_I2C@ V
PCB PCB@ V eDP-TS I2C TS_I2C@
UMA Only(Reserved) UMA@ mDP DP@ V
H62 CPU(Reserved) H62@ For Acer IOAC IOAC@ V
H82 CPU(POP) H82@ V No Acer IOAC NIOAC@
CFL i5QS CPU CFLi5QS@ Intel CNVi CNVI@ V
CFL i5 CPU CFLi5@ FOR UART BT module UART_BT@
CFL QS PCH CFLPCHQS@ FOR UART debug UART@
Extend GPIO KC3810@
CML i5QS CPU CMLi5QS@
CML i7QS CPU CMLi7QS@ Finger Print FP@ V
CML i9QS CPU CMLi9QS@ FinerPrint(with PBA) PBA@ V
CML QS PCH Remove KBLED@
CML i5 CPU CMLi5@ KB LED driver LED14P@
CML i7 CPU CMLi7@ EMR 1.8V WC18V@ Item (X4E) BOM Structure Item (X76) BOM Structure
4
CML i9 CPU EMR 3.3V WC33V@ EMI requirement EMI@ V OVRM-uPI uPI_X76@
X76869BOL01 - MICRON 4
CML PCH CMLPCH@ Thermal sensor TMS@ V EMI require reserve XEMI@ OVRM-ON ON_X76@ X76869BOL02 - SAMSUNG
TPM pop TPM@ ESD requirement ESD@ V VRAM-SAMSUNG X76SAM@ X76869BOL03 - ON OVRM
TPM non-pop NTPM@ V ESD require reserve XESD@ VRAM-MICRON X76MIC@ X76869BOL04 - UPI OVRM
dGPU circuit VGA@ V SSD3 pop SSD3@ FP ESD requirement FPESD@ V
N17P GPU N17P@ Security Classification Compal Secret Data Compal Electronics, Inc.
2019/09/20 2020/09/20
N18P GPU N18P@ V Issued Date Deciphered Date Title
N18P-G61 VGAG61@ PCB 1A 1A@ X4EAMBBOL01 PG6162 FOR EE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
N18P-G62 MP2 VGAG62@ PCB 1A With RGB 1ARGB@ X4EP4MBOL01 PG6162 IO FOR EE MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. GH51M M/B LA-K861P
A B C D E
5 4 3 2 1
DC_IN
PL101,2,3
PJP101
+19V_VIN
AC CONN. +2.5VP JDIMM1
+12.6V_BATT+ PU2501 PJ2502 +2.5V
+12.6V_BATT DDR4 Conn.
PL201,2 BATTERY +1.0VSDGPUP
JDIMM2
+1.0VSDGPU GPU
PJP201 PU1002 PJ1003
D IMVP8 D
+19VB_CPU
PUZ2,3,4,5 +VCC_CORE CPU UQ1 JPQ1 +3VS
PUB1 +19VB PLZ1,2,3,4 UO1 +3VS SATA Re-driver
EN:DRVON
R19 +3VALW_TPM U5 TPM
UV45 +3VSDGPU GPU
UM1 +3VS_WLAN JNGFF1 WLAN CARD Conn.
+19VB_CPU +3VS_WLAN
RM11 JNGFF1 WLAN CARD Conn.
CHARGER +19VB
PRG5 PLG1 +VCC_GT CPU UL1 +3V_LAN UL2 LAN
EN:DRVON R20 +3VS_TPM U5 TPM
UK1 +3V_PTP JTP1 TP Conn.
UX1 +LCDVDD JEDP1 PANEL
+19VB_CPU UM2 RM54 +3VS_SSD1 JSSD1 SSD Conn. +3VS_DVDDIO
PRA3 RA2 CODEC
PLA1 +VCC_SA CPU +3VS_SSD2
+19VB UM2 RM55 JSSD2 SSD Conn. +3VS_DVDD
EN:DRVON RA4 CODEC
RH101 +3VALW_HDA PCH
+3VALWP
EN:3V_EN +3VALW RH99 +3VALW_DSW PCH
PJ302
+19VB
PU301 +FP_VCC
EC,LID +3VLP
UK2 JFP1 FP Conn.
C C
+1.2VP
CPU,Memory JPH1 +1.05VALW_PRIM PCH
EN:SYSON +1.2V_VDDQ +1.2V_VCCPLL_OC
PJM2 RC24 CPU
RH94 +1.05VALW_PCH PCH
+19VB
PUM1 EN:SM_PG_CTRL RH102 +1.05VALW_VCCAZPLL
+0.6VSP RH103 +1.05VALW_VCCAMPHYPLL
+0.6VS_VTT +1.05VALW_XTAL
PCH
PJM3 RH105
+1.05VALWP
PU1101 +1.05VALW UQ2 RQ5 +1.05V_VCCST
+19VB
PJ1101 CPU
EN:+1.8_PG
UC4 +1.05VS_VCCSTG
EN:DGPU_PWR_EN
+1.0VS_VCCIOP
+1.8VSDGPU_AON UV48 +FP_FUSE_GPU GPU
+VCCIO
CPU
+19VB
PUH1 PJH1 +1.8VSDGPU_MAIN GPU
EN:SUSP# UG27
B UQ2 RQ9 +1.8VS RA3 +1.8VS_VDDA CODEC B

+1.8VALWP
PU1801 PJ1801 +1.8VALW RH100 +1.8VALW _PRIM PCH

+19VB
EN:SPOK_3V
RS127 +5VALW_MUX US3 CC logic/U3 MUX
+5VALWP +5VALW
PU501 JIO1 JIO1 IO/B Conn.
+19VB
PJ502 +5VALW
US11 +USB3_VCCC JTYPEC1 Type-C Conn.
US12 +USB_VCCA JUSB1 USB3.0 Conn. +VCC_FAN1

RF4 JFAN1 FAN1 Conn.
US13 +USB_VCCB JUSB2 USB3.0 Conn. +VCC_FAN2
+19VB
NVVDD_B+ RF7 JFAN1 FAN2 Conn.
GPU
PUV1 PUV2,3 PLV2,3 +NVVDD1 UE5 +5V_LEDPWR JBL2 KB BackLight Conn. +VDDA
JPA1 UA1 CODEC
UK2 +FP_VCC JFP1 FP Conn. +5VS_BL
U4 JBL1 KB BackLight Conn.
UQ1 JPQ2 +5VS +5VS_HDD
EN:1.35VSDGPU_EN RO4 JHDD1 HDD Conn.
+19VB
GPU_B+ GPU +HDMI_5V_OUT
A +1.35VSDGPU UY2 JHDMI1 HDMI Conn. A
PUW1 PLW1
+TS_PWR
RX7 JEDP1 Touch Screen
+19VB → +19VB_CPU
LX1 +INVPWR_B+
PANEL
Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
5 4 3 2 1
A B C D E
DH5VF_EVT Power Sequence AC mode

BIOS ver: V0.02W1
EC: ver: V002AT04
1 1
Plug in Power On S3 S3 Resume Power Off

+3VLP
+3VLP
EC_ON
→ 330.8ms
EC_ON
+5VALW
→ 333.3ms
+5VALW
ON/OFFBTN#
ON/OFFBTN#
→ 92.03ms
+3VALW +3VALW
→ 94.88ms → 293.7us
+1.05VALW +1.05VALW
→ 29.19ms
EC_RSMRST# EC_RSMRST#
20.1ms
2.439ms → ← →
PBTN_OUT# PBTN_OUT#
174.6ms → 19.18ms
PM_SLP_S4# PM_SLP_S4#
→ 19.22ms 100.5us
PM_SLP_S3# PM_SLP_S3#
→ 72.1us → 152.8us
2 SYSON SYSON 2
→ 275.9us → 88.37us
+1.05V_VCCST +1.05V_VCCST
→ 692.9us → 367.6us
+1.2V_VDDQ +1.2V_VDDQ
→ 910.1us 2.266ms
+2.5VS
→ +2.5VS
→ 12.7ms 13.01us 67.04ms 13us
SUSP#
→ → → SUSP#
→ 8.378us → 55.47us → 8.502us → 68.53us
+1.05VS_VCCSTG +1.05VS_VCCSTG
→ 877.7us → 618.5us → 906.0us → 686.0us
+5VS +5VS
→ 630.4us → 8.679ms → 656.1us → 11.65ms
+3VS +3VS
→ 412us → 347.6us → 424.9us 446.2us
+1.8VS +1.8VS
→ 25.34ms → 0us → 25.25ms 0us
EC_VCCST_PG EC_VCCST_PG
→ 25.35ms → 0us → 25.25ms → 13.97ms
SM_PG_CTRL SM_PG_CTRL
→ 25.36ms → 3.819ms → 25.26ms → 2.034ms
+0.6VS_VTT +0.6VS_VTT
→ 25.19ms → 26.91us → 25.59ms → 27.06us
VR_ON VR_ON
→ 1.759ms → 51.25us → 1.757ms → 48.00us
+VCC_SA +VCC_SA
→ 173.0ms → 87.75us → 167.1ms → 112.0us
3 +VCC_CORE +VCC_CORE 3
→ NA → NA → NA NA
+VCC_GT +VCC_GT
→ 12.42ms → 47.39us → 12.18ms → 47.83us
PCH_PWROK PCH_PWROK
→ 150.3ms → 61.95us → 150.6ms → 62.37us
SYS_PWROK SYS_PWROK
→ 152.3ms → 318.7us → 151.8ms
PLT_RST# PLT_RST#
4 4
2019/09/20
Compal Secret Data
2020/09/20 Title
Power Sequence
A B C D E
A B C D E
Comet Lake-H Refresh
CPU PCH NVIDIA PCB

UC1 UH1 UV1 ZZZ
1 CMLRi52@ CMLPCH@ N18PA@ PCB@ 1
S IC CL8070104441108 SRK3X R1 2.4G ABO ! S IC FH82HM470 SRJAU A0 FCBGA PCH-H ABO! S IC N18P-G61-A-A1 BGA 1358 GPU ABO ! PCB 3AU LA-K861P REV0 MB 4 S
SA0000DW130 SA0000DDP80 SA0000DVM50 DAA000OQ000
UC1 UV1
CMLRi53@ N20Z@
S IC CL8070104399510 SRH84 R1 2.5G ABO! S IC N20Z-QS1-A1 QS1 BGA 1358 S

SA0000DCP40 SA0000E1W10
UC1
CMLRi55@
S IC CL8070104409309 SRK3Z R1 2.5G ABO !

SA0000E0Y20
UC1
CFL-H
CMLRi77@ @ UC1D
S IC CL8070104399315 SRH8Q R1 2.6G ABO !

K36 D29 EDP_TXP0
SA0000DCN40 DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <38>
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <38>
2 J35 F28 2
DDI1_TXP_1 EDP_TXP_1 EDP_TXN1 EDP_TXP1 <38>
UC1 J34 E28
DDI1_TXN_1 EDP_TXN_1 EDP_TXP2 EDP_TXN1 <38>
H37 A29
EDP_TXP2 <38>
CMLRi78@ H36 DDI1_TXP_2
DDI1_TXN_2
EDP_TXP_2
EDP_TXN_2
B29 EDP_TXN2
EDP_TXP3 EDP_TXN2 <38>
eDP
J37 C28
DDI1_TXP_3 EDP_TXP_3 EDP_TXN3 EDP_TXP3 <38>
S IC CL8070104399317 SRK3Y R1 2.2G ABO! J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <38>
SA0000DW230 EDP_AUXP
D27 C26 EDP_AUXP <38>
E27 DDI1_AUXP EDP_AUXP B26 EDP_AUXN
DDI1_AUXN EDP_AUXN EDP_AUXN <38>
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37 DDI2_TXN_2 DISP_RCOMP
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil
F26
E26 DDI2_AUXP
DDI2_AUXN
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
3 C33 DDI3_TXN_2 3
B33 DDI3_TXP_3
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_SDO_R CPU_DISPA_BCLK_R <18>
A27 G25 CPU_DISPA_SDO_R <18>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI_R <18>
CFL-H_BGA1440 20191024
- SDI 20 ohm close to CPU
- BCLK/SDO 30 ohm close to PCH
4 4

CFL-H(1/8)DDI/eDP
A B C D E
A B C D E
CHANNEL-A Interleaved Memory

CFL-H
@UC1A
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_W E# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4 DDR_A_MA1 <23>
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2
AA5 AP5 DDR_A_MA3 <23>
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <23>
AB4 AP1 DDR_A_MA5 <23>
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
V4 AE3 DDR_A_MA13 <23>
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23>
U4 AU3 DDR_A_ACT# <23>
DDR_A_D48 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT#
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5 DDR_A_ALERT# <23>
DDR_A_D51 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT#
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
M5 L3 DDR_A_DQS#7 <23>
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3 DDR_A_DQS1 <23>
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR4 BC3 DDR_A_DQS3 <23>
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS5 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5 <23>
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13 For ECC DIMM
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
4 4

CFL-H(2/8)DIMMA
A B C D E
A B C D E
CHANNEL-B Interleaved Memory

CFL-H
@ UC1B
<24> DDR_B_D[0..63] DDR CHANNEL B
1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <24>
BR11 AN9 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <24>
BR8 AM8 DDR_B_CLK#1 <24>
DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
BL8 AT10 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
BJ7 AE7 DDR_B_CS#1 <24>
DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
BF11 AE8 DDR_B_ODT1 <24>
DDR_B_D21 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_W E# DDR_B_MA16_RAS# <24>
BC11 AH11 DDR_B_MA14_W E# <24>
DDR_B_D26 BB8 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 AF8 DDR_B_MA15_CAS#
DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24>
BB10 AH9 DDR_B_BA1 <24>
DDR_B_D30 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0
DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <24>
AA10 AK6 DDR_B_MA1 <24>
DDR_B_D34 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
AC10 AL5 DDR_B_MA3 <24>
DDR_B_D36 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <24>
AA8 AM6 DDR_B_MA5 <24>
DDR_B_D38 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <24>
AC7 AN10 DDR_B_MA7 <24>
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
W7 AR11 DDR_B_MA9 <24>
DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
V11 AN11 DDR_B_MA11 <24>
DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
W10 AF9 DDR_B_MA13 <24>
DDR_B_D46 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24>
V8 AT9 DDR_B_ACT# <24>
DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT#
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <24>
P7 AR8 DDR_B_ALERT# <24>
DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT#
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#1 DDR_B_DQS#0 <24>
R7 BL9 DDR_B_DQS#1 <24>
3 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2 3
L11 BC9 DDR_B_DQS#3 <24>
DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
L7 W9 DDR_B_DQS#5 <24>
DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
L10 M9 DDR_B_DQS#7 <24>
DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS1 DDR_B_DQS0 <24>
L8 BJ9 DDR_B_DQS1 <24>
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3 <24>
AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS5 DDR_B_DQS4 <24>
AY8 V9 DDR_B_DQS5 <24>
AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS7 DDR_B_DQS6 <24>
AY10 L9 DDR_B_DQS7 <24>
AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 For ECC DIMM
RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
CFL-H_BGA1440
4 Trace Width/Space: 15 mil/ 25 mil 4
Max Trace Length: 500 mil

CFL-H(3/8)DIMMB
A B C D E
A B C D E
PEG&DMI
1 1
CFL-H
UC1C
E25 B25
D25 PEG_RXP_0 PEG_TXP_0 A25
PEG_RXN_0 PEG_TXN_0
E24 B24
F24 PEG_RXP_1 PEG_TXP_1 C24
PEG_RXN_1 PEG_TXN_1
E23 B23
PEG_RXN_2 PEG_TXN_2
E22 B22
PEG_RXN_3 PEG_TXN_3
E21 B21
PEG_RXN_4 PEG_TXN_4
E20 B20
PEG_RXN_5 PEG_TXN_5
E19 B19
To N18PG61A / N20P DGPU x 8 Lane PEG_RXN_6 PEG_TXN_6 To N18PG61A / N20P DGPU x 8 Lane
E18 B18
PEG_RXN_7 PEG_TXN_7
CC33 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0201_6.3V6K 2 1VGA@ CC34
<27> PEG_CRX_C_GTX_P7 PEG_CRX_GTX_N7 PEG_RXP_8 PEG_TXP_8 PEG_CTX_GRX_N7 PEG_CTX_C_GRX_P7 <27>
2
<27> PEG_CRX_C_GTX_N7 CC35 VGA@ 1 2 0.22U_0201_6.3V6K E17 B17 0.22U_0201_6.3V6K 2 1VGA@ CC36 2
PEG_RXN_8 PEG_TXN_8 PEG_CTX_C_GRX_N7 <27>
CC37 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0201_6.3V6K 2 1VGA@ CC38
<27> PEG_CRX_C_GTX_N6 CC39 VGA@ 1 2 0.22U_0201_6.3V6K E16 B16 0.22U_0201_6.3V6K 2 1VGA@ CC40
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<14> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <14>
<14> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <14>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<14> DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 <14>
DMI_RXN_1 DMI_TXN_1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
<14> DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2 <14>
DMI_RXN_2 DMI_TXN_2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<14> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <14>
<14> DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3 <14>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
@
4 4

PEG/DMI
A B C D E
A B C D E
571391_CFL_H_PDG_Rev0p5 CFL-H
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch). UC1E
2. Route the Alert signal between the Clock and the Data signals.
3. Place those resistors close CPU side.
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%
<15> PCH_CPU_BCLK_P PCH_CPU_BCLK_N BCLKP CFG_0
<15> PCH_CPU_BCLK_N A32 BN27 CFG2 RC8 1 2 1K_0402_5%
BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG5 RC10 1 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCI_BCLKP CFG_3
<15> PCH_CPU_PCIBCLK_N C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<15> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLK24P CFG_6
<15> PCH_CPU_24M_CLK_N D31 BP20 CFG7
CLK24N CFG_7 BR23
CFG_8 BR22
1 1
CFG_9 BT23 The CFG signals have a default value of '1' if not terminated on the board.
CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13 BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
CPU_SVID_CLK_R BH32 VIDALERT# CFG_15 * 0 = Lane numbers reversed.
<97> CPU_SVID_CLK_R CPU_SVID_DAT_R VIDSCK CFG[4]: eDP enable:
BH29 BN23
H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 1 = Disabled.
PROCHOT# CFG_16 BP22 * 0 = Enabled.
DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
XDP_BPM#0 10 = 2 x8 PCI Express*
BR27 TC1 @ 11 = 1 x16 PCI Express*
BPM#_0 BT27 XDP_BPM#1 *
Sensitive BPM#_1 TC2 @
BM31 XDP_BPM#2 CFG[7]: PEG Training:
BPM#_2 TC3 @
EC_VCCST_PG H13 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 @ 0 = PEG Wait for BIOS for training.
H_CPUPW RGD BT31
<18> H_CPUPW RGD H_PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
BP35 BT28 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<17> H_PLTRST_CPU# H_PM_SYNC_R RESET# PROC_TDO CPU_XDP_TDI CPU_XDP_TDO <18>
<17> H_PM_SYNC_R BM34 BL32
H_PM_DOW N PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <18>
BP31 BP28
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <18>
BT34 BR28
<17,58> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <18> To be confirm
RC17 1 @ 2 0_0402_5% J31
<17> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <21>
@ TC5 SKTOCC# BR33 BL30 TC19 @
BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY#
20191024 PROC_SELECT# PROC_PRDY# TC20 @
PROC_SELECT#
2
@ TC6 CATERR# BM30 2
> should be unconnected on CFL/CML processor CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1% XDP_PREQ#
CFG_RCOMP XDP_PRDY# XDP_PREQ# <21>
AT13
ESD@ 20200225 AW13 ZVM# Trace Width/Space: 4 mil/ 12 mil XDP_PRDY# <21>
1000P_0402_50V7K 1 2 CC65 H_CPUPW RGD - Pop CC65 & change to 1000p_0402 MSM# Max Trace Length: 600 mil
AU13
ESD@ AY13 RSVD1 *20191024
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RSVD2 - CML RCP/PDG/Check list , PROC_TDO PU 100 ohm to VCCXT
5 OF 13 *20191104
XESD@ +1.05VS_VCCSTG - CMC@ change to always pop (RC76/77/78/79)
0.1U_0201_10V6K 1 2 CC67 H_THERMTRIP# CFL-H_BGA1440
@ Place to CPU side
ESD@ RC76 2 1 51_0402_5% CPU_XDP_TMS
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG
+1.2V_VDDQ
RC77 2 1 51_0402_5% CPU_XDP_TDI
RC78 2 1 51_0402_5% CPU_XDP_TDO

Near CPU side CC69 +3VS
8/21 follow 1050 Request 0.1U_0201_10V6K
2 1 Place to CPU side
1
RC79 2 1 51_0402_5% CPU_XDP_TCK0
+1.05V_VCCST RC23
RH1 1 2 1K_0402_5% H_THERMTRIP# 330K_0402_5% RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
PCH_JTAG_TCK1 <18>
5
1
UC3
RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
2
Vcc
DDR_PG_CTRL 2 NC 4
A Y SM_PG_CTRL <89>
G
3 +1.05VS_VCCSTG
8/21 PU 330K follow CRB 3
74AUP1G07SE-7_SOT353-5
3
1
RC21
1K_0402_5%
2
RC14 1 2 499_0402_1% H_PROCHOT#_R

<58,85> H_PROCHOT# SVID
+1.05V_VCCST
+1.05V_VCCST
1
RC22
1K_0402_5%
RC19 RC20
56_0402_1% 100_0402_1%
2
RC15 1 2 60.4_0402_1% EC_VCCST_PG

<58,78> EC_VCCST_PG_R
RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

<17> H_PM_DOW N_R <97> CPU_SVID_ALERT#_R
4 4
1
CPU_SVID_DAT_R
<97> CPU_SVID_DAT_R
RH2
@ 13_0402_5%
2

CFL-H(5/8)CFG,SVID
A B C D E
A B C D E
GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
VCCGT66 VCCGT145 @
3 BC32 BM16 AG37 VCC_SENSE_IA 3
VCCGT67 VCCGT146 VCC_SENSE VSS_SENSE_IA VCC_SENSE_IA <97>
BC35 BM17 9 OF 13 AG38 0926
VCCGT68 VCCGT147 VSS_SENSE VSS_SENSE_IA <97> Modify net by power
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 @ 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
AH37 VSS_SENSE_GT
11 OF VSSGT_SENSE VCC_SENSE_GT VSS_SENSE_GT <97>
13 AH38
VCCGT_SENSE VCC_SENSE_GT <97>
CFL-H_BGA1440
@ 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
4 4

CFL-H(6/8)VCC_CORE/GT
A B C D E
A B C D E
+1.2V_VDDQ
Max: 3300mA
+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

UC1L
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6
VCCSA1 VDDQ1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Max: 11100mA K29 AE12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 VCCSA2 VDDQ2 AF5
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12
+VCC_IO M35 VCCSA20 VDDQ20 L6 RC24 1 @ 2 0_0402_5%
Max: 6400mA VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
M36 R6
VCCSA22 VDDQ22
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23 W6
VDDQ24 1 1 1 1
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCC_SENSE_SA
VCCIO18 VCCSA_SENSE VSS_SENSE_SA VCC_SENSE_SA <97>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSS_SENSE_SA <97>
J26 150mA
J27 VCCIO20 H14 VCC_SENSE_VCCIO
VCCIO21 VCCIO_SENSE VSS_SENSE_VCCIO VCC_SENSE_VCCIO <92>
J14 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
12 OF 13 VSSIO_SENSE VSS_SENSE_VCCIO <92>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4

CFL-H(7/8)VCCSA/VCCIO/VDDQ
A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 @ TC7 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 IST_TRIG E3
VSS_4 VSS_85 VSS_166 VSS_247 VSS_329 VSS_413 Impedance Spectrum Tool Trigger @ TC8 IST_TRIG
A20 AL33 B9 BJ29 BP21 F23 @ TC9 E1
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP24 VSS_330 VSS_414 F25 D1 RSVD_TP4
VSS_6 VSS_87 VSS_168 VSS_249 VSS_331 VSS_415 @ TC10 RSVD_TP3
A24 AL4 BA11 BJ31 BP25 F27
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 @ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 @ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <21> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <21> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 @
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 @
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 @
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 @
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 @
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 @
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@
4 4

CFL-H(8/8)GND/RSVD
A B C D E
A B C D E
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<9> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <71>
<9> DMI_CTX_PRX_P0 J35 J2 USB3 MB
DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <71>
<9> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <73>
<9> DMI_CRX_PTX_P0 B33 N15 USB2 (SUB/B)
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <73>
<9> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <73>
<9> DMI_CTX_PRX_P1 F34 K3 USB2 (SUB/B)
<9> DMI_CRX_PTX_N1 C32 M10
<9> DMI_CRX_PTX_P1 B32 L9 TYPE C
DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <43>
<9> DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <38>
<9> DMI_CTX_PRX_P2 J32 L2 Camera
<9> DMI_CRX_PTX_N2 C31 K7
1 <9> DMI_CRX_PTX_P2 B31 K6 TS 1
DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_P6 <38>
<9> DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3
<9> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<9> DMI_CRX_PTX_N3 C29 G4
<9> DMI_CRX_PTX_P3 B29 G5 FingerPrint
DMI3_TXP USB2P_8 USB20_P8 <66> +3VALW
A25 M6
B25 RSVD USB2N_9 N8
P24 RSVD USB2P_9 H3
R24 RSVD USB2N_10 H2 USB_OC0# RH200 1 2 10K_0402_5%
C26 RSVD USB2P_10 R10 USB_OC1# RH201 1 2 10K_0402_5%
B26 RSVD USB2N_11 P9
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2
L26 RSVD USB2P_13 E5 USB20_N14
RSVD USB2N_14 USB20_P14 USB20_N14 <52>
M26 F6 BT For CNVI follow 571906_CNL_PCH_TA_WW11.pdf
RSVD USB2P_14 USB20_P14 <52>
D29
E28 RSVD AH36 USB_OC0#
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <43>
K29 AL40 USB_OC1# <71>
M29 RSVD GPP_E10/USB2_OC1# AJ44
RSVD GPP_E11/USB2_OC2# AL41 +3VALW
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
1
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN USB2_RCOMP RH3
P21 F4 RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE 10K_0402_5%
B18 F3 RH5 1 @ 2 0_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
2
2 GPD_7 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID 1 2 0_0402_5%
PCIE3_RXN/USB31_9_RXN USB2_ID
RH6 @ STRAP
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
1
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP RH7
N18 G45
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_P24 <68> 10K_0402_5%
R18 G46 M.2 SSD1 PCIE L3
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_DRX_N24 <68> @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 PCIE_PRX_DTX_P24 <68>
2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PRX_DTX_N24 <68>
X'tal Input:
G20 PCIE5_RXN PCIE23_TXP G49 PCIE_PTX_DRX_P23 <68>
PCIE5_RXP PCIE23_TXN PCIE_PTX_DRX_N23 <68>
M.2 SSD1 PCIE L2 High: Differential
B21 W44 Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
K21 PCIE5_TXP PCIE23_RXN H48 PCIE_PRX_DTX_N23 <68>
J21 PCIE6_RXN PCIE22_TXP H47 PCIE_PTX_DRX_P22 <68>
PCIE6_RXP PCIE22_TXN PCIE_PTX_DRX_N22 <68>
M.2 SSD1 PCIE L1
D21 U41
C21 PCIE6_TXN PCIE22_RXP U40 PCIE_PRX_DTX_P22 <68>
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PRX_DTX_N22 <68>
C23 PCIE7_TXP PCIE21_TXP G47 PCIE_PTX_DRX_P21 <68>
PCIE7_TXN PCIE21_TXN PCIE_PTX_DRX_N21 <68>
M.2 SSD1 PCIE L0
J24 R44
L24 PCIE7_RXP PCIE21_RXP T43 PCIE_PRX_DTX_P21 <68>
F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
3 3
The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes
‧
— A maximum of 16 PCIe* Ports (or devices) can be enabled
When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
4 4
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

PCH(1/8)DMI/PCIE/USB2
A B C D E
A B C D E
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H
XTAL_24M_PCH_OUT XTAL_24M_PCH_OUT_R
remove TP as C5PRH UH1G
1 EMI@ 2 BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<10> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# @ TH2
C6 Y4 @ TH3
XTAL_24M_PCH_IN 1 EMI@ 2 XTAL_24M_PCH_IN_R <10> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
1 2
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6
<10> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <10>
C8 A6
<10> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <10>
YH1
24MHZ_18PF_7R24000001 XTAL_24M_PCH_OUT_R U9 AJ6
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA# <27>
1 U10 AJ7 DGPU 1
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <27>
3 1
3 1 XCLK_BIASREF
33P_0402_50V8J
18P_0402_50V8J
RH10 1 2 60.4_0402_1% T3 AH9
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN# <73>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <73>
CH5
CH6
XCLK_BIASREF (PDG) BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN# <52>
8/24 AE15 NGFF WL+BT(KEY E)
VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <52>
BF31
BE31 GPP_B5/SRCCLKREQ0# AE6
<73> LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF1# <68>
<52> W LAN_CLKREQ# AR32 AE7 M2 SSD1
GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF1 <68>
<68> SSD2_CLKREQ# BB30
BA30 GPP_B8/SRCCLKREQ3# AC2
PCH_RTCX1 <68> SSD1_CLKREQ# GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_NGFF3# <68>
<69> SSD3_CLKREQ# AN29 AC3 M2 SSD3
GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_NGFF3 <68>
AE47
PCH_RTCX2 20190918 SSD2&3 Change AC48 GPP_H0/SRCCLKREQ6# AB2
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_NGFF2# <69>
AE41 AB3 M2 SSD2
GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_NGFF2 <69>
1 2 20191209 AF48
RH12 10M_0402_5% > SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2) AC41 GPP_H3/SRCCLKREQ9# W4
20200114 > SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1)
AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
> SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW) GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
- CH7/CH8 Change to SE173100J80 AE39
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
remove no use srcclkreq AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15#
10P_0201_50V8J
10P_0201_50V8J
1 1 AC14
V2 CLKOUT_PCIE_N8 AC15
32.768KHZ_9PF_X1A000141000200
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 2 T2 CLKOUT_PCIE_N9 U3
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 Trace Space: 15 mil CLKOUT_PCIE_P14 AC9 2
Max Trace Length: 1000 mil AA1 CLKOUT_PCIE_N10 AC11
use same part w C5MMH Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6
CLKIN_XTAL REFCLK_CNV <52>
+3VS CNP-H_BGA874 Rev1.0
1
@
RH14
RH204 1 2 10K_0402_5% LAN_CLKREQ# 10K_0402_5%
RH205 1 2 10K_0402_5% VGA_CLKREQ# <33>
RH206 1 2 10K_0402_5% W LAN_CLKREQ#
2
RH207 1 2 10K_0402_5% SSD2_CLKREQ#
RH220 1 2 10K_0402_5% SSD3_CLKREQ#
RH300 1 2 10K_0402_5% SSD1_CLKREQ#
CNP-H
UH1M
AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <52>
For DDX03 R02 BE9 BE3 CLK_CNV_PRX_DTX_P <52>
BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 <52>
BG8 BB4
+1.8VALW _PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <52>
remove SD signal from PCH BE8 BA3
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <52>
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_BRI_PTX_DRX CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <52> 3
RH15 1 2 4.7K_0402_5% AP3 BB6 CLK_CNV_PTX_DRX_P <52>
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. STRAP GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <52>
AM7 BD7 CNV_PTX_DRX_P0
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
remove CPU_C10_GATE# GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <52>
I2C_TS_INT# CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <52>
Notes: 20190927<38> AV6 BF6
1. The internal pull-down is disabled after RSMRST# I2C_TS_INT# GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_W T_RCOMP CNV_PTX_DRX_P1 <52>
AY3 BA1 RH16 1 2 150_0402_1%
de-asserts.
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. I2C_TS_RST# GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7 B12 RH17 1 2 100_0402_1%
<38> I2C_TS_RST# GPP_J10 PCIE_RCOMPN PCIE_RCOMPP
AW3 A13
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW _PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <52> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP
AY2 BD1
<52> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH20 1
BA4 BE1 2 200_0402_1% 20191024
<52> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2 - CML Check list OK
<52> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
The signal has a weak internal pull-down 20K GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
0 = VCCPSPI is connected to 3.3V rail
STRAP RSVD3
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin BC1
13 OF 13 RSVD1 AL35
strap must be a ‘ 1’ fo r th e prope r functionalit y @ TH4
of the SPI (Flash) I/Os +1.8VALW _PRIM TP
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0
Recommend external test point
20191210C
@
+1.8VALW _PRIM - RH22 change to 20K for CNVI review RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
RH22 1 2 20K_0402_1% CNV_RGI_PTX_DRX 571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
4 a weak pull up resistor to the SoC pin with a recommended value of 20K ohm. 4
RH23 2 @ 1 10K_0402_5% STRAP
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification Compal Secret Data Compal Electronics, Inc.
PCH(2/8)CLK/CNVI/SD
A B C D E
A
CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8
no follow naming GPP_I6/DDPB_CTRLDATA
AT6 AN13
<33,39> DP0_HPD_PCH GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK
<33,40> HDMI_HPD_PCH AN10 AL10
AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40
08/18 GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
AN6 GPP_F14/PS_ON#
<38> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
DDP[B..F]CTRLDATA GPP_K21 T46
This signal has a weak internal Pull-down. 5 OF 13 GPP_K20 AJ47
0 = Port B~D is not detected. GPP_H23/TIME_SYNC0
1 = Port B,C,D is detected. (Default)
CNP-H_BGA874 Rev1.0
remove CIO_PLUG_EVENT#
Notes: intel critical net recommend
1. The internal Pull-down is disabled after @
PCH_PWROK de-asserts. RH198 1 2 100K_0201_5%
2. This signal is in the primary well.
CNP-H
UH1A PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 EC_PME#_R BE36 AV29 PLT_RST#
<58,73> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <33,58,66>
RH24 0_0402_5% XESD@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
RSVD1 GPP_K12/GSXDOUT Y48 provided by the PCH to expand the GPIOs
CRB connect GND GPP_K13/GSXSLOAD on a platform that needs more GPIOs than the
W46 ones provided by the PCH.
RH186 1 @ 2 0_0402_5% AL37 GPP_K14/GSXDIN AA45
AN35 VSS GPP_K15/GSXSRESET#
TH6 @ TP
RH258 1 NTPM@ 2 0_0402_5% PCH_SPI_SI AU41 AL47 20191016
<66> PCH_SPI_SI_R SPI0_MOSI GPP_E3/CPU_GP0
RH259 1 NTPM@ 2 0_0402_5% PCH_SPI_SO BA45 AM45 RH304 1 2 0_0402_5% BT_ON - BT_ON For Intel (GPP_B3)
<66> PCH_SPI_SO_R PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 GPP_B3 BT_ON <52,58> - TP_INT# change to GPP_B4
BF32
RH260 1 NTPM@ 2 0_0402_5% PCH_SPI_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 TP_INT# 2 1 EC_TP_INT# 20191206
<66> PCH_SPI_CLK_R SPI0_CLK GPP_B4/CPU_GP3 EC_TP_INT# <58,63> - RH304 pop
AW48 DH1
SPI0_CS1# AE44 RB751V-40_SOD323-2 +3VS
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43 TP_INT# RH28 2 1 100K_0402_5%
* wait confirm CG7 SPI0_IO3 GPP_H16/SML4CLK GPP_H15 GPP_B3
PDG P348 quad mode support PH1K AT40 AC47 RH305 2 @ 1 100K_0402_5%
<66> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
CRB PU 20k AD48
+3VALW BE19 GPP_H14/SML3DATA AF47
#571182_CFL_PCH_EDS_Rev1.0 recommend 100k GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK
#571391_CFL_H_PDG_Rev0p71 BF19 AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <19> +RTCVCC
BF18 AD47
RH25 2 1 1K_0402_5% PCH_SPI_IO2 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
RH26 2 1 1K_0402_5% PCH_SPI_IO3 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
RH27 2 1 1K_0402_5% PCH_SPI_SI_R A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
+3VALW
*20191024
RH29 2 1 100K_0402_5% GPP_H15 STRAP - CML RVP PU 330K
#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. RH258 TPM@ RH259 TPM@ RH260 TPM@
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15
4.99_0402_1% 4.99_0402_1% 4.99_0402_1%
SD034499B80 SD034499B80 SD034499B80
PCH_SPI_CLK_R RH195 1 @ 2 100K_0201_5%
intel critical net recommend
PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%

SPI ROM ( 16MByte ) +3VALW
+3VALW +3VS
CH10 0.1U_0201_10V6K CH11
UH2 PCH_SPI_CS#0
1 2 1 @ 2 0.1U_0201_10V6K
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% 1 2
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R
/WP(IO2) CLK
5
4 5 PCH_SPI_SI_0_R UH3
GND DI(IO0) PCH_SPI_SI_0_R RH107 1 2 33_0402_1% PCH_SPI_SI_R
VCC
PCH_SPI_SO_0_R RH108 1 2 33_0402_1% PCH_SPI_SO_R PLT_RST# 1
W 25Q128FVSIQ_SO8 PCH_SPI_IO3_0_R RH109 1 2 33_0402_1% PCH_SPI_IO3 IN1 4
PCH_SPI_CLK_0_R PCH_SPI_CLK_R OUT PLT_RST_BUF# <52,68,69,73>
XMC P/N: SA0000B8400 RH110 1 2 33_0402_1% 2
GND
IN2
1
PCH_SPI_IO2_0_R RH111 1 2 33_0402_1% PCH_SPI_IO2
+3VALW RH199
JC1 100K_0201_5%
3
PCH_SPI_CS#0 1 8
PCH_SPI_IO2_0_R 3 CS# VCC 6 PCH_SPI_CLK_0_R XEMI@ XEMI@ MC74VHC1G08DFT2G_SC70-5 @
2
PCH_SPI_IO3_0_R 7 WP# SCLK 5 PCH_SPI_SI_0_R PCH_SPI_CLK_0_R 1 2 1 2
4 HOLD# SI/SIO0 2 PCH_SPI_SO_0_R
GND SO/SIO1 RH33 CH12
ACES_91960-0084N_MX25L3206EM2I 0_0402_5% 68P_0402_50V8J
CONN@

PCH(3/8)DDC/SPI
A
A B C D E
‧‧
#571391_CFL_H_PDG_Rev0p5
eSPI clock and eSPI data mismatched: <500 mils.
‧eSPI clock and eSPI chip select mismatched: <500 mils.
eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
@ UH1F
F9 BB39 LPC_AD0
<71> USB3_PTX_DRX_N1 USB31_1_TXN 1.8V GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <58>
F7 AW37 LPC Bus check straps
<71> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <58>
USB3 MB <71> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <58>
<71> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <58>
C3
<73> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<73> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <58> +3VS
1 USB3 IO/B <73> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <58,66> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<73> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 RCIN#
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST# RCIN# 2 1 RH219
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# @ TH51
C16
USB31_6_TXP CLK_LPC 10K_0402_5%
G14 BB36 RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_R <58>
F14 BB34
20191016 USB3_PTX_DRX_N5 C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
<73> USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 USB31_5_TXN
B15 T48
<73> USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 USB31_5_TXP GPP_K19/SMI#
USB3 IO/B <73> USB3_PRX_DTX_N5 J13 T47
USB3_PRX_DTX_P5 K13 USB31_5_RXN GPP_K18/NMI#
<73> USB3_PRX_DTX_P5 USB31_5_RXP
20191016 G12 AH40
<43> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 SSD_DEVSLP1
F11 AH35
<43> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <68>
USB3 Type C <43> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47 +3VS
<43> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
20190924 USB3_PTX_DRX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46
<43> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 USB31_4_TXP GPP_F7/SATA_DEVSLP5 SSD_DEVSLP4
B14 AR47
<43> USB3_PTX_DRX_N4 USB3_PRX_DTX_P4 USB31_4_TXN GPP_F6/SATA_DEVSLP4 SSD_DEVSLP4 <69> TPM_SERIRQ
USB3 Type C <43> USB3_PRX_DTX_P4 J15 AP48 2 1 RH37
USB3_PRX_DTX_N4 K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3 20191025
<43> USB3_PRX_DTX_N4 USB31_4_RXN - SATA Port 4 10K_0402_5%
CNP-H_BGA874 Rev1.0
LPC_PIRQA# 1 2 RH38
10K_0402_5%
CNP-H
2 @ UH1C 2
CL_CLK AR2 G36 PCIE_PRX_DTX_N9
TH10 @ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <68>
For Intel CLINK TH11 @ AT5 F36
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <68>
TH12 @ CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <68>
M.2 SSD2 PCIE L3
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <68>
V47 GPP_K8
V48 GPP_K9 K37 PCIE_PRX_DTX_N10
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP C35 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <68>
M.2 SSD2 PCIE L2
L47 B35
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <68>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <52>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 .1U_0402_16V7K PCIE_PRX_DTX_P15 <52> NGFF
N48 B40 1 2 CH1
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2
PCIE_PTX_C_DRX_N15 <52> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <52>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<68> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<68> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD2 PCIE L1 <68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP PCIE_PRX_DTX_N17
G38 K43
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <69>
AR42 PCIE17_RXP/SATA4_RXP A42 PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <69> M.2 SSD3 PCIE L0
AR48 GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN B42 PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 <69>
20190918 Port4 change to Port3 DGPU_PRSNT# GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <69>
AU47
AU46 GPP_F13/SATA_SDATAOUT0 P41 PCIE_PRX_DTX_N18
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40 PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 <69>
3 PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <69> M.2 SSD3 PCIE L1 3
<73> PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_P18 PCIE_PTX_DRX_N18 <69>
D39 D42 20190918
<73> PCIE_PTX_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <69>
GLAN D46
<73> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<73> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
SATA_PTX_DRX_N0B B38 AH41
<67> SATA_PTX_DRX_N0B SATA_PTX_DRX_P0B C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43 SATA_GP1
<67> SATA_PTX_DRX_P0B SATA_PRX_DTX_N0B C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP2 SATA_GP1 <68>
HDD <67> SATA_PRX_DTX_N0B SATA_PRX_DTX_P0B PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 @ TH50 +3VS
20191016 C46 AN47 RH187 1 PBA@ 2 10K_0402_5%
- HDD change to Port 0B <67> SATA_PRX_DTX_P0B PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATA_GP4 20191206
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5 SATA_GP4 <69> - JSSD3 detect pin change to SATA_GP4
<68> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 @ TH13
D38 AM47
<68> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48 SATA_GP4 RH303 2 1 10K_0402_5%
M.2 SSD2 PCIE L0 <68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 SATA_GP1
H42 RH39 2 1 10K_0402_5%
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48 PCH_BKL_PW M
PCIE_PTX_DRX_P20 GPP_F21/EDP_BKLTCTL PCH_BKL_PW M <38> M.2 SSD PCIE/SATA select pin
B44 AV46 ENBKL
<69> PCIE_PTX_DRX_P20 PCIE_PTX_DRX_N20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL <58>
M.2 SSD3 PCIE L3 A44 AV44
<69> PCIE_PTX_DRX_N20 PCIE_PRX_DTX_P20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <38>
R37 #571391_CFL_H_PDG_Rev0p5.pdf
<69> PCIE_PRX_DTX_P20 PCIE_PRX_DTX_N20 R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
<69> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <10>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
<69> PCIE_PTX_DRX_P19 PCIE_PTX_DRX_N19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <10,58>
M.2 SSD3 PCIE L2 C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW <69> PCIE_PTX_DRX_N19 PCIE_PRX_DTX_P19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <10>
N42 AG5
<69> PCIE_PRX_DTX_P19 PCIE_PRX_DTX_N19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <10>
20190918 M44 AE2
<69> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <10>
1
CNP-H_BGA874 Rev1.0
RH43
10K_0402_5% UMA@ XESD@
H_PECI 0.1U_0201_10V6K 1 2 CH50
2
4 4
DGPU_PRSNT#
1
RH44
GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% VGA@ DGPU_PRSNT# 2019/09/20 2020/09/20 Title
DIS,Optimus 0 PCIE/SATA/USB3/eSPI
2
Custom 1A
UMA 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
+1.2V_VDDQ
<58> ME_EN 1 @ 2
RH45 0_0402_5%
2
RH208 1 2 33_0402_5% HDA_RST# RH46
<56> HDA_RST#_R HDA_BIT_CLK
<56> HDA_BIT_CLK_R RH209 1 2 33_0402_5% 470_0402_1%
RH210 1 2 33_0402_5% HDA_SDOUT
<56> HDA_SDOUT_R HDA_SYNC
<56> HDA_SYNC_R RH211 1 2 33_0402_5%
1
DRAM_RESET# 1 @ 2
DDR_DRAMRST#_R <23,24>
RH47 0_0402_5%
21
1 CH13 33P_0201_50V8J 1
100K_0201_5% 2 1RH196 HDA_BIT_CLK CNP-H ESD@
100K_0201_5% 2 1RH197 HDA_RST# UH1D 20200302
HDA_BIT_CLK BD11 BF36 - CH13 change 33p & pop for ESD
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
intel critical net recommend <56> HDA_SDIN0 HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC @ TH14
del RF reserve cap on HDA HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# @ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33 TYPEC_3A
GPP_B1/GSPI1_CS1#/TIME_SYNC1 TYPEC_3A <43>
BE29
RH48 1 2 30_0402_5% CPU_DISPA_SDO AM2 GPP_B0/GSPI0_CS1# R47 PCH_GPP_K17
<6> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11 @ TH19
AN3 AP29 @ TH20
<6> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <58,78>
<6> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
PCM_CLK AV18 BB47 W AKE#
<52> PCM_CLK PCM_OUT GPP_D8/I2S2_SCLK WAKE# PM_SLP_A#
FOR Jefferson Peak RESET pin is glitch free,it AW18 BE40 @ TH37
<52> PCM_OUT CLKREQ_CNV# GPP_D7/I2S2_RXD GPD6/SLP_A# SLP_LAN#
BA17 BF40
is recommended that a pull-down resistor of 75K <52> CLKREQ_CNV# CNV_RF_RESET# BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 PM_SLP_S0# @ TH21
ohm on GPP_D5(CNV_RF_RESET#) <52> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# @ TH38
<56> PCH_DMIC_DATA0 BF15 BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# BE42 PM_SLP_S4# PM_SLP_S3# <58,78>
<56> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <58,78>
+RTCVCC TH22 @ AV16 BC42 @ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
TH24 @ GPP_D17/DMIC_CLK1/SNDW3_CLK
PCH_SRTCRST# BE45 SUSCLK
RH50 1 2 20K_0402_1% GPD8/SUSCLK PM_BATLOW # SUSCLK <52,68,69>
BF44
GPD0/BATLOW# BE35 SUSACK#_R
CH18 1 2 1U_0201_6.3V6M PCH_RTCRST# GPP_A15/SUSACK# @ T207
2 BE47 BC37 SUSPW RDNACK @ TH52
2
<58> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
CLR ME BD46
SRTCRST#
Delay 18~25 ms
PCH_PW ROK AY42 BG44 LAN_W AKE#
PCH_RTCRST# <58,78> PCH_PW ROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R
RH52 1 2 20K_0402_1% <58> EC_RSMRST# BA47 BG42 RH53 1 @ 2 0_0402_5% AC_PRESENT <58>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS#
SLP_SUS# PBTN_OUT#_R @T208 --No Support Deep Sx
BE46 1 @ 2 0_0402_5% PBTN_OUT# <58>
CH19 1 2 1U_0201_6.3V6M PCH_DPW ROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# RH54
PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
ECLR CMOS <19> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPW RGD PCH_SPKR <19,56>
JCMOS1 1 @ 2 0_0603_5% Delay 18~25 ms BE26 AE3
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <10>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE T209
<19> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 @
BF25 AH4 CPU_XDP_TCK0 <10>
PCH_SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <10>
<19> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <10> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <10>
PCH_SML1DATA BE27 4 OF 13 AJ3 PCH_JTAG_TCK1
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <10>
CNP-H_BGA874 @ Rev1.0
RH55 2 1 1K_0402_5% W AKE#

PM_BATLOW #
UART BT (20191014) PM_SLP_S3#
RH56 2 1 8.2K_0402_5% RH193 1 2 100K_0201_5%
- RH301 change to 100K PM_SLP_S4# RH194 1 2 100K_0201_5%
RH57 1 @ 2 100K_0402_5% AC_PRESENT_R

+3VALW intel critical net recommend
RH58 1 @ 2 100K_0402_5% PBTN_OUT#_R UART_BT@
RH301 1 2 100K_0402_5%
3 EC_RSMRST# 1 @ 2 PCH_DPW ROK 3
UART_BT@ RH59 0_0402_5%
UART_W AKE# RH302 1 2 0_0402_5% PCH_SMBALERT#
<52> UART_W AKE#
+3VALW
+3VALW _DSW
2 1 SYS_RESET#
+3VS RH183 10K_0402_5%
LAN_W AKE# RH212 1 2 10K_0402_5%
+3VS
PCH_PW ROK RH213 1 2 10K_0402_5%
EC_RSMRST# RH214 1 2 10K_0402_5%
5
100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

G
RH60 2 1 8.2K_0402_5% PM_CLKRUN# QH7B

2N7002KDW _SOT363-6
100K_0402_5% 1 2 RH61 PCH_DPW ROK
PCH_SMBCLK D_CK_SCLK
(DDR,G-Sensor) @
3 4
S
D_CK_SCLK D_CK_SCLK <23,24>

RH191 2 1 2.2K_0402_5% XESD@
D
RH192 2 1 2.2K_0402_5% D_CK_SDATA 0.1U_0201_10V6K 1 2 CH20 SYS_RESET# +3VALW

G
QH7A
2N7002KDW _SOT363-6 XESD@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%
0.1U_0201_10V6K 1 2 CH21 SYS_PW ROK
+3VALW PCH_SMBDATA 6 1D_CK_SDATA
S
D_CK_SDATA <23,24>
XESD@
D
0.1U_0201_10V6K 1 2 CH22 PCH_PW ROK

RH251 2 1 2.2K_0402_5% PCH_SMBCLK
RH252 2 1 2.2K_0402_5% PCH_SMBDATA XESD@
RH253 2 1 2.2K_0402_5% 100P_0402_50V8J 1 2 CH51 EC_RSMRST#
PCH_SML1CLK <33,58,66>
RH254 2 1 2.2K_0402_5% (EC,VGA,Thermal Sensor)
PCH_SML1DATA <33,58,66>
4 4
From ESD Team Request
1 2 PCH_SML0CLK Near PCH side
RH63 499_0402_1%
1 2 PCH_SML0DATA
RH64 499_0402_1%
PCH(5/8)PMU/HDA/SMBUS/DMIC
A B C D E
A B C D E
+3VALW
CNP-H
RH215 1 2 2.2K_0402_5% I2C_1_SCL UH1K
RH216 1 2 2.2K_0402_5% I2C_1_SDA
RH217 1 2 2.2K_0402_5% I2C_0_SCL GSPI1_MOSI BA26 BA20 GPP_D9
RH218 1 2 2.2K_0402_5% I2C_0_SDA PEN_RST# BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 GPP_D10
<64> PEN_RST# EC_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK PROJECT_ID0
AU26 BB16
<58> EC_SCI# PEN_PDCT# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS <64> PEN_PDCT# GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<33> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN SUB_DET
BF29 BF17
<38,59> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 CPU_ID 1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD
check for remove (PCH or Both) BB24
check needed? DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<33,58,85> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS W AKE_BT AP24
<52> W AKE_BT GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 BA24
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS GPP_C10/UART0A_RTS# AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PW R_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<33> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<33> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34
<52> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
+3VALW <52> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 PEN_IRQ#
<63>
I2C_1_SCL I2C_1_SDA GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 PEN_IRQ# <64>
<Touch PAD> <63> BF21 BD34
GPP_H12 I2C_1_SDA I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 PANEL_OD_EN <38>
RH74 1 @ 2 4.7K_0402_5% BC22 BF35
GPP_H12 <16> <64> I2C_0_SCL I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
<EMR> <64> I2C_0_SDA BF23 BD38
This signal has a weak internal pull-down. GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
STRAP
0 = Master Attached Flash Sharing (MAFS) enabled (Default) I2C_SDA_TS BE15
1 = Slave Attached Flash Sharing (SAFS) enabled. 20190927
<38> I2C_SDA_TS I2C_SCL_TS GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
Notes: BE14 11 OF 13
<38> I2C_SCL_TS GPP_D23/ISH_I2C2_SCL/I2C3_SCL
Warning: This strap must be configured to ‘ 0’ i f th e CNP-H_BGA874 Rev1.0
eSPI or LPC strap is configured to ‘ 0’
@
+1.8VALW _PRIM
2 CPU_ID RH255 1 H82@ 2 1K_0402_5% 2
+3VALW RH256 1 H62@ 2 10K_0402_5%
RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <18> +1.8VALW _PRIM
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS) SUB_DET RH185 1 @ 2 1K_0402_5%
RH113 1 @ 2 4.7K_0402_5%
PCH_SML0ALERT# <18>
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected
+1.8VALW _PRIM
+1.8VALW _PRIM
RH114 1 2 150K_0402_1% GPP_D9 RH84 1 2 1K_0402_5%
PCH_SML1ALERT# <18> PROJECT_ID0 RH88 1 @ 2 1K_0402_5%
SML1ALERT# / GPP_B23 has an internal pull-down. RH85 1 @ 2 10K_0402_5%
0 = Disable IntelR DCI-OOB (Default) RH89 1 2 10K_0402_5%
*1 = Enable IntelR DCI-OOB
STRAP
GPP_D10 RH86 1 @ 2 1K_0402_5%
PROJECT_ID1 RH90 1 2 1K_0402_5%
+3VS RH87 1 2 10K_0402_5%
3 RH91 1 @ 2 10K_0402_5% 3
RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

The signal has a weak internal Pull-down.
0 = Disable “ No Reboot” mode . (Default )
1 = Enable “ No Reboot” mod e (PC H wil l disabl e th e Project_ID1 Project_ID0 20190506
TCO Timer system reboot feature). This function is Project ID - defined as Project
useful when running ITP/XDP.
Notes: GPP_D10 GPP_D9 GPP_D12 GPP_D11
1. The internal Pull-down is disabled after
PCH_PWROK is high.
2020 0 0 0 0
2021 0 1 NA 0 1
Reserved 1 0 *Gaming 50 1 0
@ GSPI1_MOSI
RH80 1 2 150K_0402_1% STRAP Reserved 1 1 Gaming 60 1 1
This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC SCI capability is available on all GPIOs
Notes:
1. The internal Pull-down is disabled after PCH_PWROK is high. ‧‧
PCH GPIOs that can be routed to generate SMI# or NMI:
GPP_B14, GPP_B20, GPP_B23
‧‧ GPP_C[23:22]
GPP_D[4:0]
RH83 2 @ 1 100K_0402_5% PCH_SPKR ‧‧ GPP_E[8:0]

GPP_I[3:0]
GPP_G[7:0] (support SMI# only).
PCH_SPKR <18,56>
Top Swap Override STRAP The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
0 = Disable “ Top Swap” mode . (Default
) except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
1 = Enable “ Top Swap” mode
.
4 The internal Pull-down is disabled after PCH_PWROK is high. All GPIOs have programmable internal pull-up/pull-down resistors which are off by default. 4
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

PCH(6/8)GPIO/I2C/UART/STRAP
A B C D E
A B C D E
GPIO Group Voltage
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
@ JPH1 AA23 VCCPRIM_1P051 VCCPRIM_3P32
1 2 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
1 2 HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 GPPD 3.3V
+VCCRTCEXT
1U_0201_6.3V6M
AB22 BG47 +VCCRTCEXT * 1.8V
JUMP_43X79 AB23 VCCPRIM_1P054 DCPRTC2
1 VCCPRIM_1P055 +3VALW
CH23
AB27 V23 0.095A GPPE
VCCPRIM_1P056 VCCPRIM_3P35
0.1U_0201_10V6K
AB28 3.3V
VCCPRIM_1P057 GPPF
CH24
AB30 AN44 0.05A 1
2 AD20 VCCPRIM_1P058 VCCSPI +RTCVCC
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49
AD28 VCCPRIM_1P0511 VCCRTC2 2
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518
GPPI 3.3V Only
6.6A AC35 0.262A
6.6A U26 VCCPGPPHK1 AC36
VCCPRIM_1P0523 VCCPGPPHK2 GPPJ
22U_0603_6.3V6M
1U_0201_6.3V6M
U29 AE35 0.174A 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
1 1 VCCPRIM_1P0525 VCCPGPPEF2 +1.8VALW_PRIM
CH26
V27
VCCPRIM_1P0526 GPD
CH25
V28 AN24 0.14A 3.3V Only
V30 VCCPRIM_1P0527 VCCPGPPD AN26 +1.8VALW_PRIM
2 2 +1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0201_6.3V6M
1 1
Place Near UH1 VCCPRIM_1_0523~29 0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
3-5MM FROM PACKAGE EDGE BE48
0.42A W22 VCCDSW_3P31 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY 2
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
1 W20 Short pins AJ22,AJ23,AK22,AK23 together

VCCA_SRC_1P052
CH29
CH30
1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

VCCDPHY_1P241
CH31
0.0198A C1 AJ23 Internal LDO

C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 RH96 1 @ 2 0_0402_5%
2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
VCCMPHY_SENSE VSSMPHY_SENSE @ TH27
0.021A B1 K46 @ TH28
B2 VCCAPLL_1P051 VSSMPHY_SENSE For DDX03 R02
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053 +1.24V_PRIM_MAR
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @
4.7U_0402_6.3V6M
1
CH32
+1.05VALW_PCH
+1.05VALW_PCH 2
+1.05VALW_PCH
0.1U_0201_10V6K
1U_0201_6.3V6M
CH34
0.1U_0201_10V6K
1 1
1U_0201_6.3V6M
CH54
1 1
CH33
+3VALW
CH35
2 2 +3VALW
2 2 +3VALW +3VALW
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE +3VALW_DSW +1.8VALW +1.8VALW_PRIM
1 1 1 1
CH36
CH39
CH37
CH38
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3
RH99 1 @ 2 0_0402_5%
2 2 2 2
0.1U_0201_10V6K
1 RH100 1 @ 2 0_0603_5%
CH40
@
20200114
3 - RH100 Change to R-short 3
2
1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE

+1.05VALW_PCH +3VALW_HDA FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_VCCAZPLL RH101 2 @ 1 0_0402_5%
RH102 1 @ 2 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
1P_0402_50V8
1P_0402_50V8
CH41
CH42
1 1
reserved for cnvi
CH43
CH44
2 2
@ @
2 2 +1.8VALW_PRIM +1.8VALW_PRIM
@ @ reserve filter follow CRB
8/21
1-3MM FROM PACKAGE EDGE
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1
CH52
CH53
+1.05VALW_VCCAMPHYPLL
2 2
@
RH103 1 @ 2 0_0402_5%
22U_0603_6.3V6M
1U_0201_6.3V6M
1 1
CH46
CH45
+RTCBATT
2 2 change to 10k DH2 +RTCVCC +RTCBATT
near AG19/AG20
LC filter close to pin CONN@
RH104 2 1 1K_0402_5% 2 JRTC1
+CHGRTC 1 1
1uF 1-3MM FROM PACKAGE EDGE 1
3 2
2
4 4
3
BAV70W_SOT323-3 GND
1U_0201_6.3V6M
0.1U_0201_10V6K
1 1 4
+1.05VALW_XTAL GND
CH48
CH47
ACES_50271-0020N-001
RH105 1 @ 2 0_0402_5%
2 2 SP02000RO00
22U_0603_6.3V6M
1
CH49
2 Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
PCH(7/8)Power
A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <10>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <10>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# PCH_TRIGOUTRH106 1 PCH_TRIGOUT_R CPU_XDP_TRST# <10>
AA27 AN38 D8 R16 AK3 2 30_0402_5%
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <13>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <13>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4

PCH(8/8)GND/RSVD
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
CHANNEL-A ( Interleaved Memory ) JDIMM1A
> BOT : Reverse type (4mm) <7>

<7>
<7>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
137
139
138
140
CK0(T)
CK0#(C)
CK1(T)
REVERSE
DQ0
DQ1
DQ2
8
7
20
21
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
> Non-ECC SO-DIMM

<7> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4
4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<7> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D6
110 16
<7> DDR_A_CKE1 CKE1 DQ6 17 DDR_A_D7
<7> DDR_A_D[0..15] DDR_A_CS#0 149 DQ7 13 DDR_A_DQS0
<7> DDR_A_CS#0 DDR_A_CS#1 157 S0# DQS0(T) 11 DDR_A_DQS#0 DDR_A_DQS0 <7>
<7> DDR_A_D[16..31] <7> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <7>
D
162 D
165 S2#/C0 28 DDR_A_D8
<7> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<7> DDR_A_D[48..63] <7> DDR_A_ODT0 DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D11
<7> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
24
JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <7> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
<7> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V_VDDQ 112 VDD1 VDD11 142 +1.2V_VDDQ <7> DDR_A_BA0 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <7> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <7>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <7>
123 VDD4 VDD14 153 <7> DDR_A_MA0 DDR_A_MA1 133 A0 50 DDR_A_D16
VDD5 VDD15 <7> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
124 154 132 49
129 159 131 62
130 160 128 63
135 163 126 46
+3VS VDD9 VDD19 <7> DDR_A_MA5 DDR_A_MA6 A5 DQ20 DDR_A_D21
136 127 45
VDD10 <7> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
<7> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D23
255 258 125 59
VDDSPD VTT +0.6VS_VTT <7> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<7> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2 DDR_A_DQS2 <7>
0.1U_0201_10V6K
164 257 146 53
2.2U_0402_6.3V6M
+0.6V_DDR_VREFCA VREFCA VPP1 259 +2.5V <7> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <7>
2 2 VPP2 <7> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
CD1
119 70
<7> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
CD2
1 99 158 71
VSS VSS <7> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <7> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <7>
<7>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<7> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <7> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <7>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <7>1 DDR_A_ALERT#
240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <7>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<18,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <18,24> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
VSS VSS <18,24> D_CK_SCLK SCL DQ36 DDR_A_D37
31 188 169
35 VSS VSS 189 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <7>
VSS VSS DQS4#(C) DDR_A_DQS#4 <7>
43 197
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS
VSS
VSS
VSS
213 For ECC DIMM 100 CB5_NC
CB6_NC
DQ45
DQ46
203 DDR_A_D46
DDR_A_D47
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 60 214 104 204

61 VSS VSS 217 97 CB7_NC DQ47 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#5 DDR_A_DQS5 <7>
CD3
CD4
CD5
CD6
CD7
CD8
CD9
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <7>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <7>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <7>
89 244
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248 XESD@
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 CD10 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
VSS VSS 33P_0201_50V8J DQ57
B 1 249 DDR_A_D58 B
262 261 DQ58 250 DDR_A_D59
GND GND DQ59 232 DDR_A_D60
20200302 DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A - CD10 change to unpop for ESD DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
246
0.1uF*1 CONN@
PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) DDR_A_DQS#7 DDR_A_DQS7 <7>
2 2 240
DQS7#(C) DDR_A_DQS#7 <7>
CD11 CD12
0.1U_0201_10V6K 2.2U_0402_6.3V6M
Part Number: SP07001CY00
1 1 Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 2 1K_0402_1%
CD13 @
1
0.1U_0201_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2
1 signals
330uF*1
2
+1.2V_VDDQ CD15
RD10 CD14 0.022U_0402_16V7K
2
1K_0402_1% 0.1U_0201_10V6K
1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 @ 2 @ 2 2 2 2 2 2 2 2 2
1
DDRIV_CHA: DIMM0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
5 4 3 2 1
5 4 3 2 1
CHANNEL-B ( Interleaved Memory )

> BOT : STD type (4mm) <8> DDR_B_CLK0
DDR_B_CLK0
DDR_B_CLK#0
137
139
JDIMM2A
CK0(T)
STD
DQ0
8
7
DDR_B_D0
DDR_B_D1
> Non-ECC SO-DIMM

<8> DDR_B_CLK#0 DDR_B_CLK1 138 CK0#(C) DQ1 20 DDR_B_D2
<8> DDR_B_D[0..15] <8> DDR_B_CLK1 DDR_B_CLK#1 CK1(T) DQ2 DDR_B_D3
140 21
<8> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D4
4
<8> DDR_B_D[16..31] DDR_B_CKE0 109 DQ4 3 DDR_B_D5
<8> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D6
<8> DDR_B_D[32..47] <8> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D7
DDR_B_CS#0 149 DQ7 13 DDR_B_DQS0
D <8> DDR_B_D[48..63] <8> DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#0 DDR_B_DQS0 <8> D
157 11
<8> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#0 <8>
JDIMM2B
STD 165 S2#/C0 28 DDR_B_D8
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ 112 VDD1 VDD11 142
+1.2V_VDDQ DDR_B_ODT0 155 DQ9 41 DDR_B_D11
117 VDD2 VDD12 147 <8> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D15
118 VDD3 VDD13 148 <8> DDR_B_ODT1 ODT1 DQ11 24 DDR_B_D14
123 VDD4 VDD14 153 DDR_B_BG0 115 DQ12 25 DDR_B_D10
124 VDD5 VDD15 154 <8> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
VDD6 VDD16 <8> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
129 159 150 37
130 VDD7 VDD17 160 <8> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
135 VDD8 VDD18 163 <8> DDR_B_BA1 BA1 DQS1(T) 32 DDR_B_DQS#1 DDR_B_DQS1 <8>
+3VS VDD9 VDD19 DDR_B_MA0 DQS1#(C) DDR_B_DQS#1 <8>
136 144
VDD10 <8> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D16
133 50
<8> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <8> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
0.1U_0201_10V6K
164 257 128 63
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D22
2 2 VPP2 <8> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
CD33
127 45
CD34
1 99 122 58
VSS VSS <8> DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D21
2 102 125 59
1 1 VSS VSS <8> DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS <8> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <8>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <8> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <8>
VSS VSS <8> DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <8> DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D30
DDR_B_D25
VSS VSS <8> DDR_B_MA13 DDR_B_MA14_WE# A13 DQ25 DDR_B_D26
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <8>
<8>
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84 DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<8> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D27
DDR_B_ACT# DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26 VSS
VSS
VSS
VSS
180
181 <8> DDR_B_ACT#
DDR_B_PAR
114
ACT# DQ30
DQ31
79
80 DDR_B_D31
DDR_B_DQS3
27 184 143 76
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <8> DDR_B_PAR
<8> DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<8>
<8>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
VSS VSS <18,23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <18,23> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
VSS VSS <18,23> D_CK_SCLK SCL DQ36 DDR_B_D38
44 201 169
47 VSS VSS 202 +3VS 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <8>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <8>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40 DDR_B_D41
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 60 214 91 194
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42 DDR_B_D43
CD35
CD36
CD37
CD38
CD39
CD40
CD41
64 218 105 208

2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D46
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_B_DQS#5 DDR_B_DQS5 <8>
77 231 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8>
78 234
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
Layout Note: VSS VSS DM6#/DBI6# DQ55 DDR_B_DQS6
98 252 241 221
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <8>
FROM THE JDIMM3 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8>
262 261
GND GND
B LOTES_ADDR0205-P001A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57
+0.6V_DDRB_VREFCA
2.2uF*1 +1.2V_VDDQ 249 DDR_B_D60
DQ58 250 DDR_B_D56
0.1uF*1 DQ59 232 DDR_B_D62
Part Number: SP07001HW00 DQ60 233 DDR_B_D59
2 2 DQ61
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD DDR_B_D63
0.1U_0201_10V6K
CD64 ESD@
0.1U_0201_10V6K
CD65 ESD@
0.1U_0201_10V6K
CD66 ESD@
0.1U_0201_10V6K
CD67 ESD@
0.1U_0201_10V6K
CD68 ESD@
0.1U_0201_10V6K
CD69 ESD@
2 2 2 2 2 2 261 245
CD42 CD43 262 GND1 DQ62 246 DDR_B_D58
GND2 DQ63 242 DDR_B_DQS7
0.1U_0201_10V6K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <8>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
1 1 1 1 1 1 DQS7#(C) DDR_B_DQS#7 <8>
LOTES_ADDR0205-P001A
CONN@
20200225 2
Layout Note: - For ESD (PCB 1A)
DIMM Side CPU Side
2
CD44 @
Place near JDIMM3 0.1U_0201_10V6K RD19
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 1
signals
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RD21 CD45
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD51 1K_0402_1% 0.1U_0201_10V6K CD55

1
CD46
CD47
CD48
CD49
CD50
CD52
CD53
CD54
0.1U_0201_10V6K 0.022U_0402_16V7K
1 2
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ @ RD22
24.9_0402_1%
1
DDRIV_CHB: DIMM0
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
1A
5 4 3 2 1
A B C D E
UV1A
1/17 PCI_EXPRESS
2*22uF+3*10uF+3*4.7uF+6*1uF
Under Near +PEX_VDD
1 <33> PLTRST_VGA#_1V8 GPU GPU 1
AP11 AL27
+1.8VSDGPU_AON 10K_0201_5% PEX_WAKE_N PEX_DVDD_1 AL28
PEX_DVDD_2
1U_0201_6.3V6M
CV1
1U_0201_6.3V6M
CV2
1U_0201_6.3V6M
CV3
1U_0201_6.3V6M
CV4
1U_0201_6.3V6M
CV5
1U_0201_6.3V6M
CV6
4.7U_0402_6.3V6M
CV7
4.7U_0402_6.3V6M
CV8
4.7U_0402_6.3V6M
CV9
10U_0402_6.3V6M
CV10
10U_0402_6.3V6M
CV11
10U_0402_6.3V6M
CV12
22U_0603_6.3V6M
CV13
22U_0603_6.3V6M
CV14
22U_0603_6.3V6M
CV310
RV1 1 VGA@ 2 AN11 AL29 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PEX_RST_N PEX_DVDD_3 AM26
AU11 PEX_DVDD_4 AM28
<33> VGA_CLKREQ#_R PEX_CLKREQ_N PEX_DVDD_5 AM29
PEX_DVDD_6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
DR@
DR@
DR@
VGA@
VGA@
VGA@
DR@
VGA@
DR@
VGA@
VGA@
AR12 AM30
<15> CLK_PEG_VGA PEX_REFCLK PEX_DVDD_7
AT12 AN29
<15> CLK_PEG_VGA# PEX_REFCLK_N PEX_DVDD_8 AN30
AN13 PEX_DVDD_9 AP30
<9> PEG_CRX_C_GTX_P0 PEX_TX0 PEX_DVDD_10
<9> PEG_CRX_C_GTX_N0
AP13 AR30
PEX_TX0_N PEX_DVDD_11 AT30
AV13 PEX_DVDD_12 AU30
<9> PEG_CTX_C_GRX_P0 PEX_RX0 PEX_DVDD_13 ME Breaket
AW13 AV30 20201119
<9> PEG_CTX_C_GRX_N0 PEX_RX0_N PEX_DVDD_14 AW30
AR14 PEX_DVDD_15 AY30
<9> PEG_CRX_C_GTX_P1 PEX_TX1 PEX_DVDD_16
<9> PEG_CRX_C_GTX_N1 AT14
PEX_TX1_N
AW14
<9> PEG_CTX_C_GRX_P1 PEX_RX1
AY14
<9> PEG_CTX_C_GRX_N1 PEX_RX1_N
<9> PEG_CRX_C_GTX_P2 AN15
AP15 PEX_TX2
<9> PEG_CRX_C_GTX_N2 PEX_TX2_N
AV15
AW15
<9> PEG_CTX_C_GRX_N2 PEX_RX2_N AL24
AR16 PEX_CVDD_1 AL25
<9> PEG_CRX_C_GTX_P3 PEX_TX3 PEX_CVDD_2
AT16 AL26
<9> PEG_CRX_C_GTX_N3 PEX_TX3_N PEX_CVDD_3 AM24
AW16 PEX_CVDD_4 +1.8VSDGPU_MAIN
To N18PG61A / N20P DGPU x 8 Lane <9> PEG_CTX_C_GRX_P3 PEX_RX3 2*22uF+3*10uF+3*4.7uF+7*1uF
AY16 Near
Under GPU
AN17 AL17 GPU
<9> PEG_CRX_C_GTX_P4 PEX_TX4 PEX_HVDD_1
<9> PEG_CRX_C_GTX_N4 AP17 AL18
2 PEX_TX4_N PEX_HVDD_2 2
1U_0201_6.3V6M
CV15
1U_0201_6.3V6M
CV16
1U_0201_6.3V6M
CV17
1U_0201_6.3V6M
CV18
1U_0201_6.3V6M
CV19
1U_0201_6.3V6M
CV20
1U_0201_6.3V6M
CV21
4.7U_0402_6.3V6M
CV22
4.7U_0402_6.3V6M
CV23
4.7U_0402_6.3V6M
CV24
10U_0402_6.3V6M
CV25
10U_0402_6.3V6M
CV26
10U_0402_6.3V6M
CV27
22U_0603_6.3V6M
CV28
22U_0603_6.3V6M
CV29
AL19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AV17 PEX_HVDD_3 AL20
<9> PEG_CTX_C_GRX_P4 PEX_RX4 PEX_HVDD_4
AW17 AL21
<9> PEG_CTX_C_GRX_N4 PEX_RX4_N PEX_HVDD_5 AL22
PEX_HVDD_6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DR@
DR@
DR@
VGA@
VGA@
VGA@
DR@
DR@
VGA@
VGA@
VGA@
VGA@
DR@
DR@
VGA@
<9> PEG_CRX_C_GTX_P5 AR18 AL23
AT18 PEX_TX5 PEX_HVDD_7 AM16
<9> PEG_CRX_C_GTX_N5 PEX_TX5_N PEX_HVDD_8 AM18
AW18 PEX_HVDD_9 AM20
<9> PEG_CTX_C_GRX_P5 PEX_RX5 PEX_HVDD_10
AY18
<9> PEG_CRX_C_GTX_P6
AN19
AP19 PEX_TX6 AM22
<9> PEG_CRX_C_GTX_N6 PEX_TX6_N PEX_PLL_HVDD
AV19
AW19
<9> PEG_CRX_C_GTX_P7
AR20
AT20 PEX_TX7
<9> PEG_CRX_C_GTX_N7 PEX_TX7_N
+1.8VSDGPU_MAIN
AW20
AY20
1
AN21 CV30
AP21 PEX_TX8 VGA@ 1U_0201_6.3V6M
PEX_TX8_N
AV21 2
AW21 PEX_RX8
PEX_RX8_N
AR22
AT22 PEX_TX9
PEX_TX9_N
AW22
AY22 PEX_RX9
PEX_RX9_N
AN23
3 AP23 PEX_TX10 3
PEX_TX10_N
AV23
AW23 PEX_RX10
PEX_RX10_N
AR24
AT24 PEX_TX11
PEX_TX11_N
AW24
AY24 PEX_RX11
PEX_RX11_N
AN25
AP25 PEX_TX12
PEX_TX12_N
AV25
AW25 PEX_RX12
PEX_RX12_N
AR26
AT26 PEX_TX13
PEX_TX13_N
AW26
AY26 PEX_RX13
PEX_RX13_N
AN27
AP27 PEX_TX14
PEX_TX14_N
AV27
AW27 PEX_RX14
PEX_RX14_N AU29 TV1 @
AR28 PEX_CVDD_SENSE
AT28 PEX_TX15
PEX_TX15_N
AW28 AW29 PEX_TREMP 1 2
AY28 PEX_RX15 PEX_TERMP
PEX_RX15_N RV4 VGA@
4 2.49K_0402_1% 4
@ QN20-P1_FCBGA1358~D

N18P(1/11)-G61A/N20P PEG
A B C D E
A B C D E
UV1B
2/17 FBA UV1C
3/17 FBB
<34> FBA_D[63..0]
FBA_D0 +FB_PLLAVDD <35> FBB_D[63..0]
N35 K28
FBA_D1 M38 FBA_D0 FB_PLLVDD_2 FBB_D0 G9
FBA_D2 P34 FBA_D1 FBB_D1 H12 FBB_D0
FBA_D3 FBA_D2 FBB_D2 FBB_D1
1U_0201_6.3V6M
CV31
N37 1 J8
FBA_D4 R32 FBA_D3 FBB_D3 E11 FBB_D2
FBA_D5 U33 FBA_D4 FBB_D4 G11 FBB_D3
FBA_D6 U35 FBA_D5 FBB_D5 F7 FBB_D4
FBA_D7 FBA_D6 2 FBB_D6 FBB_D5
VGA@
U37 H10
FBA_D8 E38 FBA_D7 FBB_D7 E6 FBB_D6
FBA_D9 J36 FBA_D8 FBB_D8 J4 FBB_D7
1 FBA_D10 L35 FBA_D9 FBB_D9 D4 FBB_D8 1
FBA_D11 J34 FBA_D10 FBB_D10 F5 FBB_D9
FBA_D12 F37 FBA_D11 FBB_D11 G2 FBB_D10
FBA_D13 N33 FBA_D12 FBB_D12 H7 FBB_D11
FBA_D14 K37 FBA_D13 FBB_D13 J2 FBB_D12
FBA_D15 FBA_D14 FBA_CMD0 FBA_CMD[24..0] <34> FBB_D14 FBB_D13 FBB_CMD[24..0] <35>
E36 Y36 J6
FBA_D16 J40 FBA_D15 FBA_CMD0 AA39 FBA_CMD1 FBB_D15 H1 FBB_D14 D14 FBB_CMD0
FBA_D17 D40 FBA_D16 FBA_CMD1 AA32 FBA_CMD2 FBB_D16 A5 FBB_D15 FBB_CMD0 A17 FBB_CMD1
FBA_D18 E37 FBA_D17 FBA_CMD2 AC34 FBA_CMD3 FBB_D17 E1 FBB_D16 FBB_CMD1 J15 FBB_CMD2
FBA_D19 J38 FBA_D18 FBA_CMD3 AA33 FBA_CMD4 FBB_D18 D2 FBB_D17 FBB_CMD2 E17 FBB_CMD3
FBA_D20 C39 FBA_D19 FBA_CMD4 Y37 FBA_CMD5 FBB_D19 F2 FBB_D18 FBB_CMD3 H15 FBB_CMD4
FBA_D21 C40 FBA_D20 FBA_CMD5 Y35 FBA_CMD6 CKE A +FBVDDQ FBB_D20 C5 FBB_D19 FBB_CMD4 D17 FBB_CMD5
FBA_D22 H40 FBA_D21 FBA_CMD6 AA35 FBA_CMD7 FBB_D21 F1 FBB_D20 FBB_CMD5 E14 FBB_CMD6 +FBVDDQ
FBA_D23 G39 FBA_D22 FBA_CMD7 Y39 FBA_CMD8 FBB_D22 B4 FBB_D21 FBB_CMD6 G15 FBB_CMD7 CKE A
FBA_D24 U38 FBA_D23 FBA_CMD8 V40 FBA_CMD9 FBA_CMD14 1 VGA@ 2 FBB_D23 A3 FBB_D22 FBB_CMD7 A15 FBB_CMD8
FBA_D25 K39 FBA_D24 FBA_CMD9 Y40 FBA_CMD10 RV5 10K_0402_1% FBB_D24 A6 FBB_D23 FBB_CMD8 B14 FBB_CMD9 FBB_CMD14 1 VGA@ 2
FBA_D26 R38 FBA_D25 FBA_CMD10 Y38 FBA_CMD11 FBA_CMD44 1 VGA@ 2 FBB_D25 A12 FBB_D24 FBB_CMD9 B15 FBB_CMD10 RV6 10K_0402_1%
FBA_D27 T39 FBA_D26 FBA_CMD11 W37 FBA_CMD12 RV7 10K_0402_1% FBB_D26 C8 FBB_D25 FBB_CMD10 A14 FBB_CMD11 FBB_CMD44 1 VGA@ 2
FBA_D28 L38 FBA_D27 FBA_CMD12 AA40 FBA_CMD13 FBB_D27 A11 FBB_D26 FBB_CMD11 F17 FBB_CMD12 RV8 10K_0402_1%
FBA_D29 L40 FBA_D28 FBA_CMD13 AA38 FBA_CMD14 FBB_D28 B7 FBB_D27 FBB_CMD12 B17 FBB_CMD13
FBA_D30 M40 FBA_D29 FBA_CMD14 V38 FBA_CMD15 FBB_D29 B12 FBB_D28 FBB_CMD13 D15 FBB_CMD14
FBA_D31 U40 FBA_D30 FBA_CMD15 V39 FBA_CMD16 FBB_D30 D12 FBB_D29 FBB_CMD14 C15 FBB_CMD15
FBA_D32 AN32 FBA_D31 FBA_CMD16 AA37 FBA_CMD17 +FBVDDQ FBB_D31 A8 FBB_D30 FBB_CMD15 C14 FBB_CMD16
FBA_D33 AP35 FBA_D32 FBA_CMD17 AC38 FBA_CMD18 CKE B FBB_D32 D28 FBB_D31 FBB_CMD16 E15 FBB_CMD17
FBA_D34 AR36 FBA_D33 FBA_CMD18 AC33 FBA_CMD19 FBB_D33 F28 FBB_D32 FBB_CMD17 C17 FBB_CMD18 +FBVDDQ
FBA_D35
FBA_D36
AM34 FBA_D34 FBA_CMD19 AC36 FBA_CMD20
FBA_CMD21
FBA_CMD17 1 VGA@ 2 FBB_D34
FBB_D35
D24 FBB_D33 FBB_CMD18 J17 FBB_CMD19
FBB_CMD20
CKE B
AJ33 FBA_D35 FBA_CMD20 Y33 RV9 10K_0402_1% J26 FBB_D34 FBB_CMD19 D18
FBA_D37 AL33 FBA_D36 FBA_CMD21 Y32 FBA_CMD22 FBA_CMD41 1 VGA@ 2 FBB_D36 G27 FBB_D35 FBB_CMD20 J14 FBB_CMD21 FBB_CMD17 1 VGA@ 2
FBA_D38 AK34 FBA_D37 FBA_CMD22 AC32 FBA_CMD23 RV10 10K_0402_1% FBB_D37 H24 FBB_D36 FBB_CMD21 H14 FBB_CMD22 RV11 10K_0402_1%
FBA_D39 AK36 FBA_D38 FBA_CMD23 AC39 FBA_CMD24 FBB_D38 F24 FBB_D37 FBB_CMD22 H17 FBB_CMD23 FBB_CMD41 1 VGA@ 2
FBA_D40 AW34 FBA_D39 FBA_CMD24 V34 FBB_D39 C29 FBB_D38 FBB_CMD23 A18 FBB_CMD24 RV12 10K_0402_1%
FBA_D41 AP33 FBA_D40 FBA_CMD25_NC V36 FBB_D40 D35 FBB_D39 FBB_CMD24 F13
FBA_D42 AT35 FBA_D41 FBA_CMD26_NC V32 FBA_DEBUG0 FBB_D41 E32 FBB_D40 FBB_CMD25_NC G14
FBA_D43 FBA_D42 FBA_CMD27 FBA_CMD28 FBA_CMD[52..28] <34> FBB_D42 FBB_D41 FBB_CMD26_NC FBB_DEBUG0
AU37 AD35 F30 H13
FBA_D44 AY33 FBA_D43 FBA_CMD28 AG38 FBA_CMD29 RESET FBB_D43 G32 FBB_D42 FBB_CMD27 E18 FBB_CMD28 FBB_CMD[52..28] <35>
FBA_D45 AR32 FBA_D44 FBA_CMD29 AD32 FBA_CMD30 FBB_D44 H28 FBB_D43 FBB_CMD28 A23 FBB_CMD29
FBA_D46
FBA_D47
AU32 FBA_D45
FBA_D46
FBA_CMD30
FBA_CMD31
AG37 FBA_CMD31
FBA_CMD32 FBA_CMD3
FBB_D45
FBB_D46
C36 FBB_D44
FBB_D45
FBB_CMD29
FBB_CMD30
J18 FBB_CMD30
FBB_CMD31
RESET
AW32 AD33 1 VGA@ 2 D37 F20 change for N20P
FBA_D48 AY36 FBA_D47 FBA_CMD32 AD37 FBA_CMD33 RV13 10K_0402_1% FBB_D47 D31 FBB_D46 FBB_CMD31 H18 FBB_CMD32 FBB_CMD3 1 VGA@ 2
FBA_D49 FBA_D48 FBA_CMD33 FBA_CMD34 change for N20P FBA_CMD31 FBB_D48 FBB_D47 FBB_CMD32 FBB_CMD33
AW35 AD36 1 VGA@ 2 A33 B20 RV14 10K_0402_1%
FBA_D50 AW37 FBA_D49 FBA_CMD34 AC37 FBA_CMD35 RV15 10K_0402_1% FBB_D49 B39 FBB_D48 FBB_CMD33 G18 FBB_CMD34 FBB_CMD31 1 VGA@ 2
FBA_D51 AU39 FBA_D50 FBA_CMD35 AD40 FBA_CMD36 FBB_D50 B37 FBB_D49 FBB_CMD34 D22 FBB_CMD35 RV16 10K_0402_1%
2 FBA_D52 FBA_D51 FBA_CMD36 FBA_CMD37 FBB_D51 FBB_D50 FBB_CMD35 FBB_CMD36 2
AY35 AG33 B34 A20
FBA_D53 AT38 FBA_D52 FBA_CMD37 AF33 FBA_CMD38 FBB_D52 A38 FBB_D51 FBB_CMD36 E21 FBB_CMD37
FBA_D54 AT40 FBA_D53 FBA_CMD38 AC40 FBA_CMD39 FBB_D53 A32 FBB_D52 FBB_CMD37 F21 FBB_CMD38
FBA_D55 AV40 FBA_D54 FBA_CMD39 AF34 FBA_CMD40 FBB_D54 B38 FBB_D53 FBB_CMD38 A21 FBB_CMD39
FBA_D56 AR40 FBA_D55 FBA_CMD40 AG39 FBA_CMD41 FBB_D55 C32 FBB_D54 FBB_CMD39 D21 FBB_CMD40
FBA_D57 AJ39 FBA_D56 FBA_CMD41 AF38 FBA_CMD42 FBB_D56 B25 FBB_D55 FBB_CMD40 B23 FBB_CMD41
FBA_D58 AP39 FBA_D57 FBA_CMD42 AF37 FBA_CMD43 FBB_D57 C26 FBB_D56 FBB_CMD41 C21 FBB_CMD42
FBA_D59 AK40 FBA_D58 FBA_CMD43 AG40 FBA_CMD44 +FBVDDQ FBB_D58 A30 FBB_D57 FBB_CMD42 C20 FBB_CMD43
FBA_D60 AJ37 FBA_D59 FBA_CMD44 AD38 FBA_CMD45 FBB_D59 C24 FBB_D58 FBB_CMD43 C23 FBB_CMD44
FBA_D61 AJ40 FBA_D60 FBA_CMD45 AF39 FBA_CMD46 FBA_DEBUG0 2 @ 1 60.4_0201_1% FBB_D60 A24 FBB_D59 FBB_CMD44 C18 FBB_CMD45 +FBVDDQ
FBA_D62 AN38 FBA_D61 FBA_CMD46 AF36 FBA_CMD47 RV186 FBB_D61 C30 FBB_D60 FBB_CMD45 B18 FBB_CMD46
FBA_D63 AN40 FBA_D62 FBA_CMD47 AF32 FBA_CMD48 FBB_D62 A29 FBB_D61 FBB_CMD46 H20 FBB_CMD47 FBB_DEBUG0 2 @ 1 60.4_0201_1%
FBA_D63 FBA_CMD48 AG32 FBA_CMD49 FBA_DEBUG1 2 @ 1 60.4_0201_1% FBB_D63 B31 FBB_D62 FBB_CMD47 J20 FBB_CMD48 RV188
FBA_CMD49 AF40 FBA_CMD50 RV187 FBB_D63 FBB_CMD48 J21 FBB_CMD49
<34> FBA_DBI[7..0] FBA_DBI0 FBA_CMD50 FBA_CMD51 FBB_CMD49 FBB_CMD50 FBB_DEBUG1
R35 AG36 B21 2 @ 1 60.4_0201_1%
FBA_DBI1 FBA_DQM0 FBA_CMD51 FBA_CMD52 <35> FBB_DBI[7..0] FBB_DBI0 FBB_CMD50 FBB_CMD51
L33 AD39 F10 H21 RV189
FBA_DBI2 F38 FBA_DQM1 FBA_CMD52 AH35 FBB_DBI1 G4 FBB_DQM0 FBB_CMD51 D20 FBB_CMD52
FBA_DBI3 P40 FBA_DQM2 FBA_CMD53_NC AG34 FBB_DBI2 C3 FBB_DQM1 FBB_CMD52 G23
FBA_DBI4 AL35 FBA_DQM3 FBA_CMD54_NC AH33 FBA_DEBUG1 FBB_DBI3 B10 FBB_DQM2 FBB_CMD53_NC E23
FBA_DBI5 AU34 FBA_DQM4 FBA_CMD55 FBB_DBI4 F26 FBB_DQM3 FBB_CMD54_NC J23 FBB_DEBUG1
FBA_DBI6 AV38 FBA_DQM5 FBB_DBI5 H30 FBB_DQM4 FBB_CMD55
FBA_DBI7 AL39 FBA_DQM6 FBB_DBI6 C35 FBB_DQM5
FBA_DQM7 FBB_DBI7 A27 FBB_DQM6
FBB_DQM7
<34> FBA_EDC[7..0] FBA_EDC0 R37
FBA_EDC1 FBA_DQS_WP0 <35> FBB_EDC[7..0] FBB_EDC0
H35 D10
FBA_EDC2 F40 FBA_DQS_WP1 L37 FBB_EDC1 H3 FBB_DQS_WP0
FBA_EDC3 FBA_DQS_WP2 FBA_CLK0 FBA_CLKA0 <34> FBB_EDC2 FBB_DQS_WP1
R40 M37 C1 D6
FBA_EDC4 AL37 FBA_DQS_WP3 FBA_CLK0_N FBA_CLKA0# <34> FBB_EDC3 FBB_DQS_WP2 FBB_CLK0 FBB_CLKA0 <35>
AR38 C11 C6
FBA_EDC5 AV33 FBA_DQS_WP4 FBA_CLK1 FBA_CLKA1 <34> FBB_EDC4 FBB_DQS_WP3 FBB_CLK0_N FBB_CLKA0# <35>
AR37 D26 D29
FBA_EDC6 AY38 FBA_DQS_WP5 FBA_CLK1_N FBA_CLKA1# <34> FBB_EDC5 FBB_DQS_WP4 FBB_CLK1 FBB_CLKA1 <35>
F33 D30
FBA_EDC7 AK38 FBA_DQS_WP6 FBB_EDC6 FBB_DQS_WP5 FBB_CLK1_N FBB_CLKA1# <35>
A35
FBA_DQS_WP7 FBB_EDC7 A26 FBB_DQS_WP6
FBB_DQS_WP7
P38
FBA_WCK01 FBA_WCK01 <34>
P39 E8
FBA_WCK01_N FBA_WCK01# <34> FBB_WCK01 FBB_WCK01 <35>
E39 D8
FBA_WCK23 FBA_WCK23 <34> FBB_WCK01_N FBB_WCK01# <35>
E40 B2
AN36 B3
AN37 C27
AW39 B27
3 AV39 B36 3
A36
FBB_WCK67_N FBB_WCK67# <35>
H37
FBA_WCKB01 FBA_WCKB01 <34>
H38 F3
FBA_WCKB01_N FBA_WCKB01# <34> FBB_WCKB01 FBB_WCKB01 <35>
N40 E3
FBA_WCKB23 FBA_WCKB23 <34> FBB_WCKB01_N FBB_WCKB01# <35>
N39 A9
AV35 B9
AV36 D33
FBA_WCKB45_N FBA_WCKB45# <34> +1.8VSDGPU_MAIN FBB_WCKB45 FBB_WCKB45 <35>
AM40 C33
AM39 A28
VGA@ B28
FB_VREF +FB_PLLAVDD FBB_WCKB67_N FBB_WCKB67# <35>
F35 R31 LV1 1 2
FB_VREF FB_PLLVDD_3 TAI-TECH HCB1608KF-330T30 K13 +FB_PLLAVDD
FB_PLLVDD_1
SM01000JX00
1
3.9P_0402_50V8C
CV32
49.9_0402_1%
RV17
1U_0201_6.3V6M
CV33
1U_0201_6.3V6M
CV34
4.7U_0402_6.3V6M
CV35
4.7U_0402_6.3V6M
CV36
22U_0603_6.3V6M
CV37
1 QN20-P1_FCBGA1358~D 1 1 1 1 1
@ QN20-P1_FCBGA1358~D
@
1U_0201_6.3V6M
CV38
4.7U_0402_6.3V6M
1 1
2 2 2 2 2 2
VGA@
N18PA@
VGA@
VGA@
VGA@
VGA@
VGA@
CV39 DR@
2
2 2
VGA@
RV17
N20P@
+FBVDDQ
S RES 1/16W 2.49K +-1% 0402 +FBVDDQ
Add for N20P/N18PA Add for N20P/N18PA
for B CMD path
SD034249180 for A CMD path
1U_0201_6.3V6M
CV44
1U_0201_6.3V6M
CV45
1U_0201_6.3V6M
CV46
1U_0201_6.3V6M
CV47
1 1 1 1
1U_0201_6.3V6M
CV40
1U_0201_6.3V6M
CV41
1U_0201_6.3V6M
CV42
1U_0201_6.3V6M
CV43
1 1 1 1
2 2 2 2
VGA@
VGA@
VGA@
VGA@
2 2 2 2
VGA@
VGA@
VGA@
VGA@
4 4

N18P(2/11)-G61A/N20P VRAM
A B C D E
A B C D E
N18PA
UV1P
12/17 MISC2
+1.8VSDGPU_AON
MULTI LEVEL STRAPS
Y8 ROM_CS#
ROM_CS_N strap0 strap1 strap2 strap3 strap4 strap5
Y7 ROM_SI
ROM_SI
2
Y9 ROM_SO
1 ROM_SO ROM_SCLK 1
STRAP0 V5 Y10 RV18 RV19 RV20 RV21 RV22 RV23 RV24 RV25 RV26
STRAP1 V8 STRAP0 ROM_SCLK 100K_0402_5% 100K_0402_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0201_5%
STRAP2 Y5 STRAP1 @ @ @ VGA@ @ @ @ @ N20P@
STRAP3 V7 STRAP2
1
STRAP4 U8 STRAP3
STRAP5 V6 STRAP4
STRAP5 STRAP0
STRAP1 ROM_SI
STRAP2 ROM_SO
STRAP3 ROM_SCLK
STRAP4
STRAP5
2
2
2
RV27 RV28 RV29 RV30 RV31 RV32 RV33 RV34 RV35
100K_0402_5% 100K_0402_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0402_5% 100K_0402_5% 10K_0402_5% 100K_0201_5%
@ @ @ @ VGA@ VGA@ VGA@ VGA@ N18PA@
1
1
1
QN20-P1_FCBGA1358~D X76 BOM
@
+1.8VSDGPU_AON +1.8VSDGPU_AON
2 2
VGA@ VGA@
10K_0402_1%
1
1
RV37 2
CV48 VGA@
10K_0402_5%
0.1U_0201_10V6K
RV36
VGA@
RV39 2
33_0402_5% UV2 VGA@
N20P
2
ROM_CS# 1 2 ROM_CS_R# 1 8 RV41

ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 33_0402_5%
3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
VGA@ 4 WP#(IO2) CLK 5 ROM_SI_R 1 2 ROM_SI
RV306 GND DI(IO0)
10K_0402_1%
RV42 2
0_0402_5% W25Q80EWSSIG_SO8 VGA@

@ N18PA@ RV40
SA00009QP00 33_0402_5%
<33> ROM_WP#_R
1
DGPU VBIOS ROM 8Mb

UV2
N20P@
S IC FL 16M W25Q16JWSSIQ SOIC 8P SPI ROM

SA0000DHJ00
3 3
27MHZ_10PF_XRCGB27M000F2P18R0
RV43 VGA@ YV1
470_0402_1%
Check PN XTALOUT 2 1 XTALOUT_R 1 3 XTALIN
1 3
+1.8VSDGPU_MAIN +GPU_PLLVDD NC NC
1 1
CV55 VGA@ VGA@ 2 4 CV56 VGA@
18P_0402_50V8J 18P_0402_50V8J
2 2
VGA@ UV1Q
LV2 1 2 11/17 XTAL_PLL Crystals must have a max ESR of 80 ohm
TAI-TECH HCB1608KF-330T30
SM01000JX00 AJ9
CORE_PLL_AVDD
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
CV53
22U_0603_6.3V6M
1 1 1 1 1 1 AM9
GPCADC_AVDD
CV49 VGA@
CV50 VGA@
CV52 VGA@
CV51 VGA@
CV54
SM01000JX00 AK9
SP_PLLVDD
3000ma 33ohm@100mhz DCR 0.04
AJ10
2 2 2 2 2 2 VID_PLLVDD
VGA@
VGA@
XTAL_SSIN L4 L3 XTAL_OUTBUFF
EXT_REFCLK_FL XTAL_OUTBUFF
XTALIN L2 L1 XTALOUT
XTAL_IN XTAL_OUT
1
QN20-P1_FCBGA1358~D
VGA@ RV45 @ N18PA@ RV46
10K_0402_1% 100K_0402_1%
2
4 4

N18P(3/11)-G61A/N20P STRAP
A B C D E
A B C D E
+FBVDDQ CHA
/6*1uF+2*10uF
+FBVDDQ UV1H +FBVDDQ
14/17 FBVDDQ Under
GPU
AA31 F19
FBVDDQ_01 FBVDDQ_36
1U_0201_6.3V6M
CV60
1U_0201_6.3V6M
CV61
1U_0201_6.3V6M
CV62
1U_0201_6.3V6M
CV63
1U_0201_6.3V6M
CV64
1U_0201_6.3V6M
CV65
10U_0402_6.3V6M
CV66
10U_0402_6.3V6M
CV67
AA36 F22 1 1 1 1 1 1 1 1
AB33 FBVDDQ_02 FBVDDQ_37 F23
1 FBVDDQ_03 FBVDDQ_38 1
AB34 G16
AB35 FBVDDQ_04 FBVDDQ_39 G19
FBVDDQ_05 FBVDDQ_40 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
AB36 G21
AB39 FBVDDQ_06 FBVDDQ_41 H16
AC31 FBVDDQ_07 FBVDDQ_42 H19
AC35 FBVDDQ_08 FBVDDQ_43 H22
AD31 FBVDDQ_09 FBVDDQ_44 H23
AE33 FBVDDQ_10 FBVDDQ_45 K15
FBVDDQ_12 FBVDDQ_47 CHB
AE35 K18 /6*1uF+2*10uF
FBVDDQ_15 FBVDDQ_50
1U_0201_6.3V6M
CV70
1U_0201_6.3V6M
CV71
1U_0201_6.3V6M
CV72
1U_0201_6.3V6M
CV73
1U_0201_6.3V6M
CV74
1U_0201_6.3V6M
CV75
10U_0402_6.3V6M
CV76
10U_0402_6.3V6M
CV77
AF31 K23 1 1 1 1 1 1 1 1
AG31 FBVDDQ_16 FBVDDQ_51 K24
AG35 FBVDDQ_17 FBVDDQ_52 K25
AH31 FBVDDQ_18 FBVDDQ_53 K26
FBVDDQ_19 FBVDDQ_54 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
AH37 K30
FBVDDQ_20 FBVDDQ_55
DR@
VGA@
AH39 L31
AJ31 FBVDDQ_21 FBVDDQ_56 M31
B13 FBVDDQ_22 FBVDDQ_57 N31
B16 FBVDDQ_23 FBVDDQ_58 U31
B19 FBVDDQ_24 FBVDDQ_59 V31
B22 FBVDDQ_25 FBVDDQ_60 V33
D13 FBVDDQ_26 FBVDDQ_61 V35
D23 FBVDDQ_27 FBVDDQ_62 V37
E16 FBVDDQ_28 FBVDDQ_63 W33
FBVDDQ_29 FBVDDQ_64 GPU
E19 W35 /5*22uF+2*10uF
FBVDDQ_32 FBVDDQ_67 Near GPU
F14 Y31
FBVDDQ_33 FBVDDQ_68
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
F16 Y34 1 1 1 1 1 1 1
FBVDDQ_34 FBVDDQ_69
CV78
CV79
CV80
CV81
CV82
CV83
CV84
F18
FBVDDQ_35
2 2 2 2 2 2 2
2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1 RV180 2
+FBVDDQ FBVDDQ_GND_SENSE <108>
0_0402_5%
2
RV47
@ 0_0402_5%
1
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
FB_VDDQ_SENSE 1 1 1
CV85 VGA@
CV86 DR@
CV87 DR@
K11
FBVDDQ_SENSE FB_VDDQ_SENSE <108> +FBVDDQ
2 2 2
H32 FB_CAL_PD_VDDQ 40.2_0402_1% 1 VGA@ 2 RV48
FB_CAL_PD_VDDQ
J32 FB_CAL_PU_GND 40.2_0402_1% 1 VGA@ 2 RV49
FB_CAL_PU_GND
J33 FB_CAL_TERM_GND 40.2_0402_1% 1 VGA@ 2 RV50
FB_CAL_TERM_GND
QN20-P1_FCBGA1358~D
@
3 1uFx3 / 4.7ux3 1uFx2 +1.8VSDGPU_AON 3
Near GPU under GPU

4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CV92
CV93
CV94
CV95
CV96
CV97
CV98
CV99
1 1 1 1 1 1 1 1
UV1I VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

17/17 1V8 / NC
2 2 2 2 2 2 2 2
AR8 P10
AR9 NC_1 1V8_1 R10
AT8 NC_2 1V8_2
AT9 NC_3
AV3 NC_4
AW2 NC_5
Y6 NC_6 +FP_FUSE_GPU
NC_7
Y2
FUSE_SRC
QN20-P1_FCBGA1358~D
@
4 4

N18P(4/11)-G61A/N20P POWER
A B C D E
A B C D E
UV1D UV1E +NVVDD1 UV1F +NVVDD1 +NVVDD1 UV1G +NVVDD1 +NVVDD1 UV1J +NVVDD1
15/17 GND_1/2 16/17 GND_2/2 9/17 Configurable 13/17 VDD_1/2 4/17 VDD_2/2
Power Channels
A10 AN10 Y1 M34 AA12 AG22 T13 V21
A2 GND_001 GND_121 AN31 D25 GND GND_344 M35 AA1 AD6 AA13 VDD_01 VDD_71 AG23 T14 VDD_140 VDD_168 V22
A25 GND_002 GND_122 AN33 D27 GND_240 GND_345 M36 AA2 XVDD_1 XVDD_31 AD7 AA14 VDD_02 VDD_72 AG24 T15 VDD_141 VDD_169 V23
A31 GND_003 GND_123 AN34 D32 GND_241 GND_346 M39 AA3 XVDD_2 XVDD_32 AD8 AA15 VDD_03 VDD_73 AG25 T16 VDD_142 VDD_170 V24
A34 GND_004 GND_124 AN35 D34 GND_242 GND_347 N10 AA4 XVDD_3 XVDD_33 AD9 AA16 VDD_04 VDD_74 AG26 T17 VDD_143 VDD_171 V25
1 A37 GND_005 GND_125 AN39 D36 GND_243 GND_348 N13 AA5 XVDD_4 XVDD_34 AD10 AA17 VDD_05 VDD_75 AG27 T18 VDD_144 VDD_172 V26 1
A39 GND_006 GND_126 AN4 D39 GND_244 GND_349 N14 AA6 XVDD_5 XVDD_35 AE2 AA18 VDD_06 VDD_76 AG28 T19 VDD_145 VDD_173 V27
A4 GND_007 GND_127 AP12 D5 GND_245 GND_350 N15 AA7 XVDD_6 XVDD_36 AE4 AA19 VDD_07 VDD_77 AG29 T20 VDD_146 VDD_174 V28
A7 GND_008 GND_128 AP14 D7 GND_246 GND_351 N16 AA8 XVDD_7 XVDD_37 AE6 AA20 VDD_08 VDD_78 AH12 T21 VDD_147 VDD_175 V29
AB13 GND_009 GND_129 AP16 D9 GND_247 GND_352 N17 AA9 XVDD_8 XVDD_38 AE8 AA21 VDD_09 VDD_79 AH29 T22 VDD_148 VDD_176 W12
AB14 GND_010 GND_130 AP18 E12 GND_248 GND_353 N18 AA10 XVDD_9 XVDD_39 AE10 AA22 VDD_10 VDD_80 AJ12 T23 VDD_149 VDD_177 W17
AB15 GND_011 GND_131 AP2 E13 GND_249 GND_354 N19 AB2 XVDD_10 XVDD_40 AF1 AA23 VDD_11 VDD_81 AJ13 T24 VDD_150 VDD_178 W18
AB20 GND_016 GND_136 AP28 E29 GND_254 GND_359 N23 AC1 XVDD_15 XVDD_45 AF6 AA28 VDD_16 VDD_86 AJ18 T29 VDD_155 VDD_183 W27
AB21 GND_017 GND_137 AP32 E30 GND_255 GND_360 N24 AC2 XVDD_16 XVDD_46 AF7 AA29 VDD_17 VDD_87 AJ19 U12 VDD_156 VDD_184 W28
AB22 GND_018 GND_138 AP37 E33 GND_256 GND_361 N25 AC3 XVDD_17 XVDD_47 AF8 AB12 VDD_18 VDD_88 AJ20 U29 VDD_157 VDD_185 W29
AB23 GND_019 GND_139 AP4 E35 GND_257 GND_362 N26 AC4 XVDD_18 XVDD_48 AF9 AB29 VDD_19 VDD_89 AJ21 V12 VDD_158 VDD_186 Y12
AB24 GND_020 GND_140 AP40 E4 GND_258 GND_363 N27 AC5 XVDD_19 XVDD_49 AF10 AC12 VDD_20 VDD_90 AJ22 V13 VDD_159 VDD_187 Y13
AB25 GND_021 GND_141 AP6 E5 GND_259 GND_364 N28 AC6 XVDD_20 XVDD_50 AG1 AC13 VDD_21 VDD_91 AJ23 V14 VDD_160 VDD_188 Y14
AB26 GND_022 GND_142 AR10 E9 GND_260 GND_365 N4 AC7 XVDD_21 XVDD_51 AG2 AC14 VDD_22 VDD_92 AJ24 V15 VDD_161 VDD_189 Y15
AB27 GND_023 GND_143 AR11 F11 GND_261 GND_366 N6 AC8 XVDD_22 XVDD_52 AG3 AC15 VDD_23 VDD_93 AJ25 V16 VDD_162 VDD_190 Y16
AB28 GND_024 GND_144 AR13 F12 GND_262 GND_367 N8 AC9 XVDD_23 XVDD_53 AG4 AC16 VDD_24 VDD_94 AJ26 V17 VDD_163 VDD_191 Y21
AB31 GND_025 GND_145 AR15 F25 GND_263 GND_368 P31 AC10 XVDD_24 XVDD_54 AG5 AC17 VDD_25 VDD_95 AJ27 V18 VDD_164 VDD_192 Y22
AB32 GND_026 GND_146 AR17 F27 GND_264 GND_369 P32 AD1 XVDD_25 XVDD_55 AG6 AC18 VDD_26 VDD_96 AJ28 V19 VDD_165 VDD_193 Y23
AD13 GND_027 GND_147 AR19 F29 GND_265 GND_370 P33 AD2 XVDD_26 XVDD_56 AG7 AC19 VDD_27 VDD_97 AJ29 V20 VDD_166 VDD_194 Y24
AD14 GND_028 GND_148 AR21 F31 GND_266 GND_371 P35 AD3 XVDD_27 XVDD_57 AG8 AC20 VDD_28 VDD_98 M12 VDD_167 VDD_195 Y29
AD15 GND_029 GND_149 AR23 F32 GND_267 GND_372 P36 AD4 XVDD_28 XVDD_58 AG9 AC21 VDD_29 VDD_99 M13 VDD_196
AD16 GND_030 GND_150 AR25 F34 GND_268 GND_373 P37 AD5 XVDD_29 XVDD_59 AG10 AC22 VDD_30 VDD_100 M14
AD17 GND_031 GND_151 AR27 F36 GND_269 GND_374 R13 XVDD_30 XVDD_60 AC23 VDD_31 VDD_101 M15
AD18 GND_032 GND_152 AR29 F39 GND_270 GND_375 R14 AC24 VDD_32 VDD_102 M16
AD23 GND_037 GND_157 AR39 G1 GND_275 GND_380 R19 AC29 VDD_37 VDD_107 M21
AD24 GND_038 GND_158 AR4 G12 GND_276 GND_381 R20 AD12 VDD_38 VDD_108 M22
AD25 GND_039 GND_159 AR7 G13 GND_277 GND_382 R21 AD29 VDD_39 VDD_109 M23
AD26 GND_040 GND_160 AT11 G22 GND_278 GND_383 R22 AE12 VDD_40 VDD_110 M24
AE31 GND_043 GND_163 AT36 G29 GND_281 GND_386 R25 AE15 VDD_43 VDD_113 M27
AE32 GND_044 GND_164 AT37 G30 GND_282 GND_387 R26 AE16 VDD_44 VDD_114 M28
AF13 GND_045 GND_165 AT39 G33 GND_283 GND_388 R27 AE17 VDD_45 VDD_115 M29
AF14 GND_046 GND_166 AT4 G35 GND_284 GND_389 R28 AE18 VDD_46 VDD_116 N12
2 GND_047 GND_167 GND_285 GND_390 VDD_47 VDD_117 2
AF15 AU10 G37 R33 AE19 N29
AF16 GND_048 GND_168 AU12 G40 GND_286 GND_391 R34 AE20 VDD_48 VDD_118 P12
AF19 GND_051 GND_171 AU15 H11 GND_289 GND_394 T10 AE23 VDD_51 VDD_121 P15 M9
AF20 GND_052 GND_172 AU16 H2 GND_290 GND_395 T2 AE24 VDD_52 VDD_122 P16 RFU_VMS_SENSE M10
AF21 GND_053 GND_173 AU17 H25 GND_291 GND_396 T31 AE25 VDD_53 VDD_123 P17 RFU_GMS_SENSE
AF22 GND_054 GND_174 AU18 H26 GND_292 GND_397 T33 AE26 VDD_54 VDD_124 P18 QN20-P1_FCBGA1358~D
AF23 GND_055 GND_175 AU19 H27 GND_293 GND_398 T35 AE27 VDD_55 VDD_125 P19
GND_056 GND_176 GND_294 GND_399 VDD_56 VDD_126 @
AF24 AU2 H29 T37 AE28 P20
AF25 GND_057 GND_177 AU20 H31 GND_295 GND_400 T4 AE29 VDD_57 VDD_127 P21
AF26 GND_058 GND_178 AU21 H33 GND_296 GND_401 T40 AF12 VDD_58 VDD_128 P22
AF27 GND_059 GND_179 AU22 H34 GND_297 GND_402 T6 AF29 VDD_59 VDD_129 P23
AF28 GND_060 GND_180 AU23 H36 GND_298 GND_403 T8 AG12 VDD_60 VDD_130 P24
AH10 GND_061 GND_181 AU24 H39 GND_299 GND_404 U13 AG13 VDD_61 VDD_131 P25 RV210
AH13 GND_062 GND_182 AU25 H4 GND_300 GND_405 U14 AG14 VDD_62 VDD_132 P26 0_0201_5% 1 @ 2 RFU_GMS_SENSE
AH14 GND_063 GND_183 AU26 H5 GND_301 GND_406 U15 AG15 VDD_63 VDD_133 P27 RV211
AH15 GND_064 GND_184 AU27 H6 GND_302 GND_407 U16 AG16 VDD_64 VDD_134 P28 0_0201_5% 1 @ 2 RFU_VMS_SENSE
AH16 GND_065 GND_185 AU28 H8 GND_303 GND_408 U17 AG17 VDD_65 VDD_135 P29
AH17 GND_066 GND_186 AU31 H9 GND_304 GND_409 U18 AG18 VDD_66 VDD_136 R12
AH18 GND_067 GND_187 AU33 J1 GND_305 GND_410 U19 AG19 VDD_67 VDD_137 R29 place close GPU
AH19 GND_068 GND_188 AU35 J11 GND_306 GND_411 U20 QN20-P1_FCBGA1358~D AG20 VDD_68 VDD_138 T12
AH2 GND_069 GND_189 D11 J12 GND_307 GND_412 U21 AG21 VDD_69 VDD_139
GND_070 GND_239 GND_308 GND_413 @ VDD_70
AH20 AU36 J13 U22
AH21 GND_071 GND_190 AU4 J16 GND_309 GND_414 U23
AH24 GND_074 GND_193 AU6 J24 GND_312 GND_417 U26 L9 VDD_SENSE RV212 1 VGA@ 2 0_0201_5%
AH25 GND_075 GND_194 AU7 J27 GND_313 GND_418 U27 VDD_SENSE L10 GND_SENSE RV213 1 VGA@ 2 0_0201_5% VCC_SENSE_NVVDD1_MSVDD <103>
GND_076 GND_195 GND_314 GND_419 GND_SENSE VSS_SENSE_NVVDD1_MSVDD <103>
AH26 AU8 J29 U28
AH28 GND_078 GND_197 AV14 J30 GND_316 GND_421 U34 QN20-P1_FCBGA1358~D
AH32 GND_079 GND_198 AV16 J35 GND_317 GND_422 U36
GND_080 GND_199 GND_318 GND_423 @
AH34 AV18 J37 U39
AH36 GND_081 GND_200 AV20 J39 GND_319 GND_424 W10
AJ3 GND_085 GND_204 AV28 K12 GND_323 GND_428 W16
AJ32 GND_086 GND_205 AV32 K14 GND_324 GND_429 W2
AJ34 GND_087 GND_206 AW1 K16 GND_325 GND_430 W21
3 3
AK10 GND_091 GND_210 AW36 K27 GND_329 GND_434 W31
AK35 GND_096 GND_215 AY2 K40 GND_334 GND_439 W8
AK37 GND_097 GND_216 AY32 K6 GND_335 GND_440 Y17
AK39 GND_098 GND_217 AY34 K8 GND_336 GND_441 Y18
AL2 GND_099 GND_218 AY37 L32 GND_337 GND_442 Y19
AL30 GND_100 GND_219 AY39 L34 GND_338 GND_443 Y20
AL4 GND_101 GND_220 B1 L36 GND_339 GND_444 Y25
AL40 GND_102 GND_221 B11 L39 GND_340 GND_445 Y26
AL6 GND_103 GND_222 B24 M32 GND_341 GND_446 Y27
AL8 GND_104 GND_223 B26 M33 GND_342 GND_447 Y28
AM13 GND_105 GND_224 B29 GND_343 GND_448
AM15 GND_106 GND_225 B30
AM17 GND_107 GND_226 B32
AM19 GND_108 GND_227 B33
AM21 GND_109 GND_228 B35
AM23 GND_110 GND_229 B40 AA34
AM25 GND_111 GND_230 B5 G20 OPT_GND_1
AM27 GND_112 GND_231 B6 AB37 OPT_GND_10
AM32 GND_113 GND_232 B8 AD34 OPT_GND_2
AM33 GND_114 GND_233 C12 AE37 OPT_GND_3
AM35 GND_115 GND_234 C2 AF35 OPT_GND_4
AM36 GND_116 GND_235 C38 D16 OPT_GND_5
AM37 GND_117 GND_236 C9 D19 OPT_GND_6
AM38 GND_118 GND_237 D1 F15 OPT_GND_7
AM4 GND_119 GND_238 G17 OPT_GND_8
GND_120 OPT_GND_9
QN20-P1_FCBGA1358~D
@
QN20-P1_FCBGA1358~D
@
4 4

N18P(5/11)-G61A/N20P POWER & GND
A B C D E
5 4 3 2 1
UV1K
5/17 IFPAB
DVI
SL/DL
DP
Check layout for port connect i on.
TXC/TXC
AV1 UV1N
IFPA_L3_N AV2 DP0_TXN3 <39>
VGA@ TXC/TXC 8/17 IFPE
2 RV61 1 AP9 IFPA_L3 DP0_TXP3 <39>
VGA@
1K_0402_1% IFPAB_RSET 2 RV62 1 AM7
AW3 1K_0402_1% IFPE_RSET
TXD0/0 IFPA_L2_N DP0_TXN2 <39>
TXD0/0
AY3 HDMI DP
+GPU_PLLVDD IFPA_L2 DP0_TXP2 <39>
AN9 +GPU_PLLVDD AJ8
D
IFPAB_PLLVDD
TXD1/1
TXD1/1
IFPA_L1_N
IFPA_L1
AV5
AW5 DP0_TXN1 <39>
DP0_TXP1 <39>
DP AM8
IFPE_PLLVDD
IFPE_AUX_SDA_N
IFPE_AUX_SCL
AK8
D
1U_0201_6.3V6M
AJ1
CV240
1U_0201_6.3V6M
1 TXC IFPE_L3_N
AY5 AJ2
CV241
TXD2/2 IFPA_L0_N DP0_TXN0 <39> 1 TXC IFPE_L3
VGA@ TXD2/2
AY6
IFPA_L0 DP0_TXP0 <39> AK1
VGA@ TXD0
2 IFPE_L2_N AK2
TXD0 IFPE_L2
AJ6 2
IFPA_AUX_SDA_N AK6 DP0_AUXN <39> AM3
IFPA_AUX_SCL DP0_AUXP <39> TXD1 IFPE_L1_N AM2
TXD1
IFPAB IFPE_L1
TXC
AW9 TXD2 AM1
IFPB_L3_N AV9 IFPE_L0_N AN1
TXC IFPB_L3 TXD2 IFPE_L0
+PEX_VDD
TXD0/3 IFPB_L2_N
AV8 DP0_AUXN RV184 1 DP@ 2 100K_0402_5% Near GPU Under GPU
TXD0/3
AW8 AL11
IFPB_L2 AL12 IFP_IOVDD_1
IFP_IOVDD_2
AW6 DP0_AUXP RV185 1 DP@ 2 100K_0402_5%
TXD1/4 IFPB_L1_N
4.7U_0402_6.3V6M
CV242
1U_0201_6.3V6M
CV243
1U_0201_6.3V6M
CV244
1U_0201_6.3V6M
CV245
TXD1/4 AV6 1 1 1 1 QN20-P1_FCBGA1358~D
IFPB_L1
@
+PEX_VDD
AY8
Under GPU TXD2/5
TXD2/5
IFPB_L0_N
IFPB_L0
AY9 2 2 2 2
VGA@
VGA@
VGA@
VGA@
AK7
AL15 IFPB_AUX_SDA_N AJ7
IFP_IOVDD_5 IFPB_AUX_SCL
4.7U_0402_6.3V6M
CV246
1U_0201_6.3V6M
CV247 VGA@
1U_0201_6.3V6M
CV248 VGA@
1U_0201_6.3V6M
CV249 VGA@
1 1 1 1 AL16
AM11 IFP_IOVDD_6
AM12 IFP_IOVDD_7
IFP_IOVDD_8
2 2 2 2
VGA@
QN20-P1_FCBGA1358~D
@
C C
Near GPU
UV1L
6/17 IFPC
VGA@
2 RV67 1 AN7
1K_0402_1% IFPCD_RSET
HDMI DP
AK4
IFPC_AUX_SDA_N GPU_HDMI_CTRL_DAT <40>
AJ4
IFPC_AUX_SCL GPU_HDMI_CTRL_CLK <40>
Under GPU
+GPU_PLLVDD AM6
1 per ball TXC IFPC_L3_N GPU_HDMI_CLKN <40>
AN8 TXC
AM5
IFPCD_PLLVDD IFPC_L3 GPU_HDMI_CLKP <40>
AN5
1U_0201_6.3V6M
1U_0201_6.3V6M
TXD0 GPU_HDMI_N0 <40>

IFPC_L2_N AN6
HDMI
CV250
CV251
1 1 TXD0 IFPC_L2 GPU_HDMI_P0 <40>

VGA@
DR@
IFPC AR6
2 2
TXD1
TXD1
IFPC_L1_N
IFPC_L1
AR5
GPU_HDMI_N1
GPU_HDMI_P1
<40>
<40> 2.1
TXD2 AT5
IFPC_L0_N GPU_HDMI_N2 <40>
TXD2 AT6
IFPC_L0 GPU_HDMI_P2 <40>
Check connect i on
B AL13 B
AL14 IFP_IOVDD_3
+PEX_VDD IFP_IOVDD_4
Near GPU Under GPU QN20-P1_FCBGA1358~D

@
4.7U_0402_6.3V6M
CV252 VGA@
1U_0201_6.3V6M
CV253 VGA@
1U_0201_6.3V6M
CV254 VGA@
1U_0201_6.3V6M
CV255 VGA@
1 1 1 1
UV1M
7/17 IFPD
2 2 2 2
HDMI DP
AJ5
IFPD_AUX_SDA_N AK5
IFPD_AUX_SCL
TXC AN2
IFPD TXC
IFPD_L3_N
IFPD_L3
AN3
AR3
TXD0 IFPD_L2_N AR2
TXD0 IFPD_L2
TXD1 AR1
IFPD_L1_N AT1
TXD1 IFPD_L1
AT2
TXD2 IFPD_L0_N AT3
TXD2 IFPD_L0
1U_0201_6.3V6M
CV256 VGA@
1U_0201_6.3V6M
CV257 VGA@
1 1 AM14
AN12 IFP_IOVDD_9
IFP_IOVDD_10
A A
2 2 QN20-P1_FCBGA1358~D
@

N18P(8/11)G61A/N20P-Reserve
5 4 3 2 1
5 4 3 2 1
+1.8VSDGPU_MAIN
+1.8VSDGPU_AON
VGA_OVERT# RV70 2 VGA@ 1 10K_0201_5%

VGA_ALERT# RV71 2 VGA@ 1 10K_0201_5%
FRM_LCK# RV72 2 VGA@ 1 10K_0201_5%
5
ACIN_BUF RV73 2 VGA@ 1 10K_0201_5%
G
4 3
<36> VGA_I2CC_SCL VGA_I2CC_SCL_PWR <36,103> NVVDD_PSI
D
RV75 2 VGA@ 1 10K_0201_5%
UV1O PJT138KA_SOT363-6
10/17 MISC1 QV17A VGA@
2
PJT138KA_SOT363-6
D U1 VGA_I2CS_SCL QV17B VGA@ FBVDDQ_PSI RV76 2 VGA@ 1 10K_0201_5% D
G
I2CS_SCL V1 VGA_I2CS_SDA 1 6 GPIO22_ADC_MUX_SEL RV77 2 VGA@ 1 10K_0201_5%
VGA_OVERT# I2CS_SDA <36> VGA_I2CC_SDA VGA_I2CC_SDA_PWR <36,103>
P1
D
OVERT U2 VGA_I2CC_SCL +1.8VSDGPU_AON
AP8 I2CC_SCL V2 VGA_I2CC_SDA VGA_I2CS_SDA RV78 1 VGA@ 2 1.8K_0402_1%
TS_VREF I2CC_SDA unused pin PH 2K to 1V8AON VGA_I2CS_SCL RV79 1 VGA@ 2 1.8K_0402_1%
M2 U3 RV80 1 VGA@ 2 2K_0402_5%
THERMDN I2CB_SCL V3 RV81 1 VGA@ 2 2K_0402_5% +1.8VSDGPU_MAIN VGA_I2CC_SDA RV82 1 VGA@ 2 2K_0402_5%
M1 I2CB_SDA VGA_I2CC_SCL RV83 1 VGA@ 2 2K_0402_5%
THERMDP
P3
GPIO0 P7 GC6_FB_EN1V8 NVVDD_VID <103>
GPIO1 R4
GPIO2 U6 Intel /AMD naming
5
TV2 @ JTAG_TCK AY11 +1.8VSDGPU_AON
TV3 @ JTAG_TMS AV11 JTAG_TCK GPIO3 U7 GPIO4_EN
+1.8VSDGPU_EN colay NVVDD1_EN
G
TV4 @ JTAG_TDI AW11 JTAG_TMS GPIO4 V4 FRM_LCK# VGA_I2CS_SCL 4 3
JTAG_TDO JTAG_TDI GPIO5 R7 PCH_SML1CLK <18,58,66> GPIO4_EN
AW12 RV86 2 VGA@ 1 10K_0201_5%
D
TV5 @
10K_0402_5% 1 VGA@ 2 RV87 JTAG_TRST# AV12 JTAG_TDO GPIO6 M6 NVVDD_PSI <103> PJT138KA_SOT363-6
10K_0402_5% 1 VGA@ 2 RV88 TESTMODE AY12 JTAG_TRST_N GPIO7 L8 QV14A VGA@
NVJTAG_SEL GPIO8 M7 VGA_ALERT# VRAM_VDD_CTL <108>
GPIO9 L5
2
Y3 VRAM_VREF_CTL PJT138KA_SOT363-6
<36> ADC_IN_P ADC_IN GPIO10 R8
Y4 QV14B VGA@
G
<36> ADC_IN_N ADC_IN_N GPIO11 M3 ACIN_BUF VGA_I2CS_SDA
DV1 2 1 1 6 PCH_SML1DATA <18,58,66>
GPIO12 P6 DGPU_AC_DETECT <19,58,85>
D
VGA@
GPIO13 P5 DP0_HPD_GPU# RB751S40T1G_SOD523-2 NVVDD_PSI RV90 2 @ 1 10K_0201_5%
GPIO14 P2
GPIO15 U4 VRAM_VREF_CTL RV91 2 VGA@ 1 100K_0201_5%
GPIO16 P4 GC6_FB_EN1V8 RV92 2 VGA@ 1 10K_0201_5%
GPIO17 L6
GPIO18 R3
GPIO19 R5
GPIO20 R2
GPIO21 M5 +1.8VSDGPU_AON
GPIO22 U5 GPIO22_ADC_MUX_SEL <36>
GPIO23 L7
GPIO24 R6 VGA@
GPIO25 M4 RV94 2 N18PA@ 1 0_0402_5% FBVDDQ_PSI <108> CV258
GPIO26 R1 HDMI_HPD_GPU# GPIO26_FP_FUSE <37> 2 1 +1.8VSDGPU_AON
GPIO27 M8 RV95 2 N20P@ 1 0_0402_5% VRAM_VDD_CTL RV181 2 @ 1 10K_0201_5%
RFU_GPIO28 P8
RFU_GPIO29 P9
ROM_WP#_R <29> Intel /AMD naming 0.1U_0201_10V6K
1
VGA@
RFU_GPIO30 R9 RV96
GND VCC
C RFU_GPIO31 U9 DP0_HPD_PCH C
1 10K_0402_5%
RFU_GPIO32 V9 <16,39> DP0_HPD_PCH IN B 4 2
RFU_GPIO33 U10 PLTRST_VGA#_1V8 2 OUT Y Gate
2
RFU_GPIO34 V10 IN A 1 DP0_HPD_GPU#
RFU_GPIO35 Drain
QN20-P1_FCBGA1358~D VGA@ UV8 3 VGA@
3
NL17SZ08DFT2G_SC70-5 Source QV1
@
LBSS139WT1G_SC70-3
+1.8VSDGPU_AON
+1.8VSDGPU_AON
Intel /AMD naming
1
VGA@
RV97
VGA@ 10K_0201_5%
CV259 +1.8VSDGPU_AON PU at PCH side
2 1
VGA_CLKREQ# <15>
2
HDMI_HPD_GPU#
2
0.1U_0201_10V6K
Intel /AMD naming
5
RV98 VGA@
10K_0201_5%
VCC
6
1
<16,40> HDMI_HPD_PCH IN B
3
4 2
D
G QV16B VGA@
1
PLTRST_VGA#_1V8 2 OUT Y ALL_GPWRGD 5
D
QV16A VGA@
PJT138KA_SOT363-6
GND
1 S G
IN A @ 1 S
PJT138KA_SOT363-6
1
CV260 @
4
0.1U_0201_10V6K CV261
3
VGA@ UV9 2 0.1U_0201_10V6K
NL17SZ08DFT2G_SC70-5 2
VGA_CLKREQ#_R <27>
B B
UV15
N20P@
S IC SLG4U44276VTR STQFN 20P LOGIC SOC

SA0000DZ000
+3VS
+1.8VSDGPU_AON UV15
VGA@
0.1U_0201_10V6K 2 1 CV262 1 20
PLTRST_VGA#_1V8 VDD 1V8_MAIN_EN 1.8VSDGPU_MAIN_EN3V3 <37>
RV99 1 VGA@ 2 10K_0201_5%
GPIO4_EN 2 19
1V8_MAIN_EN_GPU PEGX_RST# PLTRST_VGA#_1V8 <27>
0.1U_0201_10V6K 2 1 CV263
@ <19> DGPU_PWR_EN 3 18 PEX_VDD_EN <37,110>
0.1U_0201_10V6K 2 1 CV264 VGA_OVERT# DGPU_PWR_EN PEX_VDD_EN
@ GC6_FB_EN1V8 RV183 2 @ 1 0_0402_5% GC6_FB_EN1V8_R 4
0.1U_0201_10V6K 2 1 CV265 GPIO4_EN RV182 2 @ 1 10K_0201_5% GC6_FB_EN_GPU 17
FB_VDD_EN FBVDDQ_EN <37,108>
@ 5
<110> PEX_VDD_PG PEX_VDD_PG
<19> GC6_FB_EN3V3
6 16 3VSDGPU_EN <37,39>
GC6_FB_EN 3V3_SYS_EN
<108> FBVDDQ_PG 7
FB_VDD_PG 15 ALL_GPWRGD
VGA_OVERT# 8 ALL_GPU_PWR_OK
OVERT#_GPU
14 GPU_OVERT# <58>
OVERT#
9 13 1V8_AON_EN <37>
<19> DGPU_HOLD_RST# DGPU_HOLD_RST# 1V8_AON_EN
12 NVVDD1_EN <37,103>
A 10 NVVDD_EN A
<16,58,66> PLT_RST# PLT_RST#
11
GND
SLG4U43589VTR_STQFN20_3X2
N18PA@
SA0000DH100

N18P(9/11)G61A/N20P-Reserve
5 4 3 2 1
A B C D E
UV5
UV4
FBA_32-63
FBA_31-0 <28> FBA_EDC4
C2
EDC0_A DQ0_A
B4
FBA_D35 <28>
C2 B4 C13 A3
<28> FBA_EDC1 EDC0_A DQ0_A FBA_D9 <28> <28> FBA_EDC5 EDC1_A DQ1_A FBA_D34 <28>
C13 A3 T2 B3
<28> FBA_EDC0 EDC1_A DQ1_A FBA_D13 <28> <28> FBA_EDC7 EDC0_B DQ2_A FBA_D33 <28>
T2 B3 T13 B2
<28> FBA_EDC2 EDC0_B DQ2_A FBA_D10 <28> <28> FBA_EDC6 EDC1_B DQ3_A FBA_D32 <28>
T13 B2 E3
<28> FBA_EDC3 EDC1_B DQ3_A FBA_D14 <28> DQ4_A FBA_D39 <28>
E3 E2
DQ4_A FBA_D12 <28> DQ5_A FBA_D37 <28>
E2 D2 F2
DQ5_A FBA_D15 <28> <28> FBA_DBI4 DBI0#_A DQ6_A FBA_D38 <28>
D2 F2 D13 G2
<28> FBA_DBI1 DBI0#_A DQ6_A FBA_D8 <28> <28> FBA_DBI5 DBI1#_A DQ7_A FBA_D36 <28>
D13 G2 R2 B11
<28> FBA_DBI0 DBI1#_A DQ7_A FBA_D11 <28> <28> FBA_DBI7 DBI0#_B DQ8_A FBA_D40 <28>
R2 B11 R13 A12
<28> FBA_DBI2 R13 DBI0#_B DQ8_A A12 FBA_D6 <28> <28> FBA_DBI6 DBI1#_B DQ9_A B12 FBA_D47 <28>
<28> FBA_DBI3 DBI1#_B DQ9_A FBA_D4 <28> DQ10_A FBA_D44 <28>
B12 B13
DQ10_A FBA_D5 <28> DQ11_A FBA_D46 <28>
B13 change for N20P J10 E12
DQ11_A FBA_D7 <28> <28> FBA_CLKA1 CK DQ12_A FBA_D41 <28>
1
change for N20P J10 E12 K10 E13 1
<28> FBA_CLKA0 CK DQ12_A FBA_D1 <28> <28> FBA_CLKA1# CK# DQ13_A FBA_D45 <28>
K10 E13 G10 F13
<28> FBA_CLKA0# G10 CK# DQ13_A F13 FBA_D2 <28> <28> FBA_CMD44 M10 CKE#_A DQ14_A G13 FBA_D43 <28>
<28> FBA_CMD14 CKE#_A DQ14_A FBA_D0 <28> <28> FBA_CMD41 CKE#_B DQ15_A FBA_D42 <28>
M10 G13
<28> FBA_CMD17 CKE#_B DQ15_A FBA_D3 <28>
U4
DQ0_B FBA_D63 <28>
U4 V3
DQ0_B FBA_D16 <28> DQ1_B FBA_D61 <28>
V3 U3
DQ1_B FBA_D22 <28> DQ2_B FBA_D60 <28>
U3 J5 U2
DQ2_B FBA_D23 <28> <28> FBA_CMD37 CABI#_A DQ3_B FBA_D57 <28>
J5 U2 K5 P3
<28> FBA_CMD10 CABI#_A DQ3_B FBA_D17 <28> <28> FBA_CMD38 CABI#_B DQ4_B FBA_D59 <28>
K5 P3 P2
<28> FBA_CMD9 CABI#_B DQ4_B FBA_D19 <28> DQ5_B FBA_D62 <28>
P2 N2
DQ5_B FBA_D21 <28> DQ6_B FBA_D58 <28>
N2 M2
DQ6_B M2 FBA_D20 <28> DQ7_B U11 FBA_D56 <28>
DQ7_B U11
FBA_D18 <28> DQ8_B V12
FBA_D54 <28> change for N20P
DQ8_B V12
FBA_D25 <28> change for N20P RV53 2 VGA@ 1 121_0402_1% J14 DQ9_B U12
FBA_D51 <28>
DQ9_B FBA_D29 <28> ZQ_A DQ10_B FBA_D53 <28>
RV54 2 VGA@ 1 121_0402_1% J14 U12 RV55 2 VGA@ 1 121_0402_1% K14 U13
ZQ_A DQ10_B FBA_D28 <28> ZQ_B DQ11_B FBA_D55 <28>
RV56 2 VGA@ 1 121_0402_1% K14 U13 P12
ZQ_B DQ11_B P12 FBA_D30 <28> DQ12_B P13 FBA_D48 <28>
DQ12_B FBA_D27 <28> DQ13_B FBA_D50 <28>
P13 N13
DQ13_B FBA_D26 <28> DQ14_B FBA_D49 <28>
N13 M13
DQ14_B FBA_D31 <28> DQ15_B FBA_D52 <28>
M13
DQ15_B FBA_D24 <28>
N5 H3
TCK CA0_A FBA_CMD33 <28>
N5 H3 F10 G11
TCK CA0_A FBA_CMD1 <28> TDI CA1_A FBA_CMD45 <28>
F10 G11 N10 G4
TDI CA1_A FBA_CMD13 <28> TDO CA2_A FBA_CMD35 <28>
N10 G4 F5 H12
TDO CA2_A FBA_CMD12 <28> TMS CA3_A FBA_CMD46 <28>
F5 H12 H5
TMS CA3_A H5 FBA_CMD24 <28> CA4_A H10 FBA_CMD36 <28>
CA4_A FBA_CMD11 <28> CA5_A FBA_CMD43 <28>
H10 J12
J12 J11
J11 J4
J4 J3
J3
CA9_A FBA_CMD2 <28>
L3
CA0_B FBA_CMD29 <28>
L3 D4 M11
CA0_B FBA_CMD5 <28> <28> FBA_WCK45 WCK_A CA1_B FBA_CMD52 <28>
D4 M11 D5 M4
<28> FBA_WCKB01 WCK_A CA1_B FBA_CMD18 <28> <28> FBA_WCK45# WCK#_A CA2_B FBA_CMD40 <28>
D5 M4 R11 L12
<28> FBA_WCKB01# R11 WCK#_A CA2_B L12 FBA_CMD7 <28> <28> FBA_WCK67 R10 WCK_B CA3_B L5 FBA_CMD50 <28>
<28> FBA_WCKB23 WCK_B CA3_B FBA_CMD20 <28> <28> FBA_WCK67# WCK#_B CA4_B FBA_CMD39 <28>
R10 L5 L10
<28> FBA_WCKB23# WCK#_B CA4_B FBA_CMD8 <28> CA5_B FBA_CMD42 <28>
L10 K12
CA5_B FBA_CMD16 <28> CA6_B FBA_CMD49 <28>
K12 change for N20P K11
CA6_B FBA_CMD21 <28> CA7_B FBA_CMD51 <28>
K11 K4
CA7_B K4 FBA_CMD19 <28>
W=16mils CA8_B K3 FBA_CMD28 <28>
change for N20P W=16mils

+FBAA_VREFC
CA8_B
CA9_B
K3
FBA_CMD6
FBA_CMD4
<28>
<28>
+FBAB_VREFC K1
VREFC
CA9_B FBA_CMD30
+FBVDDQ
<28>
K1
VREFC +FBVDDQ C1
C1 J1 VDDQ1 E1
VDDQ1 <28> FBA_CMD31 RESET# VDDQ2
J1 E1 H1
<28> FBA_CMD3 RESET# VDDQ2 VDDQ3
2 H1 L1 2
VDDQ3 L1 B1 VDDQ4 P1
B1 VDDQ4 P1 D1 VSS1 VDDQ5 T1
D1 VSS1 VDDQ5 T1 F1 VSS2 VDDQ6 J2
F1 VSS2 VDDQ6 J2 G1 VSS3 VDDQ7 K2
G1 VSS3 VDDQ7 K2 M1 VSS4 VDDQ8 C4
M1 VSS4 VDDQ8 C4 N1 VSS5 VDDQ9 F4
N1 VSS5 VDDQ9 F4 R1 VSS6 VDDQ10 N4
R1 VSS6 VDDQ10 N4 U1 VSS7 VDDQ11 T4
U1 VSS7 VDDQ11 T4 +FBAB_VREFC A2 VSS8 VDDQ12 B5
+FBAA_VREFC A2 VSS8 VDDQ12 B5 V2 VSS9 VDDQ13 U5
V2 VSS9 VDDQ13 U5 C3 VSS10 VDDQ14 B10
C3 VSS10 VDDQ14 B10 D3 VSS11 VDDQ15 U10
VSS11 VDDQ15 VSS12 VDDQ16
2
D3 U10 F3 C11
2
F3 C11 RD24 G3 F11

RD23 G3 VSS13 VDDQ17 F11 VGA@ M3 VSS14 VDDQ18 N11
1K_0402_1%
VGA@ M3 VSS14 VDDQ18 N11 N3 VSS15 VDDQ19 T11
1K_0402_1% VSS15 VDDQ19 VSS16 VDDQ20
N3 T11 R3 J13
1
R3 VSS16 VDDQ20 J13 T3 VSS17 VDDQ21 K13
1
T3 VSS17 VDDQ21 K13 A4 VSS18 VDDQ22 C14

A4 VSS18 VDDQ22 C14 E4 VSS19 VDDQ23 E14
E4 VSS19 VDDQ23 E14 H4 VSS20 VDDQ24 H14
H4 VSS20 VDDQ24 H14 L4 VSS21 VDDQ25 L14
L4 VSS21 VDDQ25 L14 P4 VSS22 VDDQ26 P14
P4 VSS22 VDDQ26 P14 V4 VSS23 VDDQ27 T14
V4 VSS23 VDDQ27 T14 C5 VSS24 VDDQ28
C5 VSS24 VDDQ28 T5 VSS25
T5 VSS25 C10 VSS26 A1
C10 VSS26 A1 T10 VSS27 VDD1 V1
T10 VSS27 VDD1 V1 A11 VSS28 VDD2 H2
A11 VSS28 VDD2 H2 E11 VSS29 VDD3 L2
E11 VSS29 VDD3 L2 H11 VSS30 VDD4 E5
H11 VSS30 VDD4 E5 L11 VSS31 VDD5 P5
L11 VSS31 VDD5 P5 P11 VSS32 VDD6 E10
P11 VSS32 VDD6 E10 V11 VSS33 VDD7 P10
V11 VSS33 VDD7 P10 C12 VSS34 VDD8 H13
C12 VSS34 VDD8 H13 D12 VSS35 VDD9 L13
D12 VSS35 VDD9 L13 F12 VSS36 VDD10 A14
F12 VSS36 VDD10 A14 G12 VSS37 VDD11 V14
G12 VSS37 VDD11 V14 M12 VSS38 VDD12 +1.8VSDGPU_AON
M12 VSS38 VDD12 +1.8VSDGPU_AON N12 VSS39
N12 VSS39 R12 VSS40 A5
R12 VSS40 A5 T12 VSS41 VPP1 V5
T12 VSS41 VPP1 V5 A13 VSS42 VPP2 A10
A13 VSS42 VPP2 A10 V13 VSS43 VPP3 V10
V13 VSS43 VPP3 V10
change for N20P B14 VSS44 VPP4
B14 VSS44 VPP4 D14 VSS45 R4
VSS45 VSS46 WCK0_t_B,NC FBA_WCKB67 <28>
D14 R4 F14 R5
VSS46 WCK0_t_B,NC FBA_WCK23 <28> VSS47 WCK0_c_B,NC FBA_WCKB67# <28>
F14 R5 G14
3
G14 VSS47 WCK0_c_B,NC FBA_WCK23# <28> M14 VSS48 G5
3
M14 VSS48 G5 N14 VSS49 RFU_A,NC M5

N14 VSS49 RFU_A,NC M5 R14 VSS50 RFU_B,NC
R14 VSS50 RFU_B,NC U14 VSS51 D10
change for N20P
180-BALL FBA_WCKB45# <28>
U14 VSS51 D10 VSS52 SGRAM GDDR6 WCK1_c_A,NC D11
180-BALL FBA_WCK01# <28> FBA_WCKB45 <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 WCK1_t_A,NC
WCK1_t_A,NC FBA_WCK01 <28>
X76@ K4Z80325BC-HC14_FBGA180~D
1uFx18
1uFx18 +FBVDDQ close or under
+FBVDDQ close or under
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CV118
CV119
CV120
CV121
CV122
CV123
CV124
CV125
CV126
CV127
CV128
CV129
CV130
CV131
CV132
CV133
CV134
CV135
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV100
CV101
CV102
CV103
CV104
CV105
CV106
CV107
CV108
CV109
CV110
CV111
CV112
CV113
CV114
CV115
CV116
CV117
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1uFx4
1uFx4 10uFx4 22uFx6 10uFx2
10uFx4 22uFx6 10uFx2 +FBVDDQ +FBVDDQ +FBVDDQ +1.8VSDGPU_AON close or under
+FBVDDQ +FBVDDQ +FBVDDQ +1.8VSDGPU_AON close or under close or under Around Around
close or under Around Around
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
CV153
CV154
CV155
CV156
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV166
CV167
CV168
CV169
2 2 2 2 2 2 1 1 1 1 1
1
CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
CV146
CV147
CV148
CV149
CV150
CV151
CV152
2 2 2 2 2 2 1 1 1 1 1
1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ DR@
2
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ DR@ 1 1 1 1 1 1 2 2 2 2 2
2
1 1 1 1 1 1 2 2 2 2 2
4 4

N18P(6/11)-G61A/N20P GDDR6 CHA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
A B C D E
A B C D E
UV7
FBB_31-0 UV6
FBB_32-63 <28> FBB_EDC4

C2
EDC0_A DQ0_A
B4
FBB_D38 <28>
C2 B4 C13 A3
<28> FBB_EDC1 EDC0_A DQ0_A FBB_D11 <28> <28> FBB_EDC5 EDC1_A DQ1_A FBB_D35 <28>
C13 A3 change for N20P T2 B3 change for N20P
<28> FBB_EDC0 EDC1_A DQ1_A FBB_D13 <28> <28> FBB_EDC7 EDC0_B DQ2_A FBB_D37 <28>
T2 B3 T13 B2
<28> FBB_EDC2 EDC0_B DQ2_A FBB_D15 <28> <28> FBB_EDC6 EDC1_B DQ3_A FBB_D34 <28>
T13 B2 E3
<28> FBB_EDC3 EDC1_B DQ3_A FBB_D8 <28> DQ4_A FBB_D39 <28>
E3 E2
DQ4_A FBB_D12 <28> DQ5_A FBB_D36 <28>
E2 D2 F2
D2 DQ5_A F2 FBB_D14 <28> <28> FBB_DBI4 D13 DBI0#_A DQ6_A G2 FBB_D33 <28>
<28> FBB_DBI1 DBI0#_A DQ6_A FBB_D9 <28> <28> FBB_DBI5 DBI1#_A DQ7_A FBB_D32 <28>
D13 G2 R2 B11
<28> FBB_DBI0 DBI1#_A DQ7_A FBB_D10 <28> <28> FBB_DBI7 DBI0#_B DQ8_A FBB_D41 <28>
R2 B11 R13 A12
<28> FBB_DBI2 DBI0#_B DQ8_A FBB_D0 <28> <28> FBB_DBI6 DBI1#_B DQ9_A FBB_D44 <28>
1 R13 A12 B12 1
<28> FBB_DBI3 DBI1#_B DQ9_A FBB_D7 <28> DQ10_A FBB_D42 <28>
change for N20P B12 change for N20P B13
DQ10_A B13 FBB_D5 <28> J10 DQ11_A E12 FBB_D47 <28>
DQ11_A FBB_D2 <28> <28> FBB_CLKA1 CK DQ12_A FBB_D40 <28>
J10 E12 K10 E13
<28> FBB_CLKA0 CK DQ12_A FBB_D3 <28> <28> FBB_CLKA1# CK# DQ13_A FBB_D46 <28>
K10 E13 G10 F13
<28> FBB_CLKA0# CK# DQ13_A FBB_D6 <28> <28> FBB_CMD44 CKE#_A DQ14_A FBB_D45 <28>
G10 F13 M10 G13
<28> FBB_CMD14 CKE#_A DQ14_A FBB_D4 <28> <28> FBB_CMD41 CKE#_B DQ15_A FBB_D43 <28>
M10 G13
<28> FBB_CMD17 CKE#_B DQ15_A FBB_D1 <28>
U4
DQ0_B FBB_D63 <28>
U4 V3
DQ0_B FBB_D16 <28> DQ1_B FBB_D58 <28>
V3 U3
DQ1_B FBB_D22 <28> DQ2_B FBB_D61 <28>
U3 J5 U2
DQ2_B FBB_D20 <28> <28> FBB_CMD37 CABI#_A DQ3_B FBB_D62 <28>
J5 U2 K5 P3
<28> FBB_CMD10 K5 CABI#_A DQ3_B P3 FBB_D23 <28> <28> FBB_CMD38 CABI#_B DQ4_B P2 FBB_D56 <28>
<28> FBB_CMD9 CABI#_B DQ4_B FBB_D17 <28> DQ5_B FBB_D57 <28>
P2 N2
DQ5_B FBB_D18 <28> DQ6_B FBB_D60 <28>
N2 M2
DQ6_B FBB_D19 <28> DQ7_B FBB_D59 <28>
M2 U11
DQ7_B FBB_D21 <28> DQ8_B FBB_D53 <28>
U11 V12
DQ8_B V12 FBB_D31 <28> 2 VGA@ 1 J14 DQ9_B U12 FBB_D48 <28>
RV57 121_0402_1%
DQ9_B FBB_D25 <28> ZQ_A DQ10_B FBB_D51 <28>
RV58 2 VGA@ 1 121_0402_1% J14 U12 RV59 2 VGA@ 1 121_0402_1% K14 U13
ZQ_A DQ10_B FBB_D30 <28> ZQ_B DQ11_B FBB_D50 <28>
RV60 2 VGA@ 1 121_0402_1% K14 U13 P12
ZQ_B DQ11_B FBB_D29 <28> DQ12_B FBB_D55 <28>
P12 P13
DQ12_B FBB_D27 <28> DQ13_B FBB_D52 <28>
P13 N13
DQ13_B FBB_D26 <28> DQ14_B FBB_D54 <28>
N13 M13
DQ14_B FBB_D28 <28> DQ15_B FBB_D49 <28>
M13
DQ15_B FBB_D24 <28>
N5 H3
TCK CA0_A FBB_CMD33 <28>
N5 H3 F10 G11
F10 TCK CA0_A G11 FBB_CMD1 <28> N10 TDI CA1_A G4 FBB_CMD45 <28>
TDI CA1_A FBB_CMD13 <28> TDO CA2_A FBB_CMD35 <28>
N10 G4 F5 H12
TDO CA2_A FBB_CMD12 <28> TMS CA3_A FBB_CMD46 <28>
F5 H12 H5
TMS CA3_A FBB_CMD24 <28> CA4_A FBB_CMD36 <28>
H5 H10
CA4_A FBB_CMD11 <28> CA5_A FBB_CMD43 <28>
H10 J12
J12 J11
J11 J4
J4 J3
J3
CA9_A FBB_CMD2 <28>
L3
L3 D4 CA0_B M11 FBB_CMD29 <28>
CA0_B FBB_CMD5 <28> <28> FBB_WCK45 WCK_A CA1_B FBB_CMD52 <28>
D4 M11 D5 M4
<28> FBB_WCKB01 WCK_A CA1_B FBB_CMD18 <28> <28> FBB_WCK45# WCK#_A CA2_B FBB_CMD40 <28>
D5 M4 R11 L12
<28> FBB_WCKB01# WCK#_A CA2_B FBB_CMD7 <28> <28> FBB_WCK67 WCK_B CA3_B FBB_CMD50 <28>
R11 L12 R10 L5
<28> FBB_WCKB23 WCK_B CA3_B FBB_CMD20 <28> <28> FBB_WCK67# WCK#_B CA4_B FBB_CMD39 <28>
R10 L5 L10
<28> FBB_WCKB23# WCK#_B CA4_B FBB_CMD8 <28> CA5_B FBB_CMD42 <28>
L10 K12
CA5_B FBB_CMD16 <28> CA6_B FBB_CMD49 <28>
K12 K11
CA6_B FBB_CMD21 <28> CA7_B FBB_CMD51 <28>
K11 change for N20P K4
change for N20P
CA7_B K4
FBB_CMD19 <28>
W=16mils CA8_B K3
FBB_CMD28 <28>
W=16mils
+FBBA_VREFC
CA8_B
CA9_B
K3
FBB_CMD6
FBB_CMD4
<28>
<28>
+FBBB_VREFC K1
VREFC
CA9_B FBB_CMD30
+FBVDDQ
<28>
K1
VREFC +FBVDDQ C1
2 2
C1 J1 VDDQ1 E1
VDDQ1 <28> FBB_CMD31 RESET# VDDQ2
J1 E1 H1
<28> FBB_CMD3 RESET# VDDQ2 VDDQ3
H1 L1
VDDQ3 L1 B1 VDDQ4 P1
B1 VDDQ4 P1 D1 VSS1 VDDQ5 T1
D1 VSS1 VDDQ5 T1 F1 VSS2 VDDQ6 J2
F1 VSS2 VDDQ6 J2 G1 VSS3 VDDQ7 K2
G1 VSS3 VDDQ7 K2 +FBBB_VREFC M1 VSS4 VDDQ8 C4
+FBBA_VREFC M1 VSS4 VDDQ8 C4 N1 VSS5 VDDQ9 F4
N1 VSS5 VDDQ9 F4 R1 VSS6 VDDQ10 N4
R1 VSS6 VDDQ10 N4 U1 VSS7 VDDQ11 T4
2
U1 T4 A2 B5
2
A2 B5 RD26 V2 U5
RD25 V2 VSS9 VDDQ13 U5 VGA@ C3 VSS10 VDDQ14 B10
1K_0402_1%
VGA@ C3 VSS10 VDDQ14 B10 D3 VSS11 VDDQ15 U10
1K_0402_1%
D3 VSS11 VDDQ15 U10 F3 VSS12 VDDQ16 C11
1
F3 VSS12 VDDQ16 C11 G3 VSS13 VDDQ17 F11
1
G3 VSS13 VDDQ17 F11 M3 VSS14 VDDQ18 N11

M3 VSS14 VDDQ18 N11 N3 VSS15 VDDQ19 T11
N3 VSS15 VDDQ19 T11 R3 VSS16 VDDQ20 J13
R3 VSS16 VDDQ20 J13 T3 VSS17 VDDQ21 K13
T3 VSS17 VDDQ21 K13 A4 VSS18 VDDQ22 C14
A4 VSS18 VDDQ22 C14 E4 VSS19 VDDQ23 E14
E4 VSS19 VDDQ23 E14 H4 VSS20 VDDQ24 H14
H4 VSS20 VDDQ24 H14 L4 VSS21 VDDQ25 L14
L4 VSS21 VDDQ25 L14 P4 VSS22 VDDQ26 P14
P4 VSS22 VDDQ26 P14 V4 VSS23 VDDQ27 T14
V4 VSS23 VDDQ27 T14 C5 VSS24 VDDQ28
C5 VSS24 VDDQ28 T5 VSS25
T5 VSS25 C10 VSS26 A1
C10 VSS26 A1 T10 VSS27 VDD1 V1
T10 VSS27 VDD1 V1 A11 VSS28 VDD2 H2
A11 VSS28 VDD2 H2 E11 VSS29 VDD3 L2
E11 VSS29 VDD3 L2 H11 VSS30 VDD4 E5
H11 VSS30 VDD4 E5 L11 VSS31 VDD5 P5
L11 VSS31 VDD5 P5 P11 VSS32 VDD6 E10
P11 VSS32 VDD6 E10 V11 VSS33 VDD7 P10
V11 VSS33 VDD7 P10 C12 VSS34 VDD8 H13
C12 VSS34 VDD8 H13 D12 VSS35 VDD9 L13
D12 VSS35 VDD9 L13 F12 VSS36 VDD10 A14
F12 VSS36 VDD10 A14 G12 VSS37 VDD11 V14
G12 VSS37 VDD11 V14 M12 VSS38 VDD12 +1.8VSDGPU_AON
M12 VSS38 VDD12 +1.8VSDGPU_AON N12 VSS39
N12 VSS39 R12 VSS40 A5
R12 VSS40 A5 T12 VSS41 VPP1 V5
T12 VSS41 VPP1 V5 A13 VSS42 VPP2 A10
A13 VSS42 VPP2 A10 V13 VSS43 VPP3 V10
V13 VSS43 VPP3 V10 B14 VSS44 VPP4
3 VSS44 VPP4 VSS45 3
B14 D14 R4
VSS45 VSS46 WCK0_t_B,NC FBB_WCKB67 <28>
D14 R4 F14 R5
VSS46 WCK0_t_B,NC FBB_WCK23 <28> VSS47 WCK0_c_B,NC FBB_WCKB67# <28>
F14 R5 G14
G14 VSS47 WCK0_c_B,NC FBB_WCK23# <28> M14 VSS48 G5
M14 VSS48 G5 N14 VSS49 RFU_A,NC M5
N14 VSS49 RFU_A,NC M5 R14 VSS50 RFU_B,NC
R14 VSS50 RFU_B,NC U14 VSS51 D10
change for N20P
U14 VSS51 D10
change for N20P VSS52
180-BALL
SGRAM GDDR6 WCK1_c_A,NC D11
FBB_WCKB45# <28>
180-BALL FBB_WCKB45 <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBB_WCK01# <28> WCK1_t_A,NC
WCK1_t_A,NC FBB_WCK01 <28>
1uFx18 1uFx18
+FBVDDQ close or under +FBVDDQ close or under
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CV170
CV171
CV172
CV173
CV174
CV175
CV176
CV177
CV178
CV179
CV180
CV181
CV182
CV183
CV184
CV185
CV186
CV187
CV188
CV189
CV190
CV191
CV192
CV193
CV194
CV195
CV196
CV197
CV198
CV199
CV200
CV201
CV202
CV203
CV204
CV205
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1uFx4 1uFx4
10uFx4 22uFx6 10uFx2 10uFx4 22uFx6 10uFx2
+FBVDDQ +FBVDDQ +FBVDDQ +1.8VSDGPU_AON close or under +FBVDDQ +FBVDDQ +FBVDDQ +1.8VSDGPU_AON close or under
close or under Around Around close or under Around Around
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
CV206
CV207
CV208
CV209
CV210
CV211
CV212
CV213
CV214
CV215
CV216
CV217
CV218
CV219
CV220
CV221
CV222
CV223
CV224
CV225
CV226
CV227
CV228
CV229
CV230
CV231
CV232
CV233
CV234
CV235
CV236
CV237
CV238
CV239
2 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1
1
1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ DR@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ DR@
2
2
1 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2
4 4

N18P(7/11)-G61A/N20P GDDR6 CHB
Size Document Number Rev
Custom 1A
A B C D E
A B C D E
GEN2 NV suggest BS_IN3,4 need also connect with BS_IN2(CSSP_FBVDD)

GEN2 gain control by VBIOS
GEN2 gain control by VBIOS No use SH_P/N need PU the same voltage as no use BS_IN
For OVRM Keep ON +3V_OVRM
RV101 GEN2@ RV106 GEN2@ RV103 GEN2@ RV109 GEN2@
1
+3V_OVRM +3VS
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% RV193
0_0402_5%
SD028000080 SD028000080 SD028000080 SD028000080 GEN1@
0_0402_5%2 OVRM@ 1 RV178
2
NV Suggest RV192 2 GEN2@ 1 0_0402_5% CSSP_FBVDD
1
CV272
CSSP_B+ 75K_0402_1%1 GEN1@ 2 RV101 PFM_CH1_BS_IN1 0.1U_0201_10V6K 100_0402_1%1 GEN1@ 2 RV103 CSSP_B+
NV Suggest OVRM@ CSSP_B+ <104>
1
1 2 CV273 1
1000P_0402_50V7K 1 2 CV271 1 RV104 2 680P_0402_50V7K
1
ON_GEN1@ GEN2@
2K_0402_5%
RV110
GEN1@
2K_0402_5%
RV111
GEN1@
2K_0402_5%
RV112
GEN1@
2K_0402_5%
RV113
GEN1@
GEN1@ 649_0402_1%
0_0402_5%2 OVRM@ 1 RV105 CSSN_B+
CSSN_B+ <104>
CSSP_FBVDD 75K_0402_1%1 GEN1@ 2 RV106 PFM_CH1_BS_IN2
2
PFM_CH1_SH_IN_P3
100_0402_1%1 GEN1@ 2 RV109 CSSP_FBVDD PFM_CH1_SH_IN_N3
1000P_0402_50V7K 1 2 CV274 1 RV108 2 CSSP_FBVDD <104> SNN_PFM_CH1_SH_IN_P4
ON_GEN1@ CV275 SNN_PFM_CH1_SH_IN_N4
1
GEN1@ 649_0402_1% 680P_0402_50V7K
1
RV114 GEN2@ RV110 GEN2@ RV111 GEN2@ RV112 GEN2@ RV113 GEN2@
@ 0_0402_5% RV115
2
@ 0_0402_5%
UPI-Semi suggest pop CV274/CV271 when GEN2 0_0402_5%2 OVRM@ 1 RV116 CSSN_FBVDD
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
2
Keep NV suggest to unpop when GEN2. CSSN_FBVDD <104>
2
UV20 SD028000080 SD028000080 SD028000080 SD028000080
3 27
6 BS_IN1 VCC
PFM_CH1_BS_IN3 11 BS_IN2 2 PFM_CH1_SH_IN_P1
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 1 PFM_CH1_SH_IN_N1
BS_IN4 SH_IN_N1 5 PFM_CH1_SH_IN_P2
SH_IN_P2 4 PFM_CH1_SH_IN_N2
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 ADC_IN_N <33>
0_0402_5%1 GEN2@ 2 RV118 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4 ADC_IN_P <33>
RV122 1 2 475_0402_1% ON_GEN1@ SH_O1 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4 OVRM@
RV123 1 2 475_0402_1% ON_GEN1@ IMON1 7 SH_O1 SH_IN_N4 ADC_IN_P RV125 1 @ 2 0_0201_5% CV276 1 2 47P_0402_50V8J
SH_O3 SH_O2 2
RV124 1 2 169_0402_1% @ 10 20
RV126 1 2 169_0402_1% @ BG_REF_OUT 17 SH_O3 DIFF_OUT_P 19 @ CV308
SH_O4 DIFF_OUT_N ADC_IN_N 47P_0402_50V8J RV127 1 @ 2 0_0201_5% CV277 1 2 47P_0402_50V8J
30 PFM_PF_BSOK_R 1
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
RV128 BS_OK OVRM@

RV123 uPI_GEN2@ 1 @ 2 PFM_ADC_MUX_SEL_R 29 8 IMON2
1 1 1 1 MUX_SEL NC BV_REF
18 1 GEN2@ 2 0_0201_5%
GEN1@
GEN1@
RV130
NC 21 ADSR0
CV278
CV279
CV280
CV281
@ @ 0_0201_5%
PFM_ADC_FILTER_EN 28 NC 31 SYNC TH1
2 0_0402_5% 2 2 2 2 ENABLE NC 2
SD028000080 ON_GEN1@
2
23 PFM_BG_REF_OUT 1 GEN1@ 2 0_0201_5% 243K_0402_1% 1 2 RV132 10K_0402_1% 1 OVRM@ 2 RV133
NV Suggest no use IMON PIN PFM_SKIP_R BG_REF_OUT PFM_BS_REF
RV131
PFM_BS_REF_R
25 24 RV134 1 GEN1@ 2 0_0201_5% RV196
uPI PD GND SKIP BS_REF 22 0_0201_5%
ON NC Floating CM_REF_IN 365K_0402_1% 1 GEN1@ 2 RV135 681K_0402_1% 2 GEN1@ 1 RV136 uPI_GEN2@
PFM_ADC_FILTER_MODE 26 33
1
MODE_SEL GND PFM_CM_REF_IN 1 2 PFM_CM_REF_IN_R
RV194 GEN1@ 0_0402_5%
PFM_BG_REF_OUT_R BG_REF_OUT
NV Suggest no use IMON PIN
NCP45492XMNTWG_QFN32_4X4 RV139 1 @ 2 0_0201_5%
<33> GPIO22_ADC_MUX_SEL ON_GEN1@
uPI PD GND
SA0000CQX00 ON NC Floating
1000P_0402_50V7K
CV309
1 1 1
1000P_0402_50V7K
CV283
GEN1@
1000P_0402_50V7K
CV284
OVRM@
@ RV132 GEN2@
NV Suggest reserve and not pop
2 2 2 1
CV285
31.6K_0402_1% OVRM@ 1000P_0402_50V7K
+3V_OVRM
SD034316280 2
NV Suggest
1
RV141
10K_0201_5%
@
2
UV20 ON_GEN2@ UV20 uPI_GEN2@

PFM_ADC_FILTER_EN
S IC NCP45495XMNTWG QFN 32P MONITOR S IC US5651AQKI WQFN 32P POWER MONITOR

1
+3V_OVRM +3V_OVRM
RV145 SA0000DUX00 SA0000DY100
10K_0201_5%
OVRM@
1
2
RV148 RV147
10K_0201_5% 10K_0201_5%
GEN2@ @
3 3
2
ADSR0 PFM_CM_REF_IN
NV Suggest 1
1
+3V_OVRM UV20 uPI_GEN1@
RV149 RV150
10K_0201_5% 10K_0201_5%
+3V_OVRM RV152 GEN2@ S IC US5650QQKI WQFN 32P POWER MONITOR @ GEN2@
SA0000CMA00
2
2
1
RV152 10K_0402_1% Pin23 : I2C_CLK(PFM_BG_REF_OUT)

1
1K_0402_1% SD034100280 RV104 uPI_GEN1@ RV122 uPI_GEN1@ RV132 uPI_GEN1@

RV151
10K_0201_5%
GEN1@ Pin24 : I2C_DATA(PFM_BS_REF)
ADSRO(Pin21) ADSR1(Pin22,PFM_CM_REF_IN)
2
@ 487_0402_1% 357_0402_1% 324K_0402_1%

SD00000EL80 SD034357080 SD034324380
2
PFM_SKIP_R
PFM_ADC_FILTER_MODE RV108 uPI_GEN1@ RV123 uPI_GEN1@
1
1
RV199 487_0402_1% 357_0402_1%

RV156 30.1K_0402_1% RV200 1 GEN2@ 2 0_0201_5% PFM_BG_REF_OUT
SD00000EL80 SD034357080 +3V_OVRM <33> VGA_I2CC_SCL
10K_0201_5% @
@ RV201 1 GEN2@ 2 0_0201_5% PFM_BS_REF
<33> VGA_I2CC_SDA
2
2
RV159 RV203 1 @ 2 0_0201_5%

<33,103> VGA_I2CC_SCL_PWR
10K_0402_1%
OVRM@ RV202 1 @ 2 0_0201_5%
<33,103> VGA_I2CC_SDA_PWR
2
PFM_PF_BSOK_R
1
4 4
RV198
24.9K_0402_1% Follow NV CRB, OVRM/PWR IC use same I2C power rail.
ON_GEN2@
2
1
CV306
1U_0201_6.3V6M
ON_GEN2@
2
N18P(10/11)-G61A/N20P OVR-M
ON-SEMI Suggest need add RC filter. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom GH51M M/B LA-K861P 1A
A B C D E
5 4 3 2 1
+1.8VSDGPU_AON +1.8VSDGPU_MAIN
RV177 1 N20P@ 2 0_0805_5%
+1.8V_AON/+3VSDGPU
D
+1.8VSDGPU_AON
+1.8V_MAIN D
+1.8VALW UV11 +1.8VALW +1.8VSDGPU_MAIN

1 14 RV176 1 N18PA@2 0_0603_5%
VIN1 VOUT1 UV12
2 13
VIN1 VOUT1 1
1V8_AON_EN VIN1
10U_0402_6.3V6M
3 12 CV295 1 2 1 1 2
<33> 1V8_AON_EN +5VALW ON1 CT1 VIN2
CV297
220P_0402_50V7K VGA@ VGA@ CV296
4 11 1U_0201_6.3V6M 7 6
VBIAS GND VIN thermal VOUT
3VSDGPU_EN 2 2
10U_0402_6.3V6M
0.1U_0201_10V6K
CV299
5 10 CV300 1 2 +5VALW 3 1 1
<33,39> 3VSDGPU_EN ON2 CT2 +3VSDGPU VBIAS
VGA@
CV298
220P_0402_50V7K VGA@
+3VS 6 9 RV190 1 N18PA@ 2 0_0402_5% MAIN_AON_EN 4 5
1 VIN2 VOUT2 <33> 1.8VSDGPU_MAIN_EN3V3 ON GND
CV301 7 8
VIN2 VOUT2 2 2
0.1U_0201_10V6K
CV303
0.1U_0201_10V6K
CV304
0.1U_0201_10V6K
1V8_AON_EN
10U_0402_6.3V6M
VGA@
VGA@
VGA@ 15 1 RV191 1 N20P@ 2 0_0402_5% 1 1 AOZ1334DI-01_DFN8-7_3X3
2 +1.8VALW GPAD
CV302
VGA@
EM5209VF_DFN14_2X3
SA000070V00
VGA@
VGA@ @
2 2 2
22U_0603_6.3V6M
VGA@
RV175 @
CV305
1M_0402_5% VGA@
2 1 1V8_AON_EN
2
RV162 @
1M_0402_5%
2 1 3VSDGPU_EN
C +1.8VSDGPU_AON
check NV +FP_FUSE_GPU C
RV173 2 N20P@ 1 0_0402_5%

1
CV294
UV14
2.2U_0402_6.3V6M
N18PA@ 1
2 2 VIN1
VIN2 12mils
+5VALW 7 6
VIN thermal VOUT
1
3 1
VBIAS CV293 RV174
4 5 2.2U_0402_6.3V6M 2.21K_0402_1%
<33> GPIO26_FP_FUSE ON GND N18PA@ N18PA@
2
1
2
2
@ AOZ1334DI-01_DFN8-7_3X3
10K_0201_5%
RV172
CV292 N18PA@
0.1U_0201_10V6K SA000070V00
N18PA@ 2
1
B B
+3VSDGPU
+PEX_VDD
2
+FBVDDQ
2
+5VS VGA@ VGA@

RV164 +5VS RV166 +NVVDD1
1_0603_5% 20_0402_5%
2
2
VGA@ VGA@
1
2
RV163 VGA@ +5VS RV168 +5VS
1
100K_0402_5% RV165 20_0402_5% VGA@

100K_0402_5% RV170
6
2
D VGA@ VGA@ 1_0603_5%
1
1
6
3VSDGPU_EN# 2 D RV167 RV169

1
1
G PEX_VDD_EN# 2 100K_0402_5% 100K_0402_5%
G
6
S D D
1
1
3
D QV2A S FBVDDQ_EN# 2 NVVDD1_EN# 2

1
3
3VSDGPU_EN 5 D QV3A G G
2N7002KDW_SOT363-6
3
3
G VGA@ 5 2N7002KDW_SOT363-6 D D
<33,110> PEX_VDD_EN G VGA@ 5 S 5 S
<33,108> FBVDDQ_EN <33,103> NVVDD1_EN
1
S G QV4A G QV5A
4
QV2B S 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6

4
2N7002KDW_SOT363-6 QV3B S VGA@ S VGA@

4
4
VGA@ 2N7002KDW_SOT363-6 QV4B QV5B
VGA@ 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
VGA@ VGA@
A A

N18P(11/11)G61A/N20P-DC INTERFACE
5 4 3 2 1
A B C D E
20191014
LCD POWER CIRCUIT - Change to +19VB
SM01000EJ00 3000ma
+3VS +LCDVDD +19VB 220ohm@100mhz DCR
0.04 +INVPW R_B+
UX1 W=60mils
5
IN OUT
1 EMI@ W=60mils Place closed to JEDP1 LED PANEL Conn.
LX1
+LCDVDD
10U_0402_6.3V6M
CX3
0.1U_0201_10V6K
CX4
2 1 1 @ HCB2012KF-221T30_0805
GND +3VS +INVPW R_B+
1U_0201_6.3V6M
CX2
1 1 2 W=60mils CONN@ JEDP1

4 3 W=60mils 1
<17> PCH_ENVDD EN OC 1
0.1U_0201_10V6K
CX7
1 1 2
0.1U_0201_10V6K
2 2 2
CX8
10U_0402_6.3V6M
CX1
SY6288C20AAC_SOT23-5 XEMI@ EMI@ 1 1 @ 1 3
3
1
2 CX5 CX6 4
1 1
68P_0402_50V8J 1000P_0402_50V7K 5 4
RX1 2 2 PCH_BKL_PW M 6 5
100K_0402_5% 2 2 2 BKOFF# 7 6
+LCDVDD EDP_HPD_R 8 7
2
9 8
10 9
11 10
PANEL_OD_EN 12 11
<19> PANEL_OD_EN 12
13
EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
LCD enable signal <6> EDP_AUXN
<6> EDP_AUXP
EDP_AUXP CX19 1 2 0.1U_0201_10V6K EDP_AUXP_C 15
16
14
15
PCH_BKL_PW M RX10 1 @ 2 100K_0402_5% EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
<17> PCH_BKL_PW M <6> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
1 2 0.1U_0201_10V6K 18
<6> EDP_TXN0 18
@ RX3 XESD@ 19
0_0402_5% CX9 1 2 220P_0402_50V8J EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20 19
EDP_HPD_R <6> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
<16> EDP_HPD 1 2 1 2 0.1U_0201_10V6K 21
<6> EDP_TXN1 21
XESD@ 22
BKOFF# CX10 1 2 220P_0402_50V8J EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
<58> BKOFF# <6> EDP_TXP2 23
1
EDP_TXN2 CX16 1 2 0.1U_0201_10V6K EDP_TXN2_C 24

<6> EDP_TXN2 I2C_TS_INT#_3VS 24
25
RX4 RX5 1 @ 2 10K_0402_5% EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
<6> EDP_TXP3 EDP_TXN3 CX18 EDP_TXN3_C 26
100K_0402_5% 1 2 0.1U_0201_10V6K 27
<6> EDP_TXN3 I2C_TS_RST#_3VS 27
20191014 28
2
- CX0/CX10 change to SE082221J80 I2C_SCL_TS_3VS 29 28

I2C_SDA_TS_3VS 30 29
31 30
32 31
Touch +TS_PW R 32
2
Screen 33 2
Panel OD USB/I2C Touch Screen Co-Lay +5VS
+3VS
TS_I2C@
+TS_PW R
<19,59> TS_EN
TS_EN 34
35
33
34 41
+1.8VS +3VS USB20_N5_CAMERA 35 GND
RX6 1 2 0_0603_5% 36 42
+LCDVDD USB20_P5_CAMERA 37 36 GND 43
For 37 GND
TS_USB@ Camera 38 44
RX7 1 2 0_0603_5% DMIC_CLK_R 39 38 GND 45
<56> DMIC_CLK_R 39 GND
1
DMIC_DATA_R 40 46
<56> DMIC_DATA_R 40 GND
@
RX11 ACES_50203-04001-002
133K_0402_1% USB20_P6 TS_USB@ RX13 1 2 0_0402_5% I2C_SCL_TS_3VS QV18A TS_I2C@ DMIC_CLK_R
<14> USB20_P6
5
USB20_N6 TS_USB@ RX19 1 2 0_0402_5% I2C_SDA_TS_3VS PJT138KA 2N SOT363-6
<14> USB20_N6 SP010014B10
2
PANEL_OD_EN DMIC_DATA_R
G
I2C_SCL_TS 4 3 I2C_SCL_TS_3VS
<19> I2C_SCL_TS
2
S
D
1
@ +3VS XESD@
RX12 DX1
10K_0402_5% RX302 1 TS_I2C@2 1K_0402_5% I2C_SCL_TS_3VS QV18B TS_I2C@ YSLC05CH_SOT23-3
2
RX303 1 TS_I2C@2 1K_0402_5% I2C_SDA_TS_3VS PJT138KA 2N SOT363-6
2
RX304 1 TS_I2C@2 100K_0402_5% I2C_TS_INT#_3VS
G
RX306 1 TS_I2C@2 100K_0402_5% I2C_TS_RST#_3VS I2C_SDA_TS 1 6 I2C_SDA_TS_3VS
<19> I2C_SDA_TS
1
20190506
- RX11 change to unpop
- BIOS needs to detect panel +1.8VS
to select H or L .
3 3
QV19A TS_I2C@
PJT138KA 2N SOT363-6 5
+1.8VS PCH Side
G
I2C_TS_INT# 4 3 I2C_TS_INT#_3VS
<15> I2C_TS_INT#
S
1
RH307 1 2 2.2K_0402_5% I2C_SCL_TS TS_USB@
RX25
RH308 1 2 2.2K_0402_5% I2C_SDA_TS QV19B TS_I2C@ 0_0402_5%
2
PJT138KA 2N SOT363-6
2
RH309 1 2 2.2K_0402_5% I2C_TS_INT#
G
I2C_TS_RST# 1 6 I2C_TS_RST#_3VS
<15> I2C_TS_RST#
S
near JEDP1
1
RX305 1 2 100K_0402_5% I2C_TS_RST# TS_USB@
RX24
0_0402_5%
near JEDP1
CAMERA
4 USB20_N5 USB20_N5_CAMERA 4
RX8 1 @ 2 0_0402_5%
<14> USB20_N5
USB20_P5 RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<14> USB20_P5

eDP CONN.
A B C D E
A B C D E
+3VS_DP DP@ +3VALW +3VS_DP

CVD1 W=40mils
0.1U_0201_10V6K UVD2
2 1 5 1
DP@ @ DP@ DP@ DP@ DP@ IN OUT
10U_0402_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CVD19
DP@
1 1 1 1 1 1 2 1
GND
CVD2
CVD3
CVD4
CVD5
CVD6
CVD7
SUSP# 4 3
<58,68,78,85,89,92> SUSP# EN OC
DP@ UVD1
2 2 2 2 2 2 1 35 SY6288C20AAC_SOT23-5 2
VCC EQ1 TH42 TP@
6 38 TH40 TP@ DP@
20 VCC EQ0
VCC I2C_EN_TBT
0921 change souce to +3VALW, CTRL to SUSP#
1 28 17 1
VCC I2C_EN
2 DPEQ1_TBT +3VS +3VS
DP@ CVD20 2 1 .1U_0402_16V7K DP0_TXP0_C 9 DPEQ1 14 DPEQ0_A1_TBT +3VS_DP
<32> DP0_TXP0 DP0_TXN0_C DP0p DPEQ0/A1
DP@ CVD21 2 1 .1U_0402_16V7K 10
<32> DP0_TXN0 DP0n
2
3 TH45 TP@ DP@ QVD1
SSEQ1
1
DP@ CVD22 2 1 .1U_0402_16V7K DP0_TXP1_C 12 11 A0_TBT RVD6 2
<32> DP0_TXP1 DP0_TXN1_C DP1p SSEQ0/A0 Gate
DP@ CVD23 2 1 .1U_0402_16V7K 13 DP@ 1M_0402_5%
<32> DP0_TXN1 DP1n DP0_HPD
RVD1 1
DP@ CVD24 2 1 .1U_0402_16V7K DP0_TXP2_C 15 21 FLIP_TBT_CLK 100K_0402_5% Drain
<32> DP0_TXP2
1
DP@ CVD25 2 1 .1U_0402_16V7K DP0_TXN2_C 16 DP2p FLIP/SCL 3
<32> DP0_TXN2 <16,33> DP0_HPD_PCH
2
DP2n Source
2
22 CTL0_TBT_SDA GPU_DP_AUXN_C DP@
DP@ CVD26 2 1 .1U_0402_16V7K DP0_TXP3_C 18 CTL0/SDA GPU_DP_AUXP_C LBSS139W T1G_SC70-3 RVD7
<32>
<32>
DP0_TXP3
DP0_TXN3
DP@ CVD27 2 1 .1U_0402_16V7K DP0_TXN3_C 19 DP3p
DP3n CTL1
23 CTL1_TBT_HPDIN
To APU 100K_0402_5%
1
DP@ Intel/AMD naming
1
DP0_RD_TXN3 31 34 DP0_RD_TXN2 RVD2
DP0_RD_TXP3 30 RX1n TX1n 33 DP0_RD_TXP2 100K_0402_5%
RX1p TX1p
2
DP0_RD_TXN0 39 37 DP0_RD_TXP1
DP0_RD_TXP0 40 RX2n
RX2p
TX2p
TX2n
36 DP0_RD_TXN1 +3VS_DP W=40mils
CONN@ JDP1
8 5 20
RVD3 1 DP@ 2 4.7K_0402_5% 7 SSTXp SSRXp 4 19 DP_PWR
+3VS_DP SSTXn SSRXn DP0_AUXN_C_SW GND
18
DP0_RD_TXN2 DP@ CVD8 2 1 .1U_0402_16V7K DP0_RD_TXN2_C 17 AUX_CH-
RVD4 1 @ 2 4.7K_0402_5% 29 27 DP0_AUXP_C_SW 16 LAN2-
RESVD1 SBU1 TH43 TP@ AUX_CH+
32 26 DP0_RD_TXP2 DP@ CVD9 2 1 .1U_0402_16V7K DP0_RD_TXP2_C 15
RESVD2 SBU2 TH44 TP@ LAN2+
2 14 2
24 GPU_DP_AUXP_C 13 GND
DP0_HPD 1 @ 2 GPU_DP_HPD_RD 41 AUXp 25 GPU_DP_AUXN_C DP0_RD_TXN3 DP@ CVD102 1 .1U_0402_16V7K DP0_RD_TXN3_C 12 GND
RVD5 0_0402_5% PAD AUXn DP0_RD_TXN1 DP@ CVD112 1 .1U_0402_16V7K DP0_RD_TXN1_C 11 LAN3- 21
DP0_RD_TXP3 DP@ CVD122 1 .1U_0402_16V7K DP0_RD_TXP3_C 10 LAN1- GND 22
TUSB546_QFN40_4X6 LAN3+ GND
1
DP0_RD_TXP1 DP@ CVD132 1 .1U_0402_16V7K DP0_RD_TXP1_C 9 23

8 LAN1+ GND 24
@ DP@ RVD9 1 2 1M_0402_5% 7 GND GND
RVD8 DP_CA_DET 6 GND
100K_0402_5% DP0_RD_TXN0 DP@ CVD142 1 .1U_0402_16V7K DP0_RD_TXN0_C 5 CA_DET
2
4 LAN0-
DP0_RD_TXP0 2 1 DP0_RD_TXP0_C 3 CFG1
DP@ CVD15 .1U_0402_16V7K DP0_HPD 2 LAN0+
+3VS_DP +3VS_DP +3VS_DP 1 HP_DET
20190924 Vender GND
1
I2C_EN_TBT RVD10 1 @ 2 1K_0402_5% A0_TBT RVD11 1 @ 2 1K_0402_5% CTL0_TBT_SDA RVD12 1 @ 2 1K_0402_5% SDAN_613007-020231
1 DP@ 2 1K_0402_5% 1 DP@ 2 1K_0402_5% 1 DP@ 2 1K_0402_5%

DC06000AIB0
RVD13 RVD14 RVD15 RVD16
1M_0402_5%
I2C Programming or pin strap programming select. SSEQ0,SSEQ1 : USB receiver equalizer gain DP@
2
I2C is only disable when this pin is '0' for upstream facing SSTXP/N +3VS_DP
0 : Pin Strap(I2C disable)(Default) F,F(Default)
need check pin4 CFG1
R : TI test mode(I2C enable at 3.3V) When I2C_EN is not '0' SSEQ0 sets I2C adress CTL1_TBT_HPDIN RVD17 1 DP@ 2 1K_0402_5%
F : I2C enabled at 1.8V
1 : I2C enabled at 3.3V RVD18 1 @ 2 1K_0402_5%
+3VS_DP +3VS_DP
DPEQ1_TBT RVD19 1 @ 2 1K_0402_5% FLIP_TBT_CLK RVD20 1 @ 2 1K_0402_5%

3 3
RVD21 1 DP@ 2 1K_0402_5% RVD22 1 DP@ 2 1K_0402_5%
DPEQ0,DPEQ1 : DP Receiver equalization gain

F,F(Default) INPUT/OUTPUT A
When I2C_EN is not '0' DPEQ0 sets I2C adress OE# S Function +3VSDGPU
+5VS
+3VS_DP DP@ CVD16
L L B1 A=B1 1 2
DPEQ0_A1_TBT RVD23 1 DP@ 2 1K_0402_5%
1
100K_0402_5%
DP@ RVD25
100K_0402_5%
DP@ RVD26
100K_0402_5%
DP@ RVD27
0.1U_0201_10V6K
RVD24 1 @ 2 1K_0402_5% L H B2 A=B2
DP0_AUXP 1 6 DP0_AUXP_PROT
D
<32> DP0_AUXP H X Z NC
S
2
DP@ DP@
+5VS QVD2A UV42
2N7002KDW _SOT363-6 16
Vcc DP0_AUXP_C_SW
G
4
2
1A
1
DP0_AUXP_PROT DP@ CVD17 1 2 0.1U_0201_10V6K DP0_AUXP_C 2 7 DP0_AUXN_C_SW

RVD28 DP_AUX_PROT 3 1B1 2A 9
DP0_AUXN_PROT DP@ DP0_AUXN_C 1B2 3A
100K_0402_5%
+5VS 10K_0402_5% 1 CVD18 1 2 0.1U_0201_10V6K 5 12
2B1 4A
1
DP@ DP@ 6
2B2
RVD29
C2776 11 15
2
3B1 OE
1
DP_AUX_PROT 0.01U_0201_6.3V7K 10 1 DP_CA_DET

G
RVD30 2 14 3B2 S
10K_0402_5% 13 4B1 8 0:DP
2
DP@ 4B2 GND 17 DP@
T-PAD 1:HDMI
1
C DP0_AUXN 4 3 DP0_AUXN_PROT
S
<32> DP0_AUXN
2
4 4
D
2 DP@ SN74CBT3257CRGYR_QFN16_4X3P5
B QVD3 QVD2B
E MMBT3904_SOT23-3 2N7002KDW _SOT363-6
3
DP@
1
R521 C
1 2 2
<33,37> 3VSDGPU_EN B DP@
10K_0402_5% E QVD4 2019/09/20 2020/09/20 Title
3
DP@ MMBT3904_SOT23-3
DP CONN (TUSB546)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K861P
A B C D E
A B C D E
+5VALW +1.1V_HDMI +3VS +VDD33_HDMI

+1.8VSDGPU_AON +VDDIO_HDMI +5VS W=40mils +HDMI_5V_OUT
LVH1 LVH2
CVH17 1 2 1 2
UVH3
1U_0201_6.3V6M BLM18KG331SN1D_2P BLM18KG331SN1D_2P
22P_0402_50V8J
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1
2 1
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1 1 1 1
RVH9 3
CVH27
CVH22
UVH2 3.83K_0402_1% OUT
CVH18
1
+3VS 10 1 1
CVH26
CVH28
CVH20
CVH29
CVH21
CVH23
VDD VOUT 2 1 1 2 2 2 2 2 2 2 2 IN
9 2 CVH30
CVH25
CVH19
@
2
CVH24 8 VIN VOUT 3 2 0.1U_0201_10V6K
10U_0402_6.3V6M 7 VIN VOUT 4 GND 2
2 1 6 VIN ADJ/NC 5 2 2
EN PGOOD AP2330W-7_SC59-3
1
1 11 1
PAD RVH10 +VDD11_HDMI +VDD33_HDMI
RT9059GQW_WDFN10_3X3 10K_0402_1% UVH1
SA000071S00 +VDDA11_HDMI 19 1
S IC RT9059GQW WDFN 10P LDO +VDDRX11_HDMI 41 VDD11 VDD33 13
2
25 VDD11 VDD33
+VDDTX11_HDMI 15 VDDA11
Vout = 0.8 * ((3.83K+10K)/10K) = 1.1064V VDDRX11 HDMI_RT_C_TX_P2 CVH9 HDMI_RT_L_TX_P2
46 37 1 2 0.22U_0201_6.3V6K DVH1
26 VDDRX11 OUT_D2p 36 HDMI_RT_C_TX_N2 CVH10 1 2 0.22U_0201_6.3V6K HDMI_RT_L_TX_N2 HDMI_RT_HPD 6 3 HDMI_CTRL_DAT
+VDDIO_HDMI 32 VDDTX11 OUT_D2n I/O4 I/O2
38 VDDTX11 34 HDMI_RT_C_TX_P1 CVH11 1 2 0.22U_0201_6.3V6K HDMI_RT_L_TX_P1
1.8V VDDTX11 OUT_D1p
+1.1V_HDMI +VDD11_HDMI 43 33 HDMI_RT_C_TX_N1 CVH12 1 2 0.22U_0201_6.3V6K HDMI_RT_L_TX_N1
VDDIO OUT_D1n 5 2
LVH3 CVH1 1 2 0.22U_0201_6.3V6K HDMI_TX_P2 2 31 HDMI_RT_C_TX_P0 CVH13 1 2 0.22U_0201_6.3V6K HDMI_RT_L_TX_P0 VDD GND
<32> GPU_HDMI_P2 HDMI_TX_N2 IN_D2p OUT_D0p HDMI_RT_C_TX_N0 CVH14 HDMI_RT_L_TX_N0
1 2 CVH2 1 2 0.22U_0201_6.3V6K 3 30 1 2 0.22U_0201_6.3V6K
<32> GPU_HDMI_N2 IN_D2n OUT_D0n
BLM18KG331SN1D_2P +HDMI_5V_OUT
CVH3 1 2 0.22U_0201_6.3V6K HDMI_TX_P1 5 28 HDMI_RT_C_CLKP CVH15 1 2 0.22U_0201_6.3V6K HDMI_RT_L_CLKP HDMI_CTRL_CLK 4 1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
4.7U_0402_6.3V6M
<32> GPU_HDMI_P1 HDMI_TX_N1 IN_D1p OUT_CLKp HDMI_RT_C_CLKN HDMI_RT_L_CLKN I/O3 I/O1

1 1 1 1 1 CVH4 1 2 0.22U_0201_6.3V6K 6 27 CVH16 1 2 0.22U_0201_6.3V6K
<32> GPU_HDMI_N1 IN_D1n OUT_CLKn AZC099-04S.R7G_SOT23-6
CVH5 1 2 0.22U_0201_6.3V6K HDMI_TX_P0 8 @ESD@ SC300001G00
CVH31
<32> GPU_HDMI_P0 HDMI_TX_N0 IN_D0p HDMI_CTRL_CLK

CVH6 1 2 0.22U_0201_6.3V6K 9 40
2 2 2 2 2 <32> GPU_HDMI_N0 IN_D0n OUT_SCL HDMI_CTRL_DAT
39
CVH32
CVH33
CVH34
CVH35
CVH7 1 2 0.22U_0201_6.3V6K HDMI_CLKP 11 OUT_SDA

<32> GPU_HDMI_CLKP HDMI_CLKN IN_CLKp
CVH8 1 2 0.22U_0201_6.3V6K 12
<32> GPU_HDMI_CLKN IN_CLKn
RVH11 1 2 0_0402_5% GPU_DP2_CTRL_CLK_R 45 42 HDMI_HPD_R RVH12 1 @ 2 1K_0402_5% HDMI_HPD
<32> GPU_HDMI_CTRL_CLK IN_SCL HPD_SRC
+VDDRX11_HDMI RVH13 1 2 0_0402_5% GPU_DP2_CTRL_DAT_R 44 29 HDMI_RT_HPD RVH40 1 2 0_0402_5% DVH2 @ESD@
<32> GPU_HDMI_CTRL_DAT IN_SDA HPD_SNK HDMI_RT_CLKN HDMI_RT_CLKN
LVH4 1 9
1 2
BLM18KG331SN1D_2P HDMI_DCIN 7 20 HDMI_ISNK PD HDMI_RT_CLKP 2 8 HDMI_RT_CLKP
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
3V3 or 1V8 HDMI_EQ 16 DC_IN ISNK 35 HDMI_PD RVH14 1 2 4.7K_0402_5% L: Normal Operation
1 1 1 1 1 HDMI_I2C_ADDR EQ PD HDMI_REXT RVH15 H: Chip power-down HDMI_RT_TX_N0 HDMI_RT_TX_N0
4 14 1 2 4.99K_0402_1% 4 7
I2C_ADDR REXT
2 Placed close to REXT pin. HDMI_RT_TX_P0 5 6 HDMI_RT_TX_P0 2
2 2 2 2 2 21 18 HDMI_CSCL TH46 @
CVH36
CVH37
CVH38
CVH39
CVH40
RVH41 2 1 1K_0402_5% HDMI_CFG1 22 CFG0 CSCL 17 HDMI_CSDA TH47 @

23 CFG1 CSDA
RVH16 1 2 4.7K_0402_5% HDMI_CFG3 24 CFG2 3
+VDDA11_HDMI +VDD33_HDMI CFG3
10 47
LVH5 CFG4 EPAD TVWDF1004AD0_DFN9
1 2 EMI Reserve for 8K
BLM18KG331SN1D_2P
SC300003Z00
0.1U_0201_10V6K
0.01U_0402_16V7K
4.7U_0402_6.3V6M
1 1 1
PS8419GTR-A1_QFN46_4P5X6P5
DVH3 @ESD@
HDMI_RT_L_CLKP RVH32 1 2 0_0201_5% HDMI_RT_CLKP HDMI_RT_TX_N1 1 9 HDMI_RT_TX_N1
2 2 2
CVH41
CVH42
CVH43
HDMI_RT_TX_P1 2 8 HDMI_RT_TX_P1
LVH10 @EMI@
+3VS +3VS 3 4 HDMI_RT_TX_N2 4 7 HDMI_RT_TX_N2
+VDDTX11_HDMI HDP Detect SM070007300
LVH6 DLM0NSN900HY2D_4P HDMI_RT_TX_P2 5 6 HDMI_RT_TX_P2
2
1 2 2 1
BLM18KG331SN1D_2P
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 1 1 1 1 1 1 RVH19 S COM FI_ PANASONIC EXC14CH900U

2
1M_0402_5% 3
G
QVH1A HDMI_RT_L_CLKN RVH33 1 2 0_0201_5% HDMI_RT_CLKN

1
2N7002KDW_SOT363-6 TVWDF1004AD0_DFN9
2 2 2 2 2 2 2
CVH44
CVH45
CVH46
CVH47
CVH48
CVH49
CVH50
1 6 HDMI_HPD SC300003Z00
S
<16,33> HDMI_HPD_PCH
D
HDMI_RT_L_TX_P2 RVH34 1 2 0_0201_5% HDMI_RT_TX_P2

2
Intel/AMD naming RVH24 1 2

0_0402_5% @ RVH26
100K_0402_5% LVH11 @EMI@
RY11 design guide rev2.0 3 4 +HDMI_5V_OUT
3 +3VS +3VS use 20K pull down. SM070007300 3
1
DLM0NSN900HY2D_4P
3
D 2 1 HDMI_CTRL_DAT RVH17 1 2 2K_0402_1%

2 RVH22 1
5 QVH1B HDMI_CTRL_CLK RVH18 1 2 2K_0402_1% +1.8VSDGPU_AON

20K_0402_1%
+3VS G
@ @ 2N7002KDW_SOT363-6 S COM FI_ PANASONIC EXC14CH900U
RVH25 GPU_HDMI_CTRL_CLK RVH20 1 @ 2 2.2K_0402_5%
4.7K_0402_5% S HDMI_RT_L_TX_N2 RVH35 1 2 0_0201_5% HDMI_RT_TX_N2 GPU_HDMI_CTRL_DAT RVH21 1 @ 2 2.2K_0402_5%
4
2
HDMI_EQ HDMI_I2C_ADDR
2 RVH27 1
HDMI_RT_L_TX_P1 RVH36 1 2 0_0201_5% HDMI_RT_TX_P1

1K_0402_5%
EQ
L0: Pull down with 1k, EQ=8dB @ RVH29 HDMI_RT_L_TX_N0 RVH1 1 2 649_0201_1% +HDMI_5V_OUT HDMI connector
L1: Pull down with 20k EQ=7dB HDMI_RT_L_TX_P0
L2: Floating 4.7K_0402_5% RVH2 1 2 649_0201_1% LVH12 @EMI@ CONN@
EQ=5dB HDMI_RT_L_TX_N1 RVH3 1 2 649_0201_1% 3 4 JHDMI1
2
L3: Pull up with 20k HDMI_RT_L_TX_P1 RVH4 1 2 649_0201_1% SM070007300 HDMI_RT_HPD 19

EQ=3dB HDMI_RT_L_TX_N2 RVH5 1 2 649_0201_1% DLM0NSN900HY2D_4P 18 HP_DET
L4:Pull up with 1k HDMI_RT_L_TX_P2 +5V
EQ=1dB RVH6 1 2 649_0201_1% 2 1 17
HDMI_RT_L_CLKN RVH7 1 2 649_0201_1% HDMI_CTRL_DAT 16 DDC/CEC_GND
HDMI_ISNK
I2C ADDR HDMI_RT_L_CLKP RVH8 1 2 649_0201_1% S COM FI_ PANASONIC EXC14CH900U HDMI_CTRL_CLK 15 SDA
L: 0x10 - 0x2F (Default) 14 SCL
M: 0x30 - 0x4F HDMI_RT_L_TX_N1 HDMI_RT_TX_N1 Reserved
RVH37 1 2 0_0201_5% 13
0.1U_0201_10V6K
H: 0x90 - 0x9f and 0xD0 - 0xDF CEC

HDMI_RT_CLKN 12 20
+3VS 11 CK- GND 21
HDMI_RT_CLKP 10 CK_shield GND 22
CVH51
1 HDMI_RT_L_TX_P0 HDMI_RT_TX_P0 HDMI_RT_TX_N0 CK+ GND

+1.8VSDGPU_AON RVH38 1 2 0_0201_5% 9 23
D0- GND
1
8
HDMI_RT_TX_P0 7 D0_shield
@ RVH30 3ohm/10pF 2 LVH13 @EMI@ HDMI_RT_TX_N1 6 D0+
4.7K_0402_5% 3 4 5 D1-
SM070007300 HDMI_RT_TX_P1 4 D1_shield
2
D1+
5
HDMI_DCIN QVH2A @ DLM0NSN900HY2D_4P HDMI_RT_TX_N2 3

2 1 2 D2-
G
D2_shield
1
4 GPU_HDMI_CTRL_CLK HDMI_CTRL_CLK HDMI_RT_TX_P2 4

DC IN 4 3 1
D2+
S
L: TMDS input is AC Coupled S COM FI_ PANASONIC EXC14CH900U

H: TMDS input is DC Coupled RVH31 PJT138KA_SOT363-6 ACON_HMR2E-AK120D
4.7K_0402_5% HDMI_RT_L_TX_N0 RVH39 1 2 0_0201_5% HDMI_RT_TX_N0
DC232000Y00
2
@
2
GPU_HDMI_CTRL_DAT 1 6 HDMI_CTRL_DAT
S
QVH2B
PJT138KA_SOT363-6
HDMI CONN.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PS8419
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
20191014
- Change to "with no Dual Role support"
- 5441E only uses the function of CC & Power SW
D D
+5VALW +5VALW _MUX
US14
5 1
IN OUT
10U_0402_6.3V6M
0.1U_0201_10V6K
2 1 1
GND
CS116
CS15
4 3
<58> USB_TYPEC_EN EN OC
SY6288C20AAC_SOT23-5 2 2
Close to Pin19
US3
VMON 17 12 CC1_VCONN
VMON CC1 CC2_VCONN CC1_VCONN <43>
14 CC2_VCONN <43>
OCP_DET# 16 CC2
<43> OCP_DET# OCP_DET
USBC_EN 15
C <43> USBC_EN VBUS_EN Type-C Port Side C
+3VO_MUX +3VO_MUX 11
System side C_TX2_1P/2N 10
C_TX2_1N/2P
4 CC1_VCONN CS130 1 2 220P_0402_50V8J
5 SSRX_1P/2N 24 CC2_VCONN CS129 1 2 220P_0402_50V8J
SSRX_1N/2P C_RX2_1P/2N
1
1
C_RX2_1N/2P
1
RS1 RS3
RS114 @ 10K_0402_5% 10K_0402_5% 6 10 Gbps 2:1 MUX 8
10K_0402_5% 7 SSTX_1P/2N C_TX1_1P/2N 9
2
SSTX_1N/2P C_TX1_1N/2P
2
PLUG_ORI M1 M0 1 @ 2
TYPEC_1P5A_EC <43,58>
RS137 0_0402_5% 2
C_RX1_1P/2N
1
3
PLUG_ORI 23 C_RX1_1N/2P
RS115 RS2 @ RS4 @ M1 21 GPIO
10K_0402_5% 10K_0402_5% 10K_0402_5% M0 22 CURRENT_M1
CURRENT_M0
2
VCON_IN
LDO_3V3
18
REXT
5V_IN
1
RS129 25
6.2K_0402_1% E-PAD
RTS5441E-GRT_QFN24_4X4
20
19
13
+5VALW _MUX +USB3_VCCC
SA0000C3L00
2
B +3VO_MUX +5VALW _MUX B
1
RS20 RS134 1 1
4.7K_0402_5% 200K_0402_1% CS14 CS117
4.7U_0402_6.3V6M 0.1U_0201_10V6K
2
OCP_DET# VMON 2 2
Close to Pin13
1
RS135
RS128 10K_0402_1%
10K_0402_5%
2
A A
5441E Current Limit confirm realtek hand-shake

M1 M0 MODE RTS5441 M0 truth table by 2018 BIOS spec
limit point
L H 0.9A TYPEC_1P5A_EC MODE Condition
H 3A 3.5A AC mode or Battery >30%
H L 1.5A
CC+USB TYPE C
L 1.5A 1.92A Battery <30% when DC mode Size Document Number Rev
H H 3A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
USB3_PTX_DRX_P3 CS112 1 2 0.33U_0201_6.3V6M USB3_CC_TX_P3_C +5VALW +USB3_VCCC

<17> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3
<17> USB3_PTX_DRX_N3 CS113 1 2 0.33U_0201_6.3V6M USB3_CC_TX_N3_C
USB3_CC_RX_P3_C
USB3_CC_RX_N3_C
SGA00003700
150U_D2_6.3VY_R15M
CS95
1
USB3_PRX_DTX_P3 2 0.33U_0201_6.3V6M USB3_CC_RX_P3_C
0.1U_0201_10V6K
0.1U_0402_25V6
22U_0805_25V6M
22U_0805_25V6M
CS121 1 1 1 1 1
<17> USB3_PRX_DTX_P3 USB3_PRX_DTX_N3 2 0.33U_0201_6.3V6M USB3_CC_RX_N3_C
CS96
CS97 @
CS98 @
CS99 @
CS122 1 +
<17> USB3_PRX_DTX_N3
2
RS130 RS131
USB3_PTX_DRX_P4 CS114 1 2 0.33U_0201_6.3V6M USB3_CC_TX_P4_C 220K_0201_1% 220K_0201_1% 2 2 2 2 2
<17> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 CS115 1 2 0.33U_0201_6.3V6M USB3_CC_TX_N4_C US11
<17> USB3_PTX_DRX_N4
1
6 1
USB3_PRX_DTX_P4 CS123 1 2 0.33U_0201_6.3V6M USB3_CC_RX_P4_C IN OUT
D <17> USB3_PRX_DTX_P4 D
USB3_PRX_DTX_N4 CS124 1 2 0.33U_0201_6.3V6M USB3_CC_RX_N4_C
<17> USB3_PRX_DTX_N4 USB3_CC_RX_P4_C RSET 5 2
USB3_CC_RX_N4_C SET GND 1 @ 2
OCP_DET# <42>
RS136 0_0402_5%
20191014 4 3 1 @ 2
<42> USBC_EN EN FLAG USB_OC0# <14>
2
RS112 0_0402_5%
- Change to "with no Dual Role support"
1
RS132 RS133 G518B1TP1U_TSOT23-6 1 20200114
- CS112/113/114/115 change to 0.33U 220K_0201_1% 220K_0201_1% RB77 -RS112 Change to R-short
47K_0402_5% Footprint : G518 CS100
20191016 0.1U_0201_10V6K
PN : SA0000BDN00
1
2
- USB3 Port5 change to Port3
2
(SILERGY SY6861B1)
20191015 - Pin SWAP for layout RSET

20191016 For ESD request - Gen2 Solution SC300006T00
1
RS109 RS110
RS113
4.3K_0402_5% 8.2K_0402_5%
6.2K_0402_1%
3 2
DS6 ESD@
USB3_CC_TX_P4_C 1 9 USB3_CC_TX_P4_C D
5 TYPEC_3A <18>
USB3_CC_TX_N4_C 2 8 USB3_CC_TX_N4_C G
USB3_CC_RX_N3_C USB3_CC_RX_N3_C G518 MOS Current Limit

4 7 S QS2B
4
C GPP_B1 GPP_B4 RSET(kΩ ) MODE limit point 2N7002KDW _SOT363-6 C
6
USB3_CC_RX_P3_C 5 6 USB3_CC_RX_P3_C (TYPEC_1P5A) (TYPEC_3A) D
L L 6.2 0.9A 1.09A 2 TYPEC_1P5A_EC <42,58>
G
L H 3.53 1.5A 1.92A
3 S QS2A
1
H 2.54 2A 2.67A 2N7002KDW _SOT363-6
L
TVW DF1004AD0_DFN9 check bios
SC300006T00 *H H 1.94 3A 3.5A 1050 is use PCH output
DS4 ESD@
1 9
2 8
USB3_CC_TX_P3_C 4 7 USB3_CC_TX_P3_C
USB3_CC_TX_N3_C 5 6 USB3_CC_TX_N3_C
TVW DF1004AD0_DFN9 +USB3_VCCC +USB3_VCCC

SC300006T00
JUSBC1 CONN@
DS3 ESD@ A1 B12
USB3_CC_RX_N4_C 1 9 USB3_CC_RX_N4_C GND GND
USB3_CC_TX_P4_C A2 B11 USB3_CC_RX_P4_C
B USB3_CC_RX_P4_C 2 8 USB3_CC_RX_P4_C USB3_CC_TX_N4_C A3 SSTXP1 SSRXP1 B10 USB3_CC_RX_N4_C B
0.1U_0402_25V6 2 1 CS84 SSTXN1 SSRXN1
TBTA_SBU1 4 7 TBTA_SBU1 A4 B9 CS87 1 2 0.1U_0402_25V6
VBUS VBUS
1
CC1_VCONN 5 6 CC1_VCONN CS13 A5 B8 TBTA_SBU2
<42> CC1_VCONN CC1 RFU2
10U_0603_25V6M
USB20_P4_L A6 B7 USB20_N4_L
2 USB20_N4_L A7 DP1 DN2 B6 USB20_P4_L
3 DN1 DP2
3
2
TBTA_SBU1 A8 B5
RFU1 CC2 CC2_VCONN <42>
TVW DF1004AD0_DFN9 0.1U_0402_25V6
SC300006T00 2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
DS19 ESD@ VBUS VBUS
DS5 ESD@ PESD24VS2UT_SOT23-3 USB3_CC_RX_N3_C A10 B3 USB3_CC_TX_N3_C
CC2_VCONN 1 9 CC2_VCONN SCA00004500 USB3_CC_RX_P3_C A11 SSRXN2 SSTXN2 B2 USB3_CC_TX_P3_C
1
SSRXP2 SSTXP2
TBTA_SBU2 2 8 TBTA_SBU2 A12 B1
GND GND
USB20_N4_L 4 7 USB20_N4_L 1
2 GND 7
USB20_P4_L 5 6 USB20_P4_L 3 GND GND 8
4 GND GND 9
5 GND GND 10
6 GND GND
3 GND
TVW DF1004AD0_DFN9 SINGA_2UB3C02-008111F

SC300006T00 DC23300TZA0
A A
SINGA_2UB3C02-008111F_24P-T
LS10 EMI@
CC1_VCONN & CC2_VCONN need 20miil trace width.
USB20_N4 2 1 USB20_N4_L
<14> USB20_N4 2 1
USB20_P4 3 4 USB20_P4_L Security Classification Compal Secret Data Compal Electronics, Inc.
<14> USB20_P4 3 4
DLM0NSN900HY2D_4P
SM070005U00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC+USB TYPE C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
20190918
C C
LAN more to IO/B

B B
A A

LAN Killer-E2600
5 4 3 2 1
A B C D E
UART BT
Wireless LAN W AKE_BT_R
UART_W AKE#_R
PCM_CLK_R
UART_BT@
UART_BT@
UART_BT@
RM62
RM63
RM64
1
1
1
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
W AKE_BT
UART_W AKE#
PCM_CLK
W AKE_BT <19>
UART_W AKE# <18>
PCM_CLK <18>
PCM_OUT_R UART_BT@ RM65 1 2 0_0402_5% PCM_OUT
PCM_OUT <18>
+3VALW W=60mils +3VS_W LAN 20191007

UM1
- Add RM62/63/64/65
1U_0201_6.3V6M
CM15
5 1
IN OUT
1
2 Co-layout with CNVi for SW debug
@ GND
1 1
4 3
2 <58> W LAN_ON EN OC UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%
UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <19>
SY6288C20AAC_SOT23-5 RM43 1 UART@ 2 0_0402_5%
UART_2_PTXD_DRXD <19>
IOAC@
+3VALW +3VS_W LAN

20191210C [FH51M CNVi review] 20191205 [FH5VF CNVi review] +3VS_W LAN
> RM69 change to 71.5k & CNVI@ Pin10 - RM41 Close to PCH
RM44 1 @ 2 0_0805_5% > RM70 set CNVI@ Pin14 - CLKREQ_CNV# PD RM69(71.5K) (Reserve) UART_W AKE#_R RM70 1 CNVI@ 2 4.7K_0402_5%
> RH22 change to 20K Pin20 - UART_WAKE PU RM70(4.7K) (Reserve)
+3VS CLKREQ_CNV# RM69 1 CNVI@ 2 71.5K_0402_1%
reserve for cnvi > RM36/RM37/RM67/RM68 change to 22 ohm Pin22 - RM36@M.2 / RH181@PCH
RM11 1 NIOAC@ 2 0_0805_5% > RM16 recommend to 4.7K (no action) Pin32 - RM37@PCH / RH22@M.2
0.1U_0201_10V6K
> RM199 recommend to pop (no action) Pin34 - RM67@M.2 / RH182@PCH
0.1U_0201_10V6K
CM14
60mil 1 1 1 1@
CM13 @
CM12 CM19 > RM45 recommend to10K (no action) Pin36 - RM68@PCH / RH15@M.2
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
> WL_OFF# recommend to PU 10K (no action)
2 2 2 2
reserve 1000p for cnvi
KEY E +3VS_W LAN
CM18 1
@
2 1000P_0402_50V7K
+3VS_W LAN JNGFF1
1 2
GND_1 3.3VAUX_2 CNVI@
3 4 @ T52 1 RM41 2
<14> USB20_P14 USB_D+ 3.3VAUX_4
(For BT) 5 6 75K_0402_1%
<14> USB20_N14 USB_D- LED1# PCM_CLK_R
10U_0402_6.3V6M
@ CM51
0.01U_0201_6.3V7K
@ CM53
10U_0402_6.3V6M
@ CM52
0.01U_0201_6.3V7K
@ CM54
1 1 1 1 7 8
2 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 @ 2 0_0201_5% 2
<15> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC PCM_OUT_R CNV_RF_RESET# <18>
<15> CNV_PRX_DTX_P1 11 12
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 @ 2 0_0201_5%
2 2 2 2 SDIO_DAT0 PCM_IN CLKREQ_CNV# <18>
<15> CNV_PRX_DTX_N0 15 16 @ T53
17 SDIO_DAT1 LED2# 18
<15> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18 UART_W AKE#_R
19 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 22_0402_5%
<15> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <15>
23
<15> CLK_CNV_PRX_DTX_P SDIO_RST
20200114 - For CNVi 24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 22_0402_5%
- CM51/CM53 Close to JNGFF1 Pin 2,4 UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX <15>
25 26 RM67 1 CNVI@ 2 22_0402_5%
- CM52/CM54 Close to JNGFF1 Pin 64,66 GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <15>
27 28 RM68 1 CNVI@ 2 22_0402_5% CNV_BRI_PTX_DRX <15>
<17> PCIE_PTX_C_DRX_P15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM12 1 @ 2 0_0201_5%
<17> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <58>
31 32 RM13 1 @ 2 0_0201_5%
GND_39 CLink_DATA E51RXD_P80CLK <58>
(link to PICE Port 3) 33 34
NGFF WL+BT (KEY E) PCIE X1
<17> PCIE_PRX_DTX_P15
<17> PCIE_PRX_DTX_N15 35
37
PER_TX_P0
PER_TX_N0
CLink_CLK
COEX3
36
38
W AKE_BT_R
20191205
39 GND_45 COEX2 40 - RM66 Change to @ for Vender review
<15> CLK_PCIE_W LAN REFCLK_P0 COEX1 SUSCLK_R
41 42 RM66 1 @ 2 0_0402_5%
<15> CLK_PCIE_W LAN# REFCLK_N0 SUSCLK(32KHz) W L_RST#_R SUSCLK <18,68,69>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0201_5%
GND_51 PERST0# BT_ON PLT_RST_BUF# <16,68,69,73>
PCIE CLK <15> W LAN_CLKREQ# 45 46
W LAN_PME# CLKREQ0# W_DISABLE2# W L_OFF# BT_ON <16,58>
47 48
PEWAKE0# W_DISABLE1# W L_OFF# <58,59>
49 50
51 GND_57 I2C_DAT 52
<15> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
53 54
<15> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ REFCLK_CNV_R RM40
55 56 1 ESD@ 2 0_0402_5% REFCLK_CNV <15>
57 GND_63 RSVD_64 58
<15> CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
59 60
<15> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62 1
3 63 GND_69 RSVD_70 64 CM17 XESD@ 3
<15> CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72
65 66 0.1U_0201_10V6K
<15> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67
GND_75 68 2 For ESD req reserve LC filter
69 GND1 close PCH
GND2
BELLW _80152-3221
CONN@ E51TXD_P80DATA_R
SP070013E00
1
RM19
100K_0402_5%
2 1 W LAN_PME#
+3VS_W LAN
RM16 10K_0402_5%
2
<58> EC_W LAN_PME# RM73 1 @ 2 0_0201_5%
reserve for BT_ON OD pull high (1.0)
BT_ON 1 @ 2
4 +3VS_W LAN 4
8.2K_0402_5% RM45

M.2 Key E (WLAN)
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
Digital MIC
DMIC_DATA 2 1 DMIC_DATA_R
RA1 0_0402_5% DMIC_DATA_R <38>
PCH_DMIC_DATA0 2 @ 1
<18> PCH_DMIC_DATA0
RA3 33_0402_5%
PCH_DMIC_CLK0 2 @ 1
TO eDP cable
<18> PCH_DMIC_CLK0
SM01000EJ00 SM01000EJ00 RA4 33_0402_5%
0926 1004
+5VS
3000ma 220ohm@100mhz +5VS_PVDD +5VS_AVDD
3000ma 220ohm@100mhz +5VS DMIC_CLK DMIC_CLK_R
DCR 0.05 DCR 0.04 2 1
LA2 LA1 LA3 EMI@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
D 1 2 1 2 SM01000Q500 D
HCB2012KF-221T30_2P_0805 HCB2012KF-221T30_2P_0805 Change PN to SM01000Q500
20191008
1
100_0402_5%
RA2
XEMI@
10P_0402_50V8J
CA7
XEMI@
1 1 1 1 1 1 - change to unpop
1
10U_0402_6.3V6M
CA8
0.1U_0201_10V6K
CA9
10U_0402_6.3V6M
CA5
0.1U_0201_10V6K
CA3
10U_0402_6.3V6M
CA6
0.1U_0201_10V6K
CA4
1 1 1 1
10U_0402_6.3V6M
CA10
0.1U_0201_10V6K
CA11
10U_0402_6.3V6M
CA12
0.1U_0201_10V6K
CA13
2
2 2 2 2 2 2
2
2 2 2 2
near
330P_0402_50V7K
CA1
XEMI@
near near GNDA Pin40 1
Pin41 Pin46
2
+1.8VS_AVDD 1 @ 2
RA5 0_0402_5%
+1.8VS Fallow Raptor
near CA14 1 2 0.1U_0201_10V6K
Pin18 1 1
10U_0402_6.3V6M
CA15
0.1U_0201_10V6K
CA16
CA17 1 2 10U_0402_6.3V6M
1 @ 2 +3VS_DVDDIO 2 2
+3VS
RA6 0_0402_5% Headphone Out
+3VS_DVDD near
GNDA Pin20 +MIC2_VREFO_R
1 @ 2
+3VS +MIC2_VREFO_L
RA7 0_0402_5%
1
2.2K_0402_5%
RA8
1 1 1
1
10U_0402_6.3V6M
CA18
0.1U_0201_10V6K
CA19
0.1U_0201_10V6K
CA20
2.2K_0402_5%
RA10
RA9 1 @ 2 0_0402_5%
+5VALW
2
2 2 2
SLEEVE
18
41
46
40
20
33
SLEEVE <73>
2
3
UA1 HDA_BITCLK_AUDIO
near RING2
DVDD-IO
PVDD1
PVDD2
AVDD1
CPVDD/AVDD2
5VSTB/AUX MODE
DVDD
Pin3 RING2 <73>
1
C C
+3VS_DVDD XEMI@
RA11
0_0402_5% HPOUT_R 1 2 HPOUT_R_1
LINE1_L HPOUT_R_1 <73>
36 RA16 47_0402_5%
2
LINE1-L(PORT-C-L)
1
LINE1_R 35 HPOUT_L 1 2 HPOUT_L_1

LINE1-R(PORT-C-R) HPOUT_L_1 <73>
1 RA17 47_0402_5%
RA42 @ XEMI@
10K_0402_5% RING2 30 43 SPKL- CA23
SLEEVE 31 MIC2-L(PORT-F-L) /RING2 SPK-OUT-L- 42 SPKL+ 22P_0402_50V8J LINE1_R CA28 1 2 4.7U_0402_6.3V6M
2
MIC2-R(PORT-F-R) /SLEEVE SPK-OUT-L+ 2

2 2
3
LINE1_L
330P_0402_50V7K
CA26
@
330P_0402_50V7K
CA27
@
TVNST52302AB0_SOT523-3
D2
@
45 SPKR+ CA24 1 2 4.7U_0402_6.3V6M
DMIC_DATA 4 SPK-OUT-R+ 44 SPKR-
GPIO2_MUTE 1 GPIO0/DMIC-DATA12 SPK-OUT-R-
<58,59> GPIO2_MUTE DMIC_CLK GPIO2/DMIC-DATA34 1 1
5
GPIO1/DMIC-CLK 27 HPOUT_L
HPOUT-L(PORT-I-L)
1
7 26 HPOUT_R 20191016
1
6 I2C-CLK HPOUT-R(PORT-I-R) - RA14 change to 0-ohm
RA41 I2C-DATA 15 HDA_SYNC_R
10K_0402_5% AUDIOLINK:SYNC 14 HDA_BITCLK_AUDIO 1 2 HDA_SYNC_R <18> GNDA GND 20191104
11 AUDIOLINK:BCLK 17 HDA_SDOUT_R RA14 0_0402_5% HDA_BIT_CLK_R <18> - Config change to @
2
8 I2S-MCLK AUDIOLINK:SDATA-OUT 16 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <18>

I2S-IN AUDIOLINK:SDATA-IN HDA_SDIN0 <18>
12 RA15 22_0402_5%
10 I2S-LRCK
9 I2S-BCLK 29 +3VS_DVDD
I2S-OUT MIC2-VREFO-R +MIC2_VREFO_R
20191025 28
- CA25 Change to 0201 SE00000UC00 MIC2-VREFO-L +MIC2_VREFO_L
100K_0402_1%
RA20
1
CA25 1 2 1U_0201_6.3V6M
23 39
24 CBP LDO1-CAP 21
CBN LDO2-CAP 19
LDO3-CAP TO Audio Jack
2
MONO_IN 34 SENSE_A 2 1 HP_PLUG#
PCBEEP HP_PLUG# <73>
1
CODEC_VREF
10U_0402_6.3V6M
CA29
10U_0402_6.3V6M
CA30
10U_0402_6.3V6M
CA31
100K_0402_5%
RA19
38 1 1 1 RA21 200K_0402_1%
VREF
0.1U_0201_10V6K
CA35
13 1
MUTE# 2 DC-DET/EAPD
PDB 25 CPVEE 2 2 2
2
SENSE_A 48 CPVEE
B B
HP/LINE1-JD(JD1) 2
1U_0201_6.3V6M
CA32
2.2U_0402_6.3V6M
CA33
47 37 1 1 RA21
I2S-IN/I2S-OUT-JD(JD2) AVSS1 22
32 AVSS2 49
MIC2-CAP Thermal Pad HP-JD LINE1-JD
1
2 2 GNDA GNDA
CA34 ALC299-CG_MQFN48_6X6
Near pin 48 200K 100K
10U_0402_6.3V6M
2 GNDA GNDA GNDA
SA0000A5L00
GNDA 20191025
ALC295 use ALC299 symbol - CA32 Change to 0201 SE00000UC00 Speaker
CONN@
EMI@ JSPK1
+3VS_DVDD SPKR+ LA6 1 2 HCB1608KF-121T30_0603 SPK_R+ 1
MUTE# M/B SPKR- LA7 1 2 HCB1608KF-121T30_0603 SPK_R- 2 1
2 3
EMI@
G1 4
Raptor:289 G2
1
RA30 1 @ 2 0_0402_5%
CVILU_CI4202M2HR0-NH
RA31 1 @ 2 0_0402_5% RA22 SP02001CK00
10K_0402_5% SPKL+
RA32 1 @ 2 0_0402_5% IO/B SPKL-
SPKL+ <73>
SPKL- <73>
2
RA33 1 @ 2 0_0402_5% RA23 2 1 0_0402_5%
<58> EC_MUTE#
RA24 2 @ 1 10K_0402_5% MUTE#
RA34 1 @ 2 0_0402_5% <18> HDA_RST#_R
BEEP
1
RA35 1 @ 2 0_0402_5%
RA36 1 @ 2 0_0402_5% @ RA25

10K_0402_5%
RA37 1 @ 2 0_0402_5%
2
RA39 2 1 22K_0402_5% BEEP#_R CA36 1 2 0.1U_0201_10V6K MONO_IN

<58> BEEP#
RA38 2 1 22K_0402_5%
<18,19> PCH_SPKR
1
A A
GND GNDA 1
@
CA37 RA40
100P_0402_50V8J 5.1K_0402_1%
2
2
20191008
- RA39/RA38 change to 22k
- RA40 change to 5.1k

Audio Code ALC295
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
EC Board ID
Analog Board ID definition, refer page 3.
RB3
+3VLP_EC +3VLP_ECA EC01@

+3VLP LB1 S RES 1/16W 0 +-5% 0402
JPB1 FBMA-L11-160808-800LMT_0603 SD028000080
1 2 1 2 +3VLP_ECA +3VLP_EC
+3VLP_EC 1 2 RB3
JUMP_43X39
2
EC_PME#
0.1U_0201_10V6K
0.1U_0201_10V6K
RB4 1 @ 2 47K_0402_5% @ 1 1 1 EC02@
CB1
CB2
CB3 S RES 1/16W 12K +-1% 0402 RB1
2
SD034120280 100K_0402_1% Ra
1 For Power consumption @ RB2 0.1U_0201_10V6K 1
2 2 2 RB3
0_0402_5%
Measurement
1
AD_BID
ECAGND EC10@
ECAGND <84>
2
S RES 1/16W 15K +-1% 0402 @ 1
+3VLP_LPC RB3 @ CB4
EC_RST# SD034150280
CB14 1 2 0.1U_0201_10V6K 0_0402_5% Rb 0.1U_0201_10V6K
RB3
111
125
2
22
33
96
67
1
9
UB1 EC01RGB@
ESPI Bus Pin : 1~5.7.8.10.12.14 S RES 1/16W 27K +-1% 0402
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
SD034270280
RB3
For turn off internal LPC module of KB9032 1 21 EC_VCCST_PG_R
<63> F9_MUTE_LED# CHG_CTL3 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <10,78>
2 23 BEEP# EC10RGB@
<71> CHG_CTL3 TPM_SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 FAN_PWM1 BEEP# <56>
XESD@ 3 26 S RES 1/16W 33K +-1% 0402
1 2 100P_0402_50V8J PLT_RST# <17,66> TPM_SERIRQ LPC_FRAME# SERIRQ EC_FAN_PWM/GPIO12 FAN_PWM2 FAN_PWM1 <77>
CB5 4 PWM Output 27 SD034330280
<17> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <77>
5
<17> LPC_AD3 LPC_AD2 LPC_AD3
7
<17> LPC_AD2 LPC_AD1 LPC_AD2 BATT_TEMP
CB6 1 2 100P_0201_50V8J ACIN 20200114 8 63
- CB6 Change to SE00000SE00 (0201) <17> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 CHG_CTL1 BATT_TEMP <84,85>
10 LPC & MISC 64
<17> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I CHG_CTL1 <71>
65
CLK_LPC_R ADP_I/AD2/GPIO3A AD_BID ADP_I <84,85>
XEMI@ XEMI@ 12 AD Input 66
2 1 2 1 CLK_LPC_R <17> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75
<16,33,66> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 VRAM_TEMP <84>
CB7 RB6 37 76 IDCHG
<77> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 IDCHG <85>
22P_0402_50V8J 33_0402_5% 20
<19> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38
<52> WLAN_ON CLKRUN#/GPIO1D
68 USB_TYPEC_EN
<63> KSI[0..7] DA0/GPIO3C EC_TP_INT# USB_TYPEC_EN <42>
DA Output EN_DFAN1/DA1/GPIO3D 70 near SOC
VR_PWRGD EC_TP_INT# <16,63> PCH_RTCRST# <18>
KSI0 55 71
KSI0/GPIO30 DA2/GPIO3E
1
KSI1 56 72 GPIO03 D
+3VLP_EC KSI2 57 KSI1/GPIO31 DA3/GPIO3F EC_CLR_CMOS 2 QB6
KSI3 58 KSI2/GPIO32 83 EC_MUTE# G
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_MUTE# <56> L2N7002WT1G_SC-70-3
1
RB10 1 2 2.2K_0402_5% EC_SMB_CK1 KSI4 59 84 USB_EN
USB_EN <73>
S SB00001GE00
3
2
RB11 1 2 2.2K_0402_5% EC_SMB_DA1 KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 RB26 2
KSI5/GPIO35 PSCLK2/GPIO4C EC_SMB_CK3 <63>
KSI6 61 PS2 Interface 86 10K_0402_5%
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK EC_SMB_DA3 <63>
KSI7 62 87
+5VS <63> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <63>
KSO0 39 88
TP_DATA <63>
2
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F
RB79 1 2 4.7K_0402_5% EC_SMB_CK3 KSO2 41 KSO1/GPIO21
RB80 1 2 4.7K_0402_5% EC_SMB_DA3 KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <17>
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_EN TP_PWR_EN <63>
20191206 KSO5 44 99 20191025 20200114
- RB79/RB80 change power source to +5VS KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <18>
- Reserved Thermal_ALERT# - RB87 Change to R-short
for power leakage . KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <84>
KSO8 47 KSO7/GPIO27 RB87 1 @ 2 0_0402_5%
KSO8/GPIO28 SPI Device Interface GPU_OVERT# <33>
KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B BT_ON_R RB85 SPOK_5V <87>
KSO10 49 120 1 @ 2 0_0402_5% BT_ON GPIO03 1 @ 2 THERMAL_ALERT#
SPOK_3V RB72 KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <16,52> THERMAL_ALERT# <66>
1 @ 2 0_0402_5% KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 RB86 0_0402_5%
KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <66>
KSO13 52
SPOK_5V RB73 1 @ 2 0_0402_5% SPOK_3V5V KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R TYPEC_1P5A_EC <42,43>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 SYS_PWROK_R 1 @ 2
KSO17/GPIO49 GPIO50 BATT_4S <85> SYS_PWROK <18,78>
90 BATT_BLUE_LED# RB7 0_0402_5%
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 BATT_BLUE_LED# <62>
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# CAPSLOCK_LED# <63>
77 GPIO 92
SPOK_3V5V EC_RSMRST# <84,85> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <62>
1 2 78 93
<84,85> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <62> +3VS
DB2 RB751V-40_SOD323-2 SYSON
<18,33,66> PCH_SML1CLK EC_SMB_CLK2/GPIO46 SYSON/GPIO56 VR_ON SYSON <78,89>
80 121
<18,33,66> PCH_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 CHG_ILMSEL VR_ON <78,92,97>
127
PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <71>
1 2 PU at CPU side SM Bus
DB3 RB751V-40_SOD323-2
PM_SLP_S3# 6 100 EC_RSMRST# GPU_OVERT# RB12 1 VGA@ 2 10K_0402_5%
<18,78> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <18>
EC_VCCST_PG_R <52> EC_WLAN_PME# GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <19,33,85>
1 2 15 102
<87,90> SPOK_3V TP_EN GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <84>
DB4 RB751V-40_SOD323-2 16 103
<63> TP_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06
GPIO0B 17 104 MAINPWON
GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <77,84,87> +3VLP_EC
3 GPIO0C 18 105 BKOFF# 3
AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 EC_PME# BKOFF# <38>
<18>
AC_PRESENT AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R EC_PME# <16,73> EC Internal PU
25 107
<63> KBL_EN FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 LID_SW#
28 108 RB13 1 2 100K_0402_1%
<77> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CHG_EN <71>
29
<77> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 ACIN
<52> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON ACIN <85>
32 112
<18,78> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <87>
<62> PWR_SUSP_LED#
ON/OFFBTN# For Thermal Portect Shutdown
TURBO_EN# 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFFBTN# <63>
<77> TURBO_EN# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <66>
116 SUSP#
SUSP#/GPXIOD05 SUSP# <39,68,78,85,89,92>
117 DB1
GPXIOD06 EC_PECI TURBO_LED# <77>
118 1 2 RB751V-40_SOD323-2
PBTN_OUT# PECI/GPXIOD07 H_PECI <10,17> 3V_EN
122 RB16 33_0402_1% MAINPWON 1 2
<18> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D 3V_EN <87>
123 124 1
<18,78> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC RB14
AGND
CB8 3V_EN_R 1 2 RB15 1 2

GND
GND
GND
GND
GND
0.1U_0201_10V6K 1M_0402_5%
XESD@ 2 1K_0402_5%
KB9022QD_LQFP128_14X14
11
24
35
94
113
ECAGND 69
CO-LAY with KB9032QA (SA000080J00) 20mil

CB9 1 2 BATT_TEMP 20200114
100P_0201_50V8J - CB6 Change to SE00000SE00 (0201)
LB2 2 1 @ RB17
FBMA-L11-160808-800LMT_0603 0_0402_5%
1 2 VR_HOT#
20191008 VR_HOT# <97>
- For KC3810 @ RB18
2015/1/9 acer require: 0_0402_5%
reserved protact circuit when H_PROCHOT# 1 2 VCOUT1_PROCHOT
<10,85> H_PROCHOT#
XESD@ <59> ESB_CLK
ESB_CLK RB84 1 @ 2 0_0402_5% adaptor 107% happen
CB10 1 2 .1U_0402_16V7K SUSP# ESB_DAT RB83 1 @ 2 0_0402_5%
<59> ESB_DAT
XESD@
CB11 1 2 .1U_0402_16V7K GPIO2_MUTE RB82 1 2 0_0402_5% GPIO0B
4 4
<56,59> GPIO2_MUTE WL_OFF# RB81 1 2 0_0402_5% GPIO0C
<52,59> WL_OFF#
ESD@
CB12 SYSON
33P_0402_50V8J
ESD@ +3VALW
CB13
33P_0402_50V8J RB78 1 2 10K_0402_5% TURBO_EN#
20191211B 2019/09/20 2020/09/20 Title
- CB12/CB13 change to 33p for ESD & ESD@ Issued Date Deciphered Date
VR_PWRGD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9022
RB76 2 @ 1 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
<97> VCCCORE_VR_PWRGD
A B C D E
5 4 3 2 1
*NMI_DBG#: is a debug pin for EC to

infrom BIOS after press hot key.
OMEN New ESB CLK&DAT for Extend I/O
D D
+3VLP_EC
KC3810@
UK3
1
KC3810@ ESB_CLK 1 13
<58> ESB_CLK ESB_CLK TEST_EN#
RK20
47K_0201_5% 2 14
GPIO00 GPIO08/CAS_DAT
KC3810_RST# 3 15
2
RST# GPIO09
KC3810_RST# ESB_DAT 4 16
<58> ESB_DAT ESB_DAT GPIO0A
TS_EN 5 17
2 <19,38> TS_EN GPIO01 GPIO0B
KC3810@
CK16 WL_OFF# 6 18
<52,58> WL_OFF# GPIO02 GPIO0C/PWM0
0.1U_0201_10V6K
1 GPIO2_MUTE 7 19
<56,58> GPIO2_MUTE GPIO03 GPIO0D/PWM1
8 20
GPIO04 GPIO0E/PWM2
9 21
GPIO05 GPIO0F/PWM3
10 22
GPIO06 GPIO10/ESB_RUN#
11 23
GPIO07/CAS_CLK GPIO11/BaseAddOpt
12 24
GND
GND VCC +3VLP_EC
0.1U_0201_10V6K
KC3810@
CK202
KC3810NF-A0_QFN24_4X4 1
25
SA00002AI00
C C
+3VLP_EC
KC3810@
RK207 2 1 4.7K_0402_5% ESB_CLK
RK208 2 1 4.7K_0402_5% ESB_DAT

KC3810@
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3VALW
+3VS
2.2K +3VS 2.2K
D
PCH_SMBCLK D_CK_SCLK D
(QH7)
PCH_SMBDATA 2N7002DW D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
+3VALW 1.8K
PCH_SML0DATA 499
Cannonlake 2K
2.2K +1.8VSDGPU_AON
PCH - H 1.8K +1.8VSDGPU_AON
+3VALW 2K
2.2K +1.8VSDGPU_MAIN I2CB_SCL
PCH_SML1CLK EC_SMB_CK2 VGA_I2CS_SCL
I2CB_SDA
(RH189/RH190) (QV2)
PCH_SML1DATA R-short EC_SMB_DA2 PJT138KA VGA_I2CS_SDA 2K
2.2K N17P-G0-K1 2K
+1.8VSDGPU_AON
2.2K
+3VLP_EC N18P-G0 I2CC_SCL
EC_SMB_CK1 100 ohm EC_SMB_CK1-1 I2CC_SDA NVVDD controller

BATTERY
EC_SMB_DA1 100 ohm EC_SMB_DA1-1 CONN
C C
KB9022 0 ohm EC_SMB_CK1_CHGR

2.2K
0 ohm EC_SMB_DA1_CHGR Charger
+3VS
+3VS 2.2K
EC_SMB_CK2
TMS_SMB_CLK
(QF1)
EC_SMB_DA2 2N7002DW THERMAL SENSOR
TMS_SMB_DATA
4.7K 2.2K
+5VALW +5VS_BL
4.7K 2.2K
+5VS_BL
EC_SMB_CK3 EC_SMB_CK3_LEDDRV
(QE62)
EC_SMB_DA3 2N7002DW EC_SMB_DA3_LEDDRV LED driver
0 ohm
0 ohm
B B
A A

N17E-GDDR5_D
5 4 3 2 1
5 4 3 2 1
Battery LED 20200211

- RG4/RG11 change to 1k
RG4 LED1
1K_0402_5%
BATT_AMB_LED# 1 2 3 A 4 JGND1
D <58> BATT_AMB_LED# +5VALW D
1 2
1 2
BATT_BLUE_LED# 1 2 1 B 2 JUMP_43X79
<58> BATT_BLUE_LED#
@
RG6
560_0402_5% LTST-C295TBKF-CA_AMBER-BLUE
Power LED
RG11 LED2
1K_0402_5% JGND2
PWR_SUSP_LED# 1 2 3 A 4 1 2
<58> PWR_SUSP_LED# 1 2
JUMP_43X79
PWR_LED# 1 2 1 B 2 @
<58> PWR_LED# +5VALW
RG10
560_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
C C
B B
A A

LED
1A
5 4 3 2 1
A B C D E
Touch Pad +3VALW

+3V_PTP
+3V_PTP
2 @ 1
ON/OFF BTN UK1
+3VALW
+3VS
0_0402_5%
2 @
RK5
1
- For TEST
4.7U_0402_6.3V6M
R17 5 1 0_0402_5% RK6
+3VLP 100K_0402_5% IN OUT +3V_PTP
2 1
CK2
2 1 2 @ CK1
CK3 GND 0.1U_0201_10V6K JTP1
2
1U_0201_6.3V6M 4 3 2 1 1
ON/OFFBTN# 1 EN OC 2 TP_CLK 2 1
<58> ON/OFFBTN# TP_DATA 2
SY6288C20AAC_SOT23-5 RK7 3
10K_0402_5%
EC PS2 4 3
1 @ 2 I2C_1_SDA_R 5 4
1 1
1
EC_TP_INT# I2C_1_SCL_R 6 5
1
<58> TP_PWR_EN PCH I2C EC_TP_INT# 6
0.1U_0201_10V6K
CK8
@XESD RK18 7
<16,58> EC_TP_INT# TP_EN 8 7
0_0603_5% TP_PWR_EN follow SYSON behavior <58> TP_EN
9 8
2 20191206 10 GND
GND
1
- Add CK203 for ESD ESD@
SW1 EVT@ +3V_PTP +3V_PTP CK203 JXT_FP202DH-008M10M
TJG-533-V-T/R_6P 20191211A 680P_0402_50V7K CONN@
2
1 3 - CK203 change to 680p for ESD
SP010020L00
1
2 4
1
20200114
2
DK2 XESD@ RK8 RK9 +3V_PTP
- set EVT@
G
6
5
TP_DATA 6 3 TP_EN QK1A 2.2K_0402_5% 2.2K_0402_5%
I/O4 I/O2
20191017 2N7002KDW_SOT363-6
2
- Add for EVT
1
6 1 I2C_1_SCL_R
S
<19> I2C_1_SCL
5 2 RK10 RK11
D
+3V_PTP VDD GND 1 @ 2 CK6 33P_0402_50V8J 4.7K_0402_5% 4.7K_0402_5%
RK12 0_0402_5%
XESD@
2
5
TP_CLK 4 1 EC_TP_INT#
G
I/O3 I/O1 QK1B CK7 33P_0402_50V8J
AZC099-04S.R7G_SOT23-6 2N7002KDW_SOT363-6 TP_CLK
TP_DATA TP_CLK <58>
SC300001G00 XESD@
3 4 I2C_1_SDA_R TP_DATA <58>
<19> I2C_1_SDA
S
D
1 2
RK13 @ 0_0402_5%
2
LED driver 20191001
- Change to +5VS only
- KBL_EN only (Check EC Code)
KB Conn. / Backlight 2
- pop (Normal & RGB)
20191016
20200115 KSI[0..7]
- Remove QE62/RE70/RE69 - R41/R18 change to R-short KSI[0..7] <58>
- PU +5VALW @ EC KSO[0..17]
KSO[0..17] <58>
+5VS +5VS_BL
U4
JKB1
5 1
IN OUT 32 34
F9_MUTE_LED#_R 32 G2
0.1U_0201_10V6K
2 <58> F9_MUTE_LED# 820_0402_5% 1 2 RE76 31 33
GND CAPSLOCK_LED#_R 31 G1
C32
820_0402_5% 1 2 RE77 30
<58> CAPSLOCK_LED# 30
R18 1 @ 2 0_0201_5% 4 3 1 29
<58> KBL_EN EN OC +5VS 29
KSO16 28
SY6288C20AAC_SOT23-5 @ KSO17 27 28
KSO0 26 27
2 KSO1 25 26
KSO2 24 25
KSO3 23 24
KSO4 22 23
KSO5 21 22
0.1U_0201_10V6K CK212 2 1 XESD@ KSO6 KSO6 20 21
KSO11 15 16
KSO12 14 15
KSO13 13 14
KSO14 12 13
KSO15 11 12
KSI0 10 11
KSI1 9 10
KSI2 8 9
3 KSI3 7 8 3
+5VS_BL
AD3 AD2 AD1 AD0 +5VS_BL KSI4 6 7
KSI5 5 6
0 0 0 1 KSI6 4 5
4
1
RE65 LED14P@ KSI7 3

4.7K_0402_1% 2 3
1 2
CE3 LED14P@ ON/OFFBTN# 1
UE4 0.1U_0201_10V6K 1
2
24 27 2 ACES_51519-03201-001
RESET Vcc CONN@
3 KB_A_LED_R_DRV#
EC_SMB_CK3 RE1 2 @ 1 0_0402_5% EC_SMB_CK3_LEDDRV 25 OUT0 4 KB_A_LED_G_DRV# SP01001RH00
<58> EC_SMB_CK3 EC_SMB_DA3 EC_SMB_DA3_LEDDRV SCL OUT1 KB_A_LED_B_DRV#
RE2 2 @ 1 0_0402_5% 26 5
<58> EC_SMB_DA3 SDA OUT2 KB_B_LED_R_DRV#
6
AD0 31 OUT3 8 KB_B_LED_G_DRV#
AD1 32 A0 OUT4 9 KB_B_LED_B_DRV# CONN@
AD2 1 A1 OUT5 10 KB_C_LED_R_DRV# JBL2
AD3 2 A2 OUT6 11 KB_C_LED_G_DRV# 16
A3 OUT7 14 KB_C_LED_B_DRV# 15 GND
AD0 12 OUT8 15 KB_D_LED_R_DRV# +5VS_BL GND
AD1 13 N.C. OUT9 16 KB_D_LED_G_DRV#
AD2 28 N.C. OUT10 17 KB_D_LED_B_DRV#
AD3 29 N.C. OUT11 19 14
30 N.C. OUT12 20 13 14
N.C. OUT13 13
1
21 KB_A_LED_R_DRV# 12
OUT14 12
1
RE75 RE74 RE73 RE72 22 KB_A_LED_G_DRV# 11

4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% RE64 OUT15 KB_A_LED_B_DRV# 10 11
LED14P@ LED14P@ LED14P@ LED14P@ @ 7 23 +5VS_BL CONN@ KB_B_LED_R_DRV# 9 10
10K_0402_5% GND GND 9
18 33 JBL1 KB_B_LED_G_DRV# 8
2
GND GND 1 KB_B_LED_B_DRV# 7 8

2
2 1 KB_C_LED_R_DRV# 6 7
TLC59116FIRHBR_VQFN32_5X5 3 2 KB_C_LED_G_DRV# 5 6
4 3 KB_C_LED_B_DRV# 4 5
- Raptor: NC for 59116F LED14P@ 4 KB_D_LED_R_DRV# 3 4
4
- Set RE64 to 10k / output = 1.875mA 5 KB_D_LED_G_DRV# 2 3
4
6 GND KB_D_LED_B_DRV# 1 2
GND 1
ACES_51524-0040N-001 ACES_51522-01401-P01
SP010022M00 SP01001R800

KB & TP & TPM Connector
A B C D E
5 4 3 2 1
CONN@
3V_PEN JEMR1
FWE 1
+3VALW +3VS +3V_PEN EMR 1A modify
I2C_0_SCL_R
I2C_0_SDA_R
PEN_PDCT_R#
2
3
4
1
2
3
D 5 4 D
@ 6 5
RH271 1 2 0_0402_5% +3V_PEN PEN_IRQ_R# 7 6
PEN_RST_R# 8 7
WC33V@ +1.8V_3V_PEN RH298 1 @ 2 0_0402_5% +3V_PEN_R 9 8
RH272 1 2 0_0402_5% 10 9
RH299 1 @ 2 0_0402_5% +1.8V_3V_PEN_R 11 10
12 11
13 12
14 GND1
GND2
ACES_50208-01201-P01
SP01001UP00
1.8V_PEN
+3VALW +1.8VALW +1.8VS +1.8V_3V_PEN
@
RH277 1 2 0_0402_5%
WC18V@
RH278 1 2 0_0402_5%
WC33V@
C RH297 1 2 0_0402_5% C
+1.8V_3V_PEN
1
RH295
2.2K_0402_5%
@
2
FWE
1A modify
20191008
1
- QY6/QY8 change to SB000016K00 RH296
Default use 0ohm(WC33V@) 2.2K_0402_5%
WC33V@
2
+1.8V_3V_PEN
+1.8V_3V_PEN MISC signal
I2C
WC18V@
5
WC18V@ QY8A
5
QY6A PJT138KA_SOT363-6
G
PJT138KA_SOT363-6 4 3 PEN_IRQ_R# +1.8V_3V_PEN
G
4 3 I2C_0_SCL_R <19> PEN_IRQ#
D
WC18V@
B <19> I2C_0_SCL B
S
RH287 QY10
RH279 1 2 2
1 2 0_0402_5% Gate
0_0402_5% WC33V@ 1 PEN_RST_R#
WC33V@ Drain
3
<19> PEN_RST# Source
WC18V@
2
WC18V@ QY8B LBSS139WT1G_SC70-3
2
QY6B PJT138KA_SOT363-6
G
PJT138KA_SOT363-6 1 6 PEN_PDCT_R#
G
1 6 I2C_0_SDA_R <19> PEN_PDCT#
D
RH293
<19> I2C_0_SDA 1 2
S
RH288
1 2 0_0402_5%
RH280 0_0402_5% WC33V@
1 2 WC33V@
0_0402_5%
WC33V@ 3ohm/10pF +3VALW 20191206
- RH285/RH286/RH292 power source change to +3VALW
WC33V@
PEN_IRQ# RH286 2 1 2.2K_0402_5%
PEN_PDCT# RH285 2 1 2.2K_0402_5% +3VALW
3ohm/10pF +1.8V_3V_PEN WC33V@ WC33V@
WC18V@ +1.8V_3V_PEN PEN_RST# RH292 2 1 2.2K_0402_5%
I2C_0_SCL_R RH275 2 1 2.2K_0402_5% WC18V@
I2C_0_SDA_R RH276 2 1 2.2K_0402_5% PEN_IRQ_R# RH284 2 1 2.2K_0402_5%
WC18V@ PEN_PDCT_R# RH283 2 1 2.2K_0402_5% +1.8V_3V_PEN
WC18V@ WC18V@
PEN_RST_R# RH290 2 1 2.2K_0402_5%
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
THERMAL SENSOR Close to Thermal SKIN

To Hall sensor/B +3VS +3VS
+3VS
1
+3VLP
1
CONN@ RF9 TMS@
JHS1 RF10 +3VS RF26
2.2K_0402_5% SMBUS ADDRESS
5
1 TMS@ 2.2K_0402_5% TMS@ 10K_0402_5%
G
2 1 QF1B TMS@ CF21 TMS@ 1001_1010b
<58> LID_SW#
2
3 2 2N7002KDW_SOT363-6 0.1U_0201_10V6K TMS@ UF3
2
4 3 2 1 1 8 TMS_SMB_CLK
4 TMS_SMB_CLK VCC SMBCLK TMS_SMB_DATA
0.1U_0201_10V6K
<18,33,58> PCH_SML1CLK 3 4 2 7
S
DXP SMBDATA THERMAL2_ALERT#
C60
5 3 6
D
1 GND DXN #ALERT
2
1 TMS@ 2 TH2_THERM#
ESD@
6 TMS@ 4 5
G
D GND +3VS #THERM GND D
QF1A RF25 10K_0402_5%
ACES_51524-0040N-001 2N7002KDW_SOT363-6 G781-1P8F_MSOP8
2
SP010022M00 6 1 TMS_SMB_DATA SA00000V200
<18,33,58> PCH_SML1DATA
S
D
20191008
- C60 change to @
Close to SO-DIMM
+3VS
+3VS
TMS@ CF20
1 SMBUS ADDRESS
1001_1000b
1
0.1U_0201_10V6K TMS@
TMS@ UF2 RF24
2 1 8 TMS_SMB_CLK 10K_0402_5%
VDD SCL
2 7 TMS_SMB_DATA
2
D+ SDA
3 6 THERMAL_ALERT#
D- ALERT# THERMAL_ALERT# <58>
1 TMS@ 2 TH_THERM# 4 5
+3VS T_CRIT# GND
RF23 10K_0402_5%
NCT7718W_MSOP8 RK209 1 @ 2 0_0402_5% THERMAL2_ALERT#

SA000067P00
C C
TPM Finger Print
+3VALW R45 +3VALW_TPM +3VS R46 +3VS_TPM

0_0603_5% 0_0603_5%
1 @ 2 1 @ 2
10U_0402_6.3V6M
0.1U_0201_10V6K
10U_0402_6.3V6M
0.1U_0201_10V6K
C57
0.1U_0201_10V6K
C58
0.1U_0201_10V6K
C55
1 1 1 1 1 1
C56
C59
C54
+3VALW @
near RK14 1 2 0_0402_5%
2 2 2 2 2 2 +FP_VCC
TPM@
TPM@ TPM@ TPM@ TPM@ TPM@

pin1 +5VALW
JFP1
RK15 1 FP@ 2 0_0402_5%
8
+FP_VCC USB20_P8_L 7 8 10
2 USB20_N8_L 7 G2
6 9
near FP@ CK4 UK2 5 6 G1
+3VALW pin8,22 1U_0201_6.3V6M 5 1 4 5
R48 TPM@ 1 IN OUT 3 4
1 3
10K_0402_5% 2 FP@ 2
1 2 PCH_SPI_CS#2 GND CK5 1 2
FP_PWR_EN 4 3 4.7U_0402_6.3V6M 1
<58> FP_PWR_EN EN OC 2 ACES_51522-00801-001
B SY6288C20AAC_SOT23-5 B
SP01001AE00
FP@
CONN@
R50 1 TPM@ 2 33_0402_1% PCH_SPI_SO_TPM_R
<16> PCH_SPI_SO_R 1 TPM@ 2 33_0402_1% PCH_SPI_SI_TPM_R
R51
<16> PCH_SPI_SI_R R52 1 TPM@ 2 33_0402_1% PCH_SPI_CLK_TPM_R
<16> PCH_SPI_CLK_R
1 @ 2 USB20_N8_L
<14> USB20_N8
RK16 0_0402_5%
U9 +3VALW_TPM 1 @ 2 USB20_P8_L
<14> USB20_P8
TH41 1 RK17 0_0402_5%
@ 29 VSB +3VS_TPM
30 SDA/GPIO0 8
SCL/GPIO1 VHIO 22
0_0402_5% 1 @ 2 R47 TPM_BADD 6 VHIO
GPIO3 2 PIN ETU801 FA577E-1200
PCH_SPI_SO_TPM_R 24 NC 3
PCH_SPI_SI_TPM_R 21 MISO NC 5 DK1 FPESD@ 1 +FP_VCC(5V) +FP_VCC(3V)
18 MOSI/GPIO7 NC 7 USB20_P8_L 6 3
<17,58> TPM_SERIRQ PIRQ/GPIO2 NC 9 I/O4 I/O2 2 USBP D+
NC 10
PCH_SPI_CLK_TPM_R 19 NC 11 3 USBN D-
20 SCLK NC 12 5 2
<16> PCH_SPI_CS#2 17 SCS/GPIO5 NC 14
+FP_VCC VDD GND 4 GND GND
<16,33,58> PLT_RST# 27 PLTRST NC 15
13 NC NC 26 5 NC NC
GPIO4 NC 25 4 1 USB20_N8_L
NC 28 I/O3 I/O1 6 NC NC
4 NC 31 AZC099-04S.R7G_SOT23-6
PP/GPIO6 NC 32 7 NC
A NC SC300001G00 A
16 8 NC
GND 23
GND 33
PGND
NPCT750AAAYX_QFN32_5X5
TPM@
SA0000AQ250 Security Classification Compal Secret Data Compal Electronics, Inc.
SA0000AQ250, S IC NPCT750AABYX QFN 32P TPM Sensors/FP/TPM
1A
5 4 3 2 1
A B C D E
+5VS_HDD FFC Type

100mils
10U_0402_6.3V6M
CO12
1
1
CONN@
1 CO13 JHDD1 1
0.1U_0201_10V6K 14
2
2 @ +5VS +5VS_HDD 13 GND
GND
RO4 1 @ 2 0_0805_5% 12
11 12
10 11
RO25 1 2 0_0201_5% G_INT2_R 9 10
20200114 @
9
8
- RO25 change to R-short 7 8
SATA_PRX_DTX_P0B CO14 2 1 0.01U_0201_6.3V7K SATA_PRX_C_DTX_P0B 6 7
<17> SATA_PRX_DTX_P0B SATA_PRX_DTX_N0B CO15 2 1 0.01U_0201_6.3V7K SATA_PRX_C_DTX_N0B 5 6
<17> SATA_PRX_DTX_N0B 4 5
SATA_PTX_DRX_N0B CO16 2 1 0.01U_0201_6.3V7K SATA_PTX_C_DRX_N0B 3 4
<17> SATA_PTX_DRX_N0B SATA_PTX_DRX_P0B CO17 2 1 0.01U_0201_6.3V7K SATA_PTX_C_DRX_P0B 2 3
<17> SATA_PTX_DRX_P0B 1 2
1
ACES_51625-01201-001
20191016 change to SATA Port 0B SP010028W00
2 2
3 3
20190918
Remove HDD Re-driver
4 4

HDD/ Re-Driver/ G-sensor
Custom 1A
A B C D E
5 4 3 2 1
20191017 Power source +3VALW

> +3VS_SSD2 : JSSD2
> +3VS_SSD3 : JSSD1 & JSSD3 UM2 +3VS_SSD2
1 14 +3VS_SSD_2 1 @ 2
2 VIN1 VOUT1 13 RM54 0_0805_5%
VIN1 VOUT1
RM53 1 @ 2 0_0201_5% +3V_NGFF_GATE 3 12 1 2
<39,58,78,85,89,92> SUSP# ON1 CT1 CM37 1000P_0402_50V7K
0.1U_0201_10V6K
1 4 11
+5VALW VBIAS GND
CM32 @
+3VS_SSD2 5 10 1 2
ON2 CT2 CM38 1000P_0402_50V7K
2 6 9 +3VS_SSD3
CONN@ 7 VIN2 VOUT2 8 +3VS_SSD_3 1 @ 2
D JSSD2 VIN2 VOUT2 RM55 0_0805_5% D
1
10U_0402_6.3V6M
0.1U_0201_10V6K
1 2 1 2 15
3 GND 3.3VAUX 4 + CM3 GPAD
PCIE_PRX_DTX_N9 5 GND 3.3VAUX 6 CM1 CM2 150U_D2_6.3VY_R15M +3VALW EM5209VF_DFN14_2X3
<17> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 PERn3 N/C 8 SGA00003700 +3VS_SSD_2 +3VS_SSD_3
<17> PCIE_PRX_DTX_P9 9 PERp3 N/C 10 2 1 2
PCIE_PTX_C_DRX_N9 GND DAS/DSS#
1U_0201_6.3V6M
1U_0201_6.3V6M
CM6 1 2 0.22U_0402_16V7K 11 12 2 2 2 2
<17> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn3 3.3VAUX
CM33
CM34
CM4 1 2 0.22U_0402_16V7K 13 14
<17> PCIE_PTX_DRX_P9 15 PETp3 3.3VAUX 16 CM35 CM36
PCIE_PRX_DTX_N10 17 GND 3.3VAUX 18
PERn2 3.3VAUX 0.1U_0201_10V6K 0.1U_0201_10V6K
<17> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 20 1 1 1 1
<17> PCIE_PRX_DTX_P10 21 PERp2 N/C 22
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND N/C 24
<17> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 N/C 26
<17> PCIE_PTX_DRX_P10 27 PETp2 N/C 28
PCIE_PRX_DTX_N11 GND N/C Place CM33 close UM2 pin 1&2
29 30
<17> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERn1 N/C 32 Place CM34 close UM2 pin 6&7
<17> PCIE_PTX_DRX_N11 CM9 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P11 37 PETn1 N/C 38 SSD_DEVSLP1
<17> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <17>
39 40
PCIE_PRX_DTX_P12 41 GND N/C 42
<17> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 PERn0/SATA_B+ N/C 44
<17> PCIE_PRX_DTX_N12 45 PERp0/SATA_B- N/C 46
<17> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA_A- N/C 50
<17> PCIE_PTX_DRX_P12 PETp0/SATA_A+ PERST# SSD2_CLKREQ#_R PLT_RST_BUF# <16,52,68,69,73>
51 52 RM7 1 @ 2 0_0201_5%
GND CLKREQ# SSD2_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF1# REFCLKn PEWake#
55 56
<15> CLK_PCIE_NGFF1 REFCLKp N/C
57 58
GND N/C
C
Pull high at PCH side 67 68 SUSCLK_SSD2 RM8 1 @ 2 0_0201_5% C
SSD2_DET# N/C SUSCLK SUSCLK <18,52,68,69>
<17> SATA_GP1 RM10 1 @ 2 0_0201_5% 69 70
71 PEDET 3.3VAUX 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX XESD@
PEDET(NC-PCIE/GND-SATA) GND PLT_RST_BUF# CM16 2 1 100P_0402_50V8J
SATA Device 0 GND
76
77
PCIE Device 1 GND
Place close to JSSD pin 50
BELLW_80159-4221 ESD request to reserve.
SP07001D300
+3VS_SSD3
CONN@
M.2 SSD
JSSD1 1
10U_0402_6.3V6M
0.1U_0201_10V6K
1 2 1 2
3 GND 3.3VAUX 4 + CM50
5 GND 3.3VAUX 6 CM46 CM44 150U_D2_6.3VY_R15M
<14> PCIE_PRX_DTX_N24 7 PERn3 N/C 8 SGA00003700
CM41 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N24 11 GND DAS/DSS# 12
<14> PCIE_PTX_DRX_N24 CM49 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P24 13 PETn3 3.3VAUX 14
<14> PCIE_PTX_DRX_P24 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<14> PCIE_PRX_DTX_N23 19 PERn2 3.3VAUX 20
B CM48 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N23 23 GND N/C 24 B
29 GND N/C 30
<14> PCIE_PRX_DTX_N22 31 PERn1 N/C 32
<14> PCIE_PTX_DRX_P22 39 PETp1 DEVSLP 40
41 GND N/C 42
<14> PCIE_PRX_DTX_P21 43 PERn0/SATA_B+ N/C 44
<14> PCIE_PTX_DRX_N21 CM43 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P21 49 PETn0/SATA_A- N/C 50 PLT_RST_BUF#
<14> PCIE_PTX_DRX_P21 PETp0/SATA_A+ PERST# SSD1_CLKREQ#_R PLT_RST_BUF# <16,52,68,69,73>
51 52 RM56 1 @ 2 0_0201_5%
53 54
55 56
57 58
GND N/C
67 68 SUSCLK_SSD1 RM57 1 @ 2 0_0201_5%

SSD1_DET# N/C SUSCLK SUSCLK <18,52,68,69>
69 70
T211 @ PEDET 3.3VAUX
71 72
73 GND 3.3VAUX 74 XESD@
75 GND 3.3VAUX PLT_RST_BUF# CM39 2 1 100P_0402_50V8J
GND
76
GND 77
GND Place close to JSSD pin 50
ESD request to reserve.
BELLW_80159-4221
A SP07001D300 A

SATA/PCIE-SSD
Custom 1A
5 4 3 2 1
5 4 3 2 1
1004
1210B +3VS_SSD3 - Remove UM3
- Power source merge +3VS_SSD3
- Add SSD3 config
D CONN@ D
JSSD3 1
10U_0402_6.3V6M
CM28
SSD3@
0.1U_0201_10V6K
CM26
SSD3@
1 2 1 2 SSD3@
3 GND 3.3VAUX 4 + CM20
5 GND 3.3VAUX 6 150U_B2_6.3VM_R35M
<17> PCIE_PRX_DTX_N20 7 PERn3 N/C 8 SGA00009M00
SSD3@ CM23 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N20 11 GND DAS/DSS# 12
<17> PCIE_PTX_DRX_N20 SSD3@ CM31 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P20 13 PETn3 3.3VAUX 14
<17> PCIE_PTX_DRX_P20 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<17> PCIE_PRX_DTX_N19 19 PERn2 3.3VAUX 20
SSD3@ CM29 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N19 23 GND N/C 24
<17> PCIE_PTX_DRX_N19 SSD3@ CM22 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P19 25 PETn2 N/C 26
29 GND N/C 30
<17> PCIE_PRX_DTX_N18 31 PERn1 N/C 32
<17> PCIE_PTX_DRX_N18 SSD3@ CM24 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P18 37 PETn1 N/C 38 SSD_DEVSLP4
<17> PCIE_PTX_DRX_P18 PETp1 DEVSLP SSD_DEVSLP4 <17>
39 40
41 GND N/C 42 20191025
<17> PCIE_PRX_DTX_P17 43 PERn0/SATA_B+ N/C 44 - SATA Port 4
<17> PCIE_PTX_DRX_N17 SSD3@ CM25 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P17 49 PETn0/SATA_A- N/C 50 PLT_RST_BUF#
<17> PCIE_PTX_DRX_P17 PETp0/SATA_A+ PERST# SSD3_CLKREQ#_R PLT_RST_BUF# <16,52,68,73>
51 52 RM48 1 @ 2 0_0201_5%
53 54
55 56
57 58
GND N/C
C C
67 68 SUSCLK_SSD3 RM52 1 @ 2 0_0201_5%
SSD3_DET# N/C SUSCLK SUSCLK <18,52,68>
<17> SATA_GP4 RM61 1 @ 2 0_0201_5% 69 70
71 PEDET 3.3VAUX 72
20191206 73 GND 3.3VAUX 74
- PEDET change to SATA_GP4 PEDET(NC-PCIE/GND-SATA) 75 GND 3.3VAUX XESD@
GND PLT_RST_BUF#
SATA Device 0 76
CM21 2 1 100P_0402_50V8J
PCIE Device 1 GND

GND
77
Place close to JSSD pin 50
BELLW_80159-4221 ESD request to reserve.
SP07001D300
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
USB3.0
20191016 For ESD request
- Gen2 Solution SC300006T00
+USB3_VCCA
DS1 ESD@
1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1 USB3_PTX_L_DRX_P1 1 9 USB3_PTX_L_DRX_P1
W=100mils
<17> USB3_PTX_DRX_P1
CS2 .1U_0402_16V7K
1 2 USB3_PTX_C_DRX_N1 RS89 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N1 USB3_PTX_L_DRX_N1 2 8 USB3_PTX_L_DRX_N1
1 2
1 <17> USB3_PTX_DRX_N1 1
CS3 .1U_0402_16V7K
RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1

USB3_PRX_L_DTX_P1 4 7 USB3_PRX_L_DTX_P1 CS5
150U_D2_6.3VY_R15M
+ CS6 EMI@
0.1U_0201_10V6K
USB3.0 Conn.
<17> USB3_PRX_DTX_P1 USB3_PRX_L_DTX_N1 5 6 USB3_PRX_L_DTX_N1 1
SGA00003700
<17> USB3_PRX_DTX_N1
RS91 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N1 2 GEN2 CONN.
CONN@
3 JUSB1
1
TVWDF1004AD0_DFN9 CHR_USB20_N1_R 2 VBUS
CHR_USB20_P1_R 3 D-
SC300006T00 D+
4
USB3_PRX_L_DTX_N1 5 GND
USB3_PRX_L_DTX_P1 6 SSRX- 10
LS3 EMI@ DS2 ESD@ 7 SSRX+ GND 11
CHR_USB20_P1 2 1 CHR_USB20_P1_R 6 3 CHR_USB20_N1_R USB3_PTX_L_DRX_N1 8 GND GND 12
2 1 I/O4 I/O2 USB3_PTX_L_DRX_P1 9 SSTX- GND 13
+USB3_VCCA SSTX+ GND
CHR_USB20_N1 3 4 CHR_USB20_N1_R ACON_GTRA0-9U1391
3 4 5 2
DLM0NSN900HY2D_4P VDD GND
SM070005U00
CHR_USB20_P1_R 4 1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
SC300001G00
2 2
USB Host Charger

0 0904 vendor recommend
1 +5VALW
+5VALW
1
CHG_CTL2
22U_0603_6.3V6M
0.1U_0201_10V6K
1 RS14 1 2 10K_0402_5% 1 1
CS9
CS7
@
@ +USB3_VCCA
RS15 1 2 10K_0402_5% CHG_ILMSEL 2 2 US12
1 12
VIN VOUT
0911 Rerserve PU, vendor suggest to EC control
2
if future need support SDP2 RS11
<14> USB20_N1 3 DM_OUT
3 <14> USB20_P1 DP_OUT 10 CHR_USB20_P1 3
0_0201_5%
2 @ 1 13 DP_IN 11 CHR_USB20_N1
<14> USB_OC1# FAULT# DM_IN
1 4
<58> CHG_ILMSEL ILIM_SEL
CS8 5 15 0831 Reserve ILIM_L R as vendor recommend
<58> CHG_EN EN ILIM_L 16
0.1U_0201_10V6K
USB Host Charger Truth Table @ 2 ILIM_HI
1
6
<58> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note 7 9
CTL2 NC
RS12
RS13
Setting 8 14
<58> CHG_CTL3 CTL3 GND 17
Thermal Pad ILM R vaule
0 1 0 1 SDP1-OFF ILIM_H Port power off @ Ios(mA)=50250/R(Kohm)
2
1
0 1 0 1 SDP1 ILIM_H Data Lines Connected @ SLGC55544CVTR_TQFN16_3X3 ILIM_Hi=2273mA
RS138 ILIM_L=1288mA(reserve)
0 1 1 1 DCP ILIM_H Data Lines Disconnected 0_0402_5%
Aut o
2
1 1 1 1 CDP ILIM_H Data Lines Connected
20191014
- For SDP measure
4 4

USB3.0 Conn/USB Charger
Custom 1A
A B C D E
5 4 3 2 1
D D
20190918 C
USB3 Port3 move to IO/B

B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
JIO1
42
41 GND2
40 GND1
USB3_PTX_DRX_P5 39 40
<17> USB3_PTX_DRX_P5 USB3_PTX_DRX_N5 39
20191016 38
<17> USB3_PTX_DRX_N5 38
- Change to Port5 37
USB3_PRX_DTX_P5 36 37
<17> USB3_PRX_DTX_P5
IO/B CONN <17> USB3_PRX_DTX_N5
USB3_PRX_DTX_N5
USB20_L_N3
35
34
33
36
35
34
USB20_L_P3 32 33
1 1
EMI@ LS13 31 32
USB20_N3 1 2 USB20_L_N3 USB20_L_N2 30 31
<14> USB20_N3 1 2 USB20_L_P2 30
29
1209A 28 29
28
<14> USB20_P3
USB20_P3 4
4 3
3 USB20_L_P3 - IO_B change pin define <17> USB3_PTX_DRX_P2
USB3_PTX_DRX_P2
USB3_PTX_DRX_N2
27
26 27
<17> USB3_PTX_DRX_N2 26
DLM0NSN900HY2D_4P 25
USB3_PRX_DTX_P2 24 25
SM070005U00 <17> USB3_PRX_DTX_P2 USB3_PRX_DTX_N2 23 24
<17> USB3_PRX_DTX_N2 23
EMI@ LS12 22
USB20_N2 1 2 USB20_L_N2 PCIE_PRX_DTX_N14 21 22
<14> USB20_N2 1 2 <17> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 21
20191008 20
- LAN PCIE&CLK Remove AC Cap > Vender confirm <17> PCIE_PRX_DTX_P14 20
19
USB20_P2 4 3 USB20_L_P2 (CL136/137/138/139) PCIE_PTX_DRX_N14 18 19
<14> USB20_P2 4 3 <17> PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 18
<17> PCIE_PTX_DRX_P14 17
DLM0NSN900HY2D_4P 16 17
CLK_PCIE_LAN 15 16
SM070005U00 <15> CLK_PCIE_LAN CLK_PCIE_LAN# 14 15
<15> CLK_PCIE_LAN# 14
13
USB_EN 12 13
EC_PME# <58> USB_EN 12
+3VALW 1 2 +3VALW 11
RL1 4.7K_0402_5%~D 10 11
LAN_CLKREQ# 9 10
remind : if no support wake,don't monitor this pin "PME#". <15> LAN_CLKREQ# EC_PME# 8 9
<16,58> EC_PME# PLT_RST_BUF# 7 8
<16,52,68,69> PLT_RST_BUF# 6 7
GNDA HP_PLUG# 6
<56> HP_PLUG# 5
RING2 4 5
<56> RING2 4
2
<56> SLEEVE SLEEVE 3 2
HPOUT_R_1 2 3
<56> HPOUT_R_1 HPOUT_L_1 2
<56> HPOUT_L_1 1
1
TW VM_FPC0518-40RC-TAGHT
JIO2
<56> SPKL- SPKL- 1

SPKL+ 2 1
<56> SPKL+ 2
+3VS 3
4 3
5 4
6 5
+5VALW 6
7
20191023 8 GND
- Add +3VS GND
CVILU_CI4206M2HRJ-NH
3 3
4 4

IO/B_LAN E2600
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
FAN Conn Screw Hole 20191210B
- H6 change to GNDA for Layout
Stand OFF Clips
@ H10 CLIP1 CLIP18
H_3P3 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P CLIP19 FD1
@ H2 @ H3 @ H4 @ H5 EMIST_SUL-12A2M_1P
H_3P0 H_3P0 H_4P0 H_3P0
+5VS RF4 @
1
0_0603_5% 40mil
1
1 @ 2 +VCC_FAN1 FIDUCIAL_C40M80
1
1 @ H11 CLIP2
H_3P3 EMIST_SUL-12A2M_1P CLIP7 CLIP20 FD2
CF6 @ EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
1000P_0402_50V7K @ H6 @ H7 @ H8 @ H9
2 H_4P0 H_5P6 H_4P0 H_4P0 @
1
+5VS RF7
1
0_0603_5% 40mil FIDUCIAL_C40M80
1 @ 2 +VCC_FAN2 @ H12 CLIP3
1
1 H_3P3 EMIST_SUL-12A2M_1P CLIP8 CLIP21 FD3
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
CF22 @ GNDA
1000P_0402_50V7K @ H14 @ H15 @ H16 @ H23 @
1
2 H_3P8 H_3P8 H_3P8 H_3P0X2P5
1
FIDUCIAL_C40M80
@ H13 CLIP4
H_3P3 EMIST_SUL-12A2M_1P CLIP22 FD4
1
+3VS EMIST_SUL-12A2M_1P
1
1
1 @ H17 @ H18 @ H19 @ H21
1
RF3 CF13 H_2P5 H_3P0 H_3P0 H_5P6 FIDUCIAL_C40M80
10K_0402_5% 4.7U_0402_6.3V6M @ H20 CLIP5
CONN@ H_3P3 EMIST_SUL-12A2M_1P CLIP23
2 JFAN1 EMIST_SUL-12A2M_1P
2
1
+VCC_FAN1 1
2 1
<58> FAN_SPEED1
1
FAN_PWM1 3 2
<58> FAN_PWM1
1
4 3
1 4
CF7 5 @ H22 CLIP6 CLIP17
1000P_0402_50V7K 6 G1 @ H24 @ H25 H_3P3 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
XEMI@ G2 H_1P4X3P5 H_1P4X4P6
2 ACES_50278-00401-001
SP02000RR00
1
1
1
+3VS
Turbo Key
1
1
RF5 CF12
10K_0402_5% 4.7U_0402_6.3V6M
CONN@
2 JFAN2
2
+VCC_FAN2 1
2 1
<58> FAN_SPEED2 FAN_PWM2 2 +5VALW
3 CONN@
<58> FAN_PWM2 3
1 4 JTRB1
CF10 5 4 1
1000P_0402_50V7K 6 G1 TURBO_LED# 2 1
G2 <58> TURBO_LED# TURBO_EN# 2
XEMI@ 3 5
2 <58> TURBO_EN# 3 G1
ACES_50278-00401-001 4 6
4 G2
SP02000RR00 ACES_51575-00401-001
SP01002LG00
+3VLP 1 @ 2
MAINPWON <58,84,87>
R23 0_0402_5%
Reset Circuit
1 @ 2
EC_RST# <58>
2
R24 0_0402_5%
R25
10K_0402_5%
1
Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
2N7002KDW_SOT363-6
side S
1
1
3
Q1B D C40
BI_GATE 5 0.1U_0201_10V6K
<84> BI_GATE G 2
2N7002KDW_SOT363-6
S
4
Reset Button
@
SW3
BI_GATE 1 2 BI_GATE
3 4
SKRPABE010_4P
SN10000CV00
change PN to SN10000CV00

FAN & Screw Hole
A B C D E
System DC inferface For Power ON/Off Sequence

@
CQ2 1 2 0.1U_0201_10V6K UQ1 @ JPQ2 PM_SLP_S3
1 14 +5VS_OUT 1 2 +3VALW
+5VALW VIN1 VOUT1 1 2 +5VS
2
2 13
G
VIN1 VOUT1
1
JUMP_43X118
SUSP# RQ1 1 @ 2 0_0402_5% 5VS_ON 3 12 1 2 R37 Q10A
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5% 2N7002KDW_SOT363-6
4 11 1 6
S
+5VALW VBIAS GND EC_VCCST_PG_R <10,58>
D
1 1
2
RQ2 2 @ 1 0_0402_5% 3VS_ON 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion
5
@ 6 9 @ JPQ1
G
+3VALW VIN2 VOUT2 +3VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +3VS
Q10B
15 JUMP_43X118 2N7002KDW_SOT363-6
GPAD Q11A 4 3
S
VR_ON <58,92,97>
D
EM5209VF_DFN14_2X3 2N7002KDW_SOT363-6 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<18,58> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
G
2 2 2 2
S
1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
Place CQ7 close UQ1 pin 1&2
G
@
Place CQ8 close UQ1 pin 6&7 Q12A
2N7002KDW_SOT363-6
1 6
S
SYS_PWROK <18,58>
D
5
G
+3VALW @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ Q12B
2N7002KDW_SOT363-6
1
4 3
S
PCH_PWROK <18,58>
2
D
R38
2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @
2
2 PM_SLP_S4 2
1
1
discharge Q13A
5
SUSP discharge SYSON# 2N7002KDW_SOT363-6 D
G
trace 20 mils 2
trace 20 mils <18,58> PM_SLP_S4# G Q13B
2N7002KDW_SOT363-6
6
Q7A D D Q7B S 4 3 SYSON
S
1
3
D
2 5 SUSP Q8B D D Q8A MOW14, For tPLT15 200us(max)
<39,58,68,85,89,92> SUSP# G G SYSON 5 2 SYSON# SLP_S4# to VDDQ ramp down
<58,89> SYSON G G
@ @
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
4
1
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
R32 @ @
10K_0402_5% P/N: SB00000EO00 footprint use SB00000ZU00
@
2
+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW
@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1.05V_VCCST_OUT RQ5 1 @ 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0201_6.3V6M
VIN1 VOUT1 1 UC4 +1.05VS_VCCSTG
SYSON RQ4 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1
4 11 VIN2
+5VALW VBIAS GND 7 6
SUSP# RQ8 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1.8VS_OUT VBIAS 2
+1.8VALW
6 9 RQ9 1 @ 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 @ 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2
+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us
+1.05VALW +1.8VALW +1.05V_VCCST_OUT +1.8VS_OUT
2 2 2 2
CQ11 CQ24 CQ9 CQ22
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1 1 1
4 4


DC Interface
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. GXXXX LA-XXXXP
5 4 3 2 1
A B C D E
1
@ PJP101
+19V_ADPIN FBMA-L11-201209-800LMA50T
EMI@ PL101 +19V_VIN 1
1 1 2
1 2 EMI@ PL102
2
EMI@ PC104
3
1000P_0402_50V7K
FBMA-L11-201209-800LMA50T
3
1
4
EMI@ PC102
PR103
100P_0402_50V8J
4 5 1 2 PR102
5
1
6 4.7_1206_5% EMI@ PL103
6
1
7 FBMA-L11-201209-800LMA50T 4.7_1206_5%
2
7 8
2
8 9 1 2
2
9
1
10
10
1
EMI@ PC101
EMI@ PC105
0.1U_0402_25V7K Bead SM01000U600
2
0.1U_0402_25V7K
2
SINGA_2DC3207-000111F
2 2
ADAPDET <85>
3 3
@0@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
4 4

DCIN
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
A B C D E
+3VLP
1
@EMI@
1 PC205 1
0.1U_0603_25V7K
1
@
PR207 100_0402_1% @ PR215 PR214
100K_0402_1%
1 2 26.7K_0402_1% 21.5K_0402_1%
EC_SMB_DA1 <58,85>
PR213
PR205 100_0402_1%
2
1
1 2
EC_SMB_CK1 <58,85>
PU201 @
1 8
VCC TMSNS1
(Common Part)
PR202 2 7 2 1
Battery Bot Side <45,47> SL200002H00
2
200K_0402_1% GND RHYST1
@
1
1 2 MAINPWON 3 6 @ PR216
+3VLP <58,77,87> MAINPWON OT1 TMSNS2
100K_0402_1%_NCP15WF104F03RC
@ PJP201 10K_0402_1% @
PIN1 GND 1 4 5
1 2 OT2 RHYST2
PIN2 GND 2 3 EC_SMB_DA1-1
1 2
BATT_TEMP <58,85>
PH202
G718TM1U_SOT23-8
PIN3 SMD
2
3 4 EC_SMB_CK1-1 PR203 1K_0402_1%
4 5 BATT_TS
PIN4 SMC 5 6 BATT_B/I
PIN5 TEMP 6 7 PH202 Near fan.
7 8
PIN6 BI 8 9 +RTCVCC
GND 10
PIN7 Batt+ GND
PIN8 Batt+ CVILU_CI9908M2HR0-NH
1
PR212
100K_0402_5%
1
2 D 2
2 PQ201
<77> BI_GATE G LBSS139LT1G 1N SOT-23-3
+17.4V_BATT+ S
3
EMI@ PL201
FBMA-L11-201209-800LMA50T
1 2 BI_S
+17.4V_BATT
EMI@ PL202 When PR204=18.7K
1
FBMA-L11-201209-800LMA50T @0@
1 2 PR217 For KB9022
0_0402_5% OTP Active Recovery
2
design reserve VCIN0_PH(V) 89'C, 1V 56'C, 2V
1
PC201 EMI@ PC202 EMI@
1000P_0402_50V7K 0.01U_0402_50V7K
2
+3VLP_ECA PH202(ohm) 8.0524K 26.11K
3/27 thermal PH1 92'C ->89'C
1
+3VLP_ECA
PR218 VGA@ PR206
16.5K_0402_1% 10K_0402_1%
1 2
ADP_I <58,85>
1
3 <58> VRAM_TEMP 3
PR204
18.7K_0402_1%
VCIN1_ADP_PROCHOT <58>
2
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
VCIN0_PH <58>
1
1
(Common Part) PC203 must close to EC pin
1
PH203 @VGA@
PH204 VGA@
PR208
SL200002H00 PH201
10K_0402_1%
2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2
2
0.1U_0402_25V6
1
PH203 Near VGA CORE CHOKE.
@ T1 PH201 is Common Part SL200002H00
@ T2
ECAGND <58>
PH204 Near VRAM CHOKE. T202 T201 must close to PH201
ADP_I=20*I(adapter)*0.01
4
I(adapter)=adapter(W)*130%/19 4

BATTERY CONN/OTP
Custom 0.1
A B C D E
5 4 3 2 1
PRB1
1
D
1M_0402_1%
2 1 2 PQB1
+19VB PQB2
G L2N7002WT1G_SC70-3 AON7380_DFN3X3-8-5 +17.4V_BATT_CHG
PRB2 S 1
3
2 1 2
+19V_P1 +19V_P2 5 3
PQB3 3M_0402_5% PQB4
EMP21N03HC_EDFN5X6-8-5
1 1
AON7380_DFN3X3-8-5 PRB3
0.005_1206_1% EMI@ PLB1
+19V_CHG
4
2 2 5A_Z80_0805_2P
5 3 3 5 1 4 1 2
+19V_VIN
10U_0603_25V6M
680P_0402_50V7K
EMI@ PCB5 2200P_0402_50V7K
PCB6 10U_0603_25V6M
PCB9 10U_0603_25V6M
EMI@ PCB29
EMI@ PCB30
EMI@ PCB4 0.1U_0402_25V6
EMI@ PCB8 0.1U_0402_25V6

2 3
1
D D
0.047U_0603_25V7M
4
4
1000P_0402_50V7K
PCB2
1 2
2
1
1
PCB1
PCB3
ACP ACN
1
4.7_0603_1%
0.022U_0603_25V7K
PRB4
4.02K_0402_1%
2
10_0402_1%
1
1
PCB11
2
PCB10
10U_0603_25V6M
0.1U_0402_25V6 PCB7
PRB5
PRB6
10U_0603_25V6M
2 1 1 2 1 2
1
PCB13
PCB14
0.01U_0402_25V7K~N @
2
0.1U_0603_25V7K
2
@
PRB7
+19V_VIN 4.02K_0402_1% BATDRV_CHG
Close to B2B first mos 1 2 ACDRV_CHG
1
PRB37
PRB8 PRB9
1 2 0_0402_5% 0_0402_5%
2 1CMSRC_CHG BATSRC_CHG
PRB10
2
1
10K_0402_50%_TPM0S103P130R
PRB38 4.02K_0402_1%
+19V_VIN 0_0402_5%
ACN_CHG
ACP_CHG
PDB1 PRB12 @ PCB15
S SCH DIO BAS40CW SOT-323 10_0805_5% 1000P_0402_50V7K
1 2
1
499K_0402_1%
3 1 2
+19V_VIN
PRB35
1 2 1
PRB11 2 ACDRV_CHG
+19VB
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB17 PQB5
2
2.2U_0603_16V6K
2
AON7506_DFN33-8-5
<82> ADAPDET ACDET PUB1
1 2 Choke 4.7uH SH00000YC00 (Common Part)
ACDRV
ACP
ACN
1
1
215K_0402_1%
68.1K_0402_1% 0_0402_5%
L2N7002WT1G_SC70-3
28
VCC (Size:6.6 x 7.3 x 3 mm)
1
D
PRB36
PRB39
CMSRC_CHG 3 (DCR:28m~33m)
PQB11
2 24
CMSRC REGN
1
G PRB16 PCB19 4
S PCB18 6 0_0603_5% 0.047U_0603_25V7M
2
2200P_0402_25V7K ACDET 25 BST_CHG 1 2BST_CHG_R 1 2

2
C EC_SMB_DA1_CHG 11 BTST C
PRB17 1 2 0_0402_5%
<58,84> EC_SMB_DA1 SDA
1
+17.4V_BATT
3
2
1
EC_SMB_CK1_CHG 12 UG_CHG
PRB13
PRB14 1 2 0_0402_5% 26 PRB19

<58,84> EC_SMB_CK1 SCL HIDRV PLB2 0.01_1206_1%
ACPRN_CHG 5 4.7UH_PCMB063T-4R7MS_8A_20%
<58,84> ADP_I PCB20 ACOK 27 LX_CHG 1 2 1 4
2
1 2 PRB181 2 0_0402_5% 7 PHASE

IADP 2 3
1
LG_CHG
4.7_1206_5%
100P_0402_50V8J 8 23 PQB6
Close to EC IDCHG LODRV
EMI@ PRB20
<58> IDCHG 9
AON7506_DFN33-8-5
@ PCB21 PMON
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
1 2 10 22 PRB21 316K_0402_1% SRP SRN
1SNUB_CHG 2
/PROCHOT GND
1
PCB22
PCB23
PCB24
1 2
@0@ 100P_0402_50V8J +3VLP 4
PRB22 PRB23 150K_0402_1%
2
0_0402_5% 13 21 ILIM_CHG 1 2
1 2 GND ILIM PRB24 @
<10,58> H_PROCHOT#
680P_0402_50V7K
@0@ 14 10_0402_1%
3
2
1
NC SRP_CHG
EMI@ PCB25
PRB25 20 1 2 ILIM=charge current limit
0_0402_5% SRP
1 2 15 19 SRN_CHG 1 2 Rsr=input current sense
2
/BATPRES SRN I(CHG_LIM)=V(ILIM)/(20*Rsr)
BATDRV_CHG
PRB26 =(3.3*150/466)/(20*0.01)
16 18 10_0402_1% PCB26
/TB_STAT BATDRV 0.1U_0402_25V6
=5.31A
29 17 BATSRC_CHG 1 2
PWPD BATSRC
<58,84> BATT_TEMP
BQ24781RUYR_WQFN28_4X4
0.1U_0402_25V6
0.1U_0402_25V6
H/L Side AON7506 SB000010A00
Rds(on):13~15.8mohm
1
PCB27
PCB28
Vgs=20V
Vds=30V
2
ID= 10.5A (Ta=70C)
B B
+3VS
For 4S per cell 4.35V battery +6V_CHG_REGN
ACDET
1
1
PRB27
1
10K_0402_1% @ PRB29 @ PRB30

PRB28 PRB31 10K_0402_1% 10K_0402_1%
2M_0402_1% 10K_0402_1%
2
1 2 ACPRN_CHG
<58> ACIN
2
DGPU_AC_DETECT <19,33,58>
2
PRB32
1
PRB33 12K_0402_1% @ PQB7A
6
0_0402_5% D 2N7002KDW_SOT363-6
2
2
G
2
1
S
1
1
@ PQB9 @ PQB7B
3
PQB8 RUM001L02_VMT3 D 2N7002KDW_SOT363-6
PRB34 LTC015EUBFS8TL_UMT3F H_PROCHOT# 2 ACIN 5
100K_0402_1% G
1 2 2
<58> BATT_4S S
4
3
3
1
D
A 2 PQB10 A
<39,58,68,78,89,92> SUSP#
G L2N7002WT1G_SC70-3
S
3

PWR_CHARGER
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
A B C D E
PR301
499K_0402_1%
ENLDO_3V5V 1 2
EN1 and EN2 dont't floating
+19VB
1
150K_0402_1%
+19VB
PR302
EMI@ PL311 @0@ PR303 PC301
FBMA-L11-201209-800LMA50T 0_0603_5% 0.1U_0402_25V7K Choke 2.2uH SH00000YV00 (Common Part)
1
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2 1
2200P_0402_50V7K
7x7X3
10U_0603_25V6M
10U_0603_25V6M
2
Isat:10A
EMI@ PC302
EMI@ PC304
0.1U_0402_25V6
1
1
DCR:13.5mΩ /15mΩ
PC305
PC306
PU301
SY8288BRAC_QFN20_3X3
1
2
2
PL301 Imax=4.9A, Ipeak=7A, Iocp:8.4A
BS
IN
IN
IN
IN
2.2UH_7.8A_20%_7X7X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18 @EMI@
+3VALWP GND GND
@ PC307
PC308
PC309
@ PC310
PC311
PC312
PR304
SPOK_3V 9 17 4.7_1206_5%
+3VLP
2
PG LDO
SN_3V 2
1
10 16
NC NC
1
PC313
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR305 GND
100K_0402_5%
11
12
13
14
15
1
@EMI@
2
PC314
680P_0402_50V7K
Vout is 3.234V~3.366V
<58,90> SPOK_3V
2
3.3V LDO 150mA~300mA
ENLDO_3V5V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
FB_3V 1 2 FB_3V_R 1 2
<58> 3V_EN
@ PJ302
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
2 2
keep short pad,

snubber is for EMI only.
+19VB EMI@ PL511 @0@ PR501 PC501

FBMA-L11-201209-800LMA50T 0_0402_5% 0.1U_0402_25V7K
1 2 +19VB_5V BST_5V 1 2 BST_5V_R 1 2
Choke 1.5uH SH000016700 (Common Part)
2200P_0402_50V7K
0.1U_0402_25V6
7x7X3
10U_0603_25V6M
10U_0603_25V6M
PU502
Isat:18A
5
SY8288CRAC_QFN20_3X3
1
DCR:14mΩ /15mΩ
@EMI@ PC517
PC502
PC503
EMI@ PC504
BS
IN
IN
IN
IN
LX_5V6 20 PL501 Imax=4.9A, Ipeak=7A, Iocp:8.4A

2
LX LX 1.5UH_9A_20%_7X7X3_M
7 19 LX_5V 1 2
GND LX +5VALWP
8 18
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VLP
1
9 17 VCC_5V 1 2
PG VCC
1
PR502
PC507
PC508
PC509
PC510
PC511
PC512
PC518
4.7_1206_5%
@EMI@
10 16 PC506
2
NC NC
1
2.2U_0402_6.3V6M
OUT
LDO
EN2
EN1
21 @
FF
PR503 GND
2
100K_0402_5%
11
12
13
14
15
2
1SN_5V
3 +5VLP 3
680P_0402_50V7K
5V LDO 150mA~300mA
4.7U_0402_6.3V6M
<58> SPOK_5V
1
ENLDO_3V5V @EMI@
PC514
PC513
2
2
PR504
2.2K_0402_5% 5V_EN
1 2 Iocp=12A
<58> EC_ON @0@ PR505
0_0402_5%
1 2 EN1 and EN2 dont't be floating.
<58,77,84> MAINPWON EN :H>0.8V ; L<0.4V PC515 PR506 @ PJ502
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
FB_5V 1 2 FB_5V_R 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_EN
1M_0402_1%
1
1
PR507
PC516
4.7U_0402_6.3V6M
2
2
4 4

+3VALW/+5VALW
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
A B C D E
Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +19VB_1.2VP PRM11 Peak Current 1A
+19VB EMI@ PLM11 2.2_0603_5%
HCB2012KF-121T50_0805 BST_1.2VP_R 1 2 BST_1.2VP
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
+1.2VP
1
PCM2
PCM3
PCM4
EMI@ PCM20
UG_1.2VP +0.6VSP
1
1 1
EMI@
PCM5
0.1U_0603_25V7K LX_1.2VP
22U_0603_6.3V6M
10U_0603_6.3V6M
2
1
PCM6
PCM7
16
17
18
19
20
4 PUM1
2
@
VLDOIN
BOOT
VTT
PHASE
UGATE
21
PAD
PQM1 LG_1.2VP 15 1
1
2
3
LGATE VTTGND
AONR32320C_DFN3X3-8-5
IOCP
14 2
PLM1 PRM1 PGND VTTSNS
1UH_11A_20%_7X7X3_M 20K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW_WQFN20_3X3 GND
1
1U_0201_6.3V6K
5
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM2 PRM3 VDDP VTTREF
4.7_1206_5% 5.1_0603_5% 35.4
1 2 VDD_1.2VP 11 5
PCM9
PCM10
PCM11
PCM12
PCM13
PCM14
+1.2VP
2
VDD VDDQ
1
PGOOD
PCM16
1 1 1 1 1 1 4 +5VALW 2 1
TON
1
SN_1.2VP
PCM17 0.033U_0402_16V7K
FB
S5
S3
2
1
@
PDM1
PQM2 1U_0201_6.3V6K 30MA_30V_0.5UA_0.4V_SOD323-2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10
6
2 2 2 2 2 2 AON7506_DFN3X3-8-5 PRM4
35.4
1
2
3
2.2_0402_1%
1
FB_1.2VP
2
EN_1.2VP
@EMI@ PCM15 PRM5
EN_0.6VSP
680P_0402_50V7K 6.34K_0402_1%
TON_1.2VP
+5VALW +1.2VP
2
Frequency 1 2
PRM6
470K_0402_1%
1
+19VB_1.2VP 1 2
2
Vout=0.75V* (1+Rup/Rdown) 2
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm @0@ PRM8 PRM7 =0.75*(1+(6.34/10))
0_0402_5% 10K_0402_1%
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A 1 2 =1.2255V 2.1%
2
<58,78> SYSON
L/S AON7506 Rds(on) :typ:13m Ohm, max:15.8m Ohm
1
@ PCM18
Idsm(TA=25)=12A, Idsm(TA=70)=10.5A 0.1U_0402_16V7K
2
Choke 1uH SH00000YE00 (Common Part) Choke: SH00000YE00 Size:7x7x3 (Common Part)
Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC @
(Size:6.86 x 6.47 x 3 mm) PRM9
(DCR:6.2m~7.2m Ohm) Rdc=Xmohm(Typ), 11mohm(Max) TOKO 0_0402_5%
Isat:15A Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers 1 2
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech <39,58,68,78,85,92> SUSP#
@ PJM2
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin
Mode Level +0.675VSP VTTREF_1.35V Rdc=6.9± 15% Panasonic @0@ PRM10 JUMP_43X118
0_0402_5% +1.2VP 1 2 +1.2V_VDDQ
S5 L off off 1 2 1 2
S3 L off on Switching Frequency: 530kHz <10> SM_PG_CTRL
S0 H on on Imax=A, Iocp=A
1
@ PCM19 @ PJM3
Iocp=10.63~12.76A JUMP_43X39
Note: S3 - sleep ; S5 - power off OVP: 110%~120% 0.1U_0402_16V7K 1 2
+0.6VSP +0.6VS_VTT
2
1 2
VFB=0.607V, Vout=1.214V
+3VALW
3 3
+5VALW
1
@ PJ2501
1
JUMP_43X39
2
2
PC2501
1U_0402_6.3V6K
2
1
PC2502
PU2501
FB=0.8V
22U_0603_6.3V6M Note:Iload(max)=4A
2
G9661MF11U_SO8 @ PJ2502
@0@ PR2501 4 5 JUMP_43X39
0_0402_5% VIN_2.5V 3 VPP NC 6 1 2
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP +2.5VP 1 2 +2.5V
GND
1 VEN ADJ 8
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND
1
0.1U_0402_16V7K
PR2503
PC2504
9
1
PR2502
Rup
PC2503
PC2505
@ PC2506
21.5K_0402_1%
2
1M_0402_5%
2
2
2
@ FB_2.5V
1
PR2504
10K_0402_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
2
4 4

+1.2VP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
A B C D E
5 4 3 2 1
D D
PR1809
100K_0402_5%
2 1
+3VALW
Choke 1uH SH00000Z200 (Common Part)
PG_1.8VALWP PG_1.8VALWP <91> 5x5x3
Isat:11A
DCR:13mΩ /14mΩ
EMI@ PL1802
+19VB FBMA-L11-201209-800LMA50T PU1801
1 2 +19VB_1.8VALWP 2 9 @0@ PR1808 PC1810 @EMI@ PR1802 @EMI@ PC1806
IN PG
10U_0603_25V6M
0_0603_5% 0.1U_0402_25V7K 4.7_1206_5% 680P_0402_50V7K
BST_1.8VALWP1 SNB_1.8VALWP
2200P_0402_50V7K
0.1U_0402_25V6
3 1 2 1 2 1 2 1 2
IN BS
1
1
PC1816
PC1815
PC1801
4 6
IN LX
2
2
5 19 PL1801 Imax=2.16A, Ipeak=3.09A, Iocp:6.2A
IN LX 1UH_6.6A_20%_5X5X3_M
LX_1.8VALWP
+1.8VALWP
EMI@
EMI@
7 20 1 2
GND LX
FB_1.8VALWP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8 14
GND FB
1
@0@ PR1801 18 17 LDO_1.8VALWP
GND VCC (R1)
330P_0402_50V7K
PC1812
PC1813
PC1814
PC1804
PC1805
PC1817
0_0402_5%
1
1 2 11 10 PC1809
2
EN NC
1
<58,87> SPOK_3V
PC1803
2.2U_0402_6.3V6M PR1803
ILMT_1.8VALWP 13 12 20.5K_0402_1%
2
ILMT NC @ @
2
1
C 15 16 C
+3VALW
2
BYP NC
1
PR1805
1M_0402_1% @ PC1811 21 PR1810
PAD
1
0.47U_0402_6.3V6K 1K_0402_1%
2
SY8286RAC_QFN20_3X3 1 2
2
LDO_1.8VALWP PC1807
2
FB = 0.6V
1U_0201_6.3V6M
1
@0@ @ PJ1801
PR1807 JUMP_43X79
1
0_0402_5% 1 2
PR1804 +1.8VALWP 1 2 +1.8VALW
2
ILMT_1.8VALWP 10K_0402_1%
(R2)
1
2
@
PR1806 Vout=0.6V* (1+Rup/Rdown)
0_0402_5% Vout=0.6V*(1+20.5/10)
=1.83V (x1.017)
2
8288RAC
Min
ILMT='0' 8A
ILMT=Floating 12A
ILMT='1' 16A
B B
A A

+1.8VALW
0.1
5 4 3 2 1
A B C D E
1 1
Choke 1uH SH00000YE00 (Common Part)

(Size:6.86 x 6.47 x 3 mm)
(DCR:6.2m~7.2m Ohm)
Choke: SH00000YE00 Size:7x7x3 (Common Part)
Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC
Rdc=Xmohm(Typ), 11mohm(Max) TOKO
Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin
Rdc=6.9± 15% Panasonic
+19VB_1VALW
EN pin don't floating @EMI@ PR1101 @EMI@ PC1101
4.7_1206_5% 680P_0402_50V7K @ PJ1101
If have pull down resistor at HW side, pls delete PR702 SNUB_1VALW
+19VB @ PJ1102
JUMP_43X79
+19VB_1VALW
PU1101 @0@ PR1102
1 2 1 2
+1.05VALWP
JUMP_43X118
1
1 2
2
+1.05VALW
1 2 2 9 PC1106
1 2 IN PG 0_0603_5% 0.1U_0402_25V7K
10U_0603_25V6M 3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL1101
0.1U_0402_25V7K
2200P_0402_50V7K
IN BS
1
1 1UH_6.6A_20%_5X5X3_M
EMI@ PC1102
EMI@ PC1103
PC1105
LX_1VALW
4
IN LX
6 1 2
+1.05VALWP
2
2 5 19 2
15.4K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
7 20
PR1104
PC1107
PC1108
PC1109
PC1110
PC1111
@ PC1116
GND LX
8 14 FB_1VALW Rup
2
GND FB PR1110
2
18 17 LDO_3V_1VALW 1K_0402_1%
GND VCC 1 2
1
EN_1VALW 11 10
EN NC PC1113 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
LDO_3V_1VALW ILMT NC
15 16 PR1106
+3VALW BYP NC Rdown 20K_0402_1%
1
21
2
@0@ PAD
PR1103 SY8288RAC_QFN20_3X3
1
0_0402_5%
PC1114
2
ILMT_1VALW 1U_0201_6.3V6M
2
1
@
PR1105
Vout=0.6V* (1+Rup/Rdown)
0_0402_5% =0.6*(1+(15.4/20))
Vout=1.062V
2
PR1107
10K_0402_1%
1 2 PG_1.8VALWP PG_1.8VALWP <90>
8288RAC
Min @ PR1108
ILMT='0' 8A 10K_0402_1%
ILMT=Floating 12A EN_1VALW 1 2
ILMT='1' 16A +3VALW
1
3 3
@ PC1115
PR1109
0.22U_0402_16V7K
2
1M_0402_1%
2
4 4

+1.05VALWP
A B C D E
5 4 3 2 1
D D
Choke: SH00000Z300 (Common Part)

Isat=14A
Rdc=10mohm(Typ), 12mohm(Max) Size:6*5.4*3 Tai-Tech
Rdc=11mohm(Typ), 12mohm(Max) Size:5.3*4.9*3 Maglayers
@EMI@ PRH1 @EMI@ PCH1 @ PJH1
can improve CNVI lose issue 4.7_1206_5% 680P_0402_50V7K 1 2
1 2 SNB_VCCIOP 1 2 +1.0VS_VCCIOP 1 2 +VCCIO
JUMP_43X118
EMI@ PLH11
HCB2012KF-121T50_0805
1 2
PUH1 @0@ PRH2

+19VB_VCCIOP 2 9 0_0603_5% PCH4
+19VB IN PG 0.1U_0402_25V7K
3 1 BST_VCCIOP 1 2BST_VCCIOP_R 1 2 PLH1
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
PCH2 0.68UH_7.9A_20%_5X5X3_M
PCH3
PCH5
LX_VCCIOP
2
4
IN LX
6 1 2
+1.0VS_VCCIOP
1
5 19
PCH10
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
@EMI@
1
EMI@
7 20
PCH6
PCH7
PCH8
PCH9
Note:Iload(max)=5.5A
PCH11
PCH12
10_0402_1%
2
GND LX @
PRH3
8 14 FB_VCCIOP
IOCP=7A~8A(typ)
2
GND FB
2
PRH4
1K_0402_1%
18 17 LDO_3V_VCCIOP @
2
GND VCC
1
EN_VCCIOP 11 10 PCH13 @
EN NC 2.2U_0402_6.3V6M
1
ILMT_VCCIOP 13 12 FB = 0.6V Rup
2
ILMT NC 1 2 =0.6*(1+(12.4k/20.5k))
15 16
+3VALW BYP NC PRH5 OVP=0.95V*115%=1.0925V
1
21 12.4K_0402_1%
C PCH14 PAD Vout=0.962V C
20.5K_0402_1%
1
1U_0201_6.3V6M SY8286RAC_QFN20_3X3
Rdown
2
PRH6
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
2
PRH7 @0@ 0_0402_5%
VCC_SENSE_VCCIO_R 1 2 VCC_SENSE_VCCIO
LDO_3V_VCCIOP VCC_SENSE_VCCIO <12>
PRH8 @0@ 0_0402_5%

1
@ PRH9 1 2 VSS_SENSE_VCCIO
VSS_SENSE_VCCIO <12>
0_0402_5%
@ PRH10 VR_ON 1 2
0_0402_5% <58,78,97> VR_ON
2
ILMT_VCCIOP PRH11
1K_0402_5%
1
SUSP# 1 2 EN_VCCIOP
<39,58,68,78,85,89> SUSP#
@ PRH12
0.1U_0402_25V6
1M_0402_5%
1
1
PCH15
check delay time with HW
PRH13
0_0402_5%
2
2
2
8286RAC
Min Typ Max
ILMT='0' 6.5A 7.5A 8.5A
ILMT=Floating 9.5A 10.5A 11.5A
ILMT='1' 12.5A 13.5A 14.5A
B B
A A

+VCCIOP
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
1 2 3 4 5
Place close to Choke in VCCSA first phase circuit

PHZ1 PRZ1 PRZ2 PR1199 NA, need confirm
100K_0402_1%_TSM0B104F4251RZ 12K_0402_1% 7.5K_0603_1%
PCZ1 1 2 1 2 1 2
PRZ3 100_0402_1% 2200P_0402_50V7K
<99> CSN_1PH SW_1PH <99> +1.05V_VCCST
1
1 2 1 2 PCZ2
100_0402_1%
1
2
PRZ4 0.01U_0402_50V7K
499_0402_1%
45.3_0402_1%
45.3_0402_1%
A @0@ PRZ9 PRZ10 10_0402_1% 1 2 PCZ3 A
PRZ5
PRZ6
PRZ7
PRZ8
0_0402_5% 1K_0402_5% 0.1U_0402_25V6
1
1 2 1 2 VSN_1PH
<12> VSS_SENSE_SA
2
@
2
2
2 1 1 2 @
PCZ4 LA-F611PR01_0531D.DSN
CSP_1PH
1000P_0402_50V7K PRZ12 PCZ5 PCZ6 PRZ13 PROCHOT# change to H_PROCHOT#(P.72 PUZ01.39)
470P_0402_50V8J
1
1.62K_0402_1% 3300P_0402_50V7-K 2200P_0402_50V7K 100_0402_1%
LA-F611PR01_0531C.DSN
1
1 2 1 2 VSP_1PH CSN_1PH_R 81215_VR_HOT
1 2
PCZ7
29.4K_0402_1%
<12> VCC_SENSE_SA +3VS PCH_PWROK change to IMVP_VR_PG(P.72 PUZ01.45) VR_HOT# <58>
PRZ14
@0@ PRZ11 PCZ8
2
PRZ15 100_0402_1% 0_0402_5% 1 2 1000P_0402_50V7K SVID_CLK_PWR_CPU
1 2
CPU_SVID_CLK_R <10>
1 2 1 2 PRZ16 49.9_0402_1%
IMON_1PH
+VCC_SA PWM1_1PH/ICCMAX1 <99>
1
PCZ9
1000P_0402_50V7K PRZ19 SVID_ALERT#_PWR_CPU
2 1
CPU_SVID_ALERT#_R <10>
12.4K_0402_1% PRZ17 @0@ PRZ18 0_0402_5%
2 1 10K_0402_1% PRZ23
PRZ21 100_0402_1% 34.8K_0402_1% SVID_DAT_PWR_CPU
1 2
<58> VCCCORE_VR_PWRGD CPU_SVID_DAT_R <10>
2
1 2 PRZ22 PCZ10 PRZ20 10_0402_1%
+VCC_CORE 1.5K_0402_1% 0.01U_0402_25V7K 1 2
@0@ PRZ24 2 1 2 1 CPU_EN
0_0402_5% SVID_CLK_PWR_CPU
<11> VCC_SENSE_IA
1 2 VSP_4PH SVID_ALERT#_PWR_CPU 1 2
VR_ON <58,78,92>
LA-F611PR01_0531C.DSN
SVID_DAT_PWR_CPU
1 2 IMVP_VR_ON change to VR_ON(P.72 PUZ01.43)
2
@0@ PRZ25
PCZ12 PCZ11 0_0402_5% PRZ26 100_0402_1%
1000P_0402_50V7K PRZ28 15P_0402_50V8J 1 2 +VCC_GT
1
1.69K_0402_1%
1 2 1 2 VSN_4PH VSN_1PH @0@ PRZ30
<11> VSS_SENSE_IA
0_0402_5%
ILIM_1PH
COMP_1PH
@0@ PRZ27 1 2 VCC_SENSE_GT <11>
PRZ29 100_0402_1% 0_0402_5% 1 2 VSP_1PH
1 2
1
PCZ13 PCZ14
2200P_0402_50V7K PRZ31 1000P_0402_50V7K
1.37K_0402_1%
2
1 2 1 2
VSS_SENSE_GT <11>
@0@ PRZ32
PUZ1 1 2 0_0402_5% PRZ33 100_0402_1%
PCZ16 PRZ34 PCZ17 NCP81215PNTXG_QFN52_6X6 1 2
53
52
51
50
49
48
47
46
45
44
43
42
41
40
15P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J PCZ15
B B
1 2 1 2 1 2 PRZ35 2200P_0402_50V7K
TAB
VR_RDY
SCLK
ALERT#
SDIO
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
PWM_1PH/ICCMAX_1PH
EN
26.1K_0402_1%
PRZ36 PRZ37 2 1 PRZ38 PCZ19 PCZ20
3.65K_0402_1% 1K_0402_1% PRZ39 49.9_0402_1% 470P_0402_50V8J 15P_0402_50V8J
1 2 1 2 1 2 29.4K_0402_1% 1 2 1 2 1 2
PCZ21 VSP_4PH 1 39 81215_VR_HOT 1 2
PCZ18 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PCZ23 2 1 1 2 1 2
2200P_0402_50V7K 2 1 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 PRZ40 PRZ41 PCZ22
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
COMP_4PH 6 FB_4PH DIFFOUT_2PH 34 FB_2PH
1 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
Place close to Choke in VCORE CSCOMP_4PH ILIM_4PH COMP_2PH ILIM_2PH
PRZ42 18.7K_0402_1% 8 32 1 2
first phase circuit CSCOMP_4PH ILIM_2PH
1
CSSUM_4PH 9 31 PRZ43 12K_0402_1% CSCOMP_2PH

75K_0402_1%
1
PHZ2 10 CSSUM_4PH CSCOMP_2PH 30 CSSUM_2PH
75K_0402_1%
PRZ44
680P_0402_50V7K
220P_0402_50V8J
CSP1_4PH 11 CSREF_4PH CSSUM_2PH 29 PHZ3
PRZ45
680P_0402_50V7K
82P_0402_50V8J
CSP1_4PH CSREF_2PH
1
CSP2_4PH CSP1_2PH
PWM1_4PH/ICCMAX_4PH
PWM1_2PH/ICCMAX_2PH
220K_0402_5%_ERTJ0EV224J 12 28 220K_0402_5%_ERTJ0EV224J
PCZ24
PCZ25
PWM4_4PH/ROSC_MPH
CSP2_4PH CSP1_2PH
2
1
CSP3_4PH
PWM2_2PH/ROSC_1PH
PCZ26 13 27 2 1 Place close to Choke in VCCGT first phase circuit
PCZ27
PCZ28
+5VALW
2
1 2
CSP3_4PH CSP2_2PH
TTSENSE_1PH/PSYS
PRZ47
165K_0402_1%
2
PWM3_4PH/VBOOT
1
191K_0603_1% 0.1U_0402_25V7K PRZ46
PWM2_4PH/ADDR
1
2
1 2 1K_0402_1% PCZ29
PRZ48
<97,98> SW1_4PH
1
TTSENSE_2PH
PRZ50 0.1U_0402_25V7K
TSENSE_4PH
2
191K_0603_1% PRZ49
CSP4_4PH
1 2 165K_0402_1%
<97,98> SW2_4PH
2
PRZ52 PRZ51
DRON
VRMP
191K_0603_1% 80.6K_0603_1%
VCC
2
1 2 2 1 1 2
<97,98> SW3_4PH SW1_2PH <97,99>
PRZ54 +5VALW
191K_0603_1% PRZ55 @ PRZ53
14
15
16
17
18
19
20
21
22
23
24
25
26
1 2 1K_0402_1% 1K_0402_1%
<97,98> SW4_4PH
1 2 PCZ30
+19VB_CPU 0.1U_0402_25V6 CSP4_4PH
CSREF_4PH PCZ31 2 1 TSENSE_4PH PCZ32
<98> CSREF_4PH
0.01U_0402_50V7K 0.1U_0402_25V6 PRZ57
1 2 TSENSE_2PH 1 2 24.9K_0402_1% CSREF_2PH
CSREF_2PH <99>
1 2 1 2
1U_0402_6.3V6K
<98,99> DRVON
PRZ59 +5VALW PRZ56 PWM2_2PH/ROSC1 1 2
1
3.74K_0402_1% 2.2_0603_5% PRZ58

PCZ33
1 2 CSP1_4PH 25.5K_0402_1%
110K_0402_1%
PRZ61
<97,98> SW1_4PH
1
2
2
4.32K_0402_1%
24.9K_0402_1%
97.6K_0402_1%
97.6K_0402_1%
C PWM1_2PH/ICCMAX2 <99> C
1
PCZ34 @ PRZ60
PRZ66
PRZ62
PRZ63
PRZ64
PRZ65
0.047U_0402_25V7K 100K_0402_1%
1
3.74K_0402_1%
2
CSREF_4PH CSP1_2PH 1 2
<98> PWM1_4PH/ICCMAX4 SW1_2PH <97,99>
1
PRZ67
2
3.74K_0402_1%
1 2 CSP2_4PH PCZ35
<97,98> SW2_4PH <98> PWM2_4PH/ADDR
0.047U_0402_25V7K
1
2
PCZ36 @ PRZ68 CSREF_2PH

0.047U_0402_25V7K 100K_0402_1%
1
CSREF_4PH <98> PWM3_4PH/VBOOT

1
PRZ69
3.74K_0402_1%
CSP3_4PH <98> PWM4_4PH/ROSCM
1 2
<97,98> SW3_4PH
2
PCZ37 @ PRZ70
0.047U_0402_25V7K 100K_0402_1%
1
CSREF_4PH
1
TSENSE_4PH TSENSE_2PH
PRZ71
1
1
3.74K_0402_1%
0_0402_5%
0_0402_5%
@0@ PRZ72
@0@ PRZ73
1 2 CSP4_4PH
<97,98> SW4_4PH
2
PCZ38 @ PRZ74 Place close to H-side,L-side MOS

2
0.047U_0402_25V7K 100K_0402_1% Place close to H-side,L-side MOS in VCCGT first phase

1
in VCORE first phase

1
CSREF_4PH
1
PHZ4 PRZ75 PHZ5 PRZ76

61.9K_0402_1% 61.9K_0402_1%
220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J
2
2
2
D D

CPU Controller
1 2 3 4 5
5 4 3 2 1
Main Func = CORE

MOSFET: DFN 5X6E
H/S Rds(on): 7.1mohm(Typ), 9.1mohm(Max)
L/S Rds(on): 2mohm(Typ), 2.5mohm(Max)
EMI@ PLZ11
HCB2012KF-121T50_0805
PRZ85 +19VB_CPU 1 2
0_0603_5% +19VB
1 2 UG1_VCORE_R PCZ39 PCZ46
0.1U_0402_25V7K
0.1U_0402_25V7K
0.1U_0402_25V7K
EMI@ PLZ12
HCB2012KF-121T50_0805
EMI@ PCZ58
EMI@ PCZ59
EMI@ PCZ60
1
1
10U_0603_25V6M
10U_0603_25V6M
1 1 1 2
33U_25V_M
33U_25V_M
PRZ77 + +
PCZ48
PCZ65
2
2
2.2_0603_5%
BST1_VCORE BST1_VCORE_R
2
1 2
PQZ1 2 2
G1
D1
AONY36352_DFN5X6D-8-7
PCZ50
D D
0.22U_0603_25V7K 7
PUZ2 D2/S1 PLZ1
1
NCP81151MNTBG_DFN8_2X2 0.15UH_NA__35A_20%
S2-3
S2-2
S2-1
1 9 1 4
G2
BST FLAG +VCC_CORE
2
2 8 UG1_VCORE 2 3
<97> PWM1_4PH/ICCMAX4 SH00001EF00(common part)
3
PWM DRVH
3 7 LX1_VCORE 7x7X3
<97,99> DRVON EN SW Isat:45A
1
+5VALW
4
VCC GND
6 @EMI@ DCR:0.9mΩ +/-5%
PRZ78
5 LG1_VCORE
DRVL 4.7_1206_5%
1 2 CSREF_4PH <97>
1
PCZ49
2
PRZ89 10_0402_1%
2 2.2U_0402_6.3V6M SNB1_VCORE
SW1_4PH <97>
1
@EMI@
PCZ51
680P_0402_50V7K
2
PRZ84
0_0603_5% +19VB_CPU
1 2UG2_VCORE_R PCZ66 PCZ67
+VCC CORE
1
10U_0603_25V6M
10U_0603_25V6M
TDC= 80A->86A
PRZ79
Peak Current= 128A->140A
2
2.2_0603_5%
2
1 2
PQZ2
OCP Current= 154A->168A
G1
D1
AONY36352_DFN5X6D-8-7 Load Line= 1.8mV/A
PCZ53
0.22U_0603_25V7K 7
Vboot= 0V
PUZ3 D2/S1 PLZ2
1
S2-3
S2-2
S2-1
1 9 1 4
G2
BST FLAG +VCC_CORE
2 8 UG2_VCORE 2 2 3 SH00001EF00(common part)
<97> PWM2_4PH/ADDR
3
PWM DRVH
DRVON 3 7 LX2_VCORE 7x7X3
EN SW Isat:45A
+5VALW 4
VCC GND
6 DCR:0.9mΩ +/-5%
1
C @EMI@ C
5 LG2_VCORE PRZ80
DRVL
4.7_1206_5%
1
PCZ52 1 2
2
2.2U_0402_6.3V6M PRZ90 10_0402_1%
2
SNB2_VCORE
SW2_4PH <97>
1
@EMI@
PCZ54
680P_0402_50V7K
2
PRZ83
0_0603_5% +19VB_CPU
1
10U_0603_25V6M
10U_0603_25V6M
PRZ81
2
2.2_0603_5%
1
1 2
PQZ3
G1
D1
PCZ56
0.22U_0603_25V7K 7
PUZ4 D2/S1 PLZ3
1
S2-3
S2-2
S2-1
1 9 1 4
G2
BST FLAG +VCC_CORE

2
2 8 UG3_VCORE 2 3
<97> PWM3_4PH/VBOOT
6
PWM DRVH
LX3_VCORE SH00001EF00(common part)
DRVON 3 7
EN SW 7x7X3
4 6 Isat:45A
+5VALW VCC GND
1
LG3_VCORE
@EMI@ DCR:0.9mΩ +/-5%
5 PRZ82
DRVL
4.7_1206_5%
1
PCZ55 1 2
2
2.2U_0402_6.3V6M PRZ91 10_0402_1%
2
SNB3_VCORE
SW3_4PH <97>
1
@EMI@
PCZ57
B B
680P_0402_50V7K
2
PRZ86
0_0603_5% +19VB_CPU
1
10U_0603_25V6M
10U_0603_25V6M
PRZ87
2
2.2_0603_5%
1
1 2
PQZ4
G1
D1
PCZ62
0.22U_0603_25V7K 7
PUZ5 D2/S1 PLZ4
1
S2-3
S2-2
S2-1
1 9 1 4
G2
BST FLAG +VCC_CORE

2
2 8 UG4_VCORE 2 3
<97> PWM4_4PH/ROSCM
6
PWM DRVH
LX4_VCORE SH00001EF00(common part)
DRVON 3 7
EN SW 7x7X3
4 6 Isat:45A
+5VALW VCC GND
1
LG4_VCORE
@EMI@ DCR:0.9mΩ +/-5%
5 PRZ88
DRVL
4.7_1206_5%
1
PCZ61 1 2
2
2.2U_0402_6.3V6M PRZ92 10_0402_1%

2
SNB4_VCORE
SW4_4PH <97>
1
@EMI@
PCZ64
680P_0402_50V7K
2
A A

+VCC_CORE
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Main Func = VCCGT/+VCCSA
D D
+19VB_CPU
MOSFET: DFN 5X6E
PCG4 PCG3 PCG8 PCG9
H/S Rds(on): 7.1mohm(Typ), 9.1mohm(Max)
L/S Rds(on): 2mohm(Typ), 2.5mohm(Max)
1
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
PRG1
2
2.2_0603_5%
BST_VCCGT 1 2 BST_VCCGT_R 1 2 UG_VCCGT_R
SH00001EF00(common part) +VCCGT
PRG3 0_0603_5%
7x7X3
1
PCG6
Isat:45A TDC= 25A
2
0.22U_0603_25V7K
PUG1 PQG1 DCR:0.9mΩ +/-5% Peak Current= 32A
G1
D1
2
1
NCP81151MNTBG_DFN8_2X2
9
AONY36352_DFN5X6D-8-7 PLG1
0.15UH_NA__35A_20%
OCP Current= 39A
BST FLAG 7
D2/S1
LX_VCCGT 1 4
+VCC_GT
Load Line= 2.7mV/A
2 8 UG_VCCGT
<97> PWM1_2PH/ICCMAX2 PWM DRVH 2 3
Vboot= 0V
S2-3
S2-2
S2-1
DRVON 3 7 LX_VCCGT
G2
EN SW
4 6 near choke
+5VALW
3
VCC GND
1
@EMI@
5 LG_VCCGT PRG2 PRG4
DRVL 10_0402_1%
4.7_1206_5%
CSREF_2PH <97>
1
PCG5 1 2
2
2.2U_0402_6.3V6M
2
SNB_VCCGT
C C
SW1_2PH <97>
1
@EMI@
PCG7
680P_0402_50V7K
2
+19VB_CPU
PCA2 PCA1
1
10U_0603_25V6M
10U_0603_25V6M
2
2
PRA2 PCA5
2.2_0603_5% 0.22U_0603_25V7K
1 2 BST_VCCSA_R 1 2 UG_VCCSA
+VCCSA
TDC= 10A
Choke 0.47uH SH00001ED00 (Commom Part) Peak Current = 11A
PQA1 (Size:5.7 x 5.4 x 3.0 mm)
PUA1
(DCR:6.2m +-5%) OCP Current= 13A
1
B NCP81253MNTBG_DFN8_2X2 EMB09A03VP_EDFN3X3-8-10 B
Load Line= 10.3mV/A
G1
D1
D1
D1
BST_VCCSA 1 8 PLA1
BST DRVH 0.47UH_MMD05CZR47M_12A_20% Vboot= 1.05V
2 7 LX_VCCSA 9 10 LX_VCCSA 1 4
<97> PWM1_1PH/ICCMAX1 PWM SW D2/S1 D1 +VCC_SA
3 6 2 3
<97,98> DRVON EN GND
G2
S2
S2
S2
4 5
+5VALW
PAD
VCC DRVL
1
@EMI@
8
PRA1
4.7_1206_5%
9
1
PCA4
CSN_1PH <97>
2
2.2U_0402_6.3V6M LG_VCCSA
2
SNB_VCCSA
1
@EMI@
PCA6 SW_1PH <97>
680P_0402_50V7K
2
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

+VCC_GT/+VCC_SA
5 4 3 2 1
A
B
C
for D
+VCC_CORE
Reverse
5
Acoustic
5
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
@
@
@
PCZ159 PCZ149 PCZ139 PCZ134 PCZ124 PCZ114 @ PCZ104 PCZ176
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R4.5M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
@
@
PCZ160 PCZ150 PCZ140 PCZ135 PCZ125 PCZ115 @ PCZ105 CML@ PCZ101
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D1_2VY_R9M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
1
2
@
@
@
PCZ161 PCZ151 PCZ141 PCZ136 PCZ126 PCZ116 PCZ106 PCZ102
30
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
@
PCZ162 PCZ152 PCZ142 PCZ137 PCZ127 PCZ117 @ PCZ107 PCZ103
15 +26@ X
X
X
X
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
@
@
PCZ163 PCZ153 PCZ143 CML@ PCZ138 PCZ128 PCZ118 PCZ108 PCZ170
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
1uF_0201
PCZ164 PCZ154 PCZ144 PCZ129 PCZ119 PCZ109 PCZ171

220uF_D7_2V
330uF_D1_2V
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@
@
@
PCZ165 PCZ155 PCZ145 PCZ130 PCZ120 PCZ110 PCZ172

2 1 2 1 2 1 2 1 2 1 2 1 2 1
22uF_0603_X5R for H62
@
@
@
PCZ166 PCZ156 PCZ146 PCZ131 PCZ121 @ PCZ111 PCZ173
4
4
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@
PCZ167 PCZ157 PCZ147 PCZ132 PCZ122 PCZ112 CML@ PCZ174

1
3
2 1 2 1 2 1 2 1 2 1 2 1 2 1
17+24@
PCZ168 PCZ158 PCZ148 PCZ133 PCZ123 @ PCZ113 PCZ175

30 X 1uF_0201
X 220uF_D7_2V
X 330uF_D1_2V
2 1 2 1 2 1 2 1
+VCC_GT
PCG133 PCG123 PCG113 PCG103

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
X 22uF_0603_X5R for H62
2 1 2 1 2 1 2 1
PCG134 PCG124 PCG114 PCG104

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+VCC_CORE CFL H82 Total VCORE Output Capacitor: CML H82 Total VCORE Output Capacitor:
2 1 2 1 2 1 2 1
@ PCG135 PCG125 PCG115 PCG105

2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PCG101
3
3
2 1 2 1 2 1 2 1 220U_D2_2V_Y

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+VCC_GT
2
1
+
2 1 2 1 2 1 2 1 PCG102
220U_D2_2V_Y
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Issued Date
2 1 2 1 2 1 2 1
2
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
12+8@
18+2@

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
X 1uF_0201
2020/07/07
@ PCG141 PCG131 @ PCG121 PCG111
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
X 220uF_D2_2V
2 1 2 1 2 1 2 1
X 22uF_0603_X5R
@ PCG142 PCG132 @ PCG122 PCG112

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Total VCCGT Output Capacitor:
2
2
Compal Secret Data

Deciphered Date
+VCC_SA
2020/09/20
2 1 2 1
2 1
@
PCA107 PCA101
PCA113 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
1+4@
10+2@
2 1 2 1
2 1
PCA108 PCA102
@ PCA114 22U_0603_6.3V6M 22U_0603_6.3V6M
Title
Date:
1U_0201_6.3V6M
2 1 2 1
Custom
2 1
@
PCA109 PCA103
@ PCA115 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
2 1 2 1
X 1uF_0201
2 1
X 22uF_0603
PCA110 PCA104
Size Document Number
@ PCA116 22U_0603_6.3V6M 22U_0603_6.3V6M

1U_0201_6.3V6M
2 1 2 1
2 1
@
PCA111 PCA105
Tuesday, December 01, 2020
1
1
@ PCA117 22U_0603_6.3V6M 22U_0603_6.3V6M

1U_0201_6.3V6M
Total VCCSA Output Capacitor:
2 1 2 1
@
PCA112 PCA106
GXXXX LA-XXXXP
22U_0603_6.3V6M 22U_0603_6.3V6M
VCORE DECOUPLING
Sheet
101
of
121
R ev
0.1
A
B
C
D
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
@ PCV1 GN20@
0.1U_0402_25V6 PRV3
2 1 24.9K_0402_1%
PRV1 N18@ PRV3

1 2 1 2
0_0402_5% 48.7K_0402_1%
NVVDD1
GPU_B+
TDC 45A
PCV2
0.1U_0402_25V6 +5VCC PRV6 Peak Current 120.5A
+3VS 1 2 4.3K_0402_1%
2 1
OCP 200A
Fsw=300kHz
91K_0402_1%
PRV9
PRV8
10K_0402_1%
10K_0402_1%
1
1
3.6K_0402_1%
2 1
PRV139
PRV140
PRV11
2
10K_0402_1% PRV2 +5VCC
D D
2 1 4.99K_0402_1%
2
2
VGA_I2CC_SDA_PWR 2 1
VGA_I2CC_SCL_PWR PCV4 @ PCV5 PRV4
0.1U_0402_25V6 0.1U_0402_25V6 3.4K_0402_1%
1
1 1 2 1 2 2 1
0_0402_5%
0_0402_5%
@ PRV142
@ PRV141 2 1 2 1 PRV7
PRV12 PRV13 442_0402_1%
0_0402_5% 0_0402_5% 1 2
2
1
1 2 2 1 PCV3
0_0402_5%
PCV6 PRV15 1U_0402_6.3V6K
PRV16
0.015U_0402_16V7K 2.4K_0402_1% 1 2
2 1 1 2
2
PRV18 @ PCV7
@0@ PRV20 0_0402_5% 0.1U_0402_25V6 PRV14
<31> VCC_SENSE_NVVDD1_MSVDD 0_0402_5% 2K_0402_1%
2
2 1 1 2
PRV21
0_0402_5%
+NVVDD1 1 2 @ @0@ PRV145
FDMF3170_REFIN
+5VCC +5VCC
ADDR/FSW_GPU
PRV22 0_0402_5%
VINMON_GPU
10_0402_1% 2 1
FDMF3170_IMON1 <104>
COMP_GPU
IMON_GPU
0.1U_0402_25V6
DAC_GPU
1
EAP_GPU
LPC_GPU
PCV8
1
NCP303150D@
@ PRV25 @ PCV11 PRV19
100K_0402_1%
1
0_0402_5% 0.1U_0402_25V6 1K_0402_1%
N18@ PRV5
GN20@ PRV29
100K_0402_1%
100K_0402_1%
2
1
@
1 2 1 2
PRV10
VOUT_S
2
@0@ PRV146
24
23
22
21
20
19
18
17
0.1U_0402_25V6
2 1 PUV1 0_0402_5%
PCV14
2
2
PRV31 2 1
DAC
VINMON
ADDR
IMON
LPC
REFOUT
COMP
EAP
FDMF3170_IMON2 <104>
2
1K_0402_1%
0.1U_0402_25V6
1
@
1
1
25 16 CSPSUM_GPU NCP303150D@
@ PCV13
C C
FB CSPSUM PRV30
@0@ PRV34 NVVDD1_FBRTN 26 15 CSNSUM_GPU 1K_0402_1%
2
<31> VSS_SENSE_NVVDD1_MSVDD 0_0402_5% FBRTN CSNSUM
2
2 1 TSENSE_GPU 27 14 CSP1_GPU
<104,105> TSENSE_GPU TSENSE CSP1
1 2 VGA_I2CC_SDA_PWR 28 13 CSP2_GPU
PRV35 <33,36> VGA_I2CC_SDA_PWR SDA UP9512QQKI_WQFN32_4X4 CSP2 @GN20@ PRV147 0_0402_5%
10_0402_1% VGA_I2CC_SCL_PWR 29 12 CSP3_GPU 1 2
<33,36> VGA_I2CC_SCL_PWR SCL CSP3 FDMF3170_IMON3 <105>
NVVDD1_FBRTN
0.1U_0402_25V6
1
1 2 EN_GPU 30 11 CSP4_GPU GN20_NCP303150D@
+3VALW EN CSP4
1
PRV39
@GN20@ PCV17
1
10K_0402_1% PSI_GPU 31 10 PRV36

10K_0402_1%
PSI 5VCC 1K_0402_1%

PRV40
2
NVVDD1_PG +5VS
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
32 9 +5VCC
2
PGOOD PWM1
6
REFADJ
PWM1_GPU
33
CH_OC
FDMF3170_REFIN <104,105>
2
PWM4
PWM3
PWM2
GND
REFIN
VREF
2 1
PQV01A
PQV01B
VID
4.7U_0402_6.3V6M
PRV42
PCV18
2 5 2.2_0603_5%
<33,37> NVVDD1_EN
8
1
2
REFIN_GPU
PWM4_GPU
PWM3_GPU
PWM2_GPU
1 2
REFADJ_GPU
CH_OC_GPU
+3VS
VREF_GPU
VID_GPU
@ PRV46
0_0402_5%
@0@
PRV50
NVVDD_PSI <33> 0_0402_5%
1 2 GN20@
6.19K_0402_1%
1
PRV53
2.8K_0402_1% @0@ PRV54 0_0402_5%
PRV44
1 2
@ PRV52
R1 2 1
GPU_PWM1 <104>
0_0402_5%
2
PRV61 @0@ PRV56 0_0402_5%

B B
100K_0402_1% 2 1
1 2 2
R3 1
GPU_PWM2 <104>
+3VS
N18@ PRV53 @0@ PRV17 0_0402_5%
@0@ PRV70 4.32K_0402_1% 2 1 GPU_PWM3 <105>
0_0402_5%
NCP303150D@ +5VS 1 2
PCV9
113K_0402_1%
110K_0402_1%
232K_0402_1%
100K_0402_1%
57.6K_0402_1%
0.1U_0402_25V6 <33> NVVDD_VID GN20@

1 2 NCP303150D@ PRV57
16.5K_0402_1%
1
PUV8 13.7K_0402_1%
N18@ PRV57
M74VHC1GT08DFT2G_SC-70 GN20@
5
PRV73
1
R4 57.6K_0402_1%
P
+5VS B GPU_DRVON <104,105>

4
2
EN_GPU 2 O
PRV71
GN20@ PRV72
N18@ PRV73
PRV69
@ PRV63
2
A
G
R2
3
PRV66
20.5K_0402_1%
2 1
QD9619A@
PRV51
0_0402_5%
PWMVID 的 RC BOM GN20@
PRV64
1 2 請根據GPU
據GPU 's conf i g 設定 274_0402_1%
1U_0402_6.3V6K
4700P_0402_50V7K
1
N18@ PRV64
309_0402_1%
1
2
PCV26
PCV25
C R5
2
1
2
1
@ PRV106
0_0402_5%
A A
NVVDD1_FBRTN
2

PWR_VGA_UP9512P
5 4 3 2 1
1 2 3 4 5
+19VB GPU_B+ FBVDD_B+

EMI@ PLV11
+NVVDD1
PRV74 PRV75
HCB2012KF-121T50_0805 TDC 45.8A
1 2 1 4 1 4
Peak Current 120.5A
EMI@ PLV12
HCB2012KF-121T50_0805
2 3 2 3 OCP current 144.6A
1 2
0.005_1206_1% 0.005_1206_1%
fsw=300kHz
NCP303150D@
PRV76
0_0402_5%
+5VS
A A
2
<36> CSSP_B+ <36> CSSN_B+ CSSP_FBVDD <36><36> CSSN_FBVDD
@
PRV77
QD9619A@ 0_0402_5%
PRV76 GPU_B+
1
37.4K_0402_1%
1 2
Use 0805 size
@0@ PRV82
5> TSENSE_GPU
0_0402_5% NCP303150D@
PCV30
PCV31
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
1 1
1 2 TMON1_FDMF3170 BST1_FDMF3170
1 2
33U_25V_M
33U_25V_M
PRV80
1
QD9619A@ 4.7_0603_1% + +
PCV32
PCV33
PCV34
PCV35
PCV78
PCV29
PCV28
PRV80
2.2_0603_1%
2
1
+5VS 2 2
EMI@
EMI@
16
17
11
10
13
9
PCV40
QD9619A@ 0.1U_0603_25V7K
VIN1
FAULT
BOOT
ZCD_EN
N/C
VIN
2
PRV85
0_0402_5%
PCV27 +NVVDD1 1 2 VOS1_FDMF3170 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE1_FDMF3170
PVCC PHASE
1 2 VCC1_FDMF3170 3
PRV78 VCC NCP303150D@
2_0402_5% 2 PUV2
AGND
1
PCV37 QD9619A@ NCP303150DMNTWG

2.2U_0402_6.3V6M 5 PUV2
PGND QD9619AQR1
2
20
PGND2
PLV2 +NVVDD1
B 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20% B
1 2 PWM1_FDMF3170 14 8 LX1_FDMF3170 1 2
GPU_DRVON <103,105> <103> GPU_PWM1 @0@ PRV79 0_0402_5% PWM SW
1
1 2 EN1_FDMF3170 15
@0@ PRV84 0_0402_5% DISB#
FDMF3170_IMON1 18
13X8X4
EMI@ PRV154
<103> FDMF3170_IMON1 IMON 4.7_1206_5%
Isat:77A
1 2 FDMF3170_REFIN1 19 DCR:0.48mΩ (+/-5%)
PGND1
2
REFIN
@0@ PRV81 0_0402_5% GPU1_SNB1
GL
TP
1
EMI@ PCV255
6
21
7
680P_0402_50V7K
2
NCP303150D@
PRV88
0_0402_5% +5VS
2
@
PRV87
QD9619A@ 0_0402_5%
PRV88 GPU_B+
1
37.4K_0402_1%
1 2
Use 0805 size
@0@ PRV92
0_0402_5%
PCV47
PCV48
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
1 2 NCP303150D@
1
QD9619A@ PRV90
PCV49
PCV41
PCV39
PCV38
PCV79
C C
PRV90 4.7_0603_1%
2.2_0603_1%
2
1
+5VS
EMI@
EMI@
16
17
11
10
13
9
PCV57
QD9619A@ 0.1U_0603_25V7K
VIN1
FAULT
BOOT
ZCD_EN
N/C
VIN
PRV95
0_0402_5%
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE2_FDMF3170
PVCC PHASE
1 2 VCC2_FDMF3170 3 NCP303150D@
PRV86 VCC PUV3
2_0402_5% 2 NCP303150DMNTWG
1
PCV54 AGND
2.2U_0402_6.3V6M 5 QD9619A@
PGND PUV3
2
20 QD9619AQR1
PGND2
PLV3 +NVVDD1
0.22UH_MHT-MHDZIR22MEM3-RT_45A_20%
1 2 PWM2_FDMF3170 14 8 LX2_FDMF3170 1 2
<103> GPU_PWM2 @0@ PRV89 0_0402_5% PWM SW
1
1 2 EN2_FDMF3170 15
@0@ PRV94 0_0402_5% DISB#
FDMF3170_IMON2 18
13X8X4
EMI@ PRV93
<103> FDMF3170_IMON2 IMON 4.7_1206_5%
Isat:77A
1 2 FDMF3170_REFIN2 19 DCR:0.48mΩ (+/-5%)
PGND1
REFIN
@0@ PRV91 0_0402_5% GPU1_SNB2
GL
TP
FDMF3170_REFIN <103,105>
1
EMI@ PCV60
6
21
D 680P_0402_50V7K D
2

PWR_+NVVDD1
1 2 3 4 5
5 4 3 2 1
GN20_NCP303150D@
PRV96
D 0_0402_5% D
+5VS
2
@GN20@
PRV97
GN20_QD9619A@ 0_0402_5%
PRV96 GPU_B+
1
37.4K_0402_1%
1 2
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0805_25VAK
10U_0805_25VAK
@GN20_EMI@ PCV64
@GN20_EMI@ PCV65
0.1U_0402_25V6
GN20_NCP303150D@
1 2 PRV100
<103,104> TSENSE_GPU
1
GN20@ PCV66
GN20@ PCV67
GN20@ PCV68
GN20@ PCV69
GN20@ PCV80
GN20_QD9619A@ 4.7_0603_1%
@GN20@ PRV102 0_0402_5% PRV100
2.2_0603_1%
2
+5VS
16
17
11
10
13
9
1
GN20@
ZCD_EN
N/C
VIN
FAULT
BOOT
VIN1
GN20_QD9619A@ PCV74
GN20@ PRV105 0_0402_5% 0.1U_0603_25V7K
2
C NC C
2.2U_0402_6.3V6M
1 2 4 12 PHASE3_FDMF3170
PVCC PHASE
1 2 VCC3_FDMF3170 3
GN20@ VCC GN20_NCP303150D@
PRV98 GN20@ 2 PUV4
AGND
1
2_0402_5% PCV71 NCP303150DMNTWG

2.2U_0402_6.3V6M 5 GN20@
PGND PUV4
2
20 QD9619AQR1_PQFN41_5X6
PGND2 GN20@
PLV4 +NVVDD1
@GN20@ PRV99 0_0402_5% 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20%
1 2 PWM3_FDMF3170 14 8 LX3_FDMF3170 1 2
<103> GPU_PWM3 PWM SW
1
1 2 EN3_FDMF3170 15
<103,104> GPU_DRVON @GN20@ PRV104 0_0402_5% DISB# GN20_EMI@
FDMF3170_IMON3
13X8X4
18 PRV103
<103> FDMF3170_IMON3 IMON 4.7_1206_5%
Isat:77A
1 2 FDMF3170_REFIN3 19 DCR:0.48mΩ (+/-5%)
PGND1
<103,104> FDMF3170_REFIN
2
REFIN
@GN20@ PRV101 0_0402_5% GPU1_SNB3
GL
TP
1
layout reference Close to IC. GN20_EMI@
B PCV77 B
6
21
7
680P_0402_50V7K
2
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
A
B
C
D
+NVVDD1
2 1 2 1 2 1
2
1
+
PCV155 PCV159 PCV251 PCV135
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 330U_D1_2VY_R9M
2 1 2 1 2 1
5
5
2
1
+
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 560U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+
2 1 2 1 2 1
2
1
+
2 1 2 1 2 1
2
1
PCV162 PCV149 PCV143 +
PCV139
2 1 2 1 2 1
2
1
+

2 1 2 1 2 1
PCV164 PCV151 PCV145

1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1 2 1
PCV165 PCV152 PCV146

1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1
PCV153 PCV147
1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1
PCV154 PCV148
1U_0201_6.3VAM 1U_0201_6.3VAM
4
4
+NVVDD1
2 1
+NVVDD
2 1 2 1 2 1
PCV215
560uF X 6
PCV283 PCV225 PCV235 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV216
1uF_0201 X 28
10uF_0402X 34
PCV280 PCV226 PCV236 10U_0402_6.3V6M

2 1
22uF_0603 X 15
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

2 1 2 1 2 1
PCV217
PCV237 PCV227 PCV279 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV218
PCV276 PCV229 PCV282 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV219
3
3
PCV228 PCV287 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV220
PCV230 PCV250 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV221
PCV231 PCV275 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV222
Issued Date
PCV232 PCV281 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV223
PCV233 PCV284 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV224
PCV234 PCV277 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M
2020/07/07
+NVVDD1
2 1 2 1
PCV254 PCV243
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCV253 PCV244
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
2
PCV252 PCV245
22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data
2 1 2 1
Deciphered Date
PCV257 PCV246
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCV256 PCV247
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
PCV248
22U_0603_6.3V6M
2020/09/20
2 1
PCV358
22U_0603_6.3V6M
2 1
PCV359
22U_0603_6.3V6M
2 1
PCV360
22U_0603_6.3V6M
Size
Title
Date:
2 1
PCV361
22U_0603_6.3V6M
Document Number
1
1
Tuesday, December 01, 2020

GXXXX LA-XXXXP
Sheet
107
PWR_VGA DECOUPLING
of
121
R ev
0.1
A
B
C
D
5 4 3 2 1
EMI@ PLW 11
FBMA-L11-201209-800LMA50T
B+_+1.35VS_VGAP 1 2
FBVDD_B+
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
0.1U_0402_25V6
PRW 1
PCW1
PCW2
PCW7
1
1
1K_0402_1%
PCW3
PCW4
PCW5
1 2
<33,37> FBVDDQ_EN
D D
2
EMI@
EMI@
EMI@
PCW 6
0.1U_0402_25V6 MOSFET: DFN 5X6E
1 2
H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)
Samesung & Micron VRAM +3VALW L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)
When,VRAM_VDD_CTL=High UG1_+1.35VS_VGAP +1.35VSDGPU
Vboot=1.25V N18P-G62
1
SW 1_+1.35VS_VGAP
When,VRAM_VDD_CTL=Low PRW 10 TDC 17.2A
Vboot=1.2V 31.6K_0402_1% 13X8X4 Peak Current 18.4A
@ PRW 3
Isat:55A OCP current 30A
2
0_0402_5% DCR:1.3mΩ (+/-5%)
1 2
fsw=400kHz
<33> FBVDDQ_PSI
PQW 1 PLW 1
AOE6930_DFN5X6E8-10 0.47UH_MHT-MHDZIR47MEM1-RT_30A_20%
4
SW 1_+1.35VS_VGAP-1
PRW 6
1 2
+FBVDDQ
G1
D2/S1_3 S1/D2
D1_1
D1_2
10K_0402_1%
1
VREF_+1.35VS_VGAP
9 10
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
560U_D2_2VM_R4.5M
1 1 1 1 1
2
PRW 4 D1_3 S2
D2/S1_2
D2/S1_1
@0@ EMI@ PRW 8
330U_D1_2VY_R9M
330U_D1_2VY_R9M
330U_D1_2VY_R9M
330U_D1_2VY_R9M
2.2_0603_5%
1
PRW 9 2 1 4.7_1206_5% + + + + +
PCW23
PCW9
PCW10
PCW28
PCW29
PCW11
PCW12
PCW13
0.1U_0402_25V6
0_0402_5%
BOOT1_+1.35VS_VGAP_R
4.99K_0402_1%
G2
2
1
<33> VRAM_VDD_CTL 1 2
PCW20
2
2 2 2 2 2
BOOT1_+1.35VS_VGAP
SNB1_+1.35VS_VGAP
PRW22
5
REF1
UG1_+1.35VS_VGAP
VID_+1.35VS_VGAP
PSI_+1.35VS_VGAP
2
EN_+1.35VS_VGAP
0.1U_0402_16V7K
1
LG1_+1.35VS_VGAP
@ PCW15
REFADJ
2
1
PRW 28
10K_0402_1%
C C
PRW 25
2
120K_0402_1%
2
REFADJ_+1.35VS_VGAP_R 1 2 REFADJ_+1.35VS_VGAP
1
EMI@ PCW 16
PCW21
2200P_0402_50V7K
1
PUW 1 680P_0402_50V7K
1
1
RT8816BGQW _W QFN20_3X3 PCW 14
3.3K_0402_1%
2
PRW23
0.22U_0603_25V7K
UGATE1
BOOT1
VID
PSI
EN
2
RBOOT
2
REFADJ_+1.35VS_VGAP 6 20 SW 1_+1.35VS_VGAP
2
REFADJ PHASE1
REFIN_+1.35VS_VGAP 7 19 LG1_+1.35VS_VGAP
REFIN_+1.35VS_VGAP REFIN LGATE1 PRW 11
2.2_0603_5%
VREF_+1.35VS_VGAP 8 18 PVCC_+1.35VS_VGAP 1 2
VREF PVCC +5VALW
PRW 12 PRW 13
2200P_0402_50V7K
1
14K_0402_1%
PRW24
PCW22
2.2_0402_1% 453K_0402_1%
1
2 1 2 1 TON_+1.35VS_VGAP 9 17 PCW 17
B+_+1.35VS_VGAP TON LGATE2
1
2.2U_0402_6.3V6M
REF2
2
OCSET/SS
RGND 10 16
PCW 18
2
2
UGATE2
RGND PHASE2
PGOOD
BOOT2
1TON_+1.35VS_VGAP_R
VSNS
2
GND
0.1U_0402_25V6
21
11
1OCset_+1.35VS_VGAP 12
13
14
15
@0@ PRW 14
0_0402_5%
1 2
FBVDDQ_PG
<30> FBVDDQ_GND_SENSE
B B
@ PRW 21
10_0402_1%
1 2
PRW17 36.5K_0402_1%
1
@ PCW 30
Vsense_+1.35VS_VGAP
1000P_0402_50V7K
2
PRW 18
10K_0402_1%
1 2
Rocset for 75.6A

+3VS
@ PRW 29
10_0402_1%
+FBVDDQ 1 2 FBVDDQ_PG <33>
@
PCW 27
0.1U_0402_25V6
1 2
1 2
<30> FB_VDDQ_SENSE
@0@ PRW 20
0_0402_5%
A A

PWR_+1.35VRAM
5 4 3 2 1
SKL_H 42
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
A B C D E
1 1
@0@ PR1010
0_0402_5%
EN_1VSDGPU 1 2
PEX_VDD_EN <33,37>
1
Current limit = 4.7A(min) PR1008 @ PC1014
0.1U_0402_16V7K
2
PR1009 1M_0402_5%
10K_0402_5% Choke 1uH SH00000YG00 (Common Part)
2
2 1
+3VALW (Size:3.8 x 3.8 x 1.9 mm)
Isat:3.42A
(DCR:20m~25m)
PU1002 Choke: SH00000YG00 Size:4x4x2 (Common Part)
<33> PEX_VDD_PG 9
1 PGND 8 Rdc=27± 20% Taiyo
FB SGND Rdc=20mohm(Typ), 25mohm(Max) Cyntec
@ PJ1001 2
PG EN
7 PL1002 Imax=1.6A, Ipeak=2.23A, Iocp:2.68A Rdc=27± 20% 3L
JUMP_43X79 1UH_2.8A_30%_4X4X2_F Rdc=30± 20% Tai-Tech
1 2 VIN_1.0VSDGPUP 3 6 LX_1.0VSDGPUP 1 2
+3VALW 1 2 IN LX +1.0VSDGPUP Rdc=32± 20% Chilisin
4 5 Rdc=36mohm(Typ), Xmohm(Max) Maglayers
68P_0402_50V8J
PGND NC
1
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1013 EMI@
PC1012
1
SY8003ADFC_DFN8_2X2 PR1007 PR1011
PC1009
PC1010
@ PC1011
22U_0603_6.3V6M 4.7_0603_5% 13.7K_0402_1%
2
2
2
2
FB_1.0VSDGPUP
1
EMI@ N18@
2
Rdown 2
1
FB=0.6V PC1008 PR1012
Note:Iload(max)=3A 680P_0402_50V7K GN20@PR1012 20K_0402_1%
22.6K_0402_1%
2
@ PJ1003
VFB=0.6V
2
JUMP_43X79
Vout=0.6V* (1+Rup/Rdown) +1.0VSDGPUP
1
1 2
2
+PEX_VDD
=0.6V* (1+13.7/22.6)
Vout=0.9637V for N20
VFB=0.6V
=0.6V* (1+13.7/22.6)
Vout=1.011V for N18
3 3
4 4

1.05VSDGPU
A B C D E
5 4 3 2 1
D D
Reserve Page C
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
0.1
5 4 3 2 1
5 4 3 2 1
Version change list Page 1 of 1 for

(P.I.R. List) PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
1105 PVT
01 NA CPU transient P97 PRZ28 change from 1k_SD034100180 to 1.69k_SD00000JB80
PCZ24 change from 82pF_SE071820J80 to 220pF_SE082221J80
D D
02 NA Vram transient P107 PCV135 change from 560u_D2_SGA00006J00 to 330u_D1_SGA00009S00 1105 PVT
03 NA Vram transient P108 PCW29 change from 330u_D1_SGA00009S00 to 560u_D2_SGA00006J00 1105 PVT
04 NA Material shortage P103 PRV72 & PRV73 change from 56.2k_SD000001580 to 57.6k_SD034576280 1105 PVT
C C
B B
A A

PIR
5 4 3 2 1
5 4 3 2 1

(P.I.R. List) PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
change PR1009 from 100K_0402_5% (SD028100380) to 10K_0402_5% (SD028100280)

change PG pull high from +3VS to +3VALW
D change PRW1 from 20K_0402_1% (SD034200280) to 1K_0402_1% (SD034100180) D
01 Design Update For EA Turning and HW 93, 94 Change the PCW27 from pop to un-pop, and . PCW27.2 net name change from +1.35VSDGPU to Vsense_+1.35VS_VGAP.
sequence 95, 97 unpop PCV135
89, 92 Change the PUV8, PCV9 from pop to un-pop. 11/14 A
Add location PRV51 0_0402_5% (SD028000080), and pop.
Change the PCW21, PCW22 From 4700P_0402_50V (SE074472K80) to 2200P_0402_50V(SE074222K80).
Delete PL1111 (HCB2012KF-121T50_0805)
Change the PQB2,PQM2 from AON7506 (SB000010A00) to EMB12N03V (SB00001HV00)

83, 85 update location PRG5 PRA3 to PUG1 PUA1
02 Design Update solution change 90, 91 PLZ1,PLG1,PLZ2,PLZ3,PLZ4 change to common part P/N (SH00001EE00) 11/16 A
pop PQZ2, PQZ4 unpop PQZ1, PQZ3
83, 85 Change PRM10, PRM8, PRV82, PRV85, PRV92, PRV95, PRV79, PRV81, PRV84, PRV89, PRV91, PRV94, PRV54, PRV56, PRV70, PRV145,
03 Design Update 0 ohm to R-short 90, 91 PRV146, PRZ72, PRZ73, PRZ25, PRZ30, PRZ32, PRZ18, PRZ9, PRZ11, PRZ24, PRZ27,PRV20, PRV34 11/16 A
change PRZ12 from 1.78K_0402_1%(SD00000WY80) to 1.62K_0402_1%(SD000003380)

change PRZ14 from 31.6K_0402_1%(SD034316280) to 28K_0402_1%(SD034280280)
change PCZ24 from 470P_0402_50V8J(SE071471J80) to 220P_0402_50V8J(SE082221J80)
C
change PRZ51 from 84.5K_0603_1%(SD014845280) to 100K_0603_1%(SD014100380) C
04 Design Update For CPU transient 89, 92 PRZ61=110k ohm @H82, PRZ61=102k ohm @H62
PRZ35=25.5k ohm @H82, PRZ35=28k ohm @H62 11/19 A
unpop PCZ101, PCZ103, PCG102
pop PCZ176
un pop PCZ120, PCZ104, PCZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124 for H82
un pop PCZ120, PCZ104, CZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124, PCZ123, PCZ127, PCZ107, PCZ113, PCZ116, PCZ114 for H62
Change the PL501 1.5uH to common part

05 Design Update solution change 84 Change the PCZ47, PCZ48, PCZ65, PCV36, PCV249 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_M (SF000007700) 12/3 A
Chnage the PRZ43 from 12.1K_0402_1% (SD034121280) to 12K_0402_1% (SD034120280)
06 Design Update solution change 87 unpop PC1811 0.47U_0402_6.3V6K (SE124474K80) 12/12 B
pop PCV149~PCV158, PCV162~PCV165, PCV258 (1U_0201_6.3V6M) 12/18 B

07 Design Update solution change 83, 97 reserve PDB2 for dead battery
12/18 B
08 Design Update solution change 87, Change PR1010, PRW9, PR1801, PR2501 from 0ohm to r-short
93, 94
附附附附 ,E SD 能能能能HS小小小
B B
到到小到到
09 Design Update For ESD request 82 Pop PC205 0.1U_0603_25V7K (SE042104K80) HS HS c ab l e 1/15 B
coupling fali
10 Design Update For EMI request 93, 96 Pop PCW1, PCV48 2200P_0402_50V7K (SE074222K80) for EMI request 1/15 B
Pop PCW2, PCV47 0.1U_0402_25V6 (SE00000G880) for EMI request
11 Design Update Design change 90, 87 delete boost circuit and PCZ47 5/7 FH58F EVT
12 Design Update Design change 90, 87 delete PC1112 5/7 FH58F EVT
change PCB15 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to 1U 16V K X5R 0402(SE00000OU00)
13 Design Update Design change change PCB16 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to S CER CAP 2.2U 16V K X5R 0402(SE000013780) 6/25 INV2
88, 93
Add PLV2, PLV3 second source S COIL .22UH TMPC1004H-R22MG-R5505-D 50A(SH00001XH00)
14 Design Update change CH_OC to 75A 95 change PRV71 from S RES 1/16W 133K +-1% 0402(SD034133380) to S RES 1/16W 113K +-1% 0402(SD034113380) 6/25 FH58F PVT
A A

PIR
5 4 3 2 1
A B C D E

Item (P.I.R. List) Date
Page Title Issue Description Solution Description HW Phase Rev.
1 52 CNVi 1205B CNVi-Intel review (FH5VF) Add RM67 / RM68 0-ohm
Add PU RM70 / PD RM69 (Reserve)
2 52 UART_BT 1205B UART_BT review RM66 Change to @ for Vender review
3 81-111 PWR SCH 1206A POWER update Combined Power SCH (1204)
4 40 HDMI 1206B HDMI EMI solution Remove RY52/RY53/CY27 , LS15 change to pop (EMI@) .
5 17/69 JSSD3 1206B JSSD3 SATA/PCIE detect SATAGP change to GP4 & RH303 PU
1 1
6 64 EMR 1206B EMR Power source RH285/RH286/RH292 power source change to +3VALW
7 63 Touch Pad 1206B ESD Add CK203(100p) for ESD
8 27 VGA 1206C CLKREQ RV83 change to pop(VGA@) / CV226 change to unpop (@)
9 19 PROJECT ID 1206C PROJECT ID defined as Project - 50 ( ID1:H / ID0:L )
10 38 Panel OD 1206C Panel OD function RX11 change to unpop & BIOS needs to detect panel to select H or L .
11 16/58 BT_ON 1206C BT_ON change to PCH RH304 pop (PCH) & RB85 unpop (EC)
12 73 IO_B conn. 1209A IO_B conn. IO_B change pin define
13 15/68/69 M.2 SSD 1209B Fixed naming > SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2)
> SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1)
> SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW)
14 52 CNVi 1209B CNVi-Intel review (FH5VF) RM70 change power source to +3VS_WLAN
15 81-111 PWR SCH 1209C POWER update Combined Power SCH (1209)
16 81-111 PWR SCH 1210A POWER update Combined Power SCH (1209B)
17 77 H6 1210B For Layout H6 change to GNDA for Layout .
18 69 SSD3 1210B BOM Config ADD "SSD3@" for BOM
19 58 Board ID 1210B Board ID config ADD DVT@ & DVTRGB@ for DVT BOM
20 52 CNVi 1210C CNVi-Intel review (FH51M) > RM69 change to 71.5k & CNVI@
> RM70 set CNVI@
2
> RH22 change to 20K 2
> RM36/RM37/RM67/RM68 change to 22 ohm
20 63 ESD 1211B > Pop CK203 680p & ESD@
> CB12/CB13 change to 33p for ESD & ESD@
3 3
4 4

PIR-HW1
A B C D E

Acer Nitro 5 AN515!55!53E5 GH51M LA-K861P Rev 1A Schematic Diagram

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Acer Nitro 5 AN515!55!53E5 GH51M LA-K861P Rev 1A Schematic Diagram

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

mDP - JDP1 HDMI - JHDMI1 eDP - JEDP1 Interleaved (DDR4 2666/2933)

- DDR4 So-DIMM 260 pin

- PCIE1.0 2.5GT/s - USB2 Port 4

RTC CKT. (JRTC1)

Power On/Of f CKT. - ON IO/B > L - On CCD Module - On IO/B

Vcc 3.3V +/- 5% *PCB Version SIGNAL

12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF SD034200380 12

+FBVDDQ +1.35VS power rail for GPU ON OFF OFF OFF

EC_SMB_CK3 LED driver 0xC0

B UQ2 RQ9 +1.8VS RA3 +1.8VS_VDDA CODEC B

PU1801 PJ1801 +1.8VALW RH100 +1.8VALW _PRIM PCH

US12 +USB_VCCA JUSB1 USB3.0 Conn. +VCC_FAN1

DH5VF_EVT Power Sequence AC mode

Plug in Power On S3 S3 Resume Power Off

Comet Lake-H Refresh

CPU PCH NVIDIA PCB

1 CMLRi52@ CMLPCH@ N18PA@ PCB@ 1

S IC CL8070104399510 SRH84 R1 2.5G ABO! S IC N20Z-QS1-A1 QS1 BGA 1358 S

S IC CL8070104409309 SRK3Z R1 2.5G ABO !

S IC CL8070104399315 SRH8Q R1 2.6G ABO !

Security Classification Compal Secret Data Compal Electronics, Inc.

CHANNEL-A Interleaved Memory

Security Classification Compal Secret Data Compal Electronics, Inc.

CHANNEL-B Interleaved Memory

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

RC78 2 1 51_0402_5% CPU_XDP_TDO

RC14 1 2 499_0402_1% H_PROCHOT#_R

RC15 1 2 60.4_0402_1% EC_VCCST_PG

RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

The 30 HSIO lanes on PCH-H supports the following configurations:

Security Classification Compal Secret Data Compal Electronics, Inc.

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

AW13 BD4 CLK_CNV_PRX_DTX_N

intel critical net recommend

PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

RH55 2 1 1K_0402_5% W AKE#

RH57 1 @ 2 100K_0402_5% AC_PRESENT_R

100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

RH60 2 1 8.2K_0402_5% PM_CLKRUN# QH7B

D_CK_SCLK D_CK_SCLK <23,24>

RH192 2 1 2.2K_0402_5% D_CK_SDATA 0.1U_0201_10V6K 1 2 CH20 SYS_RESET# +3VALW

0.1U_0201_10V6K 1 2 CH22 PCH_PW ROK

2 CPU_ID RH255 1 H82@ 2 1K_0402_5% 2

+3VALW RH256 1 H62@ 2 10K_0402_5%

RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

RH83 2 @ 1 100K_0402_5% PCH_SPKR ‧‧ GPP_E[8:0]

Security Classification Compal Secret Data Compal Electronics, Inc.

GPIO Group Voltage

1 W20 Short pins AJ22,AJ23,AK22,AK23 together

1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

0.0198A C1 AJ23 Internal LDO

1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE

2 Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title