FULLTEXT01

Main Circuits, Submodules, and Auxiliary Power Concepts
for Converters in HVDC Grids
STEFANIE HEINIG
Doctoral Thesis
in Electrical Engineering
Stockholm, Sweden 2020
KTH Royal Institute of Technology
TRITA-EECS-AVL-2020:41 SE-100 44 Stockholm
ISBN 978-91-7873-630-0 SWEDEN
Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till of-
fentlig granskning för avläggande av teknologie doktorsexamen fredagen den 25:e septem-
ber 2020 klockan 10:00 i sal Ångdomen, Kungl Tekniska högskolans bibliotek, Osquars
backe 31, Stockholm.
© Stefanie Heinig, August 2020
Tryck: Universitetsservice US AB
iii
Für Sophie
“Man muss das Unmögliche versuchen,

um das Mögliche zu erreichen.”
— Hermann Hesse
“Keep your eyes on the stars,

and your feet on the ground.”
— Theodore Roosevelt
iv
Abstract
In order to enable the massive introduction of renewable energies the need for high-
voltage direct current (HVDC) grids is anticipated. Large, globally interconnected
HVDC networks will likely be the most cost-efficient means to balance electricity de-
mand and available generation. In a meshed system it is important to ensure reliability,
robustness, failure management, and fast protection of equipment. In case of a failure
somewhere in the grid, the remaining system must be kept operational. State-of-the-
art converter implementations are either not adapted to future system requirements or
lead to increased losses, cost, and converter footprint. Therefore, this thesis examines
several aspects of how to improve the HVDC converter design and functionality with
the ultimate aim of developing reliable, highly efficient, cost-effective, more compact
and lightweight converters.
Advancements are made on several levels of the converter hardware hierarchy.
Main circuits, submodule (SM) topologies, and auxiliary power supply (APS) con-
cepts are investigated and new solutions are proposed. On main-circuit level, different
voltage-source converters (VSCs) are evaluated in terms of their energy storage ele-
ments. This is useful to compare the physical volume of capacitors required by each
topology and, thus, to address the need to develop more compact converter stations.
The theoretical analysis indicates that the required energy storage of the alternate arm
converter (AAC) is smaller compared to the modular multilevel converter (MMC).
On SM level, new topologies are evaluated with the goal to find topologies, which
enable efficient handling of dc-side short circuits, reduction of power loss, and lower
SM capacitance. The semi-full-bridge (SFB) SM is identified as one of the most
promising topologies from this point of view and is investigated in detail. A control
concept for capacitor balancing and several options for improved operation of the SFB
are presented. Furthermore, a novel SM cluster topology is proposed which features
low conduction losses and increased protection against explosion.
The availability of a reliable APS system is crucial for equipment in future HVDC
grids. Therefore, APS solutions are investigated considering design complexity, reli-
able performance, and power consumption. This thesis presents a novel combined op-
tical power and data transmission concept which is tailored to the specific requirements
of HVDC converters employing high-voltage (HV) silicon carbide (SiC) devices. The
proposed concept offers a robust solution for isolated APS and signal transmission
across any voltage barrier.
Keywords: Ac–dc power conversion, energy storage, fault tolerance, HVDC con-
verters, HVDC grid, isolated power supply, modular multilevel converter (MMC),
power system faults, silicon carbide, submodules, voltage source converter (VSC).
v
Sammanfattning
För att möjliggöra den massiva introduktionen av förnybara energikällor förutses

ett behov av högspända likströmsnät. Stora kontinentala högspända likströmsnät kom-
mer sannolikt att vara det mest kostnadseffektiva sättet att balansera elbehov och ge-
nererad effekt. I ett maskat nät är det viktigt att säkerställa tillförlitlighet, robusthet,
felhantering och snabbt skydd av utrustningen. I händelse av fel någonstans i nätet
måste resten av system kunna fortsätta att fungera. Dagens effektomvandlare är an-
tingen inte anpassade till framtida systemkrav eller leder till ökade förluster, kostna-
der och omvandlarstorlekar. Därför undersöker denna avhandling flera aspekter av hur
man kan förbättra effektomvandlarens konstruktion och funktionalitet med slutmålet
att att utveckla tillförlitliga, högeffektiva, kostnadseffektiva, mer kompakta och lättare
effektomvandlare.
Framsteg görs på flera nivåer i hierarkien av effektomvandlarens hårdvara. Huvud-
kretsar, submodulstopologier och koncept för hjälpkraftomvandlare undersöks och nya
lösningar föreslås. På huvudkretsnivån jämförs olika spänningsstyva effektomvandlare
med hänsyn till energilagringskomponenter. Detta är meningsfullt, eftersom konden-
satorstorleken har en avsevärd inverkan på effektomvandlarens volym. Kunskap om
detta kan möjliggöra mer kompakta omvandlarstationer. Den teoretiska analysen ger
vid handen att den nödvändiga energilagringsförmågan är lägre för den s.k. alternate
arm convertern (AAC) än för den s.k. modular multilevel convertern (MMC). På sub-
modulsnivån undersöks nya kretstopologier med målet att finna topologier som möjlig-
gör effektiv hantering av kortslutningar på likströmssidan, reduktion av förluster och
lägre submodulskapacitans. Den s.k. semi-full-bridge-submodulen (SFB) identifieras
som en av de mest lovande topologierna i detta hänseende och den undersöks i detalj.
En styrmetod för kondensatorspänningsbalansering och flera alternativ till förbättring
av funktionen för SFB presenteras. Vidare föreslås en submodulsklustertopologi som
erbjuder låga ledförluster och förbättrad skydd mot explosioner.
Tillgängligheten av tillförlitliga hjälpkraftsystem är kritisk för utrustning i fram-
tida högspända likströmsnät. Därför undersöks olika hjälpkraftslösningar med hänsyn
till komplexitet, tillförlitlighet och effektförbrukning. Avhandlingen presenterar ett nytt
optiskt kombinerat effekt- och dataöverföringskoncept som är skräddarsytt för de spe-
ciella kraven för högspända likströmsomvandlare baserade på kiselkarbidkomponenter.
Konceptet erbjuder en robust lösning för isolerade hjälpkraftaggregat och signalöver-
föring över godtyckliga spänningsbarriärer.
Nickelord: Ac–dc omvandling, energilagring, feltolerans, högspända likspännings-
omvandlare, högspända likströmnät, isolerande kraftaggregat, kiselkarbid, modulära
multinivåomvandlare (MMC), nätfel, spänningsstyr omvandlare, submodul.
Acknowledgements
This thesis presents the work I have carried out at the Division of Electric Power and
Energy Systems at KTH Royal Institute of Technology. The research was funded through
SweGRIDS, by the Swedish Energy Agency, and ABB. To begin with, I would like to
acknowledge these organizations for their financial support and thank everyone at ABB for
inspiring collaboration and guidance throughout my PhD studies.
I am really grateful to Hans-Peter Nee for being my supervisor. I truly appreciate his
constant encouragement, sharing his knowledge in the wide field of power electronics, and
(also very important) moments of relaxed and honest conversations. Thank you, Hansi, for
opening the door to this fantastic PhD adventure and believing in me to walk through it.
I would also like to thank my co-supervisor, Staffan Norrga, for great opportunities over
the past five years. Special thanks to my second co-supervisor, Kalle Ilves, for excellent
support and stimulating conversations. I would have learned a lot less without his will-
ingness to discuss all topics, big or small. The same goes for my PhD colleague, office
mate, and friend – he is all in one – Keijo Jacobs. I would like to sincerely thank him for
his enormous help with the laboratory setups and for engaging teamwork on research and
papers.
My working life at KTH would have been quite lonely and much less pleasant without
having it shared with my current and former colleagues at the division. Thank you for
sharing daily joy and suffering: Ilka Jahn, Tim Augustin, Barış Çiftçi, Mehrdad Nahalpar-
vari, Martin Lindahl, Daniel Johannesson, Mohsen Asoodar, Evangelos Liakos, Shubhangi
Bhadoria, Khizra Abbas, Luca Bessegato, Panagiotis Bakas, Diane Sadik, Matthijs Heuvel-
mans, Priyanka Shinde, Lars Herre, Fabian Hohn, Tin Rabuzin, Stefan Stanković, Evelin
Blom, Angelica Clark, Elis Nycander, Marina Oluić, Yixuan Wu, Gustaf Olson, Giovanni
Zanuso, Konstantina Bitsi, Jonas Millinger, and Rúdi Soares.
For the experimental work in this project I have had essential help from Jesper Freiberg
in manufacturing parts for the test setups. For this I am very grateful. A special thanks
should also be given to Elvan Helander for her kindness and capability to tackle all kinds
of challenges, e.g., ordering laser diodes from China and laser drivers from Sweden in July.
(Guess which delivery took a longer time.) Additional thanks to Brigitt Högberg, Jelena
Berg, Nicholas Honeth, Peter Lönn, Viktor Appelgren, and Eleni Nylén for their valuable
help throughout the years at KTH.
vii
viii
My time as a PhD student wouldn’t have been as enjoyable without my friends in

Stockholm and abroad. I am lucky to have you! However, I prefer to mention no one,
because I wouldn’t like to forget any of them. It is said that “good friends are like stars, you
don’t always see them, but you know they are there”. This has proven to be very true over
the last five years. Thank you all for your understanding and invaluable (moral) support.
Extra thanks to those of you who helped to review this document, notably Panagiotis Bakas,
Ilka Jahn, Katherine Dunne, and Reenie Vietheer.
Last but not least, I would like to thank my family for teaching me priceless life lessons,
in particular, how to be kind and that details make all the difference. Danke, dass ihr immer
für mich da seid!
Finally, my heartfelt thanks goes to my amazing partner in life, Mateja, who does not
need to be acknowledged to understand that this thesis would have never been finished in
time without her endless kindness and loving support. Hvala puno, M! Volim te!
Stockholm, September 2020

Stefanie Heinig
Contents
Contents ix
1 Introduction 1
1.1 Background and Context . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Main Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Original Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 List of Appended Publications . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 HVDC Grids 9
2.1 Fundamentals and Rationale . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Converter Requirements and Capabilities . . . . . . . . . . . . . . . . . 11
3 HVDC Voltage-Source Converters 15

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 The Modular Multilevel Converter . . . . . . . . . . . . . . . . . . . . . 17
3.3 The Alternate Arm Converter . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Energy Storage Requirements . . . . . . . . . . . . . . . . . . . . . . . 20
4 Submodule Topologies 23
4.1 State-of-the-Art Submodules . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Advanced Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Submodule Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 Operating Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 The Semi-Full-Bridge Submodule 33

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Capacitor Voltage Imbalance . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Full-Scale Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Optimised Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ix
x CONTENTS
6 Auxiliary Power Supplies 43

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2 Classification and Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Optical Powering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7 Closure 53
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
List of Acronyms 57
Bibliography 59
Chapter 1
Introduction
1.1 Background and Context
Increased use of uncontrollable renewable energy sources causes an ever increasing need
for long-distance and sub-sea power transmission. For these applications frequently high-
voltage direct current (HVDC), or even ultrahigh-voltage direct current (UHVDC), trans-
mission is preferable to ac transmission. In the case of sub-sea transmission, e.g., from
offshore wind power parks to shore, there is often no other alternative than to use HVDC
since ac-cable connections can be made no longer than approximately 100 km without
reactive-power compensation. So far most HVDC installations in operation and under
construction are point-to-point connections. However, it is likely that an increased use of
HVDC connections will eventually make it economically favourable to connect these into
an HVDC grid [1–4]. Most notably, the cost of equipment can be radically reduced since
fewer converter stations are needed and the reliability in the system can be increased.
Obviously, such a massive infrastructure system cannot be expected to be built over
night, but rather to develop in an organic way gradually from existing point-to-point con-
nections [5]. As of today, several multiterminal HVDC systems are planned and the first
ones are already commissioned [6]. In the near future, dc grids are foreseen to play a key
role in the offshore grid development [7]. Later on it is anticipated that step-by-step na-
tional and transnational hybrid ac–dc transmission grids will be formed. Various long-term
grid development scenarios and concepts have been presented that foresee a future global
HVDC grid that links up the grids on different continents. Such a dc overlay grid will be
likely realised with ultrahigh-voltage (UHV) DC transmission technology and overhead
line (OHL) connections due to high transfer capacity and efficient utilization [8].
As the direction of power in HVDC grids may change on many of the interconnections,
voltage source converters (VSCs) are preferable. The state-of-the-art VSC for HVDC
transmission is the modular multilevel converter (MMC), which was presented by Mar-
quardt et al. [9–12]. The MMC with half-bridge (HB) submodules (SMs) has rapidly been
established as the dominant choice of converter topology for commercial two-terminal
HVDC installations using VSCs. When planning HVDC grids, however, one of the most
1
2 CHAPTER 1. INTRODUCTION
important aspects to consider is dc-side fault handling. This calls for dc circuit breakers
(DCCBs) [13], but also for converter topologies that can handle dc-side short circuits [14].
Even if DCCBs have been proposed, cost savings and additional advantages are highly
probable if the dc-side fault current can be controlled by the converter itself and ancillary
services can be provided to the connected ac power system during fault conditions [15].
Since the HB-MMC, just like the ordinary two-level VSC, loses control of the dc-side
and ac-side currents whenever a short-circuit fault occurs on the dc side, other converter
topologies will be required. The shortcomings of the ordinary MMC with HB SMs can
be overcome by replacing the HBs with full-bridges (FBs) [16, 17]. This allows for full
control of both ac and dc-side currents even in case of a dc-side short circuit, but will add
significant cost and also increase power losses.
Today, the MMC with FB SMs is the only commercially available and already realized
converter technology which fulfils the criterion of fault current controllability. Previous
works indicate that it is interesting to have fault controlling converters, but not at the price
of an MMC with FB SMs [8, 18]. Thus, it can be concluded that state-of-the-art converter
implementations are either not adapted to HVDC grids or are costly and voluminous to
an extent that the introduction of such may be delayed, unless more cost-effective and
compact solutions are found.
Recent research shows that improvements of HVDC converters can be achieved as a
result of new converter main circuits, advanced SM topologies, and progress in semicon-
ductor technology. Several ac–dc converters and a large variety of SM topologies capable
of controlling, or at least limiting, short-circuit currents have been proposed and described
in literature [19–27]. In recent years, the reduction of capacitor size has gained impor-
tance. Hybrid VSCs, which mix elements of the classic VSC and the MMC, have been
proposed to reduce the converter footprint, which they achieve by requiring fewer SMs
with a smaller capacitance. One of the most prominent representatives of this approach is
the alternate arm converter (AAC) [19, 28, 29].
Current research on advanced SMs focuses on balancing power loss, semiconductor
cost, and SM functionality. The goal is to find topologies, which enable efficient handling
of dc-side short circuits, reduction of power loss, and lower SM capacitance. It is shown
that some new SM topologies offer benefits in combination with new semiconductor de-
vices [30, 31]. One possible way forward is the double-connection of two suitable SMs.
This measure enables significantly reduced power losses and SM capacitances [32]. The
semi-full-bridge (SFB) SM, first presented in [33], follows this approach and has been
identified in this thesis to be one of the most promising candidates.
The availability of a reliable auxiliary power supply (APS) system is crucial for con-
verters and may be even more important for their application in HVDC grids. However,
there has been comparably little research done on how state-of-the-art APS solutions can
be improved and adapted to the requirements of future high-voltage (HV) applications,
which are foreseen to employ new HV silicon and silicon carbide (SiC) semiconductor
switches [34–37].
Apart from hardware optimization, also new converter control schemes are currently
under investigation. The proposed concepts promise a faster response under transient and
fault conditions [38, 39].
1.2. RESEARCH MOTIVATION 3
1.2 Research Motivation

Based on the previous section, the following research motivation and corresponding chal-
lenges can be outlined:
1. Motive (M.1): In future interconnected HVDC networks, it is anticipated that converters

are obliged to provide more demanding network services to fulfil grid code specifications,
which are needed to govern the reliable operation and development of the grid.
• Challenges: In order to meet future system requirements, converter stations have
to be equipped with more advanced capabilities, especially during and following
dc-side faults, when connected to weak ac-grids or if OHL transmission is chosen.
Converters that can control dc-side fault currents are needed, but state-of-the-art
solutions with FB technology are very costly and lossy.
2. Motive (M.2): HVDC technology has great potential for offshore platform connections
and city center infeed applications.
• Challenges: Both applications require lightweight and more compact converter sta-
tions with a small footprint because space on platforms is precious and land space in
metropolitan areas is scarce and expensive. The SM capacitors are a driving factor
of the size, weight, and cost of today’s MMCs. They are physically large and occupy
approximately half of the SM volume [40].
3. Motive (M.3): Continental, or even intercontinental, high capacity links require UHVDC
transmission with OHL connections.
• Challenges: Future high-power converters need to handle UHVs, i.e., various parts
of the converters should have sufficiently high isolation. In a meshed system, it is
important to ensure robustness and failure management. However, the probability
of dc-line faults is much higher with OHL connections. The protection of converter
equipment and the availability of a reliable APS system is crucial.
Based on the above it can be concluded that fast dc-side fault current control, small foot-
print, and the reliable operation of UHV converters will be of increasing importance in
future HVDC grids. A description on how this thesis approached the identified challenges
follows in the next sections.
1.3 Main Objectives

The objective of this thesis is to make improvements and find technical solutions with
respect to the research motives M.1–M.3 and challenges presented in the previous section.
Accordingly, the project aims to develop reliable, highly efficient, cost-effective, more
compact and lightweight converters that will function as part of future HVDC networks,
whereas particular attention is given to converters that can handle UHV as this will be
required for large, globally interconnected networks.
This thesis focuses on:

• The investigation and improvement of SM topologies for MMCs which fulfil the
requirements of future HVDC grids (M.1).
• The evaluation of different VSC converter topologies in terms of their energy storage
elements. The objective is to identify more compact solutions (M.2).
• The development of APS solutions for UHVDC SMs (M.3).
1.4 Methodology
The findings of this thesis are derived from theoretical models of the considered converter,
SM or APS topology, on the one hand, and from simulation and experimental results, on
the other hand.
The analysis of the operating principles and energy storage requirements of the MMC
and AAC is conducted by analytical calculations. Mathematical expressions are derived
that relate the modulation index of the AAC to any overlap angle and that define the limits
of the stored energy in each arm. On the basis of the latter, the specific required nominal
energy storage for different operating points is calculated for both converters.
The most promising existing MMC SMs are investigated and compared by analytical
and numerical methods (regarding, inter alia, their equivalent SM resistance, voltage ca-
pability, fault handling, and losses). Concerning the SFB, analytical expressions for the
redistribution current, the transients in the capacitor voltages, and the duration of the bal-
ancing process are given. Furthermore, an analytical parameter study of the maximum
differences in the capacitor voltages is presented.
The verification of the analytical expressions and concepts is in most cases performed
in two steps. Firstly, time-domain simulations of the (equivalent) electronic circuits are
conducted to study and validate the behaviour in a controlled environment. To be precise,
the electronic circuit simulator software LTspice and the electromagnetic transient program
PSCAD/EMTDC (simulating detailed three-phase HVDC converter models) are used. Sec-
ondly, experiments are carried outfor validation in a non-ideal environment, except for the
AAC studies. Measurements on a full-scale prototype of the SFB SM and a down-scaled
MMC are used for validation in the presence of parasitic components, measurement noise,
etc. The behaviour of the proposed single-fiber power and data transmission system is also
verified by means of an experimental setup.
1.5 Original Contributions

This thesis has resulted in the following novel results and original contributions:
• The operating conditions of the AAC are determined to ensure zero net energy ex-
change for the converter arms over each half cycle and a general analysis of the
energy storage requirements of the AAC and MMC is provided. This is useful in
order to compare the physical volume of capacitors required by each topology under
various operating conditions [Publication I].
1.6. LIST OF APPENDED PUBLICATIONS 5
• A novel SM cluster topology is proposed which features low conduction losses and
increased protection against explosion. The implications for the converter opera-
tion and functionality are investigated and a wireless control scheme is proposed
[Publication II].
• The impact of the capacitor voltage imbalance on the operation of the SFB SM is
identified: An analytical parameter study of the maximum difference in the capacitor
voltages is conducted, the circuit parameters of a realistic SFB implementation are
identified, the current spike of the balancing current is quantified on a full-scale pro-
totype, and several options for improved operation are presented [Publication III].
• Various operation and control aspects of the SFB are addressed: A new control
mechanism is proposed to limit the divergence of the capacitor voltages and the
impact of this balancing controller on the SM performance is analysed. The con-
troller is verified by simulations and experimentally on a down-scaled MMC proto-
type [Publication IV].
• A study of the average switching frequency of the SFB associated with different
choices of bypass states is presented and compared to a FB SM. Based on the find-
ings of the analysis, a new switching method is proposed that enables a significant
reduction of switching losses of the SFB [Publication V].
• State-of-the-art APS topologies are reviewed, classified, and evaluated with respect
to their compatibility with future (U)HV applications. The focus is, amongst oth-
ers, on input voltage and output power range, reliability, electromagnetic interfer-
ence (EMI) immunity, compactness, and start-up time. Trends and prospects for
MMCs are identified and possible scenarios for future APS solutions are devised
[Publication VI].
• A combined optical power and data transmission concept is developed which is tai-
lored to the specific requirements of converters employing HV SiC devices. The
proposed concept offers a combined solution for a power supply with both limitless
isolation voltage and EMI resilient signal transmission across any voltage barrier
[Publication VII].
1.6 List of Appended Publications1

This thesis is based on the following papers in peer-reviewed international journals, con-
ference proceedings, and manuscripts:
I. S. Heinig, K. Ilves, S. Norrga, and H.-P. Nee, “On Energy Storage Requirements in
Alternate Arm Converters and Modular Multilevel Converters,” in Proc. 18th Euro-
pean Conf. on Power Electron. and Applicat. (EPE’16 ECCE Europe), Karlsruhe,
Sep. 2016.
1 Note that the papers are numbered based on the order of their discussion in this kappa, see Section 1.7.
II. K. Jacobs, S. Heinig, B. Ciftci, S. Norrga, and H.-P. Nee, “Low Loss Submodule
Cluster for Modular Multilevel Converters Suitable for Implementation with SiC
MOSFETs,” in Proc. IEEE Energy Convers. Congr. and Expo. (ECCE), Baltimore,
Sep. 2019.
III.2 S. Heinig, K. Jacobs, K. Ilves, S. Norrga, and H.-P. Nee, “Implications of Capac-
itor Voltage Imbalance on the Operation of the Semi-Full-Bridge Submodule,” in
Proc. 19th European Conf. Power Electron. and Applicat. (EPE’17 ECCE Europe),
Warsaw, Sep. 2017.
IV.3 S. Heinig, K. Jacobs, K. Ilves, L. Bessegato, P. Bakas, S. Norrga, and H.-P. Nee,
“Implications of Capacitor Voltage Imbalance on the Operation of the Semi-Full-
Bridge Submodule,” IEEE Trans. Power Electron., vol. 34, no. 10, pp. 9520-9535,
Oct. 2019.
V. S. Heinig, K. Jacobs, K. Ilves, S. Norrga, and H.-P. Nee, “Reduction of Switching

Frequency for the Semi-Full-Bridge Submodule Using Alternative Bypass States,” in
Proc. 20th European Conf. Power Electron. and Applicat. (EPE’18 ECCE Europe),
Riga, Sep. 2018.
VI. S. Heinig, K. Jacobs, K. Ilves, S. Norrga, and H.-P. Nee, “Auxiliary Power Supplies
for High-Power Converter Submodules: State-of-the-Art and Future Prospects,” IEEE
Trans. Power Electron., in review process.
VII. S. Heinig, K. Jacobs, S. Norrga, and H.-P. Nee, “Single-Fiber Combined Optical
Power and Data Transmission for High-Voltage Applications,” in IECON 2020 –
46th Annu. Conf. IEEE Ind. Electron. Soc., Singapore, Oct. 2020.
Table 1.1: Contribution of Stefanie Heinig to the appended publications.
Analysis Simulations Experiments Writing

Preparation Performance
I. ••• ••• n/a n/a •••
II. •• • ••
III. ••• ••• •• •• •••
IV. ••• ••• ••• •• •••
V. ••• ••• n/a n/a •••
VI. ••• ••• n/a n/a •••
VII. ••• ••• ••• ••• •••
(• • • major, • • partial, • minor)
2 Distinguished with the “Outstanding Young EPE Member Award 2018”.

3 Note that parts of this journal article have been presented in Publication III.
1.7. OUTLINE OF THE THESIS 7
Table 1.2: Motives M.1–M.3 and publications with corresponding scientific contributions.
I II III IV V VI VII
M.1 HVDC grids • • • • (•)
M.2 Compact converters • • • • (•) • •
M.3 UHVDC systems • • •
Related Publications
Additionally, Stefanie Heinig contributed to the following peer-reviewed international jour-
nal and conference papers:
• D. P. Sadik, S. Heinig, K. Jacobs, D. Johannesson, J. K. Lim, M. Nawaz, F. Di-
jkhuizen, M. Bakowski, S. Norrga, and H.-P. Nee, “Investigation of the surge cur-
rent capability of the body diode of SiC MOSFETs for HVDC applications,” in Proc.
18th European Conf. Power Electron. and Applicat. (EPE’16 ECCE Europe), Karl-
sruhe, Sep. 2016.
• K. Jacobs, S. Heinig, S. Norrga, and H.-P. Nee, “Comparative Evaluation of VSCs
with SiC Semiconductor Devices for HVdc Transmission,” IEEE Trans. Power Elec-
tron., in review process.
1.7 Outline of the Thesis

This PhD thesis is organized in the form of a compilation thesis. The detailed scientific
contributions are presented in the appended publications. The chapters constitute a sum-
mary of the these publications and present key concepts and analysis as well as important
simulation and experimental results. Chapter 2 is an exception to this, as it is not related to
any of the appended papers. The distribution of the publications in the thesis is illustrated
in Fig. 1.1 and the outline of this thesis is summarized as follows:
Chapter 2 describes the fundamentals of HVDC grids and their requirements related to
VSCs, serving as a foundation for this thesis and its original contributions.
Chapter 3 discusses briefly VSCs in general, and in particular the MMC and the AAC. A
comparison of energy storage requirements for these converters is presented.
Chapter 4 provides an overview and comparison of relevant SM topologies. Their impact
on the operating region of an MMC is discussed.
Chapter 5 focuses on the SFB SM. Various operation and control aspects are presented
and the main experimental results are shown.
Chapter 6 investigates APS concept for high-power converter SMs. New APS concepts
based on optical powering are proposed.
Chapter 7 summarizes the main conclusions of this thesis and proposes ideas for future
work.
Multiterminal
2 HVDCHVDC
Grids Grids
Fundamentals Requirements
Technologies
3 HVDC Voltage-Source Converters

MMC
Fundamentals AAC
AAC Energy
MMCstorage 90°
120° 60°
60
40
150° 30°

20
DC ±180° 0°
DC AC DC AC
ilter
-150° -30°
-120° -60°
-90°
I Paper
I III Paper
I III
4 Submodule Topologies
State-of-the-art
Advanced Advanced
Clusters
5 SFB S1
S1 S3 S4 66 Aux.
Aux. Power
Power
S2 S5 S7 S8
C1
Operation
Voltage Imbalance
& Control S2
C1 S6
C2
S9 S11 S12 Review and
S10
C3
S13
Future
FutureProspects
Progress
Paper
II IX Paper
IIVIII
Papers
III,I,IVIV, V Paper
VI II
Experiments
Full-Scale Prototype Semiconductors Optical Powering
SiC for HVDC
6 Gate Drivers
Papers I, IV
III, IV OpticalVII
Powering
Related
Papers VII, IX
publications
Optimised Operation
IV, V
Figure 1.1: Distribution of publications in the thesis.

Chapter 2
HVDC Grids
This chapter describes the fundamentals of HVDC grids and their requirements related to
VSCs, serving as a foundation for this thesis and its original contributions.
2.1 Fundamentals and Rationale

HVDC transmission has been a breakthrough in connecting remote regions and energy
sources with national grids, efficiently transmitting large amounts of electricity and thereby
reducing the carbon footprint compared to an equivalent ac system. Today, most HVDC
installations are point-to-point links, but various studies reason that it is favourable to con-
nect those into an HVDC grid [1, 2, 4]. Compared with traditional point-to-point HVDC
links, HVDC grids feature several potential benefits, such as:
• improved reliability, given that a fault on a point-to-point link has significant impact
on the system stability;
• improved availability, as the power flow can be rerouted in case of any contingency,
e.g., converter shutdown, since parallel paths are available (redundancy);
• improved economic benefits, due to reduced cost of equipment (see Fig. 2.1), better
utilisation of assets, and reduced capacity since peak demands do not occur in the
same time interval;
• improved environmental benefits, due to decreased conversion losses and smaller
footprint;
• improved operational flexibility, due to effectively sharing the variability of renew-
able energy generation and facilitating power trading.
Fig. 2.1 visualises how a meshed HVDC grid can lead to reduced cost of equipment. Com-
pared to a configurations with multiple point-to-point links, fewer converter stations are
needed. For example, the encircled four converters in Fig. 2.1(a) can be replaced by one
9
10 CHAPTER 2. HVDC GRIDS
Component Cost* [4]

AC-DC VSC 1 pu
DCCB
Hybrid 0.25-0.35 pu
Mechanical 0.002-0.005 pu
ag replacements
* estimated, without market experience
(a)
(b)
(a) (b)
Figure 2.1: Possible HVDC system configurations and estimated cost of equipment.
(a) Point-to-point HVDC links. (b) Meshed HVDC grid.
converter plus five DCCBs as shown in Fig. 2.1(b). A “meshed” dc grid is characterised
by multiple dc links from each dc busbar, i.e., dc connections via dc links, unlike grid con-
figurations with meshes at the ac sides, which still rely on converters for dc connections
and might, therefore, be more costly. Taking the given estimated cost of equipment into
account, the costs can be halved for hybrid DCCBs or even further reduced if mechanical
breakers are employed, which is possible if fault-blocking converters are used.
It is foreseeable that the development of a future global dc overlay grid will occur
in stages. In the first stage, HVDC grids will emerge as national and offshore grids [7].
Later on, these may be expanded to form transnational grids. Ultimately, it is anticipated
that a UHVDC (> 800 kV) backbone grid will link up the grids on different continents
due to lower losses and smaller environmental impact [41]. Development scenarios and
concepts of such a global electricity grid based on HVDC technology have been presented
under different names in the literature: “Global grid” [42], “Global interconnect” [41], or
“Intergrid” [43] as shown in Fig. 2.2.
Figure 2.2: Artistic depiction of a global HVDC grid (adapted from [43], © 2013 IEEE).
2.2. CONVERTER REQUIREMENTS AND CAPABILITIES 11
2.2 Converter Requirements and Capabilities

Based on the motives and challenges presented in Section 1.2, several converter require-
ments and capabilities are derived. Those are summarised in Fig. 2.3 and further explained
in the following Tables 2.1–2.4. Finally, an overview of how these requirements are ad-
dressed by the contributions of the appended publications is provided in Table 2.5.
In general, the optimal converter design depends on many factors. High reliability and
availability, high efficiency, and low cost are the key factors and of paramount importance
for all motives [44]. They are, thus, considered as core requirements. The other required
capabilities are categorized according to the research motives M.1–M.3. It should be noted
that some of the listed requirements are mutually dependent and some might eventually
lead to higher losses or converter cost. Therefore, it is necessary to find an optimum trade-
off between them depending on the specific application, whereas highest priority should
be given to the core requirements. However, it is to be expected that cost and performance
of converters have to be judged from a system level in the future [32].
Dc-fault handling UHV
Reliability
HVDC grids M.1 M.3 UHVDC systems
Network services Monitoring
Cost Efficiency
Small footprint Low complexity
M.2
Compact converters
Figure 2.3: Research motivation and corresponding converter requirements.

Table 2.1: Core requirements for research motives M.1–M.3.
Availability and reliability

– Components surviving events of stress beyond rated opera-
tion (surge currents during dc faults or short circuit)
– Reliable and uninterrupted converter operation in case of
component failure in the SM
– Inherent redundancy
– Minimize points of failure
– Sufficient resilience against electromagnetic noise
High efficiency
– Lower number of semiconductors in conduction path
– SM topologies featuring parallel conduction paths
– Bipolar SMs, enabling reduced rms arm current and lower
power losses
– Semiconductor devices with low on-state voltage
Low cost
– Reduced installed silicon area → reduced investment cost
– Lower power losses → reduced operational cost
– Dc-fault controllability → reduced cost for switchgear
– Reduced energy storage requirements → reduced invest-
ment cost for SM capacitors
Table 2.2: Requirements and capabilities for M.1 – HVDC grids.
Dc-fault handling
Faults occurring externally on the dc-side need to be handled in
order to ensure the stability of the grid and avoid damage to the
converter.
– SMs with bipolar terminal voltages (“FB functionality”)
– Need to generate sufficient negative voltage
– Avoid converter blocking
Grid code compliance & Network service provision
– Sufficient harmonic performance
– Required network services might be:
– Static compensator (STATCOM) mode operation
– Active discharge and polarity inversion
– Controlled dc black start
– Operation at reduced dc-link voltage
– Thermal overload capability
2.2. CONVERTER REQUIREMENTS AND CAPABILITIES 13
Table 2.3: Requirements and capabilities for M.2 – Compact converters.
Small footprint
– Keep the size of SM capacitors to a minimum
– Reduced number of SMs by increasing the SM voltage
→ reduced amount of drivers and auxiliary electronics
– Lower power losses → relaxed requirements for the cooling
system
Low complexity
– System complexity as low a possible → keep maintenance
periods short
– SM clusters (larger building blocks) → faster converter as-
sembly times and better maintainability
– Decrease required protective equipment
Table 2.4: Requirements and capabilities for M.3 – UHVDC systems.
UHV
– Sufficiently high isolation of various converters parts
– Converters employing (U)HV SiC devices (>10 kV)
– High capacitor voltages (> 30 kV)
– Reliable APS systems
Monitoring
– Smart meters on high potential
– Real-time environmental monitoring (digital twins)
– Advanced diagnostics → prescriptive maintenance
– External APS concepts for SMs/clusters:
– Anytime access to sensors and monitoring data
– Detection of fault conditions and erroneous behavior at
low, or even zero, SM voltage
Table 2.5: Requirements and publications with corresponding scientific contributions.
I II III IV V VI VII
Reliability • • • •
High efficiency • • • • •
Low cost • • • •
Dc-fault handling • • • • (•)
Grid code • (•) (•)
Small footprint • • • • (•) • •
Low complexity • • •
UHV • • •
Monitoring • •
Chapter 3
HVDC Voltage-Source Converters
This chapter describes VSCs in general, and in particular the MMC and the AAC. The
content of this chapter is based on Publication I.
In interconnected HVDC grids, the power flow in the dc links will have to reverse fre-
quently depending on the geographical distribution of renewable generation and the elec-
tricity price differential at a given point in time. VSC technology allows such power flow
reversals without altering the polarity of the direct voltage and is, therefore, the only option
for a meshed dc grid. One approach to realize more compact converters is the concept of
hybrid VSC topologies. Hybrid VSCs mix elements of the classic VSC and the MMC.
They achieve a reduced converter footprint by requiring fewer SMs with a smaller capaci-
tance. One of the most prominent representatives of this approach is the AAC. The AAC is
a new VSC technology and considered an interesting solution with respect to the research
motives M.1 and M.2 outlined in Section 1.2. Concerning M.1, the AAC features dc-fault
controllability, reduced power loss, and investment cost compared to the state-of-the-art
FB-MMC. Regarding M.2, the AAC promises to have a smaller footprint. Therefore, it
has been selected for a more in-depth analysis in this thesis. An overview of the conducted
research, applied methods, contributions, and corresponding publications is provided in
Fig. 3.1.
3.1 Introduction
Multilevel converters have brought significant improvements over the two- or three-level
VSC. Due to their large number of voltage levels, they are able to generate staircase volt-
age waveforms with relatively small steps as shown in Fig. 3.2. Thus, the current is less
distorted and bulky ac filters are no longer required. Furthermore, the power semiconduc-
tor devices can be switched at fundamental frequency, which significantly increases the
converter efficiency. VSCs for HVDC grids can be classified into dc-fault feeding (e.g.
HB-MMC) and dc-fault blocking (e.g., FB-MMC, SFB-MMC, AAC) [5]. Future HVDC
systems may consist of both converter types [15].
15
16 CHAPTER 3. HVDC VOLTAGE-SOURCE CONVERTERS
Figure 3.1: Overview of research on the AAC: methods, contributions, and corresponding
publications.
2-level 3-level 7-level

1 1 1
0 0 0
−1 −1 −1
Figure 3.2: PWM phase voltage waveforms for two-, three-, and seven-level VSCs.
3.2. THE MODULAR MULTILEVEL CONVERTER 17
3.2 The Modular Multilevel Converter

The MMC is today the worldwide standard converter topology for commercial HVDC in-
stallations using VSCs. It has also been identified as one of the prime converter candidates
for HVDC grids [2,45]. A schematic diagram of a generic MMC is shown in Fig. 3.3. Pos-
sible SM implementations acting as controllable voltage sources are discussed in Chapter 4
and illustrated there in Fig. 4.1.
SM
SM
Submodule string
SM
SM
DC AC
Figure 3.3: Schematic diagram of a generic MMC.
Unlike the previously used two- and three-level converters, the MMC does not require
direct series connection of power semiconductors even at high operating voltage. Addi-
tionally, since the number of voltage levels can be very large, a low switching frequency
per power semiconductor device is feasible whereby operation with very low losses is
made possible. Due to its scalability, the MMC has removed the upper limit in terms of
voltage for VSCs. Furthermore, it offers an excellent combination of harmonic properties
with minimal filtering requirements and low power losses. However, state-of-the-art MMC
implementations also have certain drawbacks. The high number of SMs, for example, has
a negative impact on the converter volume, complexity, and cost. The SM capacitors are
voluminous, a large amount of auxiliary equipment is needed (e.g., for control hardware
and cabling), and the cost of low-latency communication is high. The advantages and
challenges of today’s MMCs are summarized below in Table 3.1 based on [22, 46–48].
Table 3.1: Advantages and challenges of today’s MMCs.
Advantages Challenges
+ Modularity − High number of SMs
+ Scalability − Losses and controllability
+ High efficiency − Large amount of energy stored in SM capacitors
+ Low harmonics → Voluminous capacitors, risk of explosion
3.3 The Alternate Arm Converter

The AAC resembles the standard two-level converter since the two arms of the same phase
leg conduct alternately, and resembles the MMC since it generates a stair-case voltage
[19, 28, 29]. Its arms combine series switches and FB SM strings as seen in the schematic
diagram in Fig. 3.4.
"
DC DC AC
ilter
SM
S
SM
SM
SM
F !
Figure 3.4: Schematic diagram of the AAC.
When the series switches turn-ON, the FB SMs function in a similar way as the FB-based
MMC. Equipped with sufficient FB SMs, the AAC has the capability of controlling the
direct current during dc-side faults and provide network services to the ac grid like a
STATCOM. The total number of required FB SMs is significantly reduced compared to
an MMC implementation, but the series-connection of semiconductor devices is required
for implementing the so-called director switches. The basic mode of operation of a phase
leg is such that the director switches operate alternately, each conducting the output current
during half of the fundamental cycle. The direct coupling between ac and dc-side currents
implies that the inherent energy balance of a phase leg is achieved only in one specific
operation point, which is at a modulation index1 of M = 4/π. The alternation of arm con-
duction periods results in significant current harmonics at six times the fundamental, large
dc-side filter requirements, and a limited operating area close to M = 4/π.
In order to balance the power flow in case of M 6= 4/π, the operational mode with
an overlap period can be used. It is important to note that the voltage that each stack of
SMs will have to generate will be higher when operating with the overlap period as shown
in Fig. 3.5(a). During the overlap period, a current flows through the entire phase leg,
thus exchanging energy between the upper and lower arm SM strings and the dc terminal.
The arm current reference waveform with assumed linear current transition between the
two arms is depicted in Fig. 3.5(a). It can be seen that the duration of the overlap period
corresponds to an angle of 2α and that the arm current constitutes the entire ac-side phase
current.
1 The modulation index M defines the relation between the dc-side voltage V and the peak value of the
d
fundamental component of the alternating voltage V̂s .
3.3. THE ALTERNATE ARM CONVERTER 19
Vs
α
V̂
s
%t
+
Varm
Vnom
Vd
- $t
Varm
Vnom
Vd
#t
(a) Voltage waveforms (b) Arm current reference
Figure 3.5: AAC waveforms in steady-state operation with overlap period.
In [Publication I], the operating conditions of an AAC have been determined to ensure
zero net energy exchange for the converter arms over each half cycle. The analytical re-
lation between the overlap angle and the modulation index, the so-called M-α relation, is
given in (3.1) and a comparison with simulation results is shown in Fig. 3.6.
4 sin(α)
M= (3.1)
π α
The advantages and challenges of the AAC are summarized in Table 3.2. A new operation
mode with an extended-overlap (EO) period of 60◦ has been presented after [Publication I]
[49] and is, thus, not within the scope of this thesis. However, it should be mentioned that
the EO-AAC is an improved version of the AAC, because it allows for a continuous direct
current path. Moreover, the EO-AAC can operate at any ac-to-dc voltage ratio since it has
its direct current path decoupled from the ac current paths just like the MMC.
Table 3.2: Advantages and challenges of the AAC.
Advantages Challenges
+ Reduced power loss − Dc capacitor needed 1
+ Reduced component expenditure − Complex control & limited operating range 1
+ Reduced capacitor size − Series-connected semiconductor devices
+ Dc-fault controllability − Higher harmonic distortion than the MMC
1 The EO-AAC removes this drawback [49].
1.28
1.27
1.26
Modulation index m
1.25
1.24
1.23
Analytical calculation
1.22 Simulation result
1.21
0 15° 30° 45° 60°
Overlap angle (2 α)
Figure 3.6: Comparison of the analytical M-α relation and simulation results.
3.4 Energy Storage Requirements

According to motive M.2, it is considered to be useful to compare different types of mod-
ular VSCs with regard to their footprint. The objective is to identify solutions to reduce
converter volume and mass. In [Publication I], the MMC with HB and FB SMs as well
as the AAC have been benchmarked with focus on their capacitor sizing. The aim of
[Publication I] is to present a general analysis of the energy storage requirements for
these converters under various operating conditions.
The minimum required nominal stored energy can be found by taking the lower and
upper SM voltage limits into account, whereby the minimum voltage must be greater than
the reference voltage, while the maximum voltage must not exceed the rated voltage of the
SMs. The method presented in [Publication I] is calculating the required energy storage
per transferred VA based on those limits. It should be noted that the performed analysis is
based on the steady-state without considering margins for transients, faults, or additional
SMs for redundancy. Concerning the AAC, the operational mode with overlap period is
taken into account.
analysis are plotted in Fig. 3.7. It is shown that operating the MMC
The results of the √
with FB SMs at M = 2 reduces the energy storage requirements considerably compared
to HB SMs, which is in line with the results presented in [50]. There, it is found that during
nominal operating conditions of the MMC, a large amount of energy is moved back and
forth between the upper and lower arms. In order to minimize the energy variations in the
3.4. ENERGY STORAGE REQUIREMENTS 21
SM capacitors, these energy oscillations should be kept as small as possible. They√can be

eliminated at active power transfer if the modulation index is increased to M = 2. As
regards the AAC, it can be concluded from Fig. 3.7 that the required SM energy storage is
smaller compared to the MMC, even for extended overlap periods. Thus, it is likely that
the AAC can be designed with less capactive energy storage than the MMC.
90° MMC (m = 1.0) 90° AAC (m = 4/π)

√
MMC (m = 2) 30
120° 60° 120° 60° AAC (m = 0.9 · 4/π)
60 AAC (m = 4/π) AAC (m = 1.1 · 4/π)
20
40
150° 30° 150° 30°
10
20
±180° 0° ±180° 0°
-150° -30° -150° -30°
-120° -60° -120° -60°

-90° -90°
(a) Half- and full-bridge MMC vs. AAC (b) AAC operating 10% away from the sweet spot
90° AAC (no overlap, m = 4/π)
30
120° 60° AAC (30◦ overlap, m = 1.259)
AAC (60◦ overlap, m = 1.216)
20
150° 30°
10
±180° 0°
-150° -30°
-120° -60°
-90°
(c) AAC operating with overlap period acc. to M-α relation
Figure 3.7: Required nominal energy storage in kJ/MVA

Chapter 4
Submodule Topologies
This chapter serves as an overview of SM topologies in general and should prepare the
ground for the SFB topology in particular, which will be discussed in Chapter 5 hereafter.
The content of this chapter can be found in most of the appended publications, notably in
Publication II.
SMs are the fundamental building block of MMCs. All SM topologies consist of one
or several capacitors and a varying number of power semiconductor devices. Each SM
contributes to the total arm voltage with its own capacitor voltage, whereby the insertion
of the capacitor can be controlled by the semiconductor switches. Today, converters with
HB SMs or FB SMs are the only commercially available technology. Therefore, those
two topologies are hereafter referred to as state-of-the-art SMs. In order to balance power
loss, semiconductor cost, and SM functionality, a large variety of other topologies have
been proposed in literature [20–27]. They are termed advanced in this thesis since they
have not been employed in a real converter at the time of publication. The relevant SM
topologies for this thesis are illustrated in Fig. 4.1. They are reviewed and evaluated in
[Publication II] and [31] in order to address research motive M.1. A brief summary of
their merits and drawbacks is presented in the following sections.
4.1 State-of-the-Art Submodules

The dominating type of SM for HVDC applications is the HB SM, shown in Fig. 4.1(a).
The reason is that this type of SM has the lowest losses and the lowest cost. It has two
switching states, either inserting the capacitor voltage into the converter arm or bypassing
it. This enables the operation of the MMC with a modulation index in the range of {0, 1}.
Since the current passes through only one switch in both states, the HB topology offers
extremely low conduction losses. A significant drawback, however, is that it loses control
over both ac-side and dc-side currents in case of a fault on the dc side. This property makes
it less useful in HVDC grids, at least when not equipped with fast DCCBs [17].
23
24 CHAPTER 4. SUBMODULE TOPOLOGIES
)1 +3 -1 /0
23
M1 C1
*2 ,4 .2 15
C1 C1
N2
Vsm switches capacitors
V sm switches capacitors
-1 O2P Q3 -Vc1
-1 `2a b3c de -Vc1
Vsm switches capacitors 0 R1T U3 -
0 f1g h2i jkl m5 - *
0 ^2 - 0 V2W XY -
1 n1o p3q r5 Vc1
1 _1 Vc1 1 Z1[ \] Vc1 * parallel connestuvw xy z{|}~
(a) (b) (c)
31 63
C1 >1 C3 @A
52 78 :;
C2 ?2 B5 KL GH
95 <= C1
DE I
C2 J
V sm switches capacitors
-1 È2É Ê3Ë Ì5Í ÎÏ -(Vc1 ÐÑ Vc2) *
0 Ò1Ó Ô3Õ Ö× - V sm switches capacitors
0 Ø2Ù ÚÛÜ ÝÞ - -1 2 3 -(Vc1 Vc2) *
0 ß2à á5â ãä - 0 all exc 3 5 - *
1 å1æ ç3è é5ê ëì Vc1 íî Vc2 * 1 1 3 ¡¢ £¤¥ ¦§¨ ©ª Vc1 «¬ Vc2 *
2 ï1ð ñòó ôõ Vc1 ö Vc2 2 1® ¯3° ±5² ³´µ ¶· Vc1 ¸ Vc2
* parallel conne÷øùúû üý þÿ
c * parallel conne¹º»¼½ ¾¿ ÀÁÂÃÄÅÆÇ
(d) (e)
S
1
4
3

2 C1 5 8
7

6
C2 9

12
11

V sm switches capacitors 10 C3 13
-1 2, 10-12 -(Vc1 Vc2 Vc3) *
0 a !"# $3% &5' ()* +-. /11 - *
1 all exc0 123 55: ;<= >12 Vc1 ?@ Vc2 AB Vc3 *
2 CDEFGHIJKLM N10O P12Q R13 Vc1 T Vc2 *
2 rs tuvwxyz{|}~ tates
3 UVWXYZ[\]^ Vc1 _ Vc2 ` Vc3
* parallel connebdefg hi jklmnopq
(&'
Figure 4.1: SM topologies and their switching states, including SM voltage Vsm , active
switches, and active capacitors. State-of-the-art SMs: (a) HB, (b) FB. Advanced SMs:
(c) DZ, (d) SFB, (e) DCDZ, (f) CDZC3 .
4.2. ADVANCED SUBMODULES 25
In a FB SM, Fig. 4.1(b), on the other hand, the alternating voltage is independent of
the dc-side voltage. The FB can generate three voltage levels, offering the possibility to
apply negative voltage at the SM terminal and provide a counter voltage in case of dc-side
short circuits. Thereby, the FB prevents short-circuit currents flowing from the ac to the
dc side. An MMC employing FB SMs can operate with a modulation index in the range
of {0, ∞}. Moreover, since FB SMs can control the current, the diodes do not need an
overcurrent protection. Thus, the high-current bypass switch can be omitted compared to
a HB SM. Yet, it should be noted that the FB features two additional switches compared
to the HB, which leads to a doubling of power semiconductor cost and significantly in-
creased conduction losses, because there are always two switches in the arm current path.
Such an increase in losses is generally not acceptable in most high-power applications [18].
Furthermore, it is shown in [Publication II] and [31] that the FB SM topology is particu-
larly unfavourable for an implementation with SiC metal-oxide-semiconductor field effect
transistors (MOSFETs).
A mixed SM, or hybrid, configuration consisting of both HBs and FBs can reduce
losses and cost. Such an arrangement has been investigated in literature [51–54]. However,
depending on the SM ratio this implementation is limited in its operating range due to the
energy balancing between HB and FB SMs. In the case of unipolar arm currents, it is not
possible to balance the charge of a converter arm. It should be mentioned that no such
hybrid SM configuration has been studied in detail within the scope of this thesis.
4.2 Advanced Submodules

Due to the described disadvantages associated with the HB, FB, and hybrid configuration,
there is a need to develop new SM topologies with improved performance and extended
functionality to comply with the requirements of HVDC grids outlined in Section 2.2.
The application of SiC power semiconductors is one option to improve future SM topolo-
gies. This is discussed in [Publication II], [31] and [55]. SiC MOSFETs offer signifi-
cant advantages regarding losses in combination with some SM topologies featuring par-
allel conduction paths. Future UHV SiC devices promise reduced converter losses and
complexity, since less auxiliary equipment and SMs are required. Another possibility for
SM improvement is to make changes regarding the design and structural properties. Two
promising approaches shall be introduced here. One is the double-connection of two suit-
able SMs [18, 33], the other is the introduction of an additional switch in the capacitor
path [30, 32]. Both options lead to improved topologies with essentially reduced power
losses and the capability to block dc-fault currents. These benefits, however, in most cases
do not come for free, but at the cost of higher expenses for the semiconductors.
The double-zero (DZ) SM, Fig. 4.1(c), falls into the latter category. Switching out the
capacitor enables a bypass state with very low on-state resistance because the arm current is
split into two parallel paths. This state is referred to as double-zero bypass state. For power
transmission with only a small amount of reactive power, the highest arm currents can be
expected when the arm voltage is close to zero. During that time interval most SMs are
in double-zero bypass state, reducing conduction losses significantly. Moreover, the extra
switch between the capacitor terminals provides improved protection against explosion
which is a valuable feature especially for future increased capacitor voltages [31, 48].
Two SM topologies with more than one capacitor each are the double-clamp SM [56],
and the related SFB SM, Fig. 4.1(d), which is constructed by replacing the two clamp
diodes of the double-clamp SM with active switches [33, 57, 58]. The SFB can also be
thought of as a double-connection of two FB SMs and merging the two switches between
the connections into one single switch. The SFB comprises seven switches and two capac-
itors, which can be bypassed, connected in parallel, or in series. Four voltage levels (two
positive, zero, and one negative) can be achieved at the SM terminals. Hence, the SFB can
replace two conventional SMs. The SFB is discussed in detail in Chapter 5.
The double-connection principle can also be applied to the DZ SM, combining the ad-
vantages of the SFB and the DZ. This topology has been presented as the double-connected
double-zero (DCDZ) SM, Fig. 4.1(e), in [54]. Both topologies enable efficient handling
of dc-side short circuits, whereas the SFB also uses less semiconductors than two conven-
tional FB SMs. Both the SFB and the DCDZ provide the possibility to operate the converter
at increased modulation indices, which can significantly reduce the energy storage require-
ments of the SM capacitors. As regards the DCDZ, since the parallel connection of the two
capacitors is possible in all switching states except 2VC , a reduction of the capacitor size to
almost 50 % can be achieved [59].
In [Publication II], a novel SM cluster is proposed. By double-connecting DZ seg-
ments, the topology presented in Fig. 4.1(c) can be extended to an arbitrary amount of
capacitors. The topology is called cascaded double-zero cluster (CDZCn ), where ‘n’ is
the number of capacitors, i.e., the CDZC3 cluster, Fig. 4.1(f), consists of three capacitors.
Depending on the amount of capacitors in the cluster, the converter conduction losses can
be further reduced. The advantages of the CDZCn are low conduction losses, increased ro-
bustness against cluster-internal short circuits (like the DZ and DCDZ), reduced auxiliary
equipment such as control hardware and cabling, and larger building blocks, which may
enable advanced in-house testing and faster converter assembly times.
Amendment: In [Publication II], the CDZCn has been presented with enhanced nega-
tive voltage capability, where n is the amount of capacitors in the cluster. In particular, the
variant with n = 4 has been identified as interesting. Further investigations have, however,
shown that some of the described switching states cause a short circuit between capacitor
terminals. In the following, this will be discussed on the example of the CDZC4 , but has to
be addressed similarly for all cluster variants with n ≥ 4. The state -2Vc and corresponding
short circuit paths are shown in Fig. 4.2. A solution to this issue could be to replace S6
and S12 with semiconductor devices without anti-parallel diode. A drawback would be
increased complexity and potentially higher conduction losses for certain states, depend-
ing on the type of semiconductor. A SiC MOSFET is not suitable because of its inherent
body diode. An insulated gate bipolar transistor (IGBT) has no inherent anti-parallel diode,
but a built-in potential, lowering the benefit of parallel-connected current paths regarding
conduction losses. SiC junction gate field-effect transistors (JFETs) have no built-in diode
and feature a resistive conduction characteristic in forward and reverse direction. How-
ever, since SiC JFETs are normally-ON devices, they have other disadvantages, e.g., short
circuits if gate-drive power is lost.
4.3. SUBMODULE COMPARISON 27
iarm
S1 S4
S3 isc
S2 C1 S5 S8
S7
S6 C2 S9 S12
S11
S10 C3 S13 S16

S15
replace with S14 S17

C4
Figure 4.2: CDZC4 in state -2Vc causing a short circuit and discharge for C1 and C4 and
proposed solution by replacing S6 and S12 with power semiconductor devices without anti-
parallel diode.
4.3 Submodule Comparison

The previously discussed topologies are reviewed and evaluated in [Publication II] and
[31]. A brief summary is given in this section. Table 4.1 provides a comparison of SMs
regarding their structural properties, voltage capability, fault handling, complexity, and
losses. Generally, there is a trade-off between the complexity of a SM and its functionality
and reliability. The SMs are classified regarding their terminal voltage into unipolar, bipo-
lar, and asymmetric bipolar. A SM has bipolar voltage capability if the capacitor(s) can
be connected to the terminals in either polarity, i.e., both positive and negative voltage can
be inserted into the arm. This characteristic is also called “FB functionality” [18]. Bipo-
lar voltage capability is important for certain operating points and dc-fault handling. It is
worth noting that a SM with bipolar voltage capability can be operated at elevated modu-
lation index, which reduces the energy storage requirements of the converter. This feature
is described in detail in [Publication I] and Section 3.4. As regards dc-fault handling, it is
reasonable to distinguish between dc-fault blocking and dc-fault controllability. Dc-fault
blocking is the capability of a SM to generate negative voltage at its terminals by turning-
OFF (blocking) all switches. Topologies with dc-fault controllability, however, retain full
control over their switches and, thus, their current during a fault. The so-called bipolar
ratio defines how much negative relative to positive voltage can be provided. If the ratio is
one, the SM can be classified as symmetric bipolar, while if it is lower than one, the SM
can be classified as asymmetric bipolar. Such asymmetric bipolar topologies compromise
on negative voltage capability for savings in semiconductor count.
With higher capacitor voltages the protection of explosion becomes more and more
important. The most severe fault that can occur on SM level is a short circuit between the
positive and the negative terminal of one of the capacitors. Such a fault can be caused by
a failing semiconductor module. The resulting explosion may also destroy neighbouring
equipment. Therefore, it should be avoided at all cost. In the DZ, DCDZ, and CDZC3
there are always three switches between the capacitor terminals, as indicated in Table 4.1.
Hence, internal short circuits are less likely, compared to the HB, FB, and the SFB.
Concerning future HVDC grids, it is expected that the choice of SM topology will
depend on power system requirements and corresponding necessary, or desired, converter
capabilities [15]. Moreover, increased robustness against SM-internal short circuits will be
more valuable.
Table 4.1: Comparison of SM topologies and their functionality.
unipolar bipolar asymm. bipolar
C3
Z
DCD
CDZ
S FB
HB
DZ
FB
Topology
Basic building block 2 FB 2 DZ 3 DZ
# switches 2 4 5 7 9 13
# switching signals 1 2 3 3 4-5 6-13
# capacitors 1 1 1 2 2 3
Double-connection • • •
# pos. voltage levels 1 1 1 2 2 3
# neg. voltage levels 0 1 1 1 1 1
Bipolar ratio 1 1 0.5 0.5 0.33
Max. modulation index Mmax 1 ∞ ∞ 3 3 2
Dc-fault controllability • • • •
Switches betw. cap. terminals 2 2 3 2 3 3
Switch parallel connection • • • •
Capacitor parallel connection • • •
Control complexity + + ◦ ◦ ◦ −
Design complexity ++ + ◦ ◦ − −
Power loss ++ − − ◦ ◦ +
(++ excellent, + good, ◦ fair, − poor)
4.4. OPERATING REGIONS 29
4.4 Operating Regions

Case 1: Fixed sum capacitor voltage per arm
The choice of SM and therefore possible modulation index has a direct impact on the
operating range and functionality of an MMC. The operating regions of an MMC with
selected SMs are illustrated in Fig. 4.3. It is important to notice that the direct voltage, Vd ,
is given here as sum capacitor voltage, VcΣ , of the total installed SMs in one MMC arm.
Thus, VcΣ is fixed in this first case and Vd is variable. Fig. 4.3 shows that the operating
region of an HB-MMC (blue) can be extended with other SM implementations. The use of
SFB or DCDZ SMs (red) allows for such an extension. The possible operating range can
be maximised with FB and DZ SMs (yellow).
The difference between the SM types lies in the region where Vd < VcΣ . For the HB-
MMC, the ac component can never exceed the dc level in the output, i.e., no alternating
voltage can be provided in case of a dc fault and zero dc-link voltage. This is only possible
with SMs that can insert negative voltage. The FB and DZ SM, for example, can produce a
pure ac component or a dc component with fully reversed negative polarity, which can be of
interest if interoperability with current-source converters is required. Infinite modulation
index is in theory possible
√ for both topologies. The possibility to operate the MMC at
modulation index M = 2 (included in Fig. 4.3) is an attractive feature, because the active
power transfer for a given combined power rating of the semiconductors is maximized and
the storage requirements of the SM capacitors are minimized [50].
Fig. 4.4 shows the MMC arm voltage waveforms of the investigated SMs. The higher
the modulation index, the more has the dc level (dashed lines) to be reduced in order to ac-
commodate the ac component. It can also be seen that the modulation index is restricted to
M = 3 for a SFB or DCDZ MMC (red) since only half of their arm voltage can be inserted
with negative polarity.
Case 2: Fixed dc-link voltage

Fig. 4.5 shows the operation region under the condition that Vd is fixed and VcΣ is variable.
Unlike the previous case, more SMs need to be installed in order to reach a higher modula-
tion index since the dc-link voltage is kept constant. But it is again shown that the ac peak
voltage is limited for SFB or DCDZ SMs (red), whereas an MMC with FB or DZ SMs
√ operate at M = ∞. Designing an MMC for a modulation index
(yellow) could potentially
much higher than M = 2 is economically not reasonable, though. This becomes clear by
looking at the MMC arm voltage waveforms for the considered case in Fig. 4.6. In order
to achieve M = 3 (yellow), the MMC arm needs to be rated for twice the dc-link voltage,
i.e., double the amount of SMs need to be installed compared to the case with M = 1.
HB
DCDZ, SFB
DZ, FB
Mmax
]s[ emiT
Figure 4.3: MMC operating region for different SM implementations in terms of alternat-
ing voltage, v̂S , and direct voltage, Vd , given as sum capacitor voltage per arm, VcΣ .
HB
DCDZ, SFB
DZ, FB
Arm voltage [pu]
0 Varm,min
Varm,min
Varm,min
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [s]
Figure 4.4: MMC arm voltage, given as sum capacitor voltage VcΣ , for different SM imple-
mentations operating at their highest possible modulation index.
4.4. OPERATING REGIONS 31
HB

Figure 4.5: MMC operating region for different SM implementations in terms of alternat-
ing voltage, v̂s , and sum capacitor voltage per arm, VcΣ , given as dc-link voltage, Vd .
Arm voltage [pu]

Figure 4.6: MMC arm voltage, given as dc-link voltage Vd , for different modulation in-
dices.
Chapter 5
The Semi-Full-Bridge Submodule
The content of this chapter is based on Publications III, IV, and V.
Various operation and control aspects of the SFB SM have been investigated by means of
analytical studies, simulations, and experiments. An overview of the conducted research,
applied methods, contributions, and corresponding publications is provided in Fig. 5.1.
The potential problem of the parallel connection of SM capacitors with different voltages
is studied in [Publication III] and [Publication IV]. To be more specific, the redistribu-
tion current due to an existing voltage imbalance between the two capacitors of the SFB is
investigated and quantified in [Publication III]. Based on these findings, a control strategy
that can prevent such excessively high redistribution currents is presented and experimen-
tally verified in [Publication IV]. A new switching strategy is proposed and validated in
[Publication V], which enables a significant reduction of the switching losses of the SFB.
In summary, the impact of the capacitor voltage imbalance on the operation of the SFB
SM is identified, and several options for an improved operation are presented. It can be
concluded that excessively high redistribution currents can be prevented by implementing
proper control strategies, and that those are, therefore, not an obstacle for using the SFB
SM in future HVDC converters.
5.1 Introduction
The SFB SM is a promising new SM implementation for HVDC converters to be used in
future dc grids. This SM topology is particularly interesting because it uses less semicon-
ductors than the conventional FB SM, while still being able to generate negative termi-
nal voltages at both current directions, which gives it the inherent capability of handling
dc-side short circuits. The SFB also provides the possibility to operate the converter at
increased modulation indices, which can significantly reduce the energy storage require-
ments of the SM capacitors [50]. Furthermore, the combined power rating of the devices
in the SFB is 25 % lower compared to two FB SMs, considering that the middle upper and
lower switches are rated for half of the arm current. If all switches have the same current
33
34 CHAPTER 5. THE SEMI-FULL-BRIDGE SUBMODULE
¡¢£¤¥¦§ ¨

prototype
©ª«¬®¯°±²³ ´
Figure 5.1: Overview of research on the SFB SM: methods, contributions, and correspond-
ing publications.
rating, the combined power rating of the SFB is 12.5 %. Given these features, convert-
ers employing SFB SMs would meet several of the requirements outlined in Section 2.2.
The corresponding benefits of the SFB are summarized in Fig. 5.2. Despite these obvious
benefits, there has previously been the open question about possible high current spikes if
the capacitor voltages are not equal, because the SFB requires the parallel connection of
capacitors during normal operation, see Fig. 5.3. Due to the low impedance of the circuit,
any voltage imbalance may give rise to excessive redistribution currents and subsequent
oscillations between the two capacitors. From a reliability point of view this could impair
the applicability of the SFB in future HVDC converters. The aim of this research is, thus,
to provide answers and solutions on how to reliably operate the SFB SM.
5.2. CAPACITOR VOLTAGE IMBALANCE 35
¼½¾ ¿ÀÁ ÂÃÄÅÆÇÈÉÊ ËÌÍÎÏÐ ÑÒÓÔÕÖ× ØÙ ÚÛÜÝ Þßàáâãäåæ

Reduction of power loss
çèéêëìí î ïðñòóôõ
µ¶·¸¹º» terminal voltages /Vc 0 1 , V2 3 4V5
6789: ;<=>?@ABC DEFGHI

Small footprint J KMNOPQRST UVWXYZ[ \]^_à bdn eg ijklmop qr st u
ö÷øùú ûüýþÿ L h

Low cost f !"#$% &'()*+,-.
Figure 5.2: Benefits of the SFB SM with respect to research motive M.1 and M.2.
5.2 Capacitor Voltage Imbalance

The maximum voltage difference between the two SM capacitors, ∆VC,max , and the re-
sulting redistribution current, ird , have been studied analytically, by means of simulations,
and in a full-scale standalone SM laboratory setup. The analytical parameter study of the
maximum differences in the capacitor voltages reveals that the most critical parameter is
the capacitance mismatch between the two capacitors. The results show that the amount
of voltage difference should be acceptable in most of the cases, except for those where a
very high value of the capacitance tolerance has been assumed. Neglecting these unlikely
cases, the maximum difference in the capacitor voltages is 20–30 V for switching frequen-
cies in the range of 100–150 Hz as can be seen in Fig. 5.4. It should also be noted that
∆VC,max is inversely proportional to the switching frequency. The inset shows a zoom to
low switching frequencies as they are the most relevant for today’s MMC applications.
Rres
Sv
VC L✁
ird ird
VC+xVC
Sw
ag replacements
(a) (b)
Figure 5.3: (a) Switching state when the capacitors are inserted in series. (b) Capacitors
inserted in parallel, with current path during the redistribution transient (red).
80
k = ± 2.5 %
k=±5%
60
k = ± 10 %
VC,max [V] 80
40 60
40
20
20 0
50 100 150 200 250
0
0 500 1000 1500 2000 2500
Switching frequency [Hz]
Figure 5.4: Maximum difference in the capacitor voltages as a function of the capacitance
tolerance k.
5.3 Full-Scale Prototype

A full-scale laboratory prototype of the SFB has been built for the first time. Fig. 5.5 shows
the arrangement of the two capacitors and seven IGBTs connected by three layers of cop-
per plates. The prototype allows to experimentally investigate the phenomenon of transient
redistribution currents. The importance of this realistic prototype lies in the quantification
of the current spike as well as the identification of the circuit parameters. The experimen-
tal setup and measurement results are shown in Fig. 5.6. It can be seen that the circuit
is highly damped and the oscillations cease quickly. The peak current values measured
in the 30 V and 40 V experiment exceed the repetitive peak collector current rating of the
3300 V / 800 A IGBT module, which is 1600 A. Thus, a valuable finding is that the current
reaches critical levels if the voltage difference is greater than 20 V before paralleling.
Figure 5.5: CAD drawings of the full-scale prototype of the SFB SM.
5.3. FULL-SCALE PROTOTYPE 37
3000
Vc = 40V
2500
Vc = 30V
Vc = 20V
2000
Vc = 10V
1500
Current [A]
1000
500
-500
-1000
0 0.05 0.1 0.15 0.2
Time [ms]
(a) Photograph of the laboratory prototype. (b) Measured redistribution current.
Figure 5.6: Experimental setup and measurement results.
The circuit parameter values could be obtained from the measured current and are stated in
Table 5.1. Those parameters can be used in the analytical expression of the redistribution
current given in (5.1) such that its peak value can be predicted from measurements of the
capacitor voltage difference, ∆VC = VC2 −VC1 . Based on this knowledge, the SM controller
or the high-level control can decide on how to handle the voltage imbalance.
Table 5.1: Parameters of the full-scale SFB prototype.
Parameter Symbol Value

Submodule capacitance C1,2 4 mF
Stray inductance Lσ 230 nH
Equivalent resistance Rres 7.85 mΩ
∆VC − Vth,D − Vth,IGBT −t/τ

ird (t) = s e sin(ωt) (5.1)
R2res

1 1
Lσ + −
C1 C2 4
5.4 Optimised Operation

The basic operation principles of the SFB are described in detail in [Publication III, IV,
V] and are, therefore, deliberately kept concise here. The available voltage levels, VSFB , are
0, ±VC, and 2VC . Table 5.2 lists possible combinations of switching states to insert these
voltage levels. Detailed illustrations of all these switching states for positive and negative
arm currents are provided in [Publication V].
Table 5.2: Switching states of SFB SM.
VSFB Insertion of capacitors S1 S2 S3 S4 S5 S6 S7

2VC in series 1 0 0 1 0 0 1
VC in parallel 1 0 1 0 1 0 1
0 bypassed 0 1 0 1 0 1 0
0 bypassed 1 0 1 0 1 1 0
0 bypassed 0 1 1 0 1 0 1
−VC in parallel 0 1 1 0 1 1 0
New switching sequence for loss reduction

In order to avoid high oscillating redistribution currents when the two capacitors are con-
nected in parallel, it can be concluded from [Publication III] that it could be a viable
option to operate the SFB at elevated switching frequencies. However, a higher switching
frequency increases the switching losses of the SM. This motivated the investigation of the
average switching frequency and the corresponding switching losses associated with dif-
ferent choices of bypass states presented in [Publication V]. The goal was to find improved
switching sequences with lower losses.
Since transitions between parallel inserted and bypass coincide with high arm current,
there is a potential to reduce losses if these transitions are improved. The very first paper
on the SFB SM describes only one bypass state out of three possible options [33]. The two
additional bypass states are highlighted in red in Table 5.2. It should be pointed out that
all switches must be rated for the full arm current if these states are used. [Publication V]
reveals that a different number of switches are involved during transitions between insert
states and bypass states depending on the choice of the bypass state. The analysis shows
that the switching losses can be significantly reduced by using the alternative bypass states.
The effectiveness of this modulation scheme is validated by simulations of a SFB-
MMC at different operating points. Moreover, the simulation model enables the quantifi-
cation of the switching losses and a comparison to an implementation with FB SMs. The
main simulation results are presented in Fig. 5.7, whereas a detailed switching loss break-
down per device is provided in [Publication V]. The results show that operating the SFB
with the original proposed switching states lead to higher switching losses compared to a
FB implementation and that a loss reduction of up to 60 % can be achieved by employing
the alternative bypass states.
5.4. OPTIMISED OPERATION 39

Original bypass Alternative bypass
Diode Diode Diode
yz{|

[pu]
loss

~
}
M = 0.9 M = 1.4
Figure 5.7: Switching losses of a SFB and FB implementation at two operating points.
New control scheme - Balancing controller

A controller is proposed in [Publication IV] to limit the redistribution current by enabling
the balancing of the capacitor voltages before their difference exceeds a critical threshold
voltage. The fundamental principle is that only one capacitor is inserted, allowing the
arm current to either discharge the capacitor with higher voltage or charge the one with
lower voltage. Both current directions can be handled, but the control methods are either
passive (“self-balancing”) or active for negative and positive arm currents, respectively.
Illustrations of the current paths for both methods are given in Fig. 5.8 and Fig. 5.9. Further
details can be found in [Publication IV]. There, it is also shown by simulations of an
MMC equipped with five SFB SMs per arm that the impact of the balancing controller on
the output waveforms is small. It can be concluded that the controller does not impair the
converter operation.
The proposed balancing control technique has been implemented on a down-scaled
MMC prototype to verify its functionality experimentally. Details of the experiment are
provided in [Publication IV]. Fig. 5.10 and Fig. 5.11 show that the controller signifi-
cantly reduces the peak current, which verifies its functionality. It should be noted that
additional measures to ensure a safe and reliable operation of the SFB are discussed in
[Publication III] and [Publication IV].
S S3 S¤ S3
A C¢ A Cª
S S S¡ S¥ S¦ S©
C£ B C« B
S S S§ S¨
ag replacements
(a) (b)
Figure 5.8: Current path during self-balancing control, iarm < 0. (a) Current path for
VC1 < VC2 . Discharge VC2 . (b) Current path for VC1 > VC2 . Discharge VC1 .
S¬ S3 S´ S3
A C² A Cº
S S® S± Sµ S¶ S¹
C³ B C» B
S¯ S° S· S¸
ag replacements
(a) (b)
Figure 5.9: Current path during active balancing control, iarm > 0. (a) Current path for
VC1 < VC2 . Charge VC1 . (b) Current path for VC1 > VC2 . Charge VC2 .
5.4. OPTIMISED OPERATION 41
Ì 5
Current [A]
Ë
ÉÊ
ÆÇÈ
ÃÄÅ -
¼ ½ ¾ ¿ À ÁÂ 0 2 4 6 8 1
Ø
ÕÖ×
Ô
Í Î Ï Ð Ñ ÒÓ
êëìíîïð ñò
àáâãäåæ çèé
Ù Ú Û Ü Ý Þß
series
parallel
ag replacements ó ô õ ö ÷ øù ! "#
úûüý þÿT $%&' ()*+
(a) (b)
Figure 5.10: Measurements on down-scaled MMC prototype: Internal SM current and

control signal. (a) No control. (b) VC,max = 0.2V .
<=>
79:
,./
Figure 5.11: Normalized peak redistribution current measured over a period of 0.5 s.
Chapter 6
Auxiliary Power Supplies
The content of this chapter is based on Publications VI, and VII.
The availability of a reliable APS system with sufficiently high isolation and resilience
against EMI has been identified in this thesis as a critical technology gap towards the re-
alization of future UHVDC converters required for a large-scale, high capacity dc grid. It
has been pointed out in [Publication VI] and [Publication VII] that recent developments
in HV silicon and SiC power semiconductor devices are challenging state-of-the-art con-
verter and APS designs. In the future, it is likely that HV SiC technology will be employed
in HV SMs, enabling capacitor voltages of up to 30 kV. In this case, robustness against
electromagnetic noise will become even more important, because gate-drive units (GDUs)
and control electronics may be easily interfered due to the fast switching and high dv/dt
of HV SiC devices. However, state-of-the-art APS concepts are not suitable for such SM
ratings and corresponding extreme isolation requirements.
The technical solutions described in this chapter focus mainly on research motive M.3,
but address as well motive M.2, see Table 2.5. An overview of the conducted research,
applied methods, contributions, and corresponding publications is provided in Fig. 6.1.
In [Publication VI], state-of-the-art and alternative APS concepts have been reviewed,
classified, and evaluated regarding requirements for high-power converter applications. In
addition, future prospects of APS systems are discussed based on technology developments
of APS concepts, on the one hand, and technical trends with respect to converter main
circuits, e.g., (U)HV SiC devices and UHV SMs, on the other hand.
The described challenges are addressed in [Publication VII] by developing a combined
optical power and data transmission concept tailored to the specific requirements of HV
converters employing UHV SiC devices (>10 kV).
43
44 CHAPTER 6. AUXILIARY POWER SUPPLIES
F?@ABe prospects of
APS systems
POF-based APS options

for MMC submodules
Figure 6.1: Overview of research on APS solutions for HV applications: methods, contri-
butions, and corresponding publications.
6.1. INTRODUCTION 45
6.1 Introduction
Auxiliary power is required in almost all HV applications to energize GDUs, control elec-
tronics, sensors, protection circuits, and further electronic equipment. The APS is, there-
fore, an important converter component and has an influence on the overall reliability and
efficiency of the converter system. The reference point of this voltage is often not on
ground potential but on a high or even switched voltage. Depending on the application,
i.e., the power and voltages involved, supplying this auxiliary power may require special
attention and careful design. In general, there are two ways of supplying power to the
SMs in an MMC. One approach is to supply this power from the SM capacitor (internal).
The second option is to take the power from a central power source with the same ground
reference as that of the entire system (external). In this case, the gate signals and auxiliary
power are directly supplied to the SMs without the need of tapping from the capacitor.
For HV applications, such as HVDC and FACTS, the system voltage can be hundreds
of kilovolts (up to 1 MV). Such extreme requirements on isolation systems and distances
make supplying power from ground-referenced transformer-based systems infeasible. Pre-
viously, the corresponding design challenges kept external APSs from being a viable op-
tion for high-power HV converters. External powering was considered to be not practical
for these applications [60], because the possible transferable power of optical systems has
been too low until recently. However, light-based power supply systems are presently un-
der rapid development. It seems likely that their performance increases while cost reduces
in the next few years.
6.2 Classification and Concepts

The wide range of possible solutions for APSs motivates an overview of state-of-the-art and
alternative concepts. [Publication VI] presents such a review with focus on high-power
converter SMs. Possible APS concepts have been classified based on their underlying
energy transfer mechanism as shown in Fig. 6.2. They can be distinguished by their power
source as internal or external, highlighted in light and dark gray, respectively.
A qualitative evaluation of selected APS concepts, depicted in Fig. 6.3, regarding nine
technical requirements (#1–9) is provided in Table 6.1. In addition, a visual representation
of this table is given in Fig. 6.4, aiming to facilitate the identification of relative benefits
and shortcomings. The suitability of a certain APS concept is highly dependent on the re-
quirements of the application. Sometimes, a combination of concepts can be advantageous.
In the majority of cases, the most important factor deciding the choice of APS technology
is the isolation (or input) voltage. For example, the most extreme case regarding isolation
voltage is to supply power to a SM of an HVDC converter externally. The only realistic
option in this case is to use one of the optical concepts. As the voltage level goes down,
additional options are possible. In some cases, the series-connected bootstrap circuit or
snubber-based power tapping could provide a reduction of complexity and cost. However,
their need for a resistive voltage divider (or equivalent) during long OFF states of the main
power switches is a drawback.
APS concepts
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ÄÅÆÇÈÉÊ ËÌÍÎÏÐÑÒÓÔÕÖ× ¡¢£¤¥¦§

circuits ØÙÚÛÜ ÝÞßàáâãä commutated Optical li Radio Frequency
Voltage divider ¨©ª«¬® qrsuvwxyz{ Bootstrap |}~
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non-isolated isolated
IPT: Inductive power transfer POF: Power-over-fiber

ISOP: Input-series output-parallel TI: Tapped-inductor
OWPT: Optical wireless power transfer WPT: Wireless power transfer
Figure 6.2: General classification of APS concepts. Internal APS (light gray) and external
APS (dark gray).
Future internal APS solutions may build on state-of-the-art topologies, but utilize UHV
SiC technology in the APS itself to enable improved efficiency, reliability, and compact-
ness of those topologies. Flyback and TI-buck converters may be an interesting alter-
native if a HV super-cascode SiC switch replaces the series-connected MOSFETs. The
active voltage-divider-based APS in combination with a second, isolating converter is also
a promising concept for HV SMs if the required power is relatively low. Higher input
voltages may be possible with SiC power devices with higher voltage ratings, such as the
SiC super-cascode. Furthermore, HV SiC devices have reduced auxiliary power demand,
potentially allowing the use of low-power APS concepts. However, SiC technology may
motivate to increase the switching frequency of MMCs to facilitate smaller, lighter systems
that are more efficient and likely less expensive.
Several advantages are achievable by employing external APS solutions, as described
in [Publication VI] and [Publication VII]. Most importantly, this approach has the po-
tential to significantly improve system robustness and safety. Since APSs and GDUs are
independent of the local SM capacitor voltage, they can be always powered up and, hence,
the SMs can be controlled regardless of the capacitor voltage. This means also that con-
dition monitoring and diagnostics become possible at all times. In addition, a faster and
easier converter start-up can be realized, because the SMs can start pulse-width modulation
(PWM) right away.
External solutions can be combined with other APS concepts, for instance, optical
power concepts and series-connected bootstrap circuits. The power supply by light-based
APS systems is recognized in [Publication VI] and [Publication VII] as a particularly
promising emerging solution, which could prove to be useful in future HV applications.
The optical power concepts, which have been proposed and investigated as part of this
PhD project, are discussed in the next section.
6.2. CLASSIFICATION AND CONCEPTS 47
S2 Vo
Shv
Råæ
Csm Vsm Vsm
Cs R L1 L2
Vsm Rlv Sçè
S1 R1
Vo
R2 Vo Dz Slv Vo
(a) (Active) (b) Snubber (c) TI-buck (d) Monolithic flyback

Voltage divider
Dôõö÷
Csm,2
GDU
Vsm
Dëìíî
Vsm
Sê R
Cïðñò
Sé GDU Dó Vext
Vo Vo Vo
ag replacements
(e) ISOP (f) Multi-cell (g) Series-connected bootstrap circuit
GND potential switched potential

GND potential switched potential
k
Laser OPC
Vext L1 L2 Vo Vext Vo
(h) Isolation transformer (j) POF

(i) IPT (k) OWPT
Figure 6.3: APS concepts.

Table 6.1: Qualitative evaluation of APS concepts regarding technical requirements.
frag replacements
#1 #1 #1 #1
#7 #2 #7 #2 #7 #2 #7 #2
(a) (b) (g) (h)

#6 #3 #6 #3 #6 #3 #6 #3
#5 #4 #5 #4 #5 #4 #5 #4
#1 #1 #1 #1
#7 #2 #7 #2 #7 #2 #7 #2
(c) (d) (i) (j)

#6 #3 #6 #3 #6 #3 #6 #3
#5 #4 #5 #4 #5 #4 #5 #4
#1 #1 #1 ++
+
#7 #2 #7 #2 #7 #2 ◦
–
––
(e) (f) (k) # 1 Input voltage

# 2 Output power
#6 #3 #6 #3 #6 #3 # 3 Reliability
# 4 Efficiency
# 5 EMI immunity
# 6 Compactness
#5 #4 #5 #4 #5 #4 # 7 Start-up time
(a) Internal APS concepts. (b) External APS concepts.
Figure 6.4: Comparison of APS concepts (visual representation of Table 6.1).

6.3. OPTICAL POWERING 49
6.3 Optical Powering

It is reasoned in [Publication VI] that optical power concepts and bootstrap circuits may
complement each other very well. The SM cluster proposed in [Publication II] is consid-
ered an especially interesting case for their combined application in MMCs. Each cluster
would need a primary power supply, which can be supplied by power-over-fiber (POF) or
optical wireless power transfer (OWPT) to the first SM in such a cluster, while the series-
connected bootstrap circuits supply power to the APSs of the remaining cluster SMs. This
novel APS concept is illustrated in Fig. 6.5.
u

r)*+,-./01 measurements
O
L
øùúûüýþ ÿ
Central controller
external A!" #$%&'( 234 5
C
Cluster S KMN 678 n

9:;
<=> ?@BDEFGHI J PQR
Cluster n
Power
Data Submodule n TUV
Figure 6.5: Optical powering with SM clusters and series-connected bootstrap circuits
(based on [61]).
As regards POF-based systems, a wide variety of applications has been presented in lit-
erature, but [Publication VII] specifically focuses on applications in the HV range. There-
fore, technical requirements and design goals are devised, which are tailored to the specific
needs of advanced HV converters with the focus on application dependent power demand,
EMI resilient data detection, and reliability. POF technology is used in [Publication VII]
for the combined transfer of power and data over a single optical fiber. In the proposed con-
cepts, amplitude-modulated light represents a PWM signal that could be used for control
of, for instance, power semiconductor devices in high-power converters.
Different implementations for an MMC SM are suggested and illustrated in Fig. 6.6
with simplified schematics of HB SMs. The combined transmission of optical power
and data over one single fiber is reflected in the solutions presented in Fig. 6.6(c) and
Fig. 6.6(d). Major advantages are conceivable with all of the three external options as
described in the previous section. It can also be expected that the proposed POF-based
concept reduces converter volume and complexity, since the amount of auxiliary electron-
ics will be reduced. A very compact design is possible that can likely be integrated into a
power module, which is an interesting solution with respect to motive M.2.
Power Data Isolation

POF
GDU GDU GDU GDU

ag replacements
GDU APS GDU APS GDU APS GDU
POF POF POF
a) b) c) d)
Figure 6.6: APS options for an MMC SM: (a) Power supply from SM capacitor with
separate data link and isolated power to high-side GDU, (b) POF-based power supply with
separate data link and isolated power to high-side GDU, (c) Single-fiber combined optical
power and data with isolated power to high-side GDU, (d) Single-fiber combined optical
power and data directly to GDUs.
In [Publication VII], a signal detection method is presented which is specifically de-

signed to target high robustness by avoiding high-pass filters and edge detection. The
method relies on the current-source behaviour of the optical power converter (OPC). The
amplitude-modulated light signal can be detected as a robust change in output current.
Even though the concept is generally applicable, an experimental verification aiming for a
gate driver of a switch in an MMC is presented. The signal can be low-pass filtered (for
noise immunity) and forwarded to a power stage of a GDU.
The equivalent circuit diagram of the combined power and data transmission is shown
in Fig. 6.7. The behaviour of the proposed system is validated by simulations and experi-
ments. A comparative presentation of the results is shown in Fig. 6.8. A laser pulse (red)
of 10 µs length is applied in order to determine the latency of the proposed circuit. Fig. 6.8
shows a zoom into the rising and falling edge of the pulse, respectively. From the mea-
surement results, it can be concluded that it is possible to achieve transmission of a control
signal with a latency of less than 500 ns for a GDU of a high-power converter. The concept
can easily be scaled up to powers of several watt.
6.3. OPTICAL POWERING 51
Vcc Detection
R delay Vx Vslm
D3 R1
Vmeas
j
k
R lim R2 Vnop
D4 C delay
IWXY L D2
Plaser
OPC
Radd
Vout = 20 V
Vcc = 5 V
D1 Cout DZ DC
Z[\]^
Control
DC
_àbc defg hi
qtv
}~ Boost wxyz{|
Figure 6.7: Simplified diagram of the proposed POF system with novel signal detection
circuit.
Plaser µ
¶·¸
¹
x

® ¯ °±²³´
ÅÆÇÈ
5

Ä
Ã
Â
Á
À
¿
¾
½

2 ¼
»
º
1
ag replacements
¥¦ § ¨©ª«¬ low
(a) Signal pulse
-1
(b) Rising edge -0.5 0 0.5 1 11
(c) Falling edge s) ¡¢ £¤ s)
Figure 6.8: Signal detection: experimental (solid) and simulation (dashed) results.
Chapter 7
Closure
7.1 Conclusions
In this thesis, a series of original contributions has been made in advancing the power
electronic converter topology, modulation and control for handling fault currents in HVDC
grid applications, and reliably powering APS systems of future UHV SMs.
Different VSC converter topologies are evaluated in terms of their energy storage ele-
ments, because this is a costly component with high space requirements. A fair comparison
between the AAC and FB-MMC has been presented in order to compare the physical vol-
ume of capacitors required by each topology. It is found that the SM capacitor size of the
AAC can be reduced compared to the MMC. Besides, component expenditure and power
losses of the AAC topology appear favourable. Thus, it can be reasoned that the AAC may
be a viable alternative to the MMC in HVDC applications, especially when a converter
station with small footprint is preferred.
Several requirements and capabilities for converters in HVDC grids have been derived.
Promising MMC SM topologies, i.e., SMs which fulfil these requirements, have been stud-
ied and improvements are suggested. A novel type of SM cluster is proposed and compared
to relevant other SM arrangements. Implications for the converter operation and function-
ality are investigated. It has been found that the cluster features low conduction losses,
reduced auxiliary equipment, and increased robustness against cluster-internal short cir-
cuits. It can be concluded that this SM topology is a suitable candidate for future VSCs.
Moreover, the study of the SFB SM was important to contribute to enabling HVDC
grids. The SFB can handle dc grid faults, but requires the parallel connection of capacitors
during normal operation. Since this paralleling can cause a high balancing current inside
the SM, it is important to know its characteristics and how to prevent excessively high
currents by implementing proper control strategies. These questions have to be solved for
SFB-based converters to be accepted. This thesis provides the corresponding answers. The
resulting current spike when the two capacitors are connected in parallel has been analysed
in a full-scale laboratory experiment and a balancing controller is proposed, which reduces
a potential voltage difference safely if a certain maximum value is surpassed. In addition, a
53
54 CHAPTER 7. CLOSURE
new switching method is devised that enables a significant reduction of switching losses. In
summary, it has been shown that it is possible to operate the SFB SM safely and efficiently.
Consequently, it can be considered a very competitive, if not superior, alternative for future
HVDC converters compared to state-of-the-art SM implementations.
Furthermore, APS concepts for high-power converter SMs have been reviewed together
with a discussion of alternative solutions and approaches that can lead to improved APS
systems. This is likely a crucial design challenge in future HVDC grids. It is found that
the suitability of a certain APS technology, or choice of solution, is highly dependent on
the requirements of the application regarding, for instance, input voltage and output power,
reliability, EMI immunity, compactness, start-up time, to name a few.
Future solutions may build on state-of-the-art topologies but utilize (U)HV SiC tech-
nology to enable improvements in terms of efficiency, reliability, and compactness. It is
also recognized that several advantages are achievable by employing APSs with a ground-
referenced power source. In particular, light-based power supply systems are considered
most useful in this respect. Although comparably expensive today, they are currently under
rapid development with optimistic cost predictions. Their extreme voltage isolation capa-
bility and immunity to EMI, combined with various benefits on converter and system level,
enable them to be a very promising option for future APSs. Finally, a new APS concept
based on optical powering with POF technology has been proposed and experimentally
investigated. It offers a combined solution for a power supply with both limitless isolation
voltage and EMI resilient signal transmission. From the experimental results, it can be
concluded that it is possible to achieve a control signal transmission with a latency of less
than 500 ns for a GDU of a high-power converter, which is fully acceptable for most HV
applications.
To sum up, challenges and limiting factors of today’s converters are identified and
addressed, whereby trends and developments within and outside the research field have
been taken into account. Consequently, this thesis contributes to the possible development
of future improved converters and, in this way, to enabling increased use of renewable
energy sources as well as increased energy efficiency.
7.2 Future Work

The main focus of this work has been on technical challenges and solutions for converters
in HVDC grids. Therefore, most of the following suggestions for future work relate to
technical research questions. Nevertheless, this section shall be concluded with a few, but
important, closing remarks concerning non-technical aspects to be considered in the future.
As regards the comparison of energy storage requirements for the AAC and MMC,
the performed analysis is based on steady-state operation without considering margins for
transients, faults, or additional SMs for redundancy. Therefore, a study of required en-
ergy storage and semiconductor power rating for various fault conditions (reduced dc-link
voltage, dc fault, line-to-ground, and line-to-line faults) may be a research topic for the
future.
7.2. FUTURE WORK 55
The work on the SFB SM presented in this thesis can be deepened and broadened. The
SFB-MMC simulation models created as part of this thesis concentrate on a single con-
verter station. Those models could be extended to run simulation studies of an HVDC grid
with several SFB-MMCs. Moreover, the dimensioning of a converter equipped with SFBs
for fault cases is another suggestion for future work. An analysis of the loss distribution
among the switches of the SFB SM is also worth mentioning as some devices may switch
more frequently than others due to the balancing scheme. If the loss distribution is not
uniform, new modulation schemes could be studied for an improved loss distribution and
to further reduce the switching frequency per semiconductor device (e.g., tolerance-band
schemes). Furthermore, additional experiments can be performed in order to verify simula-
tion studies (e.g., SFB SM implementation with an integrated differential-mode choke [62],
MMC prototype fully equipped with SFB SMs). Apart from that, one could also devise an
optimized mechanical busbar system for the SFB full-scale prototype.
Concerning the conducted studies on the APS systems for converter SMs, an experi-
mental verification of some of the proposed concepts is encouraged. The externally pow-
ered SM with series-connected bootstrap circuits, for example, seems to be well suited for
experimental studies on the MMC prototype. The experiment can be set up with only one
APS per arm and series-connected bootstrap circuits supplying the remaining SMs. As
regards the POF-based studies, an interesting additional investigation would be to perform
a noise resilience test in an environment with realistic EMI levels to proof the robustness
and noise-immunity of the proposed signal detection method. Moreover, the circuit has po-
tential to be improved for reduced detection latencies and experiments with sending data
words instead of ON/OFF signals can be performed (e.g., to investigate the feasibility of
the concept in connection with distributed control). Another topic that can be studied in
the future is how to optimize communication and control network architectures for the
combined transmission of power and data. More work would also be required to realize a
bidirectional data link with the aim to save one additional fiber. Last but not least, the pow-
ering of multiple receiver units is an exciting topic to study, which could be particularly
interesting for APSs in MMCs.
The techno-economic evaluation of HVDC grids in general, and of the investigated
concepts in particular, is another direction for future research. A suitable subject would be
the assessment of a meshed HVDC grid with HB-MMCs in combination with DCCBs, on
the one hand, and fault-blocking/controlling converters, on the other hand. Such a study
can be performed regarding various aspect, such as semiconductor ratings, energy storage
requirements, losses, and response to various fault cases.
Finally, apart from technical and economic studies, but at least equally important, also
the environmental and social impact of large HVDC grids should be considered. Poten-
tial adverse effects may occur during construction, operation, and maintenance activities.
Thus, a careful investigation and comparison of possible alternatives is encouraged for fu-
ture work, along with the development of mitigation strategies and measures to prevent, or
reduce, negative consequences for flora, fauna, and humans.
List of Acronyms
AAC Alternate arm converter
APS Auxiliary power supply
CDZC Cascaded double-zero cluster
DCCB Dc circuit breaker
DCDZ Double-connected double-zero
DZ Double-zero
EMI Electromagnetic interference
EO Extended-overlap
FB Full-bridge
GDU Gate-drive unit
HB Half-bridge
HV High-voltage
HVDC High-voltage direct current
IGBT Insulated gate bipolar transistor
IPT Inductive power transfer
ISOP Input-series output-parallel
JFET Junction gate field-effect transistor
MMC Modular multilevel converter
MOSFET Metal-oxide-semiconductor field effect transistor
OHL Overhead line
57
58 CHAPTER 7. CLOSURE
OPC Optical power converter

OWPT Optical wireless power transfer
POF Power-over-fiber
PWM Pulse-width modulation
SFB Semi-full-bridge
SiC Silicon carbide
SM Submodule
STATCOM Static compensator
TI Tapped-inductor
UHV Ultrahigh-voltage
VSC Voltage-source converter
WPT Wireless power transfer
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Main Circuits, Submodules, and Auxiliary Power Concepts

for Converters in HVDC Grids

© Stefanie Heinig, August 2020

“Man muss das Unmögliche versuchen,

“Keep your eyes on the stars,

För att möjliggöra den massiva introduktionen av förnybara energikällor förutses

My time as a PhD student wouldn’t have been as enjoyable without my friends in

Stockholm, September 2020

3 HVDC Voltage-Source Converters 15

5 The Semi-Full-Bridge Submodule 33

6 Auxiliary Power Supplies 43

1.1 Background and Context

1.2 Research Motivation

1. Motive (M.1): In future interconnected HVDC networks, it is anticipated that converters

1.3 Main Objectives

This thesis focuses on:

1.5 Original Contributions

1.6 List of Appended Publications1

V. S. Heinig, K. Jacobs, K. Ilves, S. Norrga, and H.-P. Nee, “Reduction of Switching

Table 1.1: Contribution of Stefanie Heinig to the appended publications.

Analysis Simulations Experiments Writing

2 Distinguished with the “Outstanding Young EPE Member Award 2018”.

1.7 Outline of the Thesis

3 HVDC Voltage-Source Converters

Figure 1.1: Distribution of publications in the thesis.

2.1 Fundamentals and Rationale

Component Cost* [4]

2.2 Converter Requirements and Capabilities

Dc-fault handling UHV

Network services Monitoring

Small footprint Low complexity

Figure 2.3: Research motivation and corresponding converter requirements.

Table 2.1: Core requirements for research motives M.1–M.3.

Availability and reliability

Table 2.2: Requirements and capabilities for M.1 – HVDC grids.

Table 2.3: Requirements and capabilities for M.2 – Compact converters.

Table 2.4: Requirements and capabilities for M.3 – UHVDC systems.

Table 2.5: Requirements and publications with corresponding scientific contributions.

Dc-fault handling • • • • (•)

Grid code • (•) (•)

Small footprint • • • • (•) • •

HVDC Voltage-Source Converters

2-level 3-level 7-level

3.2 The Modular Multilevel Converter

Figure 3.3: Schematic diagram of a generic MMC.

Table 3.1: Advantages and challenges of today’s MMCs.

3.3 The Alternate Arm Converter

Figure 3.5: AAC waveforms in steady-state operation with overlap period.

Table 3.2: Advantages and challenges of the AAC.

3.4 Energy Storage Requirements

SM capacitors, these energy oscillations should be kept as small as possible. They√can be

90° MMC (m = 1.0) 90° AAC (m = 4/π)

-150° -30° -150° -30°

-120° -60° -120° -60°

(c) AAC operating with overlap period acc. to M-α relation

Figure 3.7: Required nominal energy storage in kJ/MVA

4.1 State-of-the-Art Submodules

(a) (b) (c)

4.2 Advanced Submodules

S10 C3 S13 S16

replace with S14 S17

4.3 Submodule Comparison

Table 4.1: Comparison of SM topologies and their functionality.

unipolar bipolar asymm. bipolar

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