Sample questions

Digital Electronics
SE ECS AY 2023-24

1. Derive the excitation tables of SR, JK, T and D flipflops.

2. Implement a mod 6 counter using IC 7490.
3. Explain how the JK flipflop overcomes the ambiguity of the S=R=1 condition.
4. Convert SR to JK flipflop (explain step –wise the conversion).
5. Explain the race-around condition in JK flipflops. Describe the working of the Master-
Slave JK flipflop and explain how the race around condition is avoided.
6. Implement a mod 10 using IC 74163.
7. Implement a 3-bit ring counter using T flip-flops and show the waveforms.
8. Explain the following terms:
i. Lock-out condition in counters
ii. Preset and Clear inputs of flipflops

9. Convert a JK flip-flop to a D flipflop.

10. Design a mod 5 asynchronous counter using JK flipflops.
11. Design a mod 4 synchronous counter using T flipflops.
12. Draw and explain a 3 bit up/down asynchronous counter using T flipflops.
13. Explain the operation of a Serial in Serial Out Shift register with waveforms.
14. State the applications of ring counters
15. Explain the working of a 4 bit twisted/ Johnson counter with JK flipflops
16. Using IC 74194 (Universal Shift register) design a twisted ring counter
17. Consider the following state diagram. Draw the state table and perform state
reduction using inspection/row elimination method. Also draw the reduced state
diagram.

18. Analyze the following Clocked sequential circuit: Identify type, state diagram and
state table:
Note: State diagrams/ Circuits as well as modulus of counter can vary in the paper. These
questions are to be treated as a sample