EE101 Lecture 9

Introduction to Digital Logic
Lecture 9:
Implementing Logic Functions w/
Decoder, Multiplexers, and
Memories
© Mark Redekopp, All rights reserved

Logic Function Synthesis
• Given a function description as a T.T. or
canonical form, how can we arrive at a circuit
implementation or equation (i.e. perform logic
synthesis)?
• 5 methods to be discussed
– Canonical sum/product + Simplification w/ theorems
– Karnaugh Maps
– Decoders + 1 gate per output
– Multiplexers
– Memories (used as Look-Up-Tables [LUT’s])

Decoders
• A decoder is a building block that:
– Takes in an n-bit binary number as input
– Decodes that binary number and activates the corresponding
output
– Individual outputs for EVERY input combination (i.e. 2n outputs)
3-to-8 Decoder
D0
D1
D2
3-bit binary
Z (LSB) 1 output for each
D3
number Y combination of the
D4
X (MSB) input number
D5
D6
D7
Decoders
– Takes a binary number as input
output
– Put in 6=110, Output 6 activates (‘1’)
D0 0
D1 0
D2 0
0 Z (LSB)
1 Y
D3 0
1 X (MSB)
D4 0
D5 0 Only that
D6 1 numbered output is
Binary #6
D7 0 activated
Decoders
– Takes a binary number as input
output
D0 0
D1 0
D2 0
1 Z (LSB)
0 Y
D3 0
D4 0 Only that
1 X (MSB)
D5 1 numbered output is
D6 0 activated
Binary #5
D7 0
Decoder Sizes
• A decoder w/ an n-bit input has 2n outputs
– 1 output for every combination of the n-bit input
Y0 1
Y1 0
Y2
0 A0 0
0 Y
D0
0 Y3 0
D1
0 0 A1
Y4
D2
1 0 A2 (MSB) 0
1 X (MSB)
0
D3
0 Y5
Y6
0
n inputs 2n outputs Y7 0
(2) (4)
n inputs 2n outputs
(3) (8)
2-to-4 3-to-8
Decoder Decoder
Building Decoders
Checker O0
for 000
Checker O1
for 001
Checker O2
for 010
Checker O3
for 011
3-bit Checker
number O4
for 100
[A2:A0]
Checker O5
for 101
Checker O6
for 110
Checker O7
for 111

Building Decoders
X Y D0 D1 D2 D3
D0
0 0 1 0 0 0 Y
D1
0 1 0 1 0 0
D2
X
1 0 0 0 1 0 D3
1 1 0 0 0 1
y D0
D0 = X’•Y’ y
x

Building Decoders
X Y D0 D1 D2 D3
D0
0 0 1 0 0 0 Y
D1
0 1 0 1 0 0
D2
X
1 0 0 0 1 0 D3
1 1 0 0 0 1
y D0
D0 = X’•Y’ y
x
y D1
D1 = X’•Y x
x

Building Decoders
X Y D0 D1 D2 D3
D0
0 0 1 0 0 0 Y
D1
0 1 0 1 0 0
D2
X
1 0 0 0 1 0 D3
1 1 0 0 0 1
y D0
D0 = X’•Y’ y
x
y D1
D1 = X’•Y x
x
y
D2
D2 = X•Y’ x
y
D3
D3 = X•Y x

Building Decoders
X Y D0 D1 D2 D3
D0
0 0 1 0 0 0 Y
D1
0 1 0 1 0 0
D2
X
1 0 0 0 1 0 D3
1 1 0 0 0 1
y D0
D0 = X’•Y’ = m0 y
x
y D1
D1 = X’•Y = m1 Notice output n is x
x
just minterm, mn y
D2
D2 = X•Y’ = m2 x
y
D3
D3 = X•Y = m3 x

Building Decoders
• All decoders are built by simply
implementing minterms for each
combination of the inputs
• This means a decoder is really just AND
gates with inverters!

Implementing Logic Functions
• F = ΣMNO(2,3,4,6)
= m2 + m 3 + m 4 + m 6 D0
• Since decoders are just D1
D2
minterm generators, O Z (LSB) F
D3
just OR together the N Y
D4
appropriate minterms M X (MSB)
D5
D6
D7

• F = ΣMNO(2,3,4,6)
= m2 + m 3 + m 4 + m 6 D0
• Connect the input D1
D2
variables M,N,O to the O Z (LSB) F
D3
inputs of the decoder to N Y
D4
produce the minterms M X (MSB)
D5
D6
D7

• F = ΣMNO(2,3,4,6)
= m2 + m 3 + m 4 + m 6 D0
D2
variables M,N,O to the O Z (LSB) F
D3
inputs of the decoder to N Y
D4
produce the minterms M X (MSB)
D5
• OR together where D6
F=1 D7

• F = ΣMNO(2,3,4,6)
0
= m2 + m 3 + m 4 + m 6 D0
0
0
D2
variables M,N,O to the 0 Z (LSB)
0
F
1
D3
inputs of the decoder to 1 Y
D4 0
produce the minterms 1 X (MSB)
D5
0
1
F=1 D7
0
• Test it MNO = 110

• F = ΣMNO(2,3,4,6)
0
= m2 + m 3 + m 4 + m 6 D0
1
0
D2
variables M,N,O to the 1 Z (LSB)
0
F
0
D3
inputs of the decoder to 0 Y
D4 0
produce the minterms 0 X (MSB)
D5
0
0
F=1 D7
0

Designing Circuits w/ K-Maps
• Given a description…
– Block Diagram
– Truth Table
– K-Map for each output bit (each output bit is a separate function
of the inputs)
• 3-bit unsigned decrementer (Z = X-1)
– If X[2:0] = 000 then Z[2:0] = 111, etc.
X[2:0] Z[2:0]
3-bit Unsigned
3 Decrementer 3

3-bit Number Decrementer
X2 X1 X0 Z2 Z1 Z0
0 0 0 1 1 1
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 0 1 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0
X2X1 X2X1 X2X1

X0 00 01 11 10 X0 00 01 11 10 X0 00 01 11 10
0 2 6 4 0 2 6 4 0 2 6 4
0 1 0 1 0 0 1 0 0 1 0 1 1 1 1
1 3 7 5 1 3 7 5 1 3 7 5
1 0 0 1 1 1 0 1 1 0 1 0 0 0 0
Z2 = X2X0 + X2X1 + X2’X1’X0’ Z1 = X1’X0’ + X1X0 Z0 = X0’

3-bit Decrementer
X2 X1 X0 Z2 Z1 Z0
0 0 0 1 1 1 Y0
Y1
0 0 1 0 0 0
0 1 0 0 0 1 Y2
A0
0 1 1 0 1 0 Y3
A1
1 0 0 0 1 1 Y4
A2
1 0 1 1 0 0 Y5
1 1 0 1 0 1 Y6
1 1 1 1 1 0 Y7
• When we have many outputs that are a function of the

same inputs, it may be smaller to use a decoder rather
than separate logic for each output
• F = ΣMNO(1,2,3,4,6)
• Requires 5-input OR D0
gate D1
D2
O Z (LSB) F
D3
N Y
D4
M X (MSB)
D5
D6
D7

D0
• F = ΣMNO(1,2,3,4,6) D1
D2
• Requires 5-input OR
O Z (LSB) F
D3
N Y
gate…too big! M X (MSB)
D4
D5
Implement F another D6
way… D7
F’ before
• F’ = ΣMNO(0,5,7) D0
inversion…F
after
• Requires a 3-input OR D1
D2
gate O Z (LSB)
D3
F
• To get F, just add an

N Y
D4
M X (MSB)
inversion at the end D5
• OR becomes NOR D6
D7

MULTIPLEXERS

Single Variable Theorem (T1)
X+0 = X (T1) X•1 = X (T1’)
X Y Z X Y Z
0 0 0 Hold Y 0 0 0
0 1 1 constant 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
OR AND
Whenever a variable is OR’ed with 0, Whenever a variable is AND’ed with

the output will be the same as the 1, the output will be the same as the
variable… variable…
“0 OR Anything equals that “1 AND Anything equals that
anything” anything”

Single Variable Theorem (T2)
X+1 = 1 (T2) X•0 = 0 (T2’)
X Y Z X Y Z
0 0 0 Hold Y 0 0 0
0 1 1 constant 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
OR AND
Whenever a variable is OR’ed with 1, Whenever a variable is AND’ed with

the output will be 1… 0, the output will be 0…
“1 OR anything equals 1” “0 AND anything equals 0”

Application: Channel Selector
• Given 4 input, digital music/sound channels and
4 output channels
• Given individual “select” inputs that select 1
input channel to be routed to 1 output channel
4 Input channels
011010101001101 ICH0 OCH0
101010110101010 ICH1 OCH1
Channel 4 Output
101001010101111 ICH2 Selector OCH2 channels
001010101001011 ICH3 OCH3
Input Output
OSEL0
OSEL1
OSEL2
OSEL3
ISEL0
ISEL1
ISEL2
ISEL3
Channel Channel
Select Select
Application: Steering Logic
• 4-input music channels (ICHx)
– Select one input channel (use ISELx inputs)
– Route to one output channel (use OSELx inputs)
011010101001101 ICH 0
OCH 0
101010110101010 ICH 1
OCH 1
ICH 2
101001010101111
OCH 2
ICH 3
001010101001011
OCH 3
O SEL1
O SEL2
O SEL3
O SEL0
ISEL3
ISEL1
ISEL2
ISEL0

• 1st Level of AND gates act as barriers only passing 1 channel
• OR gates combines 3 streams of 0’s with the 1 channel that got
passed (i.e. ICH1)
• 2nd Level of AND gates passes the channel to only the selected
output
Connection
ICH 0 Point ICH1
0 0 OCH 0
0 0
ICH 1 ICH1 ICH1
0 OCH 1
ICH1
1 0
ICH 2
0 ICH1 0 OCH 2
0 0
ICH 3
0 ICH1 ICH1
OCH 3
0 1
AND: 0 10 0 OR: 0 00 1 AND:

O SEL1
O SEL2
O SEL3
O SEL0
ISEL3
ISEL1
ISEL2
ISEL0
1 AND ICHx = ICHx 0 + ICH1 + 0 + 0 1 AND ICH1 = ICH1

0 AND ICHx = 0 = ICH1 0 AND ICH1 = 0
Your Turn
• Build a circuit that takes 3 inputs: S, IN0,
IN1 and outputs a single bit Y.
• It’s functions should be:
– If S = 0, Y = IN0 (IN0 passes to Y)
– If S = 1, Y = IN1 (IN1 passes to Y)
IN0
if(s==0)
Y Y = IN0
S else
Y = IN1
IN1
Multiplexers
• Along with adders, multiplexers are most used building
block
• 2n data inputs, n select bits, 1 output
• A multiplexer (“mux” for short) selects one data input and
passes it to the output
4-to-1 Mux
D0
D1
2n data inputs Y 1 output
D2
D3 S0
S1
n select bits
Multiplexers
0 D0
1 D1
2 Y 1
Thus, D2 is selected 1 D2 (D2)
and passed to the
output 0 D3 S0
S1
10
1
Select bits = 102 = 210.

Multiplexers
0 D0
1 D1
Y 0
0 D2 (D2)
0 D3 S0
S1
10
D2 is being selected and passed.

So if it changes the output
changes as well.
Multiplexers
if( S1S0 == 00)

0 D0 Y = D0
else if(S1S0 == 01)
1 D1 Y = D1
2 Y 0 else if(S1S0 == 10)
Thus, D0 is selected 0 D2 Y = D2
(D0)
and passed to the else if(S1S0 == 11)
output 0 D3 S0 Y = D3
S1
00
1
Select bits = 002 = 010.

• 1st Level of AND gates act as barriers only passing 1 channel
• OR gates combines 3 streams of 0’s with the 1 channel that got
passed (i.e. ICH1)
• 2nd Level of AND gates passes the channel to only the selected
output
Connection
ICH 0 Point ICH1
0 0 OCH 0
0 0
ICH 1 ICH1 ICH1
0 OCH 1
ICH1
1 0
ICH 2
0 ICH1 0 OCH 2
0 0
ICH 3
0 ICH1 ICH1
OCH 3
0 1
AND: 0 10 0 OR: 0 00 1 AND:

O SEL1
O SEL2
O SEL3
O SEL0
ISEL3
ISEL1
ISEL2
ISEL0
1 AND ICHx = ICHx 0 + ICH1 + 0 + 0 1 AND ICH1 = ICH1

0 AND ICHx = 0 = ICH1 0 AND ICH1 = 0
Building a Mux
• To build a mux
– Decode the select bits and include the corresponding
data input.
– Finally OR all the first level outputs together.
I0 1 0
S0
0 S1
I1 I1 I1
1 S0 1
S1S0 = 01 0 S1
1
I1
Y
I2 0
1 S0
0 S1
I3 0
1 S0
0 S1
Building a Mux
• To build a mux
– Decode the select bits and include the corresponding
data input.
– Finally OR all the first level outputs together.
I0 1 0
S0
1 S1
I1
I1
1 S0
S1S0 = 11 1 S1 I3
Y
I2 0
1 S0
1 S1
0
I3 I3
1 S0 1

1 S1 1
Simplify This
• Given F(x,y,z) = x’yz + y’z’,
F(0,y,z) =
F(1,y,z) =
• Given G(a,b,c,d) = bd’ + ab’cd + ac’d’

G(1,1,c,d) =

2-to-1 Mux
IN0
Y
if(s==0)
S
Y = IN0
else
Y = IN1
IN1
2
Thus, I0 is selected 1 I0
and passed to the Y 1 Y
output I1 S
0 (I0)
s
1-bit wide 2-to-1
mux
I0 I1
1
Select bits = 0
3-bit Prime Number Function
X Y Z P X Y Z P F
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 x
OFF-set 0 1
0 1 0 1 0 1 0 1
0 1 1 1 0 1 1 1 y 0 1
1 0 0 0 1 0 0 0 ON-set z 0 1
1 0 1 1 1 0 1 1
1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1
1 1 1 1 1 1 1 1
Primes between Truth Table
0-7
if(z==0)
z
z output 0
I0
I1
else
0 1
output 1
1
Example

Function Implementation w/ Muxes
• Implementing a function using muxes
relies is based on Shannon’s expansion
theorem which states:
– F(X1,X2,…,Xn) = X1’•F(0,X2,…,Xn) + X1•F(1,X2,…,Xn)
– X1 can be pulled out of F if we substitute an
appropriate constant and qualify it with X1’ or X1
• Now recall a 2-to-1 mux can be built as:
– F = S’•I0 + S•I1
– Comparing the two equations, Shannon’s theorem
says we can use X1 as our select bit to a 2-to-1 mux
with F(0,X2,…Xn) as input 0 of our mux and
F(1,X2,…,Xn) as input 1
Binary Decision Trees & Muxes
F(x,y,z)
Z F
0 0 x
Y Z F
0 1
X Y Z F 1 0
0 0 0 0 0 0 0 F(0,0,z) F(0,y,z) F(1,y,z)
0 0 1 0 0 1 0 y 0 1
Z F
00 1 0 1 1 0 1
0 1
F(0,0,z) F(0,1,z) F(1,0,z) F(1,1,z)
0 1 1 1 1 1 1
1 1 z 0 1
F(0,y,z) F(0,1,z)
1 0 0 0
1 0 1 1 Y Z F 0 0 1 1 0 1 0 1
11 1 0 0 0 0 0
Z F
0 0 F(x,y,z)
1 1 1 1 0 1 1
1 1 x 0 1
F(x,y,z) 1 0 0 F(1,0,z)
1 1 1 y F(0,y,z) 0 1 0 1
F(1,y,z)
Z F
F(1,y,z) F(0,0,z) F(0,1,z) F(1,0,z) F(1,1,z)
0 0 z 0 1 0 1 0 1 0 1
1 1
F(1,1,z) 0 0 1 1 0 1 0 1
Splitting on X
• We can use smaller X Y Z F
muxes by breaking 0 0 0
the truth table into
y xor z
fewer disjoint sets 0 1 1
0 (y’z + yz’)
– This increases the 1 0 1 Y
amount of logic at Z I0
F
the inputs though 1 1 0 Y
Y
• Break the truth table 0 0 1 Z
I1 S
into groups based on 0 1 1 X

some number (k) of 1 (y’ + z)
Put the k MSB’s
MSB’s 1 0 0
on the selects
• For each group, 1 1 1
describe F as a
function of the
n-k LSB’s
Implement G
X Y Z G
0 0 0
0 1 0
0
1 0 1
I0
G
1 1 1 Y
I1 S
0 0 0
0 1 1 X
1
1 0 1
1 1 0

Shannon’s Theorem
• F(X1,X2,…,Xn) = X1’•F(0,X2,…,Xn) + X1•F(1,X2,…,Xn)
• Now recall a 2-to-1 mux can be built as:
– F = S’•I0 + S•I1
– Comparing the two equations, Shannon’s theorem says we can
use X1 as our select bit to a 2-to-1 mux with F(0,X2,…Xn) as input
0 of our mux and F(1,X2,…,Xn) as input 1
• We can recursively apply Shannon’s theorem to
pull out more variables:
– F(X1,X2,…,Xn) =
X1’X2’•F(0,0,…,Xn) + X1’X2•F(0,1,…,Xn) +
X1X2’•F(1,0,…,Xn) + X1X2•F(1,1,…,Xn) +

Additional Logic
F(x,y,z) can be
broken into several
• Muxes allow us to break a X Y Z F disjoint functions
function into some number 0 0
F0(z)
of smaller, disjoint functions 0 0 z
1 1
• Use MSB’s to choose which z
F1(z) D0
small function we want 0 1
0 1 z’ z’
• By including the use of 1 0
D1
F
Y
inverters we can use a mux F2(z) 1 D2
0 1
with n-1 select bits (given a 1 0 1 z
D3
S0
function of n-var’s) 1 1 S1
• Break the truth table into 0 0

F3(z)
x y
groups of 2 rows 1 1 z
1 1 Put the n-1
• For each group, put F in MSB’s on the
terms of: z, z’, 0, or 1 selects

More Practice
X Y Z G
0 0
0 0
D0
1 0
D1
0 1 G
0 1 D2
Y
1 1
D3
0 0 S0
S1
1 0
1 1
x y
0 1
1 1
1 0

Fundamental Method
• Connect the input X Y Z F
0 D0
variables to the select 0 0 0 0
bits of the mux 0 0 1 1 1 D1
• The output of the mux 0 1 0 1 1 D2
is the output of the 0 1 1 0 0 D3
function 1 0 0 1 1 D4
Y F
• Whatever the output 1 0 1 1 1 D5
should be for each 0 D6

S1
S0
1 1 0 0
input value, attach D7
S2
1
that to the input of the 1 1 1 1
x y z
mux

Splitting on X F
x
0 1
• We can always rearrange y 0 1
our variables if it helps
make the function simpler to z 0 1
implement 0 1 0 1 0 1 0 1
X Y Z F Z X Y F F
0 0 0 0 0 0
z 0 1
0 1 1 0 1 0
0 x 0 1
0 1 0 0 1 0 0
1 1 0 y 0 1
1 1 1
0 0 0 0 0 1 0 0 0 0 1 1 1 1
0 1 1 0 1 1 F
1 1 1 0 1
1 0 0 z 1
0
1 1 1 1 1 1
0 1
• We can use muxes to implement any
arbitrary logic function
• Fundamental method
– if function has n-input variables, need a mux
w/ n-selects
– requires no additional logic; only the mux
• By adding extra logic in front of the mux
inputs we can use a smaller mux…

Binary Decision Diagram
X
• Graph (binary tree)
X Y Z F X Y Z F
representation of Y
0 0 0 0
logic function 0 0
0 Z
• Vertex = 0 0 1 0 1 0
Variable/Decision 0 1 0 1
0
0 1
0 1
• Edge = Variable 0 1 1 0
1
1 0 True
value (T / F) 1 0 0 1
False
0 1 BDD for F
0
1 0 1 1 1 1 X
1 1 0 0
1
0 0
1
Y
1 1 1 1 1 1
Z
0 1
BDD’s, Muxes, Shannon’s Thm.
X 0 1 X
• Every node in the BDD
Y 0 1 0 1 Y
is just a 2-to-1 mux
– View it in the opposite Z 0 1 0 1 0 1 0 1 Z
direction (bottom to top) 0 0 1 0 1 1 0 1
• Really using Shannon’s

0 1
theorem
X Y Z F BDD for F
0 0 True
X 0 False
1 0
0 0 1
False Path True Path 1
X
1 0 X 0 1
If X=0, Y
0 1
choose the 0 (False) path 0 Y 0 1 0 1
If X=1, 1 1
choose the 1 (True) path 1 0 0 Z 0
1
1
1 1 Z 0 1
0 1 1 0
Using a LookUp-Table to implement a function
ROMS AND MEMORIES

Memories
• Memories store (write) and retrieve (read)
data
– Read-Only Memories (ROM’s): Can only
retrieve data (contents are initialized and then
cannot be changed)
– Read-Write Memories (RWM’s): Can retrieve
data and change the contents to store new
data

ROM’s
ROM
• Memories are just tables

A0
of data with rows and A1
0 0 0 1 1
columns A2
1 1 0 1 0
• When data is read, one 2 0 1 0 0
entire row of data is 3 0 1 1 1
read out 4 1 1 0 1
• The row to be read is Address 5 1 0 0 0

Inputs
6 0 1 1 0
selected by putting a
7 1 0 1 1
binary number on the
address inputs
Data
Outputs D3 D2 D1 D0

ROM’s
ROM
• Memories are just tables

0 A0
of data with rows and 0 A1
0 0 0 1 1
columns 1 A2
1 1 0 1 0
• When data is read, one 2 0 1 0 0
entire row of data is 3 0 1 1 1
read out 4 1 1 0 1
• The row to be read is Address: 5 1 0 0 0

1002 = 410
6 0 1 1 0
selected by putting a
7 1 0 1 1
binary number on the
address inputs
Data: D3 D2 D1 D0
Row 4 is
1 1 0 1
output

ROM’s
ROM
• ROM’s are named by

A0
0 … 1
their dimensions: A1
0
1 0
– Rows x Columns
1
…
An-1 2 0 0
• n rows and m columns =>
.
n x m ROM .
• 2n rows => n address bits .
(or k rows => log2k 2n-2 0 0
address bits) 2n-1 1 1
• m cols. => m data outputs Dm-1 D0

ROM’s
• One major application of ROM’s is to
use them as LUT’s (Look-Up Tables) to
implement logic functions
• Given a logic function use a ROM to
hold all the possible answers and feed
the inputs of the function to the address
inputs to look-up the answer

Implementing Functions w/ ROM’s
8x1 ROM 8x1 ROM
Z A0 0 A0
X Y Z F 0 1 0 1
Y A1 1 A1
0 0 0 1 1 0 1 0
X A2 1 A2
0 0 1 0 2 1 2 1
X,Y,Z inputs
0 1 0 1 3 1 “look up” 3 1
the correct
0 1 1 1
4 0 answer 4 0
1 0 0 0
5 0 5 0
1 0 1 0
6 0 6 0
1 1 0 0
1 1 1 1 7 1 7 1
Arbitrary D0 D0
Logic
Function F 0

8x2 ROM 8x2 ROM
Ci A0 1 A0
X Y Ci Co S 0 0 0 0 0 0
Y A1 0 A1
0 0 0 0 0 1 0 1 1 0 1
X A2 1 A2
0 0 1 0 1 2 0 1 2 0 1
0 1 0 0 1 3 1 0 3 1 0
0 1 1 1 0
4 0 1 4 0 1
1 0 0 0 1
5 1 0 5 1 0
1 0 1 1 0
6 1 0 6 1 0
1 1 0 1 0
1 1 1 1 1 7 1 1 7 1 1
Full Adder D1 D0 D1 D0
1+0+1 = 10
Co S 1 0

4x4 Multiplier Example
ROM
Determine the dimensions
of the ROM that would be
necessary to implement a
4x4-bit unsigned multiplier
with inputs X[3:0] and
Y[3:0] and outputs P[??:0]
(Question: How many bits
are needed for P).
...
Example:
X3X2X1X0=0010
Y3Y2Y1Y0=0001
P=X*Y=2*1=2
= 0010
• To implement a function w/ n-variables
and m outputs
• Use a ROM w/ 2n rows and m columns
• Just place the output truth table values in
the ROM

EE101 Lecture 9

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Introduction to Digital Logic

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

© Mark Redekopp, All rights reserved

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• Since decoders are just D1

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• Connect the input D1

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• Connect the input D1

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• Test it MNO = 110

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• Test it MNO = 110

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X2X1 X2X1 X2X1

Z2 = X2X0 + X2X1 + X2’X1’X0’ Z1 = X1’X0’ + X1X0 Z0 = X0’

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• When we have many outputs that are a function of the

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• To get F, just add an

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Whenever a variable is OR’ed with 0, Whenever a variable is AND’ed with

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Whenever a variable is OR’ed with 1, Whenever a variable is AND’ed with

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AND: 0 10 0 OR: 0 00 1 AND:

1 AND ICHx = ICHx 0 + ICH1 + 0 + 0 1 AND ICH1 = ICH1

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D2 is being selected and passed.

if( S1S0 == 00)

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AND: 0 10 0 OR: 0 00 1 AND:

1 AND ICHx = ICHx 0 + ICH1 + 0 + 0 1 AND ICH1 = ICH1

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• Given G(a,b,c,d) = bd’ + ab’cd + ac’d’

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into groups based on 0 1 1 X

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• Break the truth table into 0 0

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bits of the mux 0 0 1 1 1 D1

• The output of the mux 0 1 0 1 1 D2

is the output of the 0 1 1 0 0 D3

• Whatever the output 1 0 1 1 1 D5

should be for each 0 D6

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• Really using Shannon’s

ROMS AND MEMORIES

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• Memories are just tables

• When data is read, one 2 0 1 0 0