Gv-R55xtoc-4gd 1.0 NP PDF

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NAVI14 GDDR6 4PCS,10L 3xDPs +1xHDMI
n
105-D332xx-00B RevB Desktop board(110W TGP)
Co p y
TABLE OF CONTENTS
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SHEET NO. SHEET NAME SHEET NO. SHEET NAME
1 TOC 26 DEBUG CIRCUITS
t
2 BLOCK DIAGRAM 27 REVISION HISTORY
C
3 NAVI14 - PCIe Interface
y
4 NAVI14 - GPIO, EXTRA
5 NAVI14 - XTAL
6 NAVI14 - POWER and GND
b t
7 NAVI14 - Decaps
8 NAVI14 - MEM CH AB
o
9 NAVI14 - MEM CH CD
a
10 GDDR6 x16 - MEM CH AB
11 GDDR6 x16 - MEM CH CD
n
12 NAVI14 - TMDPAB - USB,HDMI
g
13 NAVI14 - TMDPCD - DP,DP
i
14 NAVI14 - TMDPE - DP
15 REG VDDGFX/SOC CONTL
G Do
16 REG VDDGFX
17 REG VDDSOC
18 REG PCC
19 REG VDDCI/MVDD CNTL
20 REG VDDCI/MVDD
21 REG - 0V75
22 LDO 1V8/VPP/5V/5V_VESA
23 MECHANICAL AND THERMAL
24 POWER MANAGEMENT
25 SVI2
Title
TOC
Size Document Number Rev
Custom GV-R55XTOC-4GD 1.0
Date: Tuesday, December 10, 2019 Sheet 1 of 28
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External Connector
+12V_EXT
o y
JTAG/I2C
C
Debug
Debug Header
TMDPA
p
POWER REGULATORS DBGDATA[7:0]
TMDPB HDMI
e o
From +12 V EXT AND +12V_BUS
Regulator HOT
t
GPIO5
+VDDCR_GFX, VDDCR_SOC
PCC GPIO4 TMDPC
y C
Straps GPIOs
TMDPD
DP
b t
BIOS ROM
From +12V_BUS TMDPE

Thermal
a o
Speed control DDCVGA
+MVDD, +VDDCI_MEM, FAN
& temperature INTERRUPT PROCHOT_L
n
FAN sense Temp. Sensing D+/D-
g
From +12V_BUS
Built-in PWM FAN_OUT
i
+5V +5V_VESA FAN_IN
G Do
SVI2/I2C/Pow er Management
From +3.3V Direct:

POWER DELIVERY
VDDRN_33, +VPP
1.8V, 0.75V
100MHz
REFCLK Clock
Temperature Critical
CTF
PCI-Express
Power Sequencing
and Control Circuit NAVI14 D332 110W TGP
+3.3V_BUS
+12V_BUS
PCI-Express Bus
Title
BLOCK
l
(3) NAVI14 PCIe Edge Connector
it a
+3V3_BUS SYMBOL LEGEND
+3V3_BUS DNI DO NOT
1
26 LMSMCLK INSTALL
OUT R5
26 LMSMDATA C5 1 20.1uF 6.3V
BI 10K/X
Add fuse diho 20190902 DNI b or # ACTIVE
U3
LOW
2
C6 1 DNI 20.1uF/X 10V 3 5
+12V_BUS RST_EN A VCC
F5 0501010.WR/S INPUT_RAILS_UP 22,24 R6 1 2 0R 1 4 PERST#_BUF
15,19,23,24,28 BUO BRING UP
n
IN B Y
UNNAMED_28_74AUP1G57_I276_C OUT
R7 1 2 0R 6 GND 2 ONLY
C
+3V3_BUS
+3V3_BUS 74AUP1G57GM DIGITAL
MPCIE1 R8 1 DNI 2 10K/X GROUND
U1A
e
2
1
modify footprint 0805 colay 0603 by diho 2019..8.27 Q1B symbol1 ANALOG
+12V_PCIE A2 +12V PERST# A11 PERST# R9 R10
PERSTB AN12 GROUND
45.3K 45.3K
1
RESERVE FOR PCIE SLEW RATE A3 +12V 6 1BSS138PS/X 1% 1%
C7 C8 B1
C50 C51 +12V
2
10uF/X 10uF/X PCIESMCLK GPUSMCLK +3V3_BUS
10uF 10uF B2 +12V SMCLK B5 R3 1 DNI 2 0R/X R1 1 2 0R AN10 SMBCLK
16V 16V
5
16V 16V
B3
d
DNI DNI +12V
2
2
+3V3_BUS
Q1A
1
B6 PCIESMDAT 3 4BSS138PS/X R2 1 2 0R GPUSMDAT AP10 SMBDAT
SMDAT
A9 R13
i
+3.3V 10K/X
1
1
A10 +3.3V R4 1 DNI 2 0R/X DNI
C9 C13 C10 C11 C12 PCIE_REFCLKP
B8 +3.3V REFCLK+ A13 3 AN14 PCIE_REFCLKP
2
10u/6/X5R/6.3V/M PCIE_REFCLKN CLKREQ# CLKREQ#_PCIE
10uF/X 1uF 0.1uF 0.01uF REFCLK- A14 3 AM14 PCIE_REFCLKN CLKREQB AP13 0R/X 2 1 R14 3
6.3V 6.3V 6.3V 10V 25V
f
DNI
2
2
B10 3.3Vaux TP3
PCIE_RX0P
PETp0 B14 AR15 PCIE_RX0P
+3V3_AUX PCIE_RX0N
PETn0 B15 AP15 PCIE_RX0N
A4 GND TP5
PCIE_RX1P
A12 GND PETp1 B19 AN16 PCIE_RX1P
n
PCIE_RX1N
A15 GND PETn1 B20 AM16 PCIE_RX1N
A18 GND
PCIE_RX2P
A20 GND PETp2 B23 AR17 PCIE_RX2P
PCIE_RX2N WAKEB
A23 GND PETn2 B24 AP17 PCIE_RX2N WAKEB AR13 3
A24 GND
PCIE_RX3P
A27 B27 AN18
o
GND PETp3 PCIE_RX3P
PCIE_RX3N
A28 GND PETn3 B28 AM18 PCIE_RX3N
A31 GND
PCIE_RX4P
A34 GND PETp4 B33 AR19 PCIE_RX4P
y
PCIE_RX4N
A37 GND PETn4 B34 AP19 PCIE_RX4N
These termination should be as short as possible, never exceed 500mil

A38 GND
PCIE_RX5P
A41 GND PETp5 B37 AN20 PCIE_RX5P
UNNAMED_28_CAP_I87_A CLKREQ#_PCIE PCIE_RX5N
R15 1 2 42.2/4/1 1% C17 1 21pF 3 B12 A42 GND PETn5 B38 AM20 PCIE_RX5N
C
50V A45 GND
UNNAMED_28_CAP_I88_A PCIE_REFCLKP PCIE_RX6P
R16 1 2 42.2/4/1 1% C18 1 21pF 3 A13 A46 GND PETp6 B41 AR21 PCIE_RX6P
p
PCIE_RX6N
50V A49 GND PETn6 B42 AP21 PCIE_RX6N
UNNAMED_28_CAP_I84_A PCIE_REFCLKN
R17 1 2 42.2/4/1 1% C19 1 21pF 3 A14 A51 GND TP16
PCIE_RX7P
50V A54 GND PETp7 B45 AN22 PCIE_RX7P
UNNAMED_28_CAP_I85_A DGPU_PWR_EN_PCIE PCIE_RX7N PX_EN_T
R18 1 2 42.2/4/1 1% C20 1 21pF 3 A19 A55 GND PETn7 B46 AM22 PCIE_RX7N PX_EN AR26 R19 1 2
23,24,26 0R PX_EN
OUT
1
50V A58 GND TP18
1
UNNAMED_28_CAP_I83_A
C53
o
R20 1 2 42.2/4/1 1% C21 1 21pF PWRBRK# B30 A59 B50
3 GND PETp8
e
A62 B51 R21 0.1uF
50V GND PETn8 1K/X
UNNAMED_28_CAP_I82_A PRSNT2_B31 6.3V
R23 1 2 42.2/4/1 1% C22 1 21pF 3 B31 A63 GND DNI
2
50V A66 GND PETp9 B54
2
DGPU_PWR_OK_PCIE
t
R24 1 2 42.2/4/1 1% C23 1 21pF 3 A32 A67 GND PETn9 B55
50V A70 GND
UNNAMED_28_CAP_I56_A TH_ALERT#
R25 1 2 42.2/4/1 1% C24 1 21pF 3 A33 A71 GND PETp10 B58
50V A74 GND PETn10 B59
C
UNNAMED_28_CAP_I57_A PRSNT2_B81
R26 1 2 42.2/4/1 1% C25 1 21pF 3 B81 A75 GND
A78 B62
y
50V GND PETp11
UNNAMED_28_CAP_I55_A RSVD_A50
R27 1 2 42.2/4/1 1% C26 1 21pF 3 A50 A79 GND PETn11 B63
50V A82 GND
R28 1 2 42.2/4/1 1% C27 1 21pF PRESENCE B48 B4 B66
3 GND PETp12
50V B7 GND PETn12 B67
UNNAMED_28_CAP_I53_A RSVD_B82
t
R29 1 2 42.2/4/1 1% C28 1 21pF 3 B82 B13 GND
B16 B70
b
50V GND PETp13
UNNAMED_28_CAP_I52_A PRSNT2_B17
R30 1 2 42.2/4/1 1% C29 1 21pF 3 B17 B18 GND PETn13 B71
50V B21 GND
B22 GND PETp14 B74
B25 GND PETn14 B75
o
B26 GND
a
B29 GND PETp15 B78
B32 GND PETn15 B79
B35 GND
B36 GND
PERP0 PCIE_TX0P
B39 GND PERp0 A16 C30 1 20.22uF 6.3V AJ14 PCIE_TX0P
n
PERN0 PCIE_TX0N
g
B40 GND PERn0 A17 C31 1 20.22uF 6.3V AH14 PCIE_TX0N
B43 GND
PERP1 PCIE_TX1P
B44 GND PERp1 A21 C32 1 20.22uF 6.3V AL15 PCIE_TX1P
PCIE_TX1N
i
B47 A22 PERN1 C33 1 20.22uF 6.3V AK15 PCIE_TX1N
GND PERn1
B49 GND
PERP2 PCIE_TX2P
B52 GND PERp2 A25 C34 1 20.22uF 6.3V AJ16 PCIE_TX2P
PERN2 PCIE_TX2N
B56 GND
G Do
PERP3 PCIE_TX3P
PERN3 PCIE_TX3N
B60 GND Mechanical Key PERn3 A30 C37 1 20.22uF 6.3V AK17 PCIE_TX3N
B61 GND
+12V_BUS_B PERP4 PCIE_TX4P
+3V3_BUS B64 GND PERp4 A35 C38 1 20.22uF 6.3V AJ18 PCIE_TX4P
PERN4 PCIE_TX4N
B68 GND
1
PERP5 PCIE_TX5P
R34 MR34 PERN5 PCIE_TX5N
B72 GND PERn5 A40 C41 1 20.22uF 6.3V AK19 PCIE_TX5N
0R/X 0R/X
DNI B73 GND 2mA max current
PERP6 PCIE_TX6P
share B76 GND PERp6 A43 C42 1 20.22uF 6.3V AJ20 PCIE_TX6P
2
pads PCIE_TX6N
UNNAMED_28_MOSN_I26_G
B77 A44 PERN6 C43 1 20.22uF 6.3V AH20 PCIE_TX6N

GND PERn6
B80 GND
+3V3_AUX PERP7 PCIE_TX7P
+3V3_BUS PERp7 A47 C44 1 20.22uF 6.3V AL21 PCIE_TX7P
PERN7 PCIE_TX7N PCIE_ZVSS
PERn7 A48 C45 1 20.22uF 6.3V AK21 PCIE_TX7N PCIE_ZVSS AR23 R38 1 2 200R 1%
B9 JTAG1
1
A5 JTAG2 PERp8 A52

R36 R37 A6 A53
2.2K/X Q4 10K/X JTAG3 PERn8 Should minimize the wire
JTAGIO_LOOP Navi14 Rev0.90
2 3 DNI A7 JTAG4 resistance and parasitic
BSH111/X A8 JTAG5 PERp9 A56 capacitance from external board
2
PERn9 A57 device to internal bump.

WAKEB R40
3 1 2
3 PRESENCE A1 A60
0R/XDNI PRSNT1# PERp10 - total trace resistance < 1 ohm
PRSNT2_B17
3 B17 PRSNT2#_B17 PERn10 A61 - total parasitic capacitance < 10pF
PRSNT2_B31
3 B31 PRSNT2#_B31
B48 PRSNT2#_B48 PERp11 A64
PRSNT2_B81
3 B81 PRSNT2#_B81 PERn11 A65
PERp12 A68
WAKEB_CON
B11 WAKE# PERn12 A69
CLKREQ#_PCIE
3 B12 CLKREQ#
3 PWRBRK# B30 PWRBRK# PERp13 A72
PERn13 A73
DGPU_PWR_EN_PCIE A19 A76

3 RSVD_A19 PERp14
DGPU_PWR_OK_PCIE A32 A77
3 RSVD_A32 PERn14
TH_ALERT# A33
3 RSVD_A33
RSVD_A50
3 A50 RSVD_A50 PERp15 A80
RSVD_B82
3 B82 RSVD_B82 PERn15 A81
x16 GEN4 PCIe
Title
PCIE
l
(4) NAVI14 GPIOs & ROM Note: Internal PU/PD at GPIO pad is ~40k
it a
strength in 14nm design spec
+3V3_BUS +1V8
Internal Default
User Value Definition
R48 1GPIO_5_REG_HOT#
2 150R GFX_SOC_VRHOT#
GPIO_5_REG_HOT# IN
4 R49 1 2 190R MVDD_VDDCI_OCP#
IN
R51 1 DNI 2 10K/X
PINSTRAP_6
4
STRAP_BIF_GEN4_DIS_A
R52 1 DNI 2 10K/X 0 0: PCIe GEN 4 supported
1: PCIe GEN 4 not supported
R53 1 DNI 2 10K/X

PINSTRAP_7
4
PINSTRAP_BIF_CLK_PM_EN
n
U1B R54 1 DNI 2 10K/X 0 0: CLKREQ# power management capability is disabled
PINSTRAP_0 AJ5 PINSTRAP_0 symbol2 GPIO_0 N5 AC/DC 1: CLKREQ# power management capability is enabled
OUT
PINSTRAP_1 AJ4 PINSTRAP_1 GPIO_1 N6
BIF
FL/GL
OUT
PINSTRAP_2 AG6 PINSTRAP_2 GPIO_2 N8 FL/GL
OUT
PINSTRAP_3 AG5 R6 R56 1 DNI 2 10K/X
GPIO_13 PINSTRAP_BIF_LC_TX_SWING
e
PINSTRAP_3 GPIO_3 4
OUT
PINSTRAP_4 AF7 PINSTRAP_4 GPIO_4 R5 GPIO4_GFX_PCC#
15,18,26 VDDCR_GFX PCC (low active) R57 1 DNI 2 10K/X 0 0: Full swing mode
OUT IN
PINSTRAP_5 AF5 PINSTRAP_5 GPIO_5 T8 GPIO_5_REG_HOT# VR HOT 1: Reduced swing mode(half swing)
OUT IN
PINSTRAP_6 AF4 PINSTRAP_6 GPIO_6 T7 GPIO_6 USB C Exteranl power detect
OUT GPIO_7_ROMSCK OUT
PINSTRAP_7 AF8 PINSTRAP_7 GPIO_7_ROMSCK P5 4 ROM Control; ROMSCK
OUT
GPIO_8_ROMSI P7
GPIO_8_ROMSI
4 ROM Control; ROMSI R58 1 DNI 2 10K/X
GPIO_15
4
PINSTRAP_BIF_VGA_DIS
N4
GPIO_9_ROMSO
R59 1 DNI 2 10K/X 0
d
GPIO_9_ROMSO 4 ROM Control; ROMSO 0: VGA controller capacity enabled
GPIO_10_ROMCS#
GPIO_10_ROMCSB P4 4 ROM COntrol; ROMSCB / Pinstrap 1: The device won't be recognised as the system's VGA controller
GPIO_11
7-BIT I2C 8-BIT I2C I2C BUS GPIO_11 T4 4 Pinstrap
ADDRESS ADDRESS FUNCTION DEVICE GPIO_12
U8
i
GPIO_12 4 Pinstrap
0x30 0x60 VDDCR_GFX/SOC SCL/SDA U501/IR35217 GPIO_13 T5
GPIO_13
4 Pinstrap R60 1 DNI 2 10K/X
PINSTRAP_5
4
0 PINSTRAP_AUD_PORT_CONN[2:0]
GPIO_14 R8 Pinstrap, VGA En/Dis R61 1 DNI 2 10K/X
GPIO_15
0x22 0x44 MVDD/VDDCI SCL/SDA U701/NCP81022 GPIO_15 U5 4 Pinstrap Number of audio-capable display outputs
GPIO_16 PINSTRAP_4 0
f
GPIO_16 U6 4 Pinstrap, Board ID R62 1 DNI 2 10K/X 4
0x53 0xA6 PCC ψreserved SCL/SDA U4601/GS8601 GPIO_17 V4 GPIO_17 pinstrap, Board ID, R63 1 DNI 2 10K/X 0: All endpoints connected 4: 3 endpoints connected
OUT
GPIO_18 V8 GPIO_18 Pinstrap 1: 6 endpoints connected 5: 2 endpoints connected
OUT
GPIO_19 PINSTRAP_3 0
DCE
0x48 0x90 G6 Temperture DDCVGACLK/DATA U4000/TMP102A GPIO_19 V7 4 Pinstrap, Smbus address R64 1 DNI 2 10K/X 4 2: 5 endpoints connected 6: 1 endpoint connected
GPIO_20 V5 PD_RESET R65 1 DNI 2 10K/X 3: 4 endpoints connected 7: 0 endpoints connected
0x4C 0x98 EXT SENSOR DDCVGACLK/DATA U4001/LM96163 Deafault(PINSTRAP5,PINSTRAR4,PINSTRAR3) = 000
n
R66 1 2 10K
GPIO_12
4
0 PINSTRAP_AUD[1:0]
R67 1 DNI 2 10K/X
1: Audio for DisplayPort only

1 2
GPIO_11 0
o
R68 10K 4 2: Audio for DisplayPort and HDMI if dongle is detected
AB7 GENERICA R69 1 DNI 2 10K/X 3: Audio for both DisplayPort and HDMI
W8 GENERICB GPIO_SVC0 AD5 SVC0 R86 1 2 0R15,25 SVC_GFX_SOC Deafault(GPIO12,GPIO11) = 11
OUT
GPIO_SVD0 AD7 SVD0 R87 1 2 0R15,25 SVD_GFX_SOC
OUT
y
HPD1 W5 HPD1 GPIO_SVT0 AD4 SVT0 R88 1 2 0R15 SVT_GFX_SOC
14
IN IN
HPD2 13 Y4 GENERICC_HPD2 C60 1 DNI 20.1uF/X 10V R70 1 DNI 2 10K/X
GPIO_18
4
PINSTRAP_FIG[1:0] - No definition on NV
IN
0
Platform
HPD3 13 Y5 GENERICD_HPD3 C61 1 DNI 20.1uF/X 10V C62/C63: Close to GPU R71 1 DNI 2 10K/X
IN
HPD4 12 AB9 GENERICE_HPD4 C62 1 DNI 20.1uF/X 10V C60/C61/C64/C65: Close to VR
+3V3_BUS IN GPIO_17
C
AC8 GENERICF_HPD5 C63 1 DNI 20.1uF/X 10V R72 1 DNI 2 10K/X 4
C64 1 DNI 20.1uF/X 10V R73 1 DNI 2 10K/X 0
p
C65 1 DNI 20.1uF/X 10V
SVC1 GPIO_16
R92 1 2 1.5K GPIO_SVC1 AE6 R89 1 2 0R25 SVC_MVDD_VDDCI R74 1 2 10K 4 PINSTRAP_MVDD_FB_DIVIDER_CONFIG
OUT
R93 1 2 1.5K/4 GPIO_SVD1 AE8 SVD1 R90 1 2 0R25 SVD_MVDD_VDDCI R75 1 DNI 2 10K/X 0
OUT 0: Divider does not exist
R127 1 2 1.5K/4 GPIO_SVT1 AE5 SVT1 R91 1 2 0R25 SVT_MVDD_VDDCI RN700A 1 DNI 4 100R/X 0.1%
IN 1: Divider exists
R128 1 2 1.5K/4
e o
R76 1 DNI 2 10K/X
PINSTRAP_2
4
1 PINSTRAP_BFI_MEM_AP_SIZE[2:0] Or PINSTRAP_ROM_CONFIG[2:0]
1R130 SCL
OUT
REG_SCL 15,18,19,26 0R2 AN25 SCL R77 1 DNI 2 10K/X 100 - 512KBIT (ST) M25P05A
1R131 SDA
BI
REG_SDA 15,18,19,26 0R2 AP25 SDA 101 - 1MBIT (ST) (M25P10A)
0
t
R78 1 DNI 2 10K/X 101 - 2MBIT (ST) M25P20
PINSTRAP_1
DDCVGACLK 26,28 AN26 DDCVGACLK R79 1 DNI 2 10K/X 4 101 - 4MBIT (ST) M25P40
+1V8 OUT
DDCVGADATA 26,28 AP26 DDCVGADATA SWAPLOCKB W6 101 - 8MBIT (ST) M25P80
BI
SWAPLOCKA U9 R80 1 DNI 2 10K/X
PINSTRAP_0
4
1 100 - 512KBIT (CHINGIS) PM25LV512
C
R81 1 DNI 2 10K/X PINSTRAP_0
101 - 1MBIT (CHINGIS) PM25LV010
SMU
W9
y
GENLK_CLK Deafault(PINSTRAP2,PINSTRAR1,PINSTRAR0) = 101
1
GENLK_VSYNC Y9
R96 R97 R98
1K 1K 1K
BL_ENABLE AP11 R82 1 DNI 2 10K/X
GPIO_19
4
PINSTRAP_SMBUS_ADDR
BL_PWM_DIM AN11 R83 1 DNI 2 10K/X 0 0: 0x41h
2
TEST_PG_S5P
t
AK10 TEST_PG_S5P DIGON AR11 1: 0x40h
TEST_PG
AK7
b
TEST_PG
TEST_PG_BACO
AJ9 TEST_PG_BACO
R99 1 2 0R
PS_EN
AH9 PS_EN BAMACO_EN AH22
24,25,26 BAMACO_EN R84 1 DNI 2 10K/X
GPIO_10_ROMCS#
4
PINSTRAP_BIOS_ROM_EN
OUT
Navi14 Rev0.90 R85 1 DNI 2 10K/X 1 0: Disable the external BIOS ROM device
1
1: Enable the external BIOS ROM device
o
R100
1K/X
a
DNI
2
GPIO_6
PCB_Delay+ ROM_Delay<8ns R124 1 DNI 2 1K/X GPIO_6
4
R125 1 DNI 2 10K/X
+3V3_BUS +3V3_BUS
n
U5 BIOS1
g
3 WP VDD 8
GPIO_9_ROMSO 33/4/1 R4692 GPIO_9_ROMSO_R
4 1 2 2 SO HOLD
7
BIOS
1
GPIO_8_ROMSI 33/4/1 R4693 GPIO_8_ROMSI_R
i
4 1 2 5 SI
GPIO_7_ROMSCK 33/4/1 R4694 GPIO_7_ROMSCK_R
4 1 2 6 SCK C48
GPIO_10_ROMCS# 33/4/1 R4695 GPIO_10_ROMCS#_R 0.1uF
4 1 2 1 CE GND 4
10V
ADD by diho 20191008
2
GD25Q80C
G Do
+3.3V_BUS +3V3_BUS
改改改改by diho 2019..8.27
R10869 0/6
GPIO_10_ROMCS#
+3.3V_BUS
預預dual bios diho 20190904
+3.3V_BUS +3.3V_BUS
R5189 U4505
3 WP VDD 8
1
2 SO HOLD
7
1
R10867 R10865 R10866 5

10K/X 10K/X 10K/X 33/4/1/X SI
5% 5% 5% 6 SCK C4605
DNI R5190 1 CE GND 4 0.1uF/X
2
10V
2
GD25Q80C/X
GPIO_10_ROMCS#1
33/4/1/X
1
3
1
3
SW1
M4
M3
M2
M1
10NH1-040007-D1R
Title
GPIO
l
(5) NAVI14 XTAL
n it a
fi d e
o n y
100MHz oscilator option
C p
+1V8
Y1
B1 OSC_VDD18
1 2 4 2
1
120R VDD GND
o
DNI
e
C55 C4 C54 3 1 R109 1 DNI 2 1K/4/1
C3
10uF/X 10uF 0.1uF 2.2uF CLK NC
6.3V 6.3V 6.3V 6.3V
100.00000 MHZ
2
t
U1E
symbol5 MY1
C
XTALIN 100M_OSC
XTALIN AP7 R111 1 2 20R 3 4
OUT VDD
y
UNNAMED_5_OSC_I73_OE
2 1
GND OE
NA/X
XTALOUT AR7 XTALOUT
TP22 OVERLAP WITH Y1
+1V8
b t
R112 1 2 2.2K 1% XTRIG6 AC9 XTRIG6
R113 1 2 2.2K 1% XTRIG7 AD8 XTRIG7
XTRIG* are for debug purpose
a o
+3V3_BUS ANALOGIO
ANALOGIO AB8 TP30
OSC_GAIN2
R116 1 2 10K AR9 OSC_GAIN2
OSC_GAIN1 PLLCHARZ1_H UNNAMED_5_CAP_I11_B
R117 1 2 10K AP9 OSC_GAIN1 PLLCHARZ1_H AP12 C57 1 20.1uF 10V R122 1 2 51.1R 1%
OSC_GAIN0 PLLCHARZ1_L UNNAMED_5_CAP_I10_B
R119 1 2 10K AN9 OSC_GAIN0 PLLCHARZ1_L AR12 C58 1 20.1uF 10V R123 1 2 51.1R 1%
n
Avoid noisy area
g
OSC_GAIN[2:0] = 3'd6 Navi14 Rev0.90 Total parasitic cap < 1.2pf when C57/C58 DNI
on Production Board
i
G Do
Title
XTAL
l
(6) NAVI14 POWER AND GND
+VDDCR_GFX +VDDCR_SOC
it a
U1R U1S U1O
symbol18 symbol19 symbol15

A2 VSS#1 VSS#161 N14 AD10 VSS#321 N11 VDDCR_GFX#1 VDDCR_SOC#1 AF10
A18 VSS#8 VSS#168 N30 AD23 VSS#328 P12 VDDCR_GFX#8 VDDCR_SOC#8 AF24
A20 N32 AD27 P14 AG11 +3V3_BUS U1Q
VSS#9 VSS#169 VSS#329 VDDCR_GFX#9 VDDCR_SOC#9
A22 N34 AD29 P16 AG13 +3V3_BUS
VSS#10 VSS#170 VSS#330 VDDCR_GFX#10 VDDCR_SOC#10 symbol17
A24 VSS#11 VSS#171 P3 AD31 VSS#331 P18 VDDCR_GFX#11 VDDCR_SOC#11 AG15 AL12 VDDIO_33 VDDIO_33_S5 AL11
1
A26 VSS#12 VSS#172 P6 AD33 VSS#332 P20 VDDCR_GFX#12 VDDCR_SOC#12 AG17 DNI VDD_33_S5P AL10
1
n
A29 VSS#13 VSS#173 P10 AD35 VSS#333 P22 VDDCR_GFX#13 VDDCR_SOC#13 AG19 C1200 C1201
DNI
A31 VSS#14 VSS#174 P11 AE1 VSS#334 R11 VDDCR_GFX#14 VDDCR_SOC#14 AG21 10uF/X 1uF C1204 C1205 C1347 C1348
6.3V 6.3V
A34 VSS#15 VSS#175 P13 AE4 VSS#335 R13 VDDCR_GFX#15 VDDCR_SOC#15 AG23 1uF/X 1uF 1uF 1uF
2
6.3V 6.3V 6.3V 6.3V
B1 VSS#16 VSS#176 P15 AE7 VSS#336 R15 VDDCR_GFX#16
2
B6 P19 AE12 R19
e
VSS#18 VSS#178 VSS#338 VDDCR_GFX#18
B11 VSS#20 VSS#180 P23 AE16 VSS#340 R23 VDDCR_GFX#20 modify footprint 0805 colay 0603 by diho 2019..8.27
B13 P27 AE18 T12 +1V8
B15 P29 AE20 T14 +1V8
B17 VSS#23 VSS#183 P31 AE22 VSS#343 T16 VDDCR_GFX#23 AC10 VDD_18#1 VDDIO_18_S5 AM7
1
B19 VSS#24 VSS#184 P33 AE24 VSS#344 T18 VDDCR_GFX#24 DNI DNI DNI AD9 VDD_18#2 VDD_18_S5P AL9
1
d
B21 P35 AE28 T20 C1208 C1209 C1210 AE10
VSS#25 VSS#185 VSS#345 VDDCR_GFX#25 VDD_18#3
B23 VSS#26 VSS#186 R1 AE30 VSS#346 T22 VDDCR_GFX#26 10uF/X 10uF/X 10uF/X C1211 C1212 C1350 C1351
4V 4V 4V S0 Domain S5 Domain
B25 VSS#27 VSS#187 R4 AE32 VSS#347 U11 VDDCR_GFX#27 1uF 1uF 1uF 1uF
2
S5P Domain 6.3V 6.3V 6.3V 6.3V
B27 R7 AE34 U13
i
2
1
1
B30 VSS#29 VSS#189 R10 AF3 VSS#349 U15 VDDCR_GFX#29 DNI DNI
B32 R12 AF6 U17 C1215 C1216 C1217 C1218 C1219
B34 VSS#31 VSS#191 R14 AF11 VSS#351 U19 VDDCR_GFX#31 10uF 1uF 1uF 1uF/X 1uF/X
4V 6.3V 6.3V 6.3V 6.3V
B35 R16 AF13 U21
f
2
C5 VSS#33 VSS#193 R18 AF15 VSS#353 U23 VDDCR_GFX#33
C7 R20 AF17 V12 +0V75
C10 R22 AF19 V14 +0V75
C12 VSS#36 VSS#196 R24 AF21 VSS#356 V16 VDDCR_GFX#36 AM23 VDD_075#1 VDDCR_075_S5 AN24
1
C14 VSS#37 VSS#197 R28 AF23 VSS#357 V18 VDDCR_GFX#37 DNI DNI AP23 VDD_075#2 VDDCR_075_S5P AM24
1
C16 VSS#38 VSS#198 R30 AF29 VSS#358 V20 VDDCR_GFX#38
C1222 C1223 C1224 AP24 VDD_075#3
C18 R32 AF31 V22 C1225 C1226 C1353 C1354
n
VSS#39 VSS#199 VSS#359 VDDCR_GFX#39 10uF/X 47uF 22u/8/X6S/6.3V/M
4V 4V 4V
C20 VSS#40 VSS#200 R34 AF33 VSS#360 W11 VDDCR_GFX#40 AR24 VDD_075#4 1uF 1uF 2.2uF 1uF
2
6.3V 6.3V 4V 6.3V
C22 VSS#41 VSS#201 T3 AF35 VSS#361 W13 VDDCR_GFX#41
2
1
1
C24 VSS#42 VSS#202 T6 AG1 VSS#362 W15 VDDCR_GFX#42 DNI DNI DNI
1
C26 VSS#43 VSS#203 T10 AG4 VSS#363 W17 VDDCR_GFX#43
C1229 C1230 C1231 C1232 C1233
DNI
C29 VSS#44 VSS#204 T11 AG7 VSS#364 W19 VDDCR_GFX#44 2.2uF/X 1uF 2.2uF 1uF/X 1uF/X C1234
4V 6.3V 4V 6.3V 6.3V
C31 T13 AG12 W21
o
VSS#45 VSS#205 VSS#365 VDDCR_GFX#45 1uF/X
2
6.3V
D6 VSS#46 VSS#206 T15 AG14 VSS#366 W23 VDDCR_GFX#46
2
D9 VSS#47 VSS#207 T17 AG16 VSS#367 Y12 VDDCR_GFX#47
D13 T21 AG20 Y16
y
D21 VSS#53 VSS#213 T31 AG30 VSS#373 AA11 VDDCR_GFX#53
C
p
D27 VSS#56 VSS#216 U1 AH13 VSS#376 AA17 VDDCR_GFX#56
E2 VSS#59 VSS#219 U10 AH19 VSS#379 AA23 VDDCR_GFX#59 VDDAN_18_EFUSE = 1.8V
E5 VSS#60 VSS#220 U12 AH21 VSS#380 AB12 VDDCR_GFX#60 VDDAN_18_EFUSE AA10
1
E7 VSS#61 VSS#221 U14 AH24 VSS#381 AB14 VDDCR_GFX#61 DNI
1
o
E10 U16 AH27 AB16 C1237
e
E12 VSS#63 VSS#223 U18 AJ3 VSS#383 AB18 VDDCR_GFX#63 1uF/X R1207
6.3V 0R
E14 VSS#64 VSS#224 U20 AJ7 VSS#384 AB20 VDDCR_GFX#64
2
E16 VSS#65 VSS#225 U22 AJ10 VSS#385 AB22 VDDCR_GFX#65
2
E18 VSS#66 VSS#226 U24 AJ13 VSS#386 AC11 VDDCR_GFX#66
t
Navi14 Rev0.90
C
E29 VSS#71 VSS#231 V3 AJ23 VSS#391 AC21 VDDCR_GFX#71
E31 VSS#72 VSS#232 V6 AJ25 VSS#392 AC23 VDDCR_GFX#72
y
E33 VSS#73 VSS#233 V10 AJ29 VSS#393 AD12 VDDCR_GFX#73
E35 VSS#74 VSS#234 V11 AJ31 VSS#394 AD14 VDDCR_GFX#74
F3 VSS#75 VSS#235 V13 AJ33 VSS#395 AD16 VDDCR_GFX#75
F6 VSS#76 VSS#236 V15 AJ35 VSS#396 AD18 VDDCR_GFX#76
F9 VSS#77 VSS#237 V17 AK1 VSS#397 AD20 VDDCR_GFX#77
t
F11 VSS#78 VSS#238 V19 AK4 VSS#398 AD22 VDDCR_GFX#78
F13 V21 AK6 AE11
b
F15 VSS#80 VSS#240 V23 AK9 VSS#400 AE13 VDDCR_GFX#80
F17 VSS#81 VSS#241 V27 AK11 VSS#401 AE15 VDDCR_GFX#81 FB_VDDCR_GFX AH12
15,26 FB_VDDCR_GFX
OUT
F19 VSS#82 VSS#242 V29 AK12 VSS#402 AE17 VDDCR_GFX#82 FB_VDDCR_SOC AJ12
15,26 FB_VDDCR_SOC
OUT
o
F25 V35 AK18 AE23 AH11 FB_VSS_A
a
VSS#85 VSS#245 VSS#405 VDDCR_GFX#85 FB_VSS_A 15,26 OUT
F27 VSS#86 VSS#246 W1 AK20 VSS#406
Navi14 Rev0.90
F30 VSS#87 VSS#247 W4 AK22 VSS#407
F32 VSS#88 VSS#248 W7 AK26 VSS#408
F34 VSS#89 VSS#249 W10 AK30 VSS#409
G1 VSS#90 VSS#250 W12 AK32 VSS#410
n
G4 W14 AK34
g
VSS#91 VSS#251 VSS#411
G7 VSS#92 VSS#252 W16 AL3 VSS#412
G10 VSS#93 VSS#253 W18 AL7 VSS#413
G12 VSS#94 VSS#254 W20 AL14 VSS#414
i
G14 VSS#95 VSS#255 W22 AL16 VSS#415
G16 VSS#96 VSS#256 W24 AL18 VSS#416
G18 VSS#97 VSS#257 W28 AL20 VSS#417
G20 VSS#98 VSS#258 W30 AL22 VSS#418
G22 VSS#99 VSS#259 W32 AL27 VSS#419
G Do
G24 VSS#100 VSS#260 W34 AL31 VSS#420
G26 VSS#101 VSS#261 Y3 AL33 VSS#421
G31 VSS#102 VSS#262 Y6 AL35 VSS#422
G33 VSS#103 VSS#263 Y10 AM2 VSS#423
G35 VSS#104 VSS#264 Y11 AM6 VSS#424
H9 VSS#105 VSS#265 Y13 AM9 VSS#425
H11 VSS#106 VSS#266 Y15 AM10 VSS#426
H13 VSS#107 VSS#267 Y17 AM11 VSS#427
H15 VSS#108 VSS#268 Y19 AM12 VSS#428
H17 VSS#109 VSS#269 Y21 AM13 VSS#429
H19 VSS#110 VSS#270 Y23 AM15 VSS#430
H21 VSS#111 VSS#271 Y27 AM17 VSS#431
H23 VSS#112 VSS#272 Y29 AM19 VSS#432 +VDDCI +MVDD
H25 VSS#113 VSS#273 Y31 AM21 VSS#433
U1P
H27 VSS#114 VSS#274 Y33 AM25 VSS#434 symbol16
J3 VSS#115 VSS#275 Y35 AM29 VSS#435 M9 VDDCI_MEM#1 VDDIO_MEM#1 L7
J5 VSS#116 VSS#276 AA1 AM34 VSS#436 M14 VDDCI_MEM#2 VDDIO_MEM#2 L11
J8 VSS#117 VSS#277 AA4 AN1 VSS#437 M16 VDDCI_MEM#3 VDDIO_MEM#3 L13
J18 VSS#121 VSS#281 AA16 AN15 VSS#441 P24 VDDCI_MEM#7 VDDIO_MEM#7 L21
J20 VSS#122 VSS#282 AA18 AN17 VSS#442 T24 VDDCI_MEM#8 VDDIO_MEM#8 L23
J22 VSS#123 VSS#283 AA20 AN19 VSS#443 V24 VDDCI_MEM#9 VDDIO_MEM#9 L25
J24 VSS#124 VSS#284 AA22 AN21 VSS#444 Y24 VDDCI_MEM#10 VDDIO_MEM#10 N25
J28 VSS#125 VSS#285 AA24 AN23 VSS#445 AB24 VDDCI_MEM#11 VDDIO_MEM#11 R25
J30 VSS#126 VSS#286 AA28 AN30 VSS#446 VDDIO_MEM#12 U25
J32 VSS#127 VSS#287 AA30 AP1 VSS#447 VDDIO_MEM#13 W25
J34 VSS#128 VSS#288 AA32 AP2 VSS#448 VDDIO_MEM#14 AA25
K3 VSS#129 VSS#289 AA34 AP6 VSS#449 VDDIO_MEM#15 AC25
K6 VSS#130 VSS#290 AB3 AP14 VSS#450 VDDIO_MEM#16 AE25
K29 VSS#131 VSS#291 AB6 AP16 VSS#451
K31 VSS#132 VSS#292 AB10 AP18 VSS#452
K33 VSS#133 VSS#293 AB11 AP20 VSS#453
K35 VSS#134 VSS#294 AB13 AP22 VSS#454
L1 VSS#135 VSS#295 AB15 AP31 VSS#455
L4 VSS#136 VSS#296 AB17 AP34 VSS#456 FB_VDDIO_MEM
19 N9 FB_VDDIO_MEM
OUT
L28 VSS#137 VSS#297 AB19 AP35 VSS#457 FB_VDDCI_MEM
19 P9 FB_VDDCI_MEM
OUT
L30 VSS#138 VSS#298 AB21 AR2 VSS#458
L32 VSS#139 VSS#299 AB23 AR6 VSS#459 FB_VSS_B
19 N10 FB_VSS_B
OUT
L34 VSS#140 VSS#300 AB27 AR10 VSS#460
Navi14 Rev0.90
M3 VSS#141 VSS#301 AB29 AR14 VSS#461
M5 VSS#142 VSS#302 AB31 AR16 VSS#462
M8 VSS#143 VSS#303 AB33 AR18 VSS#463
M10 VSS#144 VSS#304 AB35 AR20 VSS#464
M11 VSS#145 VSS#305 AC1 AR22 VSS#465
M13 VSS#146 VSS#306 AC4 AR25 VSS#466
M15 VSS#147 VSS#307 AC7 AR34 VSS#467
M17 VSS#148 VSS#308 AC12
M19 VSS#149 VSS#309 AC14 Navi14 Rev0.90
M21 VSS#150 VSS#310 AC16
M23 VSS#151 VSS#311 AC18
M24 VSS#152 VSS#312 AC20
M27 VSS#153 VSS#313 AC22
M29 VSS#154 VSS#314 AC24
M31 VSS#155 VSS#315 AC28
M33 VSS#156 VSS#316 AC30
M35 VSS#157 VSS#317 AC32
N1 VSS#158 VSS#318 AC34
N7 VSS#159 VSS#319 AD3
N12 VSS#160 VSS#320 AD6 U1T
symbol20
Navi14 Rev0.90
A1_DETECT B2
FREE#1 AH10
FREE#2 AJ11
FREE#3 AL24
Navi14 Rev0.90
Title
POWER
Custom
GV-R55XTOC-4GD 1.0
l
(7) NAVI14 Decaps
n it a
e
+VDDCR_GFX +VDDCR_GFX decoupling caps (10uF - 0402)
+VDDCR_SOC decoupling caps
d
+VDDCR_SOC
10uF - 0402 x81 10uF 0402 x5

1
1
+MVDD
i
C1238 C1239 C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1247 C1410 C1411 C1412 C1413 C1414 C1415 C1430 C1431 +VDDCI +VDDCI_MEM decoupling caps
10uF 10uF 10uF 1uF 1uF 10uF 10uF 1uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
10uF 0402 x10
10uF 0402 x11
1
4V 4V 4V 6.3V 6.3V 4V 4V 6.3V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
1
C1280 C1281 C1284 C1285 C1300 C1286
f
1
1
10uF 1uF 1uF 10uF 1uF 1uF C1268 C1269 C1270 C1272 C1273 C1274 C1275 C1276
C1248 C1249 C1250 C1251 C1252 C1253 C1254 C1255 C1256 C1257 4V 6.3V 6.3V 4V 6.3V 6.3V
+VDDCR_SOC 1uF 1uF 10uF 10uF 10uF 10uF 10uF 10uF
2
6.3V 6.3V 4V 4V 4V 4V 4V 4V
1uF 10uF 10uF 10uF 10uF 1uF 1uF 1uF 1uF 1uF
22uF 0603 x3
2
6.3V 4V 4V 4V 4V 6.3V 6.3V 6.3V 6.3V 6.3V
2
1
1
1
C1416 C1417 C1418 C1301 C1302 C1303 C1305 C1291 C1292 C1293
C1258 C1359 C1360 C1361 C1362 C1363 C1364 C1365 C1366 C1367
n
4V 4V 4V 6.3V 6.3V 4V 4V 4V 6.3V 4V
2
4V 6.3V 6.3V 4V 4V 4V 4V 4V 4V 4V
2
1
1uF 0201 x1
1
1
C1277
C1368 C1369 C1370 C1371 C1372 C1373 C1374 C1375 C1376 C1377 1uF
1uF 0201 x8 4V
o
2
1
1
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
2
C1278 C1279 C1282 C1283 C1287 C1288 C1289 C1304
1
1
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
C1378 C1379 C1380 C1381 C1382 C1383 C1384 C1385 C1386 C1387 4V 4V 4V 4V 4V 4V 4V 4V
y
2
2
4V 4V 6.3V 6.3V 6.3V 4V 4V 4V 4V 6.3V
2
2
1
C
C1388 C1389 C1390 C1391 C1392 C1393 C1394 C1395 C1396 C1397
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
p
2
2
1
C1398 C1399 C1400 C1401 C1402 C1403 C1404 C1405 C1406 C1407
6.3V 6.3V 6.3V 6.3V 4V 4V 4V 4V 6.3V 4V
2
e o
1
C1408 C1409 C1420 C1421 C1422 C1423 C1424 C1425 C1426 C1427
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
t
2
2
1
C1428
1uF
C
6.3V
2
b y t
+VDDCR_GFX +VDDCR_GFX decoupling caps
47uF - 0805 x4
1
o
C1327 C1328 C1329 C1330
a
47uF 47uF 47uF 47uF
4V 4V 4V 4V
2
n
22uF - 0603 x2
g
1
C1337 C1338
22uF 22uF
i
4V 4V
2
G Do
Title
DECAPS
Custom
GV-R55XTOC-4GD 1.0
l
(8) NAVI14 MEM INTERFACE CH A/B
n it a
i d e
U1K U1L
DQA0_[0..15] 10 symbol11 10 DQA1_[0..15] DQB0_[0..15] 10 symbol12 10 DQB1_[0..15]

BI DQA0_0 DQA1_0 BI BI DQB0_0 DQB1_0 BI
f
0 10 8 AN35 DQA0_0 DQA1_0 AL32 10 8 0 0 10 8 W33 DQB0_0 DQB1_0 U29 10 8 0
DQA0_1 DQA1_1 DQB0_1 DQB1_1
1 10 8 AM33 DQA0_1 DQA1_1 AK31 10 8 1 1 10 8 V32 DQB0_1 DQB1_1 T30 10 8 1
2 10 8 AL34 DQA0_2 DQA1_2 AJ30 10 8 2 2 10 8 V34 DQB0_2 DQB1_2 T28 10 8 2
3 10 8 AK35 DQA0_3 DQA1_3 AG29 10 8 3 3 10 8 U35 DQB0_3 DQB1_3 R31 10 8 3
4 10 8 AJ34 DQA0_4 DQA1_4 AF28 10 8 4 4 10 8 T34 DQB0_4 DQB1_4 P28 10 8 4
5 10 8 AG35 DQA0_5 DQA1_5 AE31 10 8 5 5 10 8 R35 DQB0_5 DQB1_5 N31 10 8 5
n
6 10 8 AG33 DQA0_6 DQA1_6 AE29 10 8 6 6 10 8 R33 DQB0_6 DQB1_6 N29 10 8 6
7 10 8 AF32 DQA0_7 DQA1_7 AD28 10 8 7 7 10 8 P32 DQB0_7 DQB1_7 M28 10 8 7
8 10 8 AD34 DQA0_8 DQA1_8 AB30 10 8 8 8 10 8 M34 DQB0_8 DQB1_8 K30 10 8 8
9 10 8 AC35 DQA0_9 DQA1_9 AA31 10 8 9 9 10 8 L35 DQB0_9 DQB1_9 J31 10 8 9
DQA0_10 DQA1_10 DQB0_10 DQB1_10
10 10 8 AC33 DQA0_10 DQA1_10 AA29 10 8 10 10 10 8 L33 DQB0_10 DQB1_10 J29 10 8 10
DQA0_11 DQA1_11 DQB0_11 DQB1_11
AB32 Y30 K32 G32
o
11 10 8 DQA0_11 DQA1_11 10 8 11 11 10 8 DQB0_11 DQB1_11 10 8 11
DQA0_12 DQA1_12 DQB0_12 DQB1_12
12 10 8 AA33 DQA0_12 DQA1_12 W29 10 8 12 12 10 8 J33 DQB0_12 DQB1_12 F31 10 8 12
DQA0_13 DQA1_13 DQB0_13 DQB1_13
13 10 8 Y32 DQA0_13 DQA1_13 V30 10 8 13 13 10 8 G34 DQB0_13 DQB1_13 E34 10 8 13
DQA0_14 DQA1_14 DQB0_14 DQB1_14
14 10 8 Y34 DQA0_14 DQA1_14 V28 10 8 14 14 10 8 F35 DQB0_14 DQB1_14 E32 10 8 14
y
DQA0_15 DQA1_15 DQB0_15 DQB1_15
15 10 8 W35 DQA0_15 DQA1_15 U31 10 8 15 15 10 8 C35 DQB0_15 DQB1_15 D33 10 8 15
CAA0_[0..9] 10 10 CAA1_[0..9] CAB0_[0..9] 10 10 CAB1_[0..9]
OUT CAA0_0 CAA1_0 OUT OUT CAB0_0 CAB1_0 OUT
0 10 8 AN31 CAA0_0 CAA1_0 AM26 10 8 0 0 10 8 Y25 CAB0_0 CAB1_0 AB25 10 8 0
CAA0_1 CAA1_1 CAB0_1 CAB1_1
1 10 8 AJ26 CAA0_1 CAA1_1 AD26 10 8 1 1 10 8 R26 CAB0_1 CAB1_1 L27 10 8 1
C
2 10 8 AR33 CAA0_2 CAA1_2 AJ24 10 8 2 2 10 8 W27 CAB0_2 CAB1_2 AC27 10 8 2
3 10 8 AH26 CAA0_3 CAA1_3 AF25 10 8 3 3 10 8 P26 CAB0_3 CAB1_3 N26 10 8 3
p
4 10 8 AP32 CAA0_4 CAA1_4 AL25 10 8 4 4 10 8 W26 CAB0_4 CAB1_4 AC26 10 8 4
5 10 8 AK27 CAA0_5 CAA1_5 AE26 10 8 5 5 10 8 T25 CAB0_5 CAB1_5 M25 10 8 5
6 10 8 AG25 CAA0_6 CAA1_6 AF26 10 8 6 6 10 8 P25 CAB0_6 CAB1_6 N27 10 8 6
7 10 8 AK29 CAA0_7 CAA1_7 AE27 10 8 7 7 10 8 T26 CAB0_7 CAB1_7 M26 10 8 7
8 10 8 AM31 CAA0_8 CAA1_8 AK25 10 8 8 8 10 8 V26 CAB0_8 CAB1_8 AB26 10 8 8
o
9 10 8 AR31 CAA0_9 CAA1_9 AM27 10 8 9 9 10 8 Y26 CAB0_9 CAB1_9 AA26 10 8 9
e
WCKA0_0
10 AE35 WCKA0_0 WCKA1_0 AC31 10 WCKA1_0
BI BI
WCKA0B_0
10 AF34 WCKA0B_0 WCKA1B_0 AD30 10 WCKA1B_0 WCKB0_0
10 N35 WCKB0_0 WCKB1_0 L31 10 WCKB1_0
BI BI BI BI
t
WCKB0B_0
10 P34 WCKB0B_0 WCKB1B_0 M30 10 WCKB1B_0
BI BI
WCKA0_1
10 AE33 WCKA0_1 WCKA1_1 AC29 10 WCKA1_1
BI BI
WCKA0B_1
10 AD32 WCKA0B_1 WCKA1B_1 AB28 10 WCKA1B_1 WCKB0_1
10 N33 WCKB0_1 WCKB1_1 L29 10 WCKB1_1
BI BI BI BI
WCKB0B_1
10 M32 WCKB0B_1 WCKB1B_1 K28 10 WCKB1B_1
BI BI
C
EDCA0_0
10 AJ32 EDCA0_0 EDCA1_0 AG31 10 EDCA1_0
BI BI
EDCA0_1 AB34 W31 EDCA1_1 EDCB0_0 T32 R29 10 EDCB1_0
y
10 EDCA0_1 EDCA1_1 10 10 EDCB0_0 EDCB1_0
BI BI BI BI
EDCB0_1
10 K34 EDCB0_1 EDCB1_1 F33 10 EDCB1_1
BI BI
DBIA0_0
10 AK33 DBIA0_0 DBIA1_0 AF30 10 DBIA1_0
BI BI
DBIA0_1
10 AA35 DBIA0_1 DBIA1_1 Y28 10 DBIA1_1 DBIB0_0
10 U33 DBIB0_0 DBIB1_0 P30 10 DBIB1_0
BI BI BI BI
DBIB0_1
10 J35 DBIB0_1 DBIB1_1 G30 10 DBIB1_1
BI BI
t
CABIA010 AM30 CABIA0 CABIA1 AL26 10 CABIA1
OUT OUT
CABIB0 V25 AA27 10 CABIB1
b
10 CABIB0 CABIB1
OUT OUT
CKEA010 AJ27 CKEA0 CKEA1 AD25 10 CKEA1
OUT OUT
CKEB0
10 R27 CKEB0 CKEB1 L26 10 CKEB1
OUT OUT
CKA 10 AL29 CKA
OUT
CKAB 10 AL30 CKAB CKB10 U26 CKB
o
OUT OUT
CKBB
10 U27 CKBB
OUT
a
MEM_CALRA MEM_CALRB
R3600 1 2 118R 1% AH25 MEM_CALR_A R3601 1 2 118R 1% K26 MEM_CALR_B
g n
DRAM_RSTA DRAM_RSTB
DRAM_RSTA_R 10 R3602 1 2 UNNAMED_30_CAP_I3_A
49.9R 1% R3603 1 2 10R 1% AK24 DRAM_RSTA DRAM_RSTB_R 10 R3604 1 2 UNNAMED_30_CAP_I76_A
49.9R 1% R3605 1 2 10R 1% AD24 DRAM_RSTB
OUT OUT
1
1
1
1
C3600 C3601
i
120pF R3606 120pF R3607
50V 5.1K Navi14 Rev0.90 50V 5.1K Navi14 Rev0.90
1% 1%
2
2
2
2
G Do
Title
MEM CH AB
l
(9) NAVI14 MEM INTERFACE CH C/D
n it a
i d e
U1N
U1M DQD0_[0..15] symbol14 DQD1_[0..15]
BI 11 11 BI
DQD0_0 DQD1_0
f
DQC0_[0..15] 11 symbol13 11 DQC1_[0..15] 0 11 9 A17 DQD0_0 DQD1_0 E19 11 9 0
BI DQC0_0 DQC1_0 BI DQD0_1 DQD1_1
0 11 9 A33 DQC0_0 DQC1_0 C32 11 9 0 1 11 9 B16 DQD0_1 DQD1_1 H18 11 9 1
DQC0_1 DQC1_1 DQD0_2 DQD1_2
1 11 9 A30 DQC0_1 DQC1_1 D31 11 9 1 2 11 9 D16 DQD0_2 DQD1_2 F18 11 9 2
2 11 9 B29 DQC0_2 DQC1_2 B31 11 9 2 3 11 9 C15 DQD0_3 DQD1_3 G17 11 9 3
3 11 9 C27 DQC0_3 DQC1_3 E30 11 9 3 4 11 9 D14 DQD0_4 DQD1_4 F16 11 9 4
4 11 9 D26 DQC0_4 DQC1_4 D29 11 9 4 5 11 9 C13 DQD0_5 DQD1_5 G15 11 9 5
DQC1_5
n
DQC0_5 DQD0_6 DQD1_6
5 11 9 C25 DQC0_5 DQC1_5 G27 11 9 5 6 11 9 A13 DQD0_6 DQD1_6 E15 11 9 6
6 11 9 A25 DQC0_6 DQC1_6 E27 11 9 6 7 11 9 B12 DQD0_7 DQD1_7 F14 11 9 7
7 11 9 B24 DQC0_7 DQC1_7 F26 11 9 7 8 11 9 D10 DQD0_8 DQD1_8 H12 11 9 8
8 11 9 D22 DQC0_8 DQC1_8 H24 11 9 8 9 11 9 C9 DQD0_9 DQD1_9 G11 11 9 9
9 11 9 C21 DQC0_9 DQC1_9 G23 11 9 9 10 11 9 A9 DQD0_10 DQD1_10 E11 11 9 10
DQC0_10 DQC1_10 DQD0_11 DQD1_11
A21 E23 11 9 B7 H10
o
10 11 9 DQC0_10 DQC1_10 10 11 11 9 DQD0_11 DQD1_11 11 9 11
DQC0_11 DQC1_11 DQD0_12 DQD1_12
11 11 9 B20 DQC0_11 DQC1_11 H22 11 9 11 12 11 9 A6 DQD0_12 DQD1_12 G9 11 9 12
DQC0_12 DQC1_12 DQD0_13 DQD1_13
12 11 9 A19 DQC0_12 DQC1_12 E21 11 9 12 13 11 9 B5 DQD0_13 DQD1_13 F7 11 9 13
DQC0_13 DQC1_13 DQD0_14 DQD1_14
13 11 9 B18 DQC0_13 DQC1_13 H20 11 9 13 14 11 9 C4 DQD0_14 DQD1_14 E6 11 9 14
y
DQC0_14 DQC1_14 DQD0_15 DQD1_15
14 11 9 D18 DQC0_14 DQC1_14 F20 11 9 14 15 11 9 A3 DQD0_15 DQD1_15 D5 11 9 15
DQC0_15 DQC1_15
15 11 9 C17 DQC0_15 DQC1_15 G19 11 9 15 CAD0_[0..9] 11 11 CAD1_[0..9]
OUT CAD0_0 CAD1_0 OUT
CAC0_[0..9] 11 11 CAC1_[0..9] 0 11 9 E3 CAD0_0 CAD1_0 K4 11 9 0
OUT CAC0_0 CAC1_0 OUT CAD0_1 CAD1_1
0 11 9 L16 CAC0_0 CAC1_0 L14 11 9 0 1 11 9 K7 CAD0_1 CAD1_1 K12 11 9 1
CAC0_1 CAC1_1 CAD0_2 CAD1_2
C
1 11 9 K21 CAC0_1 CAC1_1 J25 11 9 1 2 11 9 C1 CAD0_2 CAD1_2 M7 11 9 2
2 11 9 J17 CAC0_2 CAC1_2 J13 11 9 2 3 11 9 K8 CAD0_3 CAD1_3 L10 11 9 3
p
3 11 9 K22 CAC0_3 CAC1_3 K23 11 9 3 4 11 9 D2 CAD0_4 CAD1_4 L5 11 9 4
4 11 9 K17 CAC0_4 CAC1_4 K13 11 9 4 5 11 9 J6 CAD0_5 CAD1_5 K11 11 9 5
5 11 9 L20 CAC0_5 CAC1_5 L24 11 9 5 6 11 9 L9 CAD0_6 CAD1_6 K10 11 9 6
6 11 9 L22 CAC0_6 CAC1_6 J23 11 9 6 7 11 9 G6 CAD0_7 CAD1_7 J11 11 9 7
7 11 9 K20 CAC0_7 CAC1_7 K24 11 9 7 8 11 9 E4 CAD0_8 CAD1_8 L6 11 9 8
o
8 11 9 K18 CAC0_8 CAC1_8 K14 11 9 8 9 11 9 E1 CAD0_9 CAD1_9 J4 11 9 9
e
CAC0_9 CAC1_9
9 11 9 K16 CAC0_9 CAC1_9 K15 11 9 9
WCKD0_0
11 C11 WCKD0_0 WCKD1_0 G13 11 WCKD1_0
BI BI
WCKC0_0
11 C23 WCKC0_0 WCKC1_0 G25 11
WCKC1_0 WCKD0B_0
11 D12 WCKD0B_0 WCKD1B_0 H14 11 WCKD1B_0
BI BI BI BI
t
WCKC0B_0
11 D24 WCKC0B_0 WCKC1B_0 H26 11
WCKC1B_0
BI BI
WCKD0_1
11 A11 WCKD0_1 WCKD1_1 E13 11 WCKD1_1
BI BI
WCKC0_1
11 A23 WCKC0_1 WCKC1_1 E25 11
WCKC1_1 WCKD0B_1
11 B10 WCKD0B_1 WCKD1B_1 F12 11 WCKD1B_1
BI BI BI BI
WCKC0B_1
11 B22 WCKC0B_1 WCKC1B_1 F24 11
WCKC1B_1
BI BI
C
EDCD0_0
11 B14 EDCD0_0 EDCD1_0 E17 11 EDCD1_0
BI BI
EDCC0_0 B26 C30 EDCC1_0 EDCD0_1 D7 E9 EDCD1_1
y
11 EDCC0_0 EDCC1_0 11 11 EDCD0_1 EDCD1_1 11
BI BI BI BI
EDCC0_1
11 D20 EDCC0_1 EDCC1_1 G21 11
EDCC1_1
BI BI
DBID0_0
11 A15 DBID0_0 DBID1_0 H16 11 DBID1_0
BI BI
DBIC0_0
11 A27 DBIC0_0 DBIC1_0 F29 11
DBIC1_0 DBID0_1
11 C6 DBID0_1 DBID1_1 F10 11 DBID1_1
BI BI BI BI
DBIC0_1
11 C19 DBIC0_1 DBIC1_1 F22 11
DBIC1_1
BI BI
t
CABID0
11 F4 CABID0 CABID1 K5 11 CABID1
OUT OUT
CABIC011 L18 J15 CABIC1
b
CABIC0 CABIC1 11
OUT OUT
CKED0
11 J7 CKED0 CKED1 L12 11 CKED1
OUT OUT
CKEC011 J21 CKEC0 CKEC1 K25 11
CKEC1
OUT OUT
CKD11 G5 CKD
OUT +MVDD
CKC 11 K19 CKC CKDB
11 F5 CKDB
o
OUT +MVDD OUT
CKCB 11 J19 CKCB
OUT
1
MEM_CALRD
R3608 1 2 118R 1% L8 MEM_CALR_D
1
MEM_CALRC R3610
R3609 1 2 118R 1% G29 MEM_CALR_C
40.2R
R3611 1%
40.2R
1%
2
DRAM_RSTD MVREFD_1
g
DRAM_RSTD_R 11 R3612 1 2 UNNAMED_29_CAP_I72_A
49.9R 1% R3613 1 2 10R 1% M6 DRAM_RSTD MVREFD_1 D3
2
OUT
1
DRAM_RSTC MVREFD_0
DRAM_RSTC_R 11 R3614 1 2 UNNAMED_29_CAP_I6_A
49.9R 1% R3615 1 2 10R 1% M12 DRAM_RSTC MVREFD_0 AN32
OUT
1
1
C3602
1
1
120pF C3604 R3617
i
C3603 50V R3616 100R
120pF C3605 R3619 5.1K 1uF 1%
R3618
2
50V 100R 1% Navi14 Rev0.90 6.3V
5.1K 1uF 1%
2
2
1% Navi14 Rev0.90 6.3V
2
G Do
Title
MEM CH CD
l
(10) GDDR6x16 CHAB Memory
U2000
n it a U2100
e
DQA0_[15..0] 8 8 DQA1_[15..0] DQB0_[15..0] 8 8 DQB1_[15..0]
BI DQA0_15 DQA1_10 BI BI DQB0_15 DQB1_10 BI
15 10 8 G13 M13 10 8 10 15 10 8 G13 M13 10 8 10
DQA0_14 DQ15_A DQ15_B DQA1_9 DQB0_14 DQ15_A DQ15_B DQB1_9
14 10 8 F13 N13 10 8 9 14 10 8 F13 N13 10 8 9
12 10 8 E13 P13 10 8 11 12 10 8 E13 P13 10 8 11
13 10 8 E12 P12 10 8 8 13 10 8 E12 P12 10 8 8
11 10 8 B13 U13 10 8 13 11 10 8 B13 U13 10 8 13
d
9 10 8 B12 U12 10 8 12 9 10 8 B12 U12 10 8 12
10 10 8 A12 V12 10 8 14 10 10 8 A12 V12 10 8 14
8 10 8 B11 U11 10 8 15 8 10 8 B11 U11 10 8 15
0 10 8 G2 M2 10 8 5 0 10 8 G2 M2 10 8 5
i
1 10 8 F2 N2 10 8 6 1 10 8 F2 N2 10 8 6
3 10 8 E2 P2 10 8 4 3 10 8 E2 P2 10 8 4
2 10 8 E3 P3 10 8 7 2 10 8 E3 P3 10 8 7
4 10 8 B2 U2 10 8 2 4 10 8 B2 U2 10 8 2
f
6 10 8 B3 U3 10 8 3 6 10 8 B3 U3 10 8 3
5 10 8 A3 V3 10 8 1 5 10 8 A3 V3 10 8 1
7 10 8 B4 U4 10 8 0 7 10 8 B4 U4 10 8 0
DQ0_A DQ0_B DQ0_A DQ0_B
CAA0_[9..0] 8 8 CAA1_[9..0] CAB0_[9..0] 8 8 CAB1_[9..0]

IN CAA0_9 CAA1_9 IN IN CAB0_9 CAB1_9 IN
9 10 8 J3 K3 10 8 9 9 10 8 J3 K3 10 8 9
CAA0_8 CA9_A CA9_B CAA1_8 CAB0_8 CA9_A CA9_B CAB1_8
10 8 J4 K4 10 8 J4 K4
n
8 10 8 8 8 10 8 8
7 10 8 J11 K11 10 8 7 7 10 8 J11 K11 10 8 7
6 10 8 J12 K12 10 8 6 6 10 8 J12 K12 10 8 6
5 10 8 H10 L10 10 8 5 5 10 8 H10 L10 10 8 5
4 10 8 H5 L5 10 8 4 4 10 8 H5 L5 10 8 4
3 10 8 H12 L12 10 8 3 3 10 8 H12 L12 10 8 3
10 8 G4 M4 10 8 G4 M4
o
2 10 8 2 2 10 8 2
1 10 8 G11 M11 10 8 1 1 10 8 G11 M11 10 8 1
0 10 8 H3 L3 10 8 0 0 10 8 H3 L3 10 8 0
CA0_A CA0_B CA0_A CA0_B
CKEA0 G10 M10 8 CKEB0 G10 M108
y
8 CKE_N_A CKE_N_B CKEA1 8 CKE_N_A CKE_N_B CKEB1
IN IN IN IN
WCKA0_18 D11 WCK1_t_A/NC WCK1_T_B R11 8 WCKA1_1 WCKB0_1 8 D11 WCK1_t_A/NC WCK1_T_B R11 8 WCKB1_1
IN IN IN IN
WCKA0B_1
8 D10 WCK1_c_A/NC WCK1_C_B R10 8 WCKA1B_1 WCKB0B_1
8 D10 WCK1_c_A/NC WCK1_C_B R10 8 WCKB1B_1
IN IN IN IN
C
WCKA0_0
8 D4 WCK0_T_B/NC R4 8 WCKA1_0 WCKB0_0
8 D4 WCK0_T_B/NC R4 8 WCKB1_0
IN WCK0_t_A IN IN WCK0_t_A IN
WCKA0B_0
8 D5 WCK0_C_B/NC R5 8 WCKA1B_0 WCKB0B_0
8 D5 WCK0_C_B/NC R5 8 WCKB1B_0
IN WCK0_c_A IN IN WCK0_c_A IN
p
EDCA0_1
8 C13 T13 8 EDCA1_1 EDCB0_1
8 C13 T13 8 EDCB1_1
OUT EDC1_A EDC1_B OUT OUT EDC1_A EDC1_B OUT
EDCA0_0 8 C2 T2 8 EDCA1_0 EDCB0_0 8 C2 T2 8 EDCB1_0
DBIA0_1
8 D13 R13 8 DBIA1_1 DBIB0_1
8 D13 R13 8 DBIB1_1
BI DBI1_A DBI1_B BI BI DBI1_A DBI1_B BI
DBIA0_0 8 D2 R2 8 DBIA1_0 DBIB0_0 8 D2 R2 8 DBIB1_0
+MVDD
BI DBI0_A DBI0_B BI +MVDD
BI DBI0_A DBI0_B BI
e o
CABIA0 8 J5 CABI_N_A CABI_N_B K5 8 CABIA1 CABIB0 8 J5 CABI_N_A CABI_N_B K5 8 CABIB1
IN IN IN IN
R2000 1 DNI 2 2.37K 1% R2100 1 DNI 2 2.37K 1%
VREFC_A VREFC_B
R2002 1 2 5.49K/4/1 K1 R2102 1 2 5.49K/4/1 K1
VREFC VREFC
C2000 1 21uF 6.3V C2100 1 21uF 6.3V
t
DNI DNI
Use internal G6 Vrefc, tie it to GND ZQ_A_A0 Use internal G6 Vrefc, tie it to GND ZQ_A_B0
ZQ_B_A1 ZQ_B_B1
R2004 1 2 120R 1% J14 K14 R2005 1 2 120R 1% R2104 1 2 120R 1% J14 K14 R2105 1 2 120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
G5 RFU_A/NC RFU_B/NC M5 G5 RFU_A/NC RFU_B/NC M5
C
CKA 8 J10 CKB 8 J10
IN CK_t IN CK_t
CKAB
8 K10 CKBB
8 K10
y
IN CK_c IN CK_c
DRAM_RSTA_R
8 J1 DRAM_RSTB_R
8 J1
IN RESET_n IN RESET_n
HDT_TCK
10,11 N5 HDT_TCK
10,11 N5
IN TCK IN TCK
t
HDT_TDO_BCH 10,11 F10 HDT_TDO_CCH 11 F10
IN TDI IN TDI
HDT_TDO_ACH N10 HDT_TDO_BCH N10
b
IN 11 TDO IN 10,11 TDO
HDT_TMS
10,11 F5 HDT_TMS
10,11 F5
IN TMS IN TMS
+MVDD +MVDD
o
V14 U14 V14 U14
a
VDD_12 VSS_52 VDD_12 VSS_52
A14 R14 A14 R14
L13 N14 L13 N14
H13 M14 H13 M14
P10 G14 GDDR6 CHA +VDDCR_MEM Decoupling Caps P10 G14
P5 VDD_7 F14 P5 VDD_7 F14
n
VSS_47 VSS_47
E10 D14 E10 D14
g
E5 B14 +MVDD E5 B14
L2 V13 L2 V13
H2 A13 H2 A13
i
1
1
V1 T12 V1 T12
A1 R12 C2002 C2003 C2004 C2005 C2006 C2007 C2008 C2009 C2010 C2011 C2012 A1 R12
N12 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF N12
VSS_40 +MVDD 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS_40
M12 2 M12
2
VSS_39 VSS_39
+MVDD G12 +MVDD G12
VSS_38 VSS_38
G Do
F12 F12
VSS_37 VSS_37
1
1
T14 D12 T14 D12
VDDQ_28 VSS_36 VDDQ_28 VSS_36
P14 C12 C2013 C2014 C2015 C2016 C2017 C2018 C2019 C2020 C2021 C2022 C2023 P14 C12
L14 V11 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF L14 V11
VDDQ_26 VSS_34 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDQ_26 VSS_34
H14 T10 H14 T10
2
2
E14 P11 E14 P11
C14 L11 +VPP C14 L11
K13 H11 K13 H11
J13 E11 J13 E11
1
1
N11 T5 N11 T5
T11 A11 C2024 C2025 C2026 C2027 C2028 T11 A11
U10 V4 10uF 1uF 1uF 1uF 1uF U10 V4
VDDQ_18 VSS_26 4V 6.3V 6.3V 6.3V 6.3V VDDQ_18 VSS_26
T4 C10 T4 C10
2
2
F11 P4 F11 P4
B10 L4 B10 L4
U5 H4 U5 H4
C11 E4 C11 E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHB +VDDCR_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
T1 G3 T1 G3
P1 F3 +MVDD P1 F3
L1 D3 L1 D3
H1 C3 H1 C3
1
1
E1 V2 E1 V2
C1 A2 C2102 C2103 C2104 C2105 C2106 C2107 C2108 C2109 C2110 C2111 C2112 C1 A2
U1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF U1
R1 R1
2
2
VSS_7 VSS_7
+VPP N1 +VPP N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
1
V10 G1 V10 G1
VPP_4 VSS_4 VPP_4 VSS_4
A10 F1 C2113 C2114 C2115 C2116 C2117 C2118 C2119 C2120 C2121 C2122 C2123 A10 F1
V5 D1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF V5 D1
VPP_2 VSS_2 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VPP_2 VSS_2
A5 GDDR6 B1 A5 GDDR6 B1
2
2
+VPP
1
C2124 C2125 C2126 C2127 C2128
10uF 1uF 1uF 1uF 1uF

4V 6.3V 6.3V 6.3V 6.3V
2
Title
MEM CH AB
Custom
GV-R55XTOC-4GD 1.0
l
(11) GDDR6x16 CHCD Memory
U2200
n it a DNI
U2300
e
DQC1_[15..0] 9 9 DQC0_[15..0] DQD1_[15..0] 9 9 DQD0_[15..0]
BI DQC1_5 DQC0_0 BI BI DQD1_5 DQD0_0 BI
5 11 9 G13 M13 11 9 0 5 11 9 G13 M13 11 9 0
DQC1_6 DQ15_A DQ15_B DQC0_1 DQD1_6 DQ15_A DQ15_B DQD0_1
6 11 9 F13 N13 11 9 1 6 11 9 F13 N13 11 9 1
4 11 9 E13 P13 11 9 3 4 11 9 E13 P13 11 9 3
7 11 9 E12 P12 11 9 2 7 11 9 E12 P12 11 9 2
2 11 9 B13 U13 11 9 4 2 11 9 B13 U13 11 9 4
d
3 11 9 B12 U12 11 9 6 3 11 9 B12 U12 11 9 6
1 11 9 A12 V12 11 9 5 1 11 9 A12 V12 11 9 5
0 11 9 B11 U11 11 9 7 0 11 9 B11 U11 11 9 7
10 11 9 G2 M2 11 9 15 10 11 9 G2 M2 11 9 15
i
9 11 9 F2 N2 11 9 14 9 11 9 F2 N2 11 9 14
11 11 9 E2 P2 11 9 12 11 11 9 E2 P2 11 9 12
8 11 9 E3 P3 11 9 13 8 11 9 E3 P3 11 9 13
13 11 9 B2 U2 11 9 11 13 11 9 B2 U2 11 9 11
f
12 11 9 B3 U3 11 9 9 12 11 9 B3 U3 11 9 9
14 11 9 A3 V3 11 9 10 14 11 9 A3 V3 11 9 10
15 11 9 B4 U4 11 9 8 15 11 9 B4 U4 11 9 8
DQ0_A DQ0_B DQ0_A DQ0_B
CAC1_[9..0] 9 9 CAC0_[9..0] CAD1_[9..0] 9 9 CAD0_[9..0]

IN CAC1_9 CAC0_9 IN IN CAD1_9 CAD0_9 IN
9 11 9 J3 K3 11 9 9 9 11 9 J3 K3 11 9 9
CAC1_8 CA9_A CA9_B CAC0_8 CAD1_8 CA9_A CA9_B CAD0_8
11 9 J4 K4 11 9 J4 K4
n
8 11 9 8 8 11 9 8
7 11 9 J11 K11 11 9 7 7 11 9 J11 K11 11 9 7
6 11 9 J12 K12 11 9 6 6 11 9 J12 K12 11 9 6
5 11 9 H10 L10 11 9 5 5 11 9 H10 L10 11 9 5
4 11 9 H5 L5 11 9 4 4 11 9 H5 L5 11 9 4
3 11 9 H12 L12 11 9 3 3 11 9 H12 L12 11 9 3
11 9 G4 M4 11 9 G4 M4
o
2 11 9 2 2 11 9 2
1 11 9 G11 M11 11 9 1 1 11 9 G11 M11 11 9 1
0 11 9 H3 L3 11 9 0 0 11 9 H3 L3 11 9 0
CA0_A CA0_B CA0_A CA0_B
CKEC1 G10 M10 9 CKED1 G10 M109
y
9 CKE_N_A CKE_N_B CKEC0 9 CKE_N_A CKE_N_B CKED0
IN IN IN IN
WCKC1_0 9 D11 WCK1_t_A/NC WCK1_T_B R11 9 WCKC0_0 WCKD1_0 9 D11 WCK1_t_A/NC WCK1_T_B R11 9 WCKD0_0
IN IN IN IN
WCKC1B_0
9 D10 WCK1_c_A/NC WCK1_C_B R10 9 WCKC0B_0 WCKD1B_0
9 D10 WCK1_c_A/NC WCK1_C_B R10 9 WCKD0B_0
IN IN IN IN
C
WCKC1_1
9 D4 WCK0_T_B/NC R4 9 WCKC0_1 WCKD1_1
9 D4 WCK0_T_B/NC R4 9 WCKD0_1
IN WCK0_t_A IN IN WCK0_t_A IN
WCKC1B_1
9 D5 WCK0_C_B/NC R5 9 WCKC0B_1 WCKD1B_1
9 D5 WCK0_C_B/NC R5 9 WCKD0B_1
IN WCK0_c_A IN IN WCK0_c_A IN
p
EDCC1_0
9 C13 T13 9 EDCC0_0 EDCD1_0
9 C13 T13 9 EDCD0_0
EDCC1_1 9 C2 T2 9 EDCC0_1 EDCD1_1 9 C2 T2 9 EDCD0_1
DBIC1_0
9 D13 R13 9 DBIC0_0 DBID1_0
9 D13 R13 9 DBID0_0
BI DBI1_A DBI1_B BI BI DBI1_A DBI1_B BI
DBIC1_1 9 D2 R2 9 DBIC0_1 DBID1_1 9 D2 R2 9 DBID0_1
+MVDD
BI DBI0_A DBI0_B BI +MVDD
BI DBI0_A DBI0_B BI
e o
CABIC1 9 J5 CABI_N_A CABI_N_B K5 9 CABIC0 CABID1 9 J5 CABI_N_A CABI_N_B K5 9 CABID0
IN IN IN IN
R2200 1 DNI 2 2.37K 1% R2300 1 DNI 2 2.37K DNI 1%
VREFC_C VREFC_D
R2202 1 2 5.49K/4/1 K1 R2302 1 2 5.49K/4/1 K1
VREFC VREFC
C2200 1 21uF 6.3V C2300 1 21uF 6.3V
t
DNI DNI
Use internal G6 Vrefc, tie it to GND ZQ_A_C1 Use internal G6 Vrefc, tie it to GND DNI ZQ_A_D1 DNI
ZQ_B_C0 ZQ_B_D0
R2204 1 2 120R 1% J14 K14 R2205 1 2 120R 1% R2304 1 2 120R 1% J14 K14 R2305 1 2 120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
G5 RFU_A/NC RFU_B/NC M5 G5 RFU_A/NC RFU_B/NC M5
C
CKC 9 J10 CKD 9 J10
IN CK_t IN CK_t
CKCB
9 K10 CKDB
9 K10
y
IN CK_c IN CK_c
DRAM_RSTC_R
9 J1 DRAM_RSTD_R
9 J1
IN HDT_TCK RESET_n IN RESET_n
N5 HDT_TCK
10,11 N5
IN 10,11 TCK IN TCK
t
HDT_TDI F10 HDT_TDO_ACH 10 F10
IN TDI IN TDI
HDT_TDO_CCH N10 HDT_TDO N10
b
IN HDT_TMS 10 TDO IN TDO
F5 HDT_TMS
10,11 F5
IN 10,11 TMS IN TMS
HDT_TCK +MVDD +MVDD

TP2200
o
TP2201 HDT_TDO
V14 U14 V14 U14
a
TP2202 11 For 128bit VDD_12 VSS_52 VDD_12 VSS_52
HDT_TDO_ACH
10
11 For 96bit A14 R14 A14 R14
TP2203 VDD_11 VSS_51 VDD_11 VSS_51
HDT_TDO_BCH 10 For 64bit L13 N14 L13 N14
10 H13 M14 H13 M14
P10
VDD_8
G14 GDDR6 CHC +VDDCR_MEM Decoupling Caps P10
VDD_8
G14
C->B->A->D VSS_48 VSS_48
P5 VDD_7 F14 P5 VDD_7 F14
n
VSS_47 VSS_47
E10 D14 E10 D14
g
E5 B14 +MVDD E5 B14
L2 V13 L2 V13
H2 A13 H2 A13
i
1
1
V1 T12 V1 T12
A1 R12 C2202 C2203 C2204 C2205 C2206 C2207 C2208 C2209 C2210 C2211 C2212 A1 R12
N12 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF N12
M12 2 M12
2
VSS_39 VSS_39
+MVDD G12 +MVDD G12
VSS_38 VSS_38
G Do
F12 F12
VSS_37 VSS_37
1
1
T14 D12 T14 D12
P14 C12 C2213 C2214 C2215 C2216 C2217 C2218 C2219 C2220 C2221 C2222 C2223 P14 C12
L14 V11 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF L14 V11
VDDQ_26 VSS_34 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDQ_26 VSS_34
H14 T10 H14 T10
2
2
E14 P11 E14 P11
C14 L11 +VPP C14 L11
K13 H11 K13 H11
J13 E11 J13 E11
1
1
N11 T5 N11 T5
T11 A11 C2224 C2225 C2226 C2227 C2228 T11 A11
U10 V4 10uF 1uF 1uF 1uF 1uF U10 V4
VDDQ_18 VSS_26 4V 6.3V 6.3V 6.3V 6.3V VDDQ_18 VSS_26
T4 C10 T4 C10
2
2
F11 P4 F11 P4
B10 L4 B10 L4
U5 H4 U5 H4
C11 E4 C11 E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHD +VDDCR_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
T1 G3 T1 G3
P1 F3 +MVDD P1 F3
L1 D3 L1 D3
H1 C3 H1 C3
1
1
E1 V2 DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI E1 V2
C1 A2 C2302 C2303 C2304 C2305 C2306 C2307 C2308 C2309 C2310 C2311 C2312 C1 A2
U1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF U1
R1 R1
2
2
VSS_7 VSS_7
+VPP N1 +VPP N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
1
V10 G1 DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI V10 G1
A10 F1 C2313 C2314 C2315 C2316 C2317 C2318 C2319 C2320 C2321 C2322 C2323 A10 F1
V5 D1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF V5 D1
VPP_2 VSS_2 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VPP_2 VSS_2
A5 GDDR6 B1 A5 GDDR6 B1
2
2
+VPP
+MVDD
1
DNI DNI DNI DNI DNI

1
C2324 C2325 C2326 C2327 C2328

DNI DNI
10uF 1uF 1uF 1uF 1uF + +
C2361 C2362
4V 6.3V 6.3V 6.3V 6.3V 470uF/X 470uF/X
2
2V 2V
Reserved
2
Title
MEM CH CD
Custom
GV-R55XTOC-4GD 1.0
l
U1F
(12) TMDP AB
it a
symbol6
USBC0_RXP2/TX2P_DPA0P AJ2
USBC0_RXN2/TX2M_DPA0N AJ1
USBC0_TXP2/TX1P_DPA1P AK3
USBC0_TXN2/TX1M_DPA1N AK2
USBC0_TXP1/USB_0_TXP0/TX0P_DPA2P AG2
USBC0_TXN1/USB_0_TXN0/TX0M_DPA2N AG3
n
USBC0_RXP1/USB_0_RXP0/TXCAP_DPA3P AF1
USBC0_RXN1/USB_0_RXN0/TXCAM_DPA3N AF2
AC5
e
DDCAUX5P
DNI
USB0_ZVSS
R1703 1 2 200R/X 1% AL6 USB_ZVSS DDCAUX5N AC6
Navi14 Rev0.90
d
+3V3_BUS
i
U1U
symbol 21
USBPD_I2C_MASTER_SDA
R1713 1 2 10K AP5 USBPD_I2C_MASTER_SDA
USBPD_I2C_MASTER_SCL
f
R1702 1 2 10K AR5 USBPD_I2C_MASTER_SCL
USB_PD_INTERRUPT
R1700 1 2 10K AN6 USB_PD_INTERRUPT
USBPD_I2C_SLAVE_SDA
R1711 1 2 10K AN4 USBPD_I2C_SLAVE_SDA
USBPD_I2C_SLAVE_SCL
R1710 1 2 10K AP4 USBPD_I2C_SLAVE_SCL
n
USB_VAUX_PRESENT
R1701 1 2 10K AM5 USB_VAUX_PRESENT
o
USB_OCP#
R1709 1 2 10K AR3 USB_OCP0
y
AM3 USB20_TXRTUNE
C p
AL1 USB20_DP0
AL2 USB20_DM0
USB_OBS
o
R1712 1 2 10K AG8 USB_OBS
e
Navi14 Rev0.90
b y t t C
a o
改footprint
n
U1J
g
symbol10
Add GND voids underneath J1750
+5V_VESA
TX2P_DPB0P UNNAMED_7_CAP_I76_B
CTX2P
TX2P_DPB0P AE3 C1750 1 20.1uF 6.3V R1780 1 2 0/4 1% 12 1 TMDS Data 2+
UNNAMED_7_IND_I89_B
i
L17801 2 0/4 R1770 1 2 499R 1% +5V Pwr 18
1
TX2M_DPB0N UNNAMED_7_CAP_I72_B
CTX2N
TX2M_DPB0N AE2 C1751 1 20.1uF 6.3V R1781 1 2 0/4 1% 12 3 TMDS Data 2-
UNNAMED_7_IND_I90_B
L17811 2 0/4 R1771 1 2 499R 1% C1758
CTX1P
TX1P_DPB1P AD2 C1752 1 20.1uF 6.3V R1782 1 2 0/4 1% 12 4 TMDS Data 1+ 1u/4/X5R/6.3V/K
UNNAMED_7_IND_I91_B 16V
L17821 2 0/4 R1772 1 2 499R 1%
G Do
2
CTX1N
TX1M_DPB1N AD1 C1753 1 20.1uF 6.3V R1783 1 2 0/4 1% 12 6 TMDS Data 1-
UNNAMED_7_IND_I87_B
L17831 2 0/4 R1773 1 2 499R 1%
CTX0P
TX0P_DPB2P AC3 C1754 1 20.1uF 6.3V R1784 1 2 0/4 1% 12 7 TMDS Data 0+
UNNAMED_7_IND_I88_B
L17841 2 0/4 R1774 1 2 499R 1%
CTX0N
TX0M_DPB2N AC2 C1755 1 20.1uF 6.3V R1785 1 2 0/4 1% 12 9 TMDS Data 0-
UNNAMED_7_IND_I84_B
L17851 2 0/4 R1775 1 2 499R 1%
TXCBP_DPB3P UNNAMED_7_CAP_I70_B
CTXCP
TXCBP_DPB3P AB2 C1756 1 20.1uF 6.3V R1786 1 2 0/4 1% 12 10 TMDS Clock+
UNNAMED_7_IND_I85_B
L17861 2 0/4 R1776 1 2 499R 1%
TXCBM_DPB3N UNNAMED_7_CAP_I69_B
CTXCN
TXCBM_DPB3N AB1 C1757 1 20.1uF 6.3V R1787 1 2 0/4 1% 12 12 TMDS Clock-
DPB_ZVSS UNNAMED_7_IND_I86_B
R1760 1 2 200R 1% V9 DPB_ZVSS 1 6 L17871 2 0/4 R1777 1 2 499R 1%
DPC_ZVSS DDCAUX4P DDC4CLK_HDMI
R1761 1 2 200R 1% T9 DPC_ZVSS DDCAUX4P AB4 12
DPD_ZVSS Q1750B
R1762 1 2 200R 1% R9 DPD_ZVSS
DPE_ZVSS 2N7002DW DDC4DAT_HDMI
R1764 1 2 200R 1% P8 DPE_ZVSS DDCAUX4N AB5 DDCAUX4N 4 3 12
2
Q1750A
1
Navi14 Rev0.90 2N7002DW +12V_BUS_B

R1750 R1751 R1752 R1753
5
10K 10K 2.2K 2.2K DPB_GND
1
15 DDC Clock
2
+3V3_BUS R1788
100K
16 DDC Data D0 Shld 8
3
OPTIONAL ESD PROTECTION DIODES D1 Shld 5
2
DVI_HDMI_EN Q1753 +3V3_BUS
+3V3_BUS +5V_VESA 1 D2 Shld 2
1
D1750 D1751 11
2N7002L Clk Shld
3
CTXCN 1 3 CTX1N 1 3 C1778 17
12 12 GND (+5V) SCREW1750
2
Q1751 UNNAMED_7_NPN_I21_B HPD_HDMI
0.1uF 1 R1756 1 12 2 22K 19 Hot Plog Detect
CTXCP CTX1P 16V
12 2 8 12 2 8 MMBT3904 CASE 20
2
SCREW
HPD4 4 R1757 1 2 10K 14 NC CASE 21
2
OUT
CTX0N 4 CTX2N 4 22
12 12 CASE
6 CTX0P 6 CTX2P 13 23
12 12 CEC CASE
CTX0P 5 7 CTX0N CTX2P 5 7 CTX2N
12 12 12 12
9 CTXCP 9 CTX1P
12 12 HDMI/19P/BK/F/RA/S/Au
10 CTXCN 10 CTX1N
DNI 12 DNI 12
ESD8104MUTAG/X ESD8104MUTAG/X
D1752
HPD_HDMI
12 1 3
改改改改 diho 20190827
2 8
DDC4DAT_HDMI
12 4
DDC4CLK_HDMI
6 12
DDC4CLK_HDMI DDC4DAT_HDMI
12 5 7 12
9
HPD_HDMI
10 12
ESD8104MUTAG
Title
TMDPAB
l
(13) TMDP D/E
it a
U1G +3V3_DPCD
J1800
symbol7 Add GND voids underneath F1800
+3V3_BUS
TX2P_DPC0P DPC_0P
TX2P_DPC0P AA3 C1800 1 20.1uF 6.3V 13 1 ML_Lane_0p DP_PWR 20 2 1
1
DNI
n
TX2M_DPC0N DPC_0N 1.5A
AA2 C1801 1 20.1uF 6.3V 13 3 C1810 C1811
TX2M_DPC0N ML_Lane_0n
22uF 100uF/X
TX1P_DPC1P DPC_1P 6.3V 6.3V
TX1P_DPC1P Y2 C1802 1 20.1uF 6.3V 13 4 ML_Lane_1p
2
TX1M_DPC1N DPC_1N
Y1 C1803 1 20.1uF 6.3V 13 6
e
TX1M_DPC1N ML_Lane_1n
TX0P_DPC2P DPC_2P
TX0P_DPC2P W3 C1804 1 20.1uF 6.3V 13 7 ML_Lane_2p modify footprint 0805 colay 0603 by diho 2019..8.27
TX0M_DPC2N DPC_2N
TX0M_DPC2N W2 C1805 1 20.1uF 6.3V 13 9 ML_Lane_2n
TXCCP_DPC3P DPC_3P
V2 C1806 1 20.1uF 6.3V 13 10
d
TXCCP_DPC3P ML_Lane_3p
TXCCM_DPC3N DPC_3N
TXCCM_DPC3N V1 C1807 1 20.1uF 6.3V 13 12 ML_Lane_3n
SCREW1800
i
SCREW
DDCAUX3P UNNAMED_9_CAP_I97_A AUXP_DPC
DDCAUX3P AA5 R1800 1 2 0/4 1% C1808 1 20.1uF 6.3V 13 15 AUX_CHp
R1801 1 2 100K
DDCAUX3N UNNAMED_9_CAP_I40_A AUXN_DPC
DDCAUX3N AA6 R1802 1 2 0/4 1% C1809 1 20.1uF 6.3V 13 17 AUX_CHn
1
f
DNI DNI R1803 1 2 100K
+3V3_DPCD
+12V_BUS_B +12V_BUS_B
Navi14 Rev0.90 C1812 C1813 改改改改diho 20190827
47pF/X 47pF/X +3V3_BUS
50V 50V UNNAMED_9_MOSN_I20_D
4 3 3 4 AUXP_DPC
PWR_RTN 19
3
21 21
Q1800A UNNAMED_9_MOSN_I38_D
Q1801B UNNAMED_9_NPN_I69_B HPD_DPC
1 6 6 1 R1804 R1805 5 R1806 1 2 22K 13 18 Hot_Det 22 22
2N7002DW Q1802A
n
Q1800B Q1802B 10K 10K 23
2N7002DW MMDT3904-7 23
5
2N7002DW 2N7002DW
HPD3 4 R1807 1 2 10K 24 24
4
OUT
GND_0 2
3
AUX_DPC_BYPSS_EN
GND_1 5
Q1803 DPC_DONGLE_DET
1 DPC_DONGLE_DET
13 13 CONFIG 1 GND_2 8
6
1 2 11
o
R1808 1M GND_3
UNNAMED_9_DISPLAYPORT_I87_PIN14
Q1801A 2
UNNAMED_9_MOSN_I61_D
R1809 1 2 5.1M 14 16
CONFIG 2 GND_6
2
MMDT3904-7 2N7002E
1
y
DISPLAY/20P/BK/OS/RA/S/GF
U1H +3V3_DPCD
J1850
symbol8
Add GND voids underneath
TX2P_DPD0P DPD_0P
TX2P_DPD0P U3 C1850 1 20.1uF 6.3V 13 1 ML_Lane_0p DP_PWR 20
1
C
DNI
TX2M_DPD0N DPD_0N C1860 C1861
TX2M_DPD0N U2 C1851 1 20.1uF 6.3V 13 3 ML_Lane_0n
p
22uF 100uF/X
TX1P_DPD1P DPD_1P 6.3V 6.3V
TX1P_DPD1P T2 C1852 1 20.1uF 6.3V 13 4 ML_Lane_1p
2
TX1M_DPD1N DPD_1N
TX1M_DPD1N T1 C1853 1 20.1uF 6.3V 13 6 ML_Lane_1n
TX0P_DPD2P DPD_2P
o
TX0P_DPD2P R3 C1854 1 20.1uF 6.3V 13 7 ML_Lane_2p modify footprint 0805 colay 0603 by diho 2019..8.28
e
TX0M_DPD2N DPD_2N
TX0M_DPD2N R2 C1855 1 20.1uF 6.3V 13 9 ML_Lane_2n
TXCDP_DPD3P DPD_3P
t
TXCDP_DPD3P P2 C1856 1 20.1uF 6.3V 13 10 ML_Lane_3p
TXCDM_DPD3N DPD_3N
TXCDM_DPD3N P1 C1857 1 20.1uF 6.3V 13 12 ML_Lane_3n
SCREW1850
SCREW
C
DDCAUX2P UNNAMED_9_CAP_I26_A AUXP_DPD
DDCAUX2P AA8 R1850 1 2 0/4 1% C1858 1 20.1uF 6.3V 13 15 AUX_CHp
R1851 1 2 100K
y
DDCAUX2N UNNAMED_9_CAP_I27_A AUXN_DPD
DDCAUX2N AA9 R1852 1 2 0/4 1% C1859 1 20.1uF 6.3V 13 17 AUX_CHn
1
1
DNI DNI R1853 1 2 100K
Navi14 Rev0.90 +3V3_DPCD
C1862 C1863 +12V_BUS_B +12V_BUS_B
47pF/X 47pF/X +3V3_BUS

50V 50V UNNAMED_9_MOSN_I18_D
t
4 3 3 4 PWR_RTN 19
2
3
21
b
21
Q1850A UNNAMED_9_MOSN_I22_D
Q1851B UNNAMED_9_NPN_I52_B HPD_DPD
1 6 6 1 R1854 R1855 5 R1856 1 2 22K 13 18 Hot_Det 22 22
2N7002DW Q1852A
Q1850B Q1852B 10K 10K 23
2N7002DW MMDT3904-7 23
5
2N7002DW 2N7002DW
HPD2 4 R1857 1 2 10K 24 24
4
OUT
GND_0 2
o 2
3
AUX_DPD_BYPSS_EN
GND_1 5
a
Q1853 DPD_DONGLE_DET
1 DPD_DONGLE_DET
13 13 CONFIG 1 GND_2 8
6
R1858 1 2 1M GND_3 11
Q1851A 2
R1859 1 2 5.1M 14 16
CONFIG 2 GND_6
2
MMDT3904-7 2N7002E
n
1
g
改改改改diho 20190827
13
13
13
13
OPTIONAL ESD PROTECTION DIODES
DPC_3N
DPC_3P
DPC_2N
DPC_2P
1
DNI
D1800
6
7
9
10
DPC_2P
DPC_2N
13
DPC_3P
DPC_3N
13
13
13
13
13
13
13
DPC_1N
DPC_1P
DPC_0N
DPC_0P
1
5
D1801
DNI
3
6
7
9
10
DPC_0P
DPC_0N
DPC_1P
DPC_1N
13
13
13
13
13
13
13
13
DPD_3N
DPD_3P
DPD_2N
DPD_2P
1
5
i
G Do
D1850
DNI
3
6
7
9
10
DPD_2P
DPD_2N
13
DPD_3P
DPD_3N
13
13
13
13
13
13
13
DPD_1N
DPD_1P
DPD_0N
DPD_0P
1
5
D1851
DNI
3
6
7
9
10
DPD_0P
DPD_0N
DPD_1P
DPD_1N
13
13
13
13
ESD8004/X ESD8004/X ESD8004/X ESD8004/X
D1852
HPD_DPD
13 1 3
D1802
HPD_DPC AUXN_DPD
13 1 3 13 2 8
AUXN_DPC AUXP_DPD
13 2 8 13 4
DPD_DONGLE_DET
6 13
AUXP_DPC DPD_DONGLE_DET AUXP_DPD
13 4 13 5 7 13
DPC_DONGLE_DET AUXN_DPD
6 13 9 13
DPC_DONGLE_DET AUXP_DPC HPD_DPD
13 5 7 13 10 13
AUXN_DPC
9 13
HPD_DPC
10 13 ESD8004
ESD8004 Title
TMDPCD
l
(14) TMDP C
it a
modify footprint 0805 colay 0603 by diho 2019..8.27
+3V3_DPE +3V3_BUS
U1I
J1900
symbol9
Add GND voids underneath F1900
TX2P_DPE0P DPE_0P
TX2P_DPE0P N3 C1900 1 20.1u/4/X7R/16V/K
6.3V 14 1 ML_Lane_0p DP_PWR 20 2 1
1
DNI 1206L150THWR/S
TX2M_DPE0N DPE_0N C1910 C1911
TX2M_DPE0N N2 C1901 1 20.1u/4/X7R/16V/K
6.3V 14 3 ML_Lane_0n
22u/6/X5R/6.3V/M 100uF/X
TX1P_DPE1P DPE_1P 6.3V 6.3V
TX1P_DPE1P M2 C1902 1 20.1u/4/X7R/16V/K
6.3V 14 4 ML_Lane_1p
2
e
TX1M_DPE1N DPE_1N
TX1M_DPE1N M1 C1903 1 20.1u/4/X7R/16V/K
TX0P_DPE2P DPE_2P
TX0P_DPE2P L3 C1904 1 20.1u/4/X7R/16V/K
6.3V 14 7 ML_Lane_2p
TX0M_DPE2N DPE_2N
TX0M_DPE2N L2 C1905 1 20.1u/4/X7R/16V/K
d
TXCEP_DPE3P DPE_3P
TXCEP_DPE3P K2 C1906 1 20.1u/4/X7R/16V/K
6.3V 14 10 ML_Lane_3p
TXCEM_DPE3N DPE_3N
K1 C1907 1 20.1u/4/X7R/16V/K
6.3V 14 12 SCREW1900
i
TXCEM_DPE3N ML_Lane_3n
SCREW
DDCAUX1P UNNAMED_13_CAP_I260_A AUXP_DPE
DDCAUX1P Y7 R1900 1 2 0/4 1% C1908 1 20.1u/4/X7R/16V/K
6.3V 14 15 AUX_CHp
R1901 1 2 100K/4
AUXN_DPE
f
DDCAUX1N Y8 DDCAUX1N R1902 1 2 0/4 1% C1909 1 20.1u/4/X7R/16V/K
6.3V 14 17 AUX_CHn
1
DNI DNI R1903 1 2 100K/4
+3V3_DPE
Navi14 Rev0.90 C1912 C1913 +12V_BUS_B +12V_BUS_B +3V3_BUS
47pF/X 47pF/X
50V 50V
PWR_RTN 19
Q1901B
Q1902B
6
21 21
n
Q1900A UNNAMED_13_NPN_I290_B HPD_DPE
1 6 6 1 R1904 R1905 2 R1906 1 14 2 22K/4 18 Hot_Det 22 22
Q1901A
Q1902A
10K/4 10K/4 23
MMDT3904G-3T6R/SOT-363/200mA 23
4 3 3 4 24 24
1
2N7002DW/SOT363/50pF/7m
2N7002DW/SOT363/50pF/7m HPD1 4 R1907 1 2 10K/4 GND_0 2
2
OUT
3
2N7002DW/SOT363/50pF/7m 2N7002DW/SOT363/50pF/7m
GND_1 5
Q1904 DPE_DONGLE_DET
1 13 8
o
14 CONFIG 1 GND_2
3
AUX_DPE_BYPASS_EN
GND_3 11
Q1900B 5
R1908 1 2 1M/4 R1909 1 2 5.1M/4 14 16
CONFIG 2 GND_6
2
MMDT3904G-3T6R/SOT-363/200mA L2N7002SLT1G/SOT23/21pF/2.8OHM
y
4
C
改改改改diho 20190827
te o p
y C
D1950 D1951
DPE_3N DPE_1N
14 1 3 14 1 3
DPE_3P DPE_1P
14 2 8 14 2 8
t
DPE_2N DPE_0N
4 4
b
14 14
DPE_2P DPE_0P
6 14 6 14
DPE_2P DPE_2N DPE_0P DPE_0N
14 5 7 14 14 5 7 14
DPE_3P DPE_1P
9 14 9 14
DPE_3N DPE_1N
10 14 10 14
o
Stuff DP by diho 2019..8.27
DNI DNI
a
ESD8004/X ESD8004/X
D1952
HPD_DPE
14 1 3
n
AUXN_DPE
g
14 2 8
AUXP_DPE
14 4
DPE_DONGLE_DET
i
6 14
DPE_DONGLE_DET AUXP_DPE
14 5 7 14
AUXN_DPE
9 14
HPD_DPE
10 14
G Do
ESD8004MUTAG/UDFN10/S
Title
TMDPE
l
REG - VDDGFX/VDDSOC CTRL
it a
VDDGFX_PWM1
16 OUT
VDDGFX_PWM2
16 OUT
VDDGFX_PWM3
16
VDDSOC_RCS_P OUT
17 1 R500 2
3.48K/4/1 VDDGFX_PWM4
17 16 OUT
1%
1
R501 C500 VDDGFX_PWM5
16
3.65K/4/1 82pF
OUT
1% 50V
VDDGFX_PWM6
16
2
VDDSOC_RCS_N OUT
17 1 R502 2
n
3.48K/4/1 VDDSOC_PWM1
17 17
OUT
1%
VDDSOC_LOC_P 17 1 R503 2 modify 0402 by diho.su 20190901
IN
100R
+3V3_BUS
1
FB_VDDCR_SOC 1 R504 2
e
6,26
IN
1
0R C501
FB_VSS_A 1 R505 2 0.0033uF
6,15,26 C502 C503
IN 50V
2.2u/4/X5R/6.3V/M 0.1uF
0R
2
6.3V 16V
2
VDDSOC_LOC_N 17 1 R506 2
IN VDDCGND
d
100R
16 1 R507 2
2.74K/4/1
16
VDDGFX_RCS_P 1%
1
i
1
R508 C504
1
3.83K/4/1 82pF
38
1% 50V U500 R509
4.99K
VDDGFX_RCS_N R510 R511
2
1%
f
1 2 4.99K 4.99K
VCC
16 R512
2
RSCP_L2 1% 1%
16
2.74K/4/1 40 RCSP_L2 PWM1 28
2
1% RSCM_L2
39 RCSM_L2 PWM2 29
PWM3 30
VSEN_L2
37 VSEN_L2 PWM4 31
VRTN_L2
change LL match choke value by diho 2019..8.27 36 VRTN_L2 PWM5 32
n
PWM6 33
RCSP 2 RCSP
RCSM 3 RCSM PWM1_L2/PWM8 35
VDDGFX_LOC_P 16 100R 1 R513 2 PWM2_L2/PWM7 34
IN
VSEN 5 VSEN
1
0R 1 2 6
o
FB_VDDCR_GFX 6,26 R514 VRTN VRTN
IN UNNAMED_21_IR35217M_I36_VRDY1
FB_VSS_A 6,15,26 0R 1 R515 2 C505 VRDY1 11 1 R516 2 VDDGFX_PGOOD
IN 0.0033uF
OUT
54 ISEN1 0R
50V UNNAMED_21_IR35217M_I36_VRDY2 VDDSOC_PGOOD
VDDGFX_LOC_N 16 100R 1 R517 2 55 IRTN1 VRDY2 4 1 R518 2
2
IN OUT
y
52 ISEN2 0R
1
VDDGFX_I1_P 16 53 IRTN2 NC#13 13
IN
50 ISEN3 NC#15 15 R519 R520
VDDGFX_I1_N 51 IRTN3 NC#41 41 4.7K 4.7K
16
IN
C
48 ISEN4
2
VDDGFX_I2_P 16 49 IRTN4
IN
p
46 20 VRHOT_ICRIT# 1 R521 2
ISEN5 VRHOT_ICRIT# 4 GFX_SOC_VRHOT# OUT
VDDGFX_I2_N 16 47 IRTN5 0R
IN
DNI 1 ISEN6
SM_ALERT#
VDDGFX_I3_P 16 56 IRTN6 SM_ALERT# 23
IN
1 R522 2
o
VDDGFX_I3_N 16 0R/X 42 ISEN1_L2/ISEN8 IMON 7 UNNAMED_21_CAP_I27_A
e
IN
1
DNI 43 IRTN1_L2/IRTN8
ISEN2_L2
VDDGFX_I4_P 16 1 R524 2 44 ISEN2_L2/ISEN7 C506 16V
IN IRTN2_L2
1 R525 2 0R 45 IRTN2_L2/IRTN7 0.01uF VDDCGND
t
VDDGFX_I4_N 16 0R/X
2
IN
9 TSEN1 SVT/SV_ALERT# 17 SVT 1 R526 2 SVT_GFX_SOC
4
OUT
VDDGFX_I5_P 16 0R
IN
1 R527 2 27 TSEN2/VAUXSEN
C
UNNAMED_21_IR35217M_I36_IOUTALERT
VDDGFX_I5_N 16 0R/X IOUT_ALERT#/PIN_ALERT# 26 1 R528 2 GPIO4_GFX_PCC#
4,18,26
IN OUT
VINSEN 14
y
VINSEN 0R
VDDGFX_I6_P 16
IN
1 R529 2 24 SM_DIO CFILT 10 V18A
1
VDDGFX_I6_N 16 0R/X 25 SM_CLK
IN
TH 57 C507 C508
VDDIO 4.7uF 0.47uF
t
16 VDDIO/SV_ADDR TH 58
6.3V 6.3V
VDDSOC_I1_P 59
b
17 TH
2
IN VDDCGND
TH 60
UNNAMED_21_IR35217M_I36_SVC
VDDSOC_I1_N 17 18 SVC/SV_CLK TH 61
IN UNNAMED_21_IR35217M_I36_SVD
19 SVD/SV_DIO TH 62
VDDGFX_TSEN_P 16 1 R530 2 UNNAMED_21_CAP_I81_A
TH 63
o
IN
0R PWROK 12 PWROK/EN_L2/CATFLT TH 64
a
1
TH 65
1
R531 TH 66
13K I_IN
C509 8 I_IN TH 67
1%
0.01uF 68
TH
2
16V
VDDGFX_TSEN_N 16 1 R532 2 TH 70
n
2
IN VDDCGND
g
0R 21 EN TH 69
TH 71 +3V3_BUS
VDDSOC_TSEN_P 17 22 ADDR_PROT TH 72
IN
1
i
1
VDDCGND
C510 IR35217M
0.01uF
R533 16V
13.3K
2
1%
G Do
2
5
VDDSOC_TSEN_N 17 1 R534 2 U501B
IN VDDCGND
0R R535 C511
1
+12V_EXT_A 845R 0.01uF
1% 16V
26.1K C512
2
1
2
1%
1%
1
R536 2 1% 0.1uF
DNI 16V
1
1
+12V_BUS_B NC7SZ08P5X
R537
R538
C513
2
1
1000pF/X
C514 R539 50V
1 2 R541 0.01uF 7.5K VDDCGND
1K
1K
R540
1
1K 16V 0.1%
1
1% VDDCGND
26.1K 1%
2
2
R542 R543
2
4.7K 4.7K
U501A
VDDCGND PERST#_BUF 1
3,19,23,24,28
2
IN VDDGFX_VDDSOC_PWROK
4 15
VDDCGND VDDGFX_PGOOD VDDGFX_VDDSOC_PGOOD
REG_SDA 4,18,19,26 15 1 R544 2 2
IN
0R
NC7SZ08P5X
REG_SCL 4,18,19,26
IN
1
VDDSOC_PGOOD
DNI DNI 15 1 R545 2
C515 C516 0R
1
2
3
47pF/X 47pF/X
J500 50V 50V
NS500 SCHEMATIC
2
DEBUG 2 1
+1V8
HEADER_1X3/X VDDCGND NS501 SCHEMATIC
1 R546 2 2 1
1
0R NS502 SCHEMATIC
C517 2 1
0.1uF
16V NS503 SCHEMATIC
2 1
2
VDDCGND
NS504 SCHEMATIC
2 1
SVC_GFX_SOC 4,25 1 R549 2 NS505 SCHEMATIC
IN
0R 2 1
SVD_GFX_SOC 4,25 1 R550 2
IN VDDCGND
0R
1
DNI DNI
1
R553 C520
100K/X 1000pF/X
50V R554
10K/X
2
1%
2
VDDCGND
DNI
VDDGFX_SOC_EN 24
IN
1 VDDGFX_VDDSOC_PWROK
R555 2
1
VDDGFX_VDDSOC_PWROK
IN 0R
C521
0.01uF
16V
2
VDDCGND
Title
REG DDGFX SOC
l
REG - VDDGFX
it a
PLACE NEXT TO PHASE 3 HALF BRIDGE
1
15 VDDGFX_TSEN_P
OUT
R556
47K VDDGFX_TSEN_N
1% 15 OUT
AMD CHOKE
2
HF Inductor 0.22uH 10% CORE 0.15uH 42A/100A MAGIC
DCR=0.4mR Irms=50A Isat=70A SMD 11.5*10.3*4 DCR=0.5m +/-7%
+VDDGFX_SOURCE1 10.8x7.7x9.9mm SMT +12V_EXT_A VDDGFX_I2_P
15 OUT
n
0805 Colay 0603 by diho 2019.8.27 15 VDDGFX_I1_P
OUT
0805 Colay 0603 by diho 2019.8.27 改改改改 by diho 2019..8.27
改改改改 by diho 2019..8.27 15 VDDGFX_I2_N
OUT
1
15 VDDGFX_I1_N
OUT
1
LFPAK D 5 C522 LFPAK D 5
C534
+ Q501 + 0.1uF Q500 1 R557 2 1 2
C523 C524 C525 C526 C527 C528 C535 C529 C530 C531 C532 C533 16V
270u/FP/D/16V/88/12m 10uF 4.7u/6/X5R/16V/K
10uF 4.7u/6/X5R/16V/K
0.1uF 1 2
UNNAMED_39_NETSHORT_I133_N2
1 2 10uF 270u/FP/D/16V/88/12m 10uF 10uF 10uF 1.43K/4/1 0.22uF 25V
e
R558
2
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V VDDGFX_PHS2_UG 1%
2
2 0805 0805 4G 1.43K/4/1 0.22uF 25V
0805 0805 1 R559 2 4G
2
VDDGFX_PHS1_UG 1%
NS506
NS507
1 R560 2 S 1 1/6 S 1
+VDDGFX_SOURCE1 +12V_EXT_A 0603
NS508
NS509
0.22uH/X
1/6 2 1 R561 2 2
1
L500
0603 VDDGFX_PHS2_BOOT
10K DNI
0.22uH/X
1 R562 2 1 R563 2 3 1 R564 2 1 R565 2 3
1
L501
VDDGFX_PHS1_BOOT VDDGFX_PHS2_SWNODE
1
1
1R 1 R566 2 UNNAMED_39_CAP_I144_A
10K DNI 1R 1R 1 2
VDDGFX_PHS1_SWNODE
1
C536 1R 1 2 C537 U503 C538
L510 0.15uH/42A/S/0.5m
d
1uF U504 C539 1uF 0.22uF
16V 16V 25V
UNNAMED_39_CHL8510_I39_HIGATE
0603 0.22uF 0603 1 BOOT HI_GATE 10

2
1
25V L511 0.15uH/42A/S/0.5m
1 BOOT HI_GATE 10 4 VCC SWITCH 9 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7%
2
VDDGFX_PHS2_LG
1
UNNAMED_39_CHL8510_I39_PWM
4 9 5 VDDGFX_PWM2 1 15R567 2 3 6 5 5 C540
i
VCC SWITCH
VDDGFX_PHS1_LG
LFPAK D IN PWM LO_GATE LFPAK D LFPAK D
1
VDDGFX_PWM1 1 R568 2 3 6 Q504 5 0R Q502 Q503 R569 0.1uF
IN 15 PWM LO_GATE LFPAK D 2.2/8
R570 C541 16V
0R Q505 2 HVCC MODE 8 0805
2
2.2/8
4G 4G 4G
UNNAMED_39_CHL8510_I157_MODE
2 8 0805 0.1uF 5 7 DNI
HVCC MODE LVCC GND
12
1
1
DNI 16V
S 4G S S
5 7 1 11 1 1
f
LVCC GND GND
2
1
1
11 2 S 1 C542 C543 R571 2 2 C544
GND CHL8510CR 0R
1
C545 C546 R572 3 2 10u/8/X6S/16V/M
0.1uF 3 3 2.2n/6/X7R/50V/K
CHL8510CR 0R
C547 16V 16V 50V
10u/8/X6S/16V/M 0.1uF 3 0805 0603
2
16V 16V DNI
0805 2.2n/6/X7R/50V/K
2
2
50V
0603
2
DNI
n
VDDGFX_RCS_P
1
15 OUT
PLACE BETWEEN PHASE 1 AND 2 INDUCTORS R10868
o
R573
10K VDDGFX_RCS_N
1% 15 OUT
+12V_EXT_A
2
+12V_EXT_A
1%
0805 Colay 0603 by diho 2019.8.27 0805 Colay 0603 by diho 2019.8.27 改改改改 by diho 2019..8.27
y
10K/4/X 15 VDDGFX_I3_P 15 VDDGFX_I4_P
OUT OUT
改改改改 by diho 2019..8.27
15 VDDGFX_I3_N 15 VDDGFX_I4_N
OUT OUT
1
1
+ 5 + 5
C548 C549 C550 C551 C552 C553 LFPAK D C560
C554 C555 C556 C557 C558 C559 LFPAK D C561
C
270u/FP/D/16V/88/12m 10uF 10uF 10uF 10uF 0.1uF Q506 1 R574 2 1 2 10uF 10uF 270u/FP/D/16V/88/12m
10uF 10uF 0.1uF Q507 1 R575 2 1 2
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
1.43K/4/1 0.22uF 25V 1.43K/4/1 0.22uF 25V
0805 0805 0805 0805
2
2
1% 1%
2
VDDGFX_PHS3_UG VDDGFX_PHS4_UG
p
1 R576 2 4G 1 R577 2 4G
+12V_EXT_A +12V_EXT_A
NS510
NS511
NS512
NS513
1/6 S 1 1/6 S 1
0603 0603
0.22uH/X
0.22uH/X
1 R578 2 UNNAMED_39_CAP_I226_A
1 R579 2 2 1 R580 2 1 10K 2 2
1
L502
L503
VDDGFX_PHS3_BOOT VDDGFX_PHS4_BOOT R581
1
1
1R 1 R582 2 10K DNI 3 1R 1 R583 2 DNI 3 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7%
VDDGFX_PHS3_SWNODE VDDGFX_PHS4_SWNODE
1
1
C562 1R 1 2 C563 1R 1 2
1uF U505 C564 1uF U506 C565
1
16V L512 0.15uH/42A/S/0.5m 16V L513 0.15uH/42A/S/0.5m
o
0.22uF 0.22uF
e
0603 0603
2
2
1
1
25V
UNNAMED_39_CHL8510_I224_HIGATE 25V
UNNAMED_39_CHL8510_I95_HIGATE
C566
1 BOOT HI_GATE 10 1 BOOT HI_GATE 10
2
2
4 9 R584 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7% 4 9 R585 0.1uF
VCC SWITCH 2.2/8 VCC SWITCH 2.2/8
VDDGFX_PHS3_LG VDDGFX_PHS4_LG 16V
VDDGFX_PWM3 15 1 R586 2 3 PWM LO_GATE 6 LFPAK D 5 0805 VDDGFX_PWM4 15 1 R587 2 3 PWM LO_GATE 6 LFPAK D 5 LFPAK D 5 0805
2
IN IN
1
DNI DNI
0R Q508 D 5 0R Q510 Q511
t
LFPAK
2
Q509
2 HVCC MODE 8 C567 2 HVCC MODE 8
1
5 LVCC GND 7 4G 0.1uF 5 LVCC GND 7 4G 4G
16V
1
1
GND 11 S 1 4G GND 11 S 1 S 1 C568
2
C569 C570 R588 2 S 1 2.2n/6/X7R/50V/K
C571 C572 C573 R589 2 2 2.2n/6/X7R/50V/K
CHL8510CR 0R CHL8510CR 0R
C
50V
10u/8/X6S/16V/M 0.1uF 3 2 10u/8/X6S/16V/M
0.1uF 3 3 0603
2
16V 16V 50V 16V 16V DNI
0805 3 0603 0805
y
2
2
DNI
t
+12V_EXT_A
改改改改 by diho 2019..8.27 15 VDDGFX_I5_P
OUT
+VDDCR_GFX
0805 Colay 0603 by diho 2019.8.27
b
15 VDDGFX_I5_N
OUT
1
1
LFPAK D 5
C580
+ Q512 1 2
R590 1 2 R591
C574 C575 C576 C577 C578 C579 100R
o
270u/FP/D/16V/88/12m 10uF 10uF 10uF 10uF 0.1uF 1.43K/4/1 0.22uF 25V
16V 16V 16V 16V 16V 16V VDDGFX_PHS5_UG 1%
2
2
1 R592 2 4G
a
0805 0805
2
2
NS514
NS515
1/6 S 1
+12V_EXT_A 0603
0.22uH/X
1 R593 2 2
1
1
L504
VDDGFX_PHS5_BOOT
1 R594 2 1 R595 2 UNNAMED_39_CAP_I208_A
10K DNI 3
VDDGFX_PHS5_SWNODE
1
1 2
1R 1R
2
C581 U507 C582
n
L514 0.15uH/42A/S/0.5m
NS516
NS517
1uF 0.22uF
g
1
16V 25V
0603 1 BOOT HI_GATE 10
2
1
4 9 R596 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7%
VCC SWITCH 2.2/8
VDDGFX_PHS5_LG
1
VDDGFX_PWM5 15 1 R597 2 3 PWM LO_GATE 6 LFPAK D 5 LFPAK D 5 0805
IN
i
DNI C583
0R Q513 Q514 15 VDDGFX_LOC_P
2
UNNAMED_39_CHL8510_I232_MODE OUT
2 HVCC MODE 8 0.1uF
1
16V
5 LVCC GND 7 4G 4G 15 VDDGFX_LOC_N
2
OUT
1
11 S 1 S 1 C584
GND
C585 C586 R598 2 2 2.2n/6/X7R/50V/K
CHL8510CR 0R
G Do
50V
10u/8/X6S/16V/M
0.1uF 3 3 0603 改改改改 Colay 0603 by diho 2019..8.27
2
16V 16V DNI

0805
2
1
1
1
C587 C588 C589 C590 C591 C592 C593 C594 C595 C596 C597 C598 C599 C600 C601 C602
+ + + + + + 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M
C603 C604 C605 C606 C607 C608
+12V_EXT_A 820uF 820uF 820uF 820uF 820uF 820uF 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
2
3V 3V 3V 3V 3V 3V
0805 Colay 0603 by diho 2019.8.27 改改改改 by diho 2019..8.27 6.3X8 6.3X8 6.3X8 6.3X8 6.3X8 6.3X8 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm
2
15 VDDGFX_I6_P
OUT
15 VDDGFX_I6_N
OUT
1
C609 C610 C611 C612 C613 LFPAK D 5

C614
10uF 10uF 10uF 10uF 0.1uF Q515 1 2
R599 1 2
16V 16V 16V 16V 16V
1
1.43K/4/1 0.22uF 25V
0805 0805
2
VDDGFX_PHS6_UG 1%
2
1
1 R600 2 4G C615 C616 C617 C618 C619 C620 C621 C622 C623 C624 C625 C626 C627 C628 C629 C630
+12V_EXT_A
NS518
NS519
1/6 S 1 R624 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M
0603 100R 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
0.22uH/X
1 R601 2 1 R602 2 2 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
1
2
L505
1
VDDGFX_PHS6_BOOT
1 2 3
1R R603 10K 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm
2
VDDGFX_PHS6_SWNODE
1
C631 1R 1 2
1uF U508 C632
16V L515 0.15uH/42A/S/0.5m
0603 0.22uF
2
25V
1 BOOT HI_GATE 10
2
4 9 R604 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7%

VCC SWITCH 2.2/8
VDDGFX_PHS6_LG
VDDGFX_PWM6 15 1 R605 2 3 PWM LO_GATE 6 LFPAK D 5 LFPAK D 5 0805
IN
1
DNI
0R Q516 Q517
2
2 8 C633
HVCC MODE
5 LVCC GND 7 4G 4G 0.1uF
1
16V
GND 11 S 1 S 1
2
C634 C635 R606 2 2 C636

CHL8510CR 0R
10u/8/X6S/16V/M
0.1uF 3 3 2.2n/6/X7R/50V/K
16V 16V 50V
0805 0603
2
DNI
Title
REG VDDGFX
Custom
GV-R55XTOC-4GD 1.0
l
REG: VDDSOC
n it a
fi d e
n
Place close to the inductor
o
VDDSOC_TSEN_P 15
OUT
R607
47K VDDSOC_TSEN_N 15
1% OUT
y
+VDDSOC_SOURCE
C
改改改改新新Q620 by diho 2019.8.27
p
0805 Colay 0603 by diho 2019.8.27
1
AMD CHOKE
RH INDUCTOR 0.27uH 20% +
C637 C638 C639 C640 C641
+VDDSOC_SOURCE ,Isat=62A Irms=36A,Rdc=0.82mR 5%,
R608
5 10uF 4.7u/6/X5R/16V/K
10uF 270u/FP/D/16V/88/12m 10uF
LFPAK D 16V 16V 16V 16V 16V
Q618 11.5x7.5x5mm,SMT
o
1 2 UNNAMED_38_CAP_I46_A
2
1
1 R609 2 UNNAMED_38_CAP_I42_A
1R
1
4G
UNNAMED_38_MOSN2D3STH_I38_G4
C642 1R 1 R610 2
1uF U509 C643 1/6 S 1 L611 0.36uH/28A/S/1.05m +VDDCR_SOC
16V
t
0603 0.22uF 1 R611 2 2 CORE 0.36uH 28A/60A MAGIC
2
25V VDDSOC_HG
1
UNNAMED_38_CHL8510_I45_BOOT
BOOT HI_GATE 10 10K 3 L601 SMD 11.5*10.6*4 DCR=1.05m+/-7%
2
VDDSOC_PH 1%
4 VCC SWITCH 9 1 2
VDDSOC_PWM1 15 1 R612 2 3 PWM LO_GATE 6 0.27uH/X
IN
1
C
0R
2
+ +
NS520
2 8 5 5 R613 C644 C645 C646 C647 C648
D D
y
HVCC MODE LFPAK LFPAK 100R C649 C650
NS521
5 7 Q619 Q620 R614 22u/6/X5R/6.3V/M 2.2u/4/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 820uF
22u/6/X5R/6.3V/M 820uF
LVCC GND
1
2.2R 3V 3V
1
1
2.5V 2.5V 2.5V 2.5V 2.5V
GND 11
2
VDDSOC_LG C653
C651 C652
CHL8510CR
R615 4G 4G 1 R616 2 1 2
12
0R
4.7u/6/X5R/16V/K S S
0.1uF 1 1 1.65K/4/1 0.22uF 25V
1%
2
16V 16V C654
t
0805 2 2
2
NS522
NS523
3 3 0.0022uF
b
50V
1
15 VDDSOC_I1_N BI
15 VDDSOC_I1_P 15 VDDSOC_LOC_P
o
OUT OUT
a
15 VDDSOC_LOC_N
OUT
g n
VDDSOC_RCS_P
15
OUT
1
i
Place next to vddc phase inductor R617
10K VDDSOC_RCS_N
15
1% OUT
2
G Do
Title
REG VDDSOC
l
PCC
it a
1.8V REFERENCE DAC
INITIAL VOLTAGE = 1.8V
I2C ADDRESS(7bit/8bit) 0x53/0xA6
n
1
+1V8
e
R4600
13.3K/X
1%
1
C4601
DNI
0.1uF/X U4601 R4653
16V 2K/X
1 VCC VID0 8 1%
2
2 7
d
GND VID1 DNI
2
UNNAMED_42_RES_I26_B UNNAMED_42_RES_I44_B
REG_SCL R4637
4,15,19,26 1 2 0R/X 3 SCL VREF 6 UNNAMED_42_CAP_I38_A
1 R4619 2 1 R4651 2 1 R4655 2 UNNAMED_42_CAP_I67_A
IN
1
UNNAMED_42_RES_I25_B
REG_SDA R4638
4,15,19,26 1 2 0R/X 4 SDA R1 5 UNNAMED_42_RES_I37_A 2K/X
0R/X 0R/X DNI
IN 1%
1
TS0T23-8 C4689
i
DNI
1
GS8601-ATD/X 0.1uF/X R4654
DNI 2K/X
1
R4650 16V
C4602 1%
2
2K/X
0.033uF/X 1%
R4601
2
16V
f
127K/X
2
1%
2
1 R4628 2
+5V_VR 127K/X
1%
n
1 R4602 2
+3V3_BUS 10R/X
1%
1
5
R4633
10K/X
1
PCC_DAC_OUT
1%
y
C4600
UNNAMED_42_CAP_I43_B
1 2 3 C4613
2
1
1000pF/X50V U4600
0.1uF/X
V+
1
1
C4604 16V
UNNAMED_42_COMPARATOR_I55_OPOUT
+VDDCR_GFX 1 1 R4634 2 4,15,26 GPIO4_GFX_PCC#
2
R4635 R4636
OUT
10pF/X 0R/X
NS4603 0R/X 0R/X 50V
V-
C
2 1 1 R4613 2 DNI 4
2
TLV3201AIDBV/X
182R/X UNNAMED_42_LMP8640_I39_IN
2
p
1%
UNNAMED_42_LMP8640_I39_IN_1
3
2
1
IN-
IN+
R4615 R4617
UNNAMED_42_LMP8640_I39_NC
1.82K/X 10K/X 5
1% 1% NC#5 TP4600
C4691
o
1 2
e
2
2
6 UNNAMED_42_CAP_I49_A 10pF/X50V DNI
U4602 V+
NS4600 TSOT-6 1 R4690 2
2 1 1 R4605 2 1 R4614 2 LMP8640MK/X 100R/X
1%
1
t
DNI
0R/X 182R/X 1.1mm 1
VOUT
1%
C4610 R4691 C4690
49.9K/X
V-
0.1uF/X 1% 0.1uF/X
16V 16V
NS4601
2
C
UNNAMED_42_NETSHORT_I16_N1 UNNAMED_42_RES_I17_B
2 1 1 R4606 2
0R/X
a b y o t
i g
G Do n
Title
REG PCC
l
REG - MVDD/VDDCI CTRL
n it a
d e
+3V3_BUS +3V3_BUS
i
2
5
1%
1%
f
U700B NST700
1 2
R798
R799
1
1K
1K
C760
1
0.1uF
6.3V NST701
NC7SZ08P5X 1 2
2
U700A
1
n
PERST#_BUF 3,15,23,24,28
IN
4
MVDD_PGOOD R786 MVDD_VDDCI_PWRGD
19 1 2 2 AGND1
0R
VDDCI_PGOOD R785 NC7SZ08P5X
19 1 2
0R DNI
o
MR700
1 2 UNNAMED_37_RES_I128_B
+12V_BUS_B
0R/X
y
2
1%
R751
MVDD_CSSUM R714
MVDD OCP ~30A 19 19,20 1 2 MVDD_ISENP1
IN
2
+5V_VR 47K/4/1
1K
+1V8
1
1%
C
R755
0R
R754 MVDD_CSCOMP R723 R722
1 2 UNNAMED_37_CAP_I84_A MVDD_DRON 1 2 1 2
20 OUT 19
R75319 VCC1
p
2.2R 1 2 47K 1% 232K/4/1
1
1%
1
MVDD_PWM1
3.3R 20 Match choke R724
C742
OUT
1
C761 1 2 1 2
1uF R734 R735
C759 C758 1 2 19,20 1 2 MVDD_ISENN1
6.3V IN
1
4.7uF 0.01uF 100K 330p/4/NPO/50V/J
50V
10K 1% 0/4 1% C743
2
10V 25V R725 1%
MVDD_ILM 1 2 1 2
C756 19
1
o
0.01uF 24K/4/1
e
50V 1% 1000pF 50V
MVDD_VDDCI_PWROK AGND1
11
13
OUT 25 C757 R736
1
U701 0.1uF 100K/X R737
19,20 1 2 MVDD_ISENP1
25V 1% IN
VCC
1
VRMP
SVD_MVDD_VDDCI_VR25 3.6K/4/1
PWROK R726 R727
2
BI 1%
2 32 AGND1 1K 3.4K
t
SVD DRON 1% 1% C744
R756 VR_SVT1 R728 R718
SVT_MVDD_VDDCI_VR
25 1 2 3 SVT PWM1/SR 31 1 21 2 19,20 1 2 MVDD_ISENN1
12
2
OUT IN
0R 4 SVC CSN1 34UNNAMED_37_CAP_I58_A
10R 1% 10R 1%
SVC_MVDD_VDDCI_VR25 5 33 1000pF 50V
IN VDDIO CSP1 C745
R738 0.0022uF
1 2
50V
C
R739 VCC1 MVDD_DROOP R729
15.8K 1 2 19 19 1 2
2
1%
1
MVDD_VDDCI_EN
24 10 EN 2K 1%
0R
y
IN UNNAMED_37_NCP81022_I105_PWM2IMAXNB
PWM2/IMAXNB 29 C755
MVDD_PGOOD 9 38 AGND1 0.01uF MVDD_CSREF
OUT VDD_PWRGD CSN2 50V 19
1
1
TSC700 CSP2 37
AGND1
MVDD_FB 1 TSR700 2 1 TSR701 2 R740
R781 C781 19 1 2 1 2 C746

100K 100pF/X 50 1000pF
1% 50V 0R/XDNI 10R 1% DIFF 0R 50V
t
680pF 50V 30
UNNAMED_37_NCP81022_I105_PWM3IMAX
AGND1
DNI C762 C763 PWM3/IMAX
2
2
1
1 TSR702 2 R758 R759

UNNAMED_37_CAP_I89_A UNNAMED_37_CAP_I83_A
1 21 2 1 21 2 47 36
b
COMP CSN3
TSC701 24.9K 1% 47.5R 1% 3.3K/4/1 1% CSP3 35
0.0056uF 1n/4/X7R/50V/K
50V 2.2n/4/X7R/50V/K
50V R743
1 2 AGND1
16V R741
48 18K 1 2 VCC1
C764 FB 19
2
1%
1
R760 UNNAMED_37_NCP81022_I105_PWM4ADD
DNI 1 2 1 2 PWM4/ADD 28 2K 1%
o
UNNAMED_37_RES_I164_B UNNAMED_37_NCP81022_I105_TRBST UNNAMED_37_NCP81022_I105_CSN4
MVDD_LOC_P 1 R788 2 49 39
20 1K 1% TRBST CSN4 C754
100/4 AGND1 100p/4/NPO/50V/J
50V MVDD_FB 40 AGND1 0.01uF
a
20
1% 19 2% CSP4 50V
24
OUT
AGND1
R742
1 2
NR757 MVDD_CSSUM
FB_VDDIO_MEM 16 R795 2 1 2 FB_MVDD_VR 51 VDD CSSUM 43 19 0R
IN
1
0R 402R AGND1
0.1% MVDD_CSCOMP
DNI C765 52 VSS CSCOMP 44 19
n
1
1000pF/X R744
FB_VSS_B 1 2
g
IN 6 50V
NR762 R761 MVDD_ILM
1 2 DNI C768 DNI C767 1 2 45.3K 1%
2
VDDCI_CSSUM R715 VDDCI_ISENP1

0R 0.1uF/X 0.1uF/X 30K 42 46 119,20 2
16V 16V C766 IOUT ILIM 19 19 IN
MVDD_LOC_N 1% UNNAMED_37_CAP_I108_B
20 1 R789 2 FB_MVDD_VSS_VR 1 2 47K/4/1

2
i
1%
AGND1
0.1uF 16V
R745
100/4 MVDD_DROOP
24
20 1% DNI OUT VDDCI_CSCOMP
2K
VCC1 R730 R717
UNNAMED_37_RES_I34_A
DROOP 45 19 AGND1 1 2 19 19 1 2 1 2
VDDCI_PGOOD AGND1 AGND1 8 MVDD_CSREF
OUT VDDNB_PWRGD 47K 1% 137K/4/1 1%
AGND1
R746
CSREF 41 19 1 2 R719 C747
UNNAMED_37_NCP81022_I105_DIFFNB
VDDCI_FB TSC702 17 DIFFNB 0R 1 2 1 2
G Do
TSR703 TSR704
19 1 2 1 2 1 2 C769 C770
R764 UNNAMED_37_CAP_I110_A R763 UNNAMED_37_CAP_I104_A
VDDCI_ILM 100K 470pF/X50V
0R/XDNI 10R 1% 1 21 2 1 21 2 19 COMPNB MVDD OCP ~35A C748
680pF 50V VDDCI_PWM1 R720 1%
47.5R 1% 3.3K/4/1 1% PWM1NB/SRNB 27 20 19 1 2 1 2
OUT
1
TSR705 1n/4/X7R/50V/K
50V 2.2n/4/X7R/50V/K
50V R747
TSC703 1 2 CSN1NB 26UNNAMED_37_CAP_I101_A
1 2 13.7K
1% 2.2n/4/X7R/50V/K
50V
0.0056uF 25 Match choke
16V 24.9K 1% C771 CSP1NB 10K 1%
1
R765
1 2 1 2 16 FBNB
1
+VDDCI VDDCI_FB
1K 1% R721 R731
2
19 R748
100p/4/NPO/50V/J
50V 18 AGND1 1 VDDCI_ISENN1
2 1K 3.32K
2% TRBSTNB VDDCI_CSSUM 19,20
C752 IN 1% 1% C749
1
NR702 0.01uF R732 UNNAMED_37_CAP_I38_A
UNNAMED_37_CAP_I38_B R716 VDDCI_ISENN1
1 2 UNNAMED_37_CAP_I159_A
CSSUMNB 24 19 0/4 1% 1 21 2 119,20 2
IN
12
2
50V
AGND1
402R 1% VDDCI_CSCOMP C753 R750 10R 1% 10R 1%
2
0.1uF 100K/X R749 VDDCI_ISENP1 1000pF 50V
CSCOMPNB 22 19 19,20 1 2 C750
R779 25V 1% IN
FB_VDDCI_MEM 6 1 2 15 3.6K/4/1 VDDCI_DROOP 0.0022uF
IN VDDNB
2
1% 50V
1
NR704 R733
0R 1 2 AGND1
19 1 2
1
AGND1
30K 23 VDDCI_ILM
DNI NC700 IOUTNB 0R
1%
0.1uF/X 20
16V NC701 ILIMNB 19 C751
1 2 1000pF
2
50V
2
0.1uF 16V 6 VDDCI_DROOP
SCL
REG_SCL
4,15,18,26 AGND1 7 SDA DROOPNB 21 19
IN UNNAMED_37_NCP81022_I105_OCPL
14 OCP_L
AGND1
4,15,18,26
REG_SDA
BI
AGND_59
AGND_57
AGND_55
AGND_54
AGND_56
AGND_58
AGND_60
AGND_1
NR705
ROSC
1 2
4
MVDD_VDDCI_OCP#
OUT
0R
NCP81022
1 12
59
57
55
53
54
56
58
60
1
NR782
10K
NR706
47K/4/1
2
1%
+3V3_BUS
47K WF~400KHZ
2
AGND1
AGND1
Title
REG VDDCI_MVDD
Custom
GV-R55XTOC-4GD 1.0
l
REG - MVDD/VDDCI
n it a
e
+MVDD_SOURCE
fi d
1
DNI
改改改改 by diho 2019.8.27 C701 C703 +
C702 C704 C705 C706 C707 C708 C790 C791 C792
1000pF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 150uF/X
50V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
2
LFPAK D 5 AMD CHOKE 0.82uH 20%
n
Q700 Isat=31.0A, Irms=16.5A,
Rdc=3.85mR, 8.7x8.1x5.0mm SMT
+5V_VR 4G +MVDD
S 1 L703 0.36uH/28A/S/1.05m
1
R702 22.2R
2 CORE 0.36uH 28A/60A MAGIC SMD 11.5*10.3*4 DCR=1.05±7%
1
SMD 11.5*10.6*4 DCR=1.05m+/-7%
0.82uH/X
3 0805 Colay 0603 by diho 2019.8.27
L700
C741 NS701
1
1u/4/X5R/6.3V/K R703
1 2 1 2 1 2 MVDD_LOC_P 19
10V
1/6 C9356 19
2
y
R704 0.1uF/X
U710 1 2 NS702 6.3V
4
10K 1% 1 2 MVDD_LOC_N 19
2
1
MVDD_UG
8
VCC
DRVH 19
1
R706 UNNAMED_36_NCP5901B_I80_PWM
MVDD_PWM1 119 2 2 PWM C738 LFPAK D 5 R777
IN
2
R705 MVDD_PH 2.2R + +
C
UNNAMED_36_NCP5901B_I80_BST UNNAMED_36_CAP_I73_A
1 1 21 2 Q702 100R C712 C713
0R BST R700 C710 C711 C734 C735 C715 C714
R707
NS720
NS721
UNNAMED_36_NCP5901B_I80_EN
MVDD_DRON 119,20 2 3 22u/6/X5R/6.3V/M
22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M
22u/6/X5R/6.3V/M 0.1uF 820uF 820uF
EN 1R
2
IN 2.5V 2.5V 2.5V 6.3V 3V 3V
p
0.1u/6/X7R/25V/K
25V 2.5V 2.5V
49.9R 1% SW 7 4G DNI ADD
2
S
1
2
MVDD_LG
DRVL 5 2
3 C737
9 1000pF
TH
GND
50V
o
603 19 MVDD_ISENP1
e
1
+VDDCI_SOURCE
NCP81151 19
6
19 MVDD_ISENN1
t
19
C
1
1
y
改改改改 by diho 2019.8.28 C717 C718 C719 C720
C721
C722 C723
1000pF 10uF 10uF 10uF 10uF 10uF 10uF

50V 16V 16V 16V 16V 16V 16V
2
+5V_VR 5
LFPAK D
Q703 AMD CHOKE
t
RH INDUCTOR, 0.33uH 20%, +VDDCI
1
R710 22.2RUNNAMED_36_CAP_I92_A
b
1
4G Isat=31A Irms=16A, 0805 Colay 0603 by diho 2019.8.28

S 1 DCR=4..08mR 5%, 8x8x2mm SMT L702 0.36uH/28A/S/1.05m
C740
1u/4/X5R/6.3V/K R712
1 2 2
10V
0.33uH/X
1/6 3
o
L701
2
R713
U711 1 2 CORE 0.36uH 28A/60A MAGIC
a
4
10K 1% SMD 11.5*10.6*4 DCR=1.05m+/-7% 2 1

VDDCI_UG
8
VCC
DRVH
1
R708 UNNAMED_36_NCP5901B_I97_PWM
VDDCI_PWM1 1 19 2 2 PWM C739
IN R711
UNNAMED_36_NCP5901B_I97_BST UNNAMED_36_CAP_I88_A
C726 C727 C728 C729 + +
0R BST 1 1 21 2 LFPAK D 5 R776 C733 C732 C730 C731
R709 UNNAMED_36_NCP5901B_I97_EN
100R 22u/8/X6S/6.3V/M
22u/6/X5R/6.3V/M
22u/8/X6S/6.3V/M 22u/8/X6S/6.3V/M
22u/8/X6S/6.3V/M 0.1uF 330uF 470uF
MVDD_DRON 1 19,20 2 3 EN 1R Q704
n
IN 0.1u/6/X7R/25V/K
25V VDDCI_PH 4V 4V 4V 4V 4V 6.3V 2V 2V
g
49.9R 1% SW 7
2
2
2
4G
VDDCI_LG 2.2R
NS723
NS724
DRVL 5 S 1 R701
i
2
1
TH 9 3 DNI
1
GND
2
NCP81151
6
C736
G Do
1000pF
50V
603
1
19 VDDCI_ISENP1
19
19 VDDCI_ISENN1
19
Title
REG VDDCI_MVDD
l
REG - 0.75V
it a
0V75_SENSE_N
0V75_SENSE_P
n
B902 +12V_BUS_B
1 2
e
+3V3_BUS 30R/X
0805 Colay 0603 by diho 2019.8.27
B901
1 2 UNNAMED_35_BEAD_I37_A
30R
1
R922
2 1 UNNAMED_35_NETSHORT_I11_N1
d
R902 C901 C902 C903 C904 C905 C906 0R
1R 0.1uF 10u/6/X5R/6.3V/M
10u/6/X5R/6.3V/M
10u/6/X5R/6.3V/M
10u/6/X5R/6.3V/M
10u/6/X5R/6.3V/M
1% 16V 16V 16V 16V 16V 16V R921
2 1 UNNAMED_35_NETSHORT_I10_N1
i
2
2
0R
f
1
0.75V_CSP
0V75_PWRGD 24
OUT
R904
0.75V_CSN 0.75V_VCC 1R
1%
2
1
C907 R906 LFPAK D 5
n
0.0015uF 3.01K Q901
50V 1% C915
1uF 0.75V_VCCP
C917
12
2
16V R911
4G
1 2 1 2
1
R916
S 1 1
2
15
R905 0.8V_AGND 0R
1
301R s 2 0.22uF 25V
1% C916 8.45K 1%
R907 0.75V_VSEN
VCC
1 2 13 6 1uF 3
o
CSP PGOOD R910
2
16V
1
1R AMD CHOKE
0R
2
1%
1
C911 12 CSN HF Inductor, 1.0uH 20%
2
100pF Irms=10.4A, Isat=16.6A,
VCCP 1 R912
50V
1
R917 Rdc=8.1mR 5%
NS901
NS905
NS906
49.9K 1 2
C912 0V8
2
1% 8.0x7.7x2.0mm SMT
1
1 2 10 VSEN U900 1.87K 1%
1
s 0.75V_BOOT
NS902
33pF 50V
BOOT 4 C924 Colay C9347放放C923正正正
2
0.22uF
1.0uH/X
0.8V_AGND
L901
25V
C
0V75_FB 24 C913 8 COMP +0V75
2
IN 1% R908 UNNAMED_35_CAP_I64_A 0.75V_UG
1
20K 2 1 2 UG 5 1 2
p
1
C988 0.0056uF 16V
1
DNI C950 1 2 9 FB
0.75V_SWNODE L911 1uH/11A/S
1000pF/X 3 SMD_078X072 COMMON + +
50V PHASE C926 R950 C9347 C923 C920 C921 C922 C927 C9350 C9349
470pF/X50V 0.1uF 100R 470u/S/2V/X/6m470uF/X 22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M/X
22u/8/X6S/6.3V/M
22u/6/X5R/6.3V/M 22u/6/X5R/6.3V/M/X
22u/6/X5R/6.3V/M
DNI
2
16V 2V 2V 4V 4V 4V 4V 4V 4V
24 11 FBG
2
IN 0.75V_LG
CORE 1uH 11A /16A
o
+12V_BUS_B LG 2
e
1
SMD 7.3*6.8*3mm
14 ROSC/EN THM 17 LFPAK D 5 R915
DCR=8±10%mOHM
2.2/8
THM 18 Q902
1
t
THM 19 colay C9347
2
R913
4G
UNNAMED_35_GS7250_I55_SYNC UNNAMED_35_MOSN4D3STH_I34_G4
R963 7 SYNC 20 1 2
GND
THM
6
100K S 1
1% DNI 0R
1
2 Q905B 2
C914 R909
2
16
1
C
100pF/X 61.9K GS7260
2N7002DW R923 3
50V 1%
3
0R
y
R914 C918
1
0V75_EN 5 Q905A 49.9K 2.2n/4/X7R/50V/K

24
2
IN 1% 50V
1
2N7002DW DNI Ref=0.6V
2
R990
4
1
49.9K/X
1% s
t
R964 C980
2
100K 100pF/X
b
1% 50V 0.8V_AGND
DNI
2
s
s
0.8V_AGND
0.8V_AGND
a o
DNI
NS907
1 DNI 2
NS908
1 DNI 2
g n
NS909
1 2
i
0.8V_AGND
G Do
Title
REG 0V75
l
LDO - 1V8/VPP/5V
it a
+3V3_BUS
+3V3_BUS 1206 1/2W 0805 Colay 0603 by diho 2019.8.28
1
R300 1 2 1R 1%
1
R301 1 2 1R 1% C308 C309
R302 1 2 UNNAMED_41_CAP_I71_A
1R 1% C300 C301 22uF/X 22u/6/X5R/6.3V/M
n
6.3V 6.3V
22uF/X 22u/6/X5R/6.3V/M 0805 Colay 0603 by diho 2019.8.27 DNI
2
6.3V 6.3V
DNI +1V8 +5V_VR +VPP
2
+3V3_BUS U301
VOUT = 0.8 x (1 + FBR3/FBR4)
U300 VOUT = 0.8 x (1 + FBR3/FBR4) 3 6
VIN VOUT
1
+3V3_BUS +5V_VR 3 6
e
VIN VOUT
1
VPP_FB C310 C311 C312
R332 1 2 0R 4 VDD FB 7
1
1V8_FB C302 C303 C304
R330 1 2 0R/X 4 VDD FB 7 R333 1 2 UNNAMED_41_CAP_I18_A
0R/X 10u/6/X5R/6.3V/M 10u/6/X5R/6.3V/M 0.1uF
1
2
C313 VPP_REFIN 6.3V 6.3V 16V
R331 1 2 UNNAMED_41_CAP_I23_A
0R 10u/6/X5R/6.3V/M 10u/6/X5R/6.3V/M 0.1uF DNI VPP_EN 24 2 EN NC 5
2
C305 1V8_REFIN 6.3V 6.3V 16V NS300 IN
INPUT_RAILS_UP 2 5 1uF
THMPAD
DNI 3,24 EN NC
2
IN 16V NS301
1uF VPP_PWRGD 1 8
THMPAD
24 POK GND
2
OUT
1
16V
1V8_PWRGD 1 8
d
24 POK GND
2
1
OUT
1
C314
GS7103-A
9
C306 FB_VPP+
GS7103-A 0.1uF/X
1
FB_1V8+ +3V3_BUS 10V
0.1uF/X
i
DNI
2
1
1
10V C315
+3V3_BUS DNI
1
C307 R311 1 DNI 2 0R/X R312 180pF
12.7K
1
R305 +5V_VR 50V
R304 1 DNI 2 0R/X 180pF FBR3 1%
2
12.7K
1
50V
f
+5V_VR FBR3 1% R313
2
10K/X
R306
2
10K/X
3
DNI
DNI
2
1
1
DNI R314
DNI 5 Q301B
2
33.2K/X
1
R307 MMDT3904-7/X R315
UNNAMED_41_NPN_I33_C
5 Q300B 1% FBR4
33.2K/X 10K
6
MMDT3904-7/X R308 DNI
UNNAMED_41_NPN_I50_C
1% FBR4 DNI 402 1%
4
10K
6
n
DNI UNNAMED_41_NPN_I33_B
DNI 402 1% 2 Q301A

2
2
UNNAMED_41_NPN_I50_B
2 MMDT3904-7/X
Q300A
1
MMDT3904-7/X
1
1
R316
1
10K/X
R309
10K/X DNI
2
DNI
2
e C o p y
y t C
5V REGULATOR
b t
+12V_BUS_B
a o
+5V_VESA
DNI 改footprint
1
+5V_VR
DNI NCP718AMTADJTBG
C326 R324
100K MU302
1uF 1% F300
25V DNI UNNAMED_41_NCP718_I199_OUT
6 IN OUT 1 MR325 1 DNI 2 0R 1 2
n
2
g
1
UNNAMED_41_NCP718_I199_NCADJ
C327 200mA
4 EN NC_ADJ 2 C425 24V
R327 1u/4/X5R/6.3V/K
10uF/X
10K 16V
2
16V
i
5
GND
NC R325 DNI
2
2
DNI
TH
0R/X
2
5V_EN 24
7
IN
HDMI: 50mA
1
1
DNI
G Do
R328
3.16K
1%
2
+12V_BUS_B
UNNAMED_41_RES_I203_A
MC78M05CDT/X
U302 改改改10GL6-017805-10R 消消消diho 20190831

1 IN OUT 3
1
GND
TAB
C431
10u/8/X5R/16V/K/X
2
16V
20%
2
Title
LDO 1V8_VPP_5V
l
(27) MECH AND THERM MANAGEMENT
it a
+3V3_BUS
+3V3_BUS
U1D
Differential Routing
1
1
AJ22 ALERT_L symbol4 DPLUS AP27 26 GPU_D+ C200
OUT
1
R237
100K IN
PROCHOT_L 26 AN27 PROCHOT_L 0.1uF
C201 R200 6.3V +3V3_BUS
OUT
CTF 23 AR29 CTF
2
0R
0.0022uF/X
D200
2
TS_A 50V U201

TP200 AH23 TS_A DMINUS AR27 26 GPU_D- A C
2
UNNAMED_19_NAVI14M4_I35_PWRBRKB OUT UNNAMED_19_74VC1G123_I154_AN
AK13 PWRBRKB PX_EN R201 1 2 0R 1 8 DNI
IN 3,23,24,26 A VCC
2 7 1N4148W/X
B Rext/Cext
n
UNNAMED_19_74VC1G123_I154_CLRN
23 TEMPIN PERST#_BUF R202

3,15,19,23,24,28 1 DNI 2 0R/X 3 CLR Cext 6 C202 1 210u/6/X5R/6.3V/M
6.3V R203 1 2 1M
IN Q_OUT
1
AP30 PUMPIN 4 5
UNNAMED_19_CAP_I28_A UNNAMED_19_CAP_I28_B
PUMPIN GND Q 23
C203 2 1 2 AL23 AR30 PUMPOUT +12V_BUS_B +12V_EXT_A
R262 0R/X TEMPIN TEMPIN PUMPOUT
390pF/X DST3904DJ-7/X Q200A SN74LVC1G123DCT
1
50V Differential Routing
FANIN AN29
23,26 FAN_IN_ASIC
2
IN
1
1 2 AK23 AP29 R205 R206
e
R263 0R/X TEMPINRETURN TEMPINRETURN FANOUT 23,28 FAN_OUT B200 B201
OUT 10K 10K/X
DNI 220R 220R/X
DNI
1
Navi14 Rev0.90
support for off-chip 23
2
R204 C4692
0R/X temperature sensing
2
12V_FAN
1
DNIi.e. Voltage Regulators, GDDR6 memory
1
+3V3_BUS 1n/4/X7R/50V/K
R215
2
10K
1
C204
1
DNI
d
R207 10uF
2
20K 16V
R256
2
2
1
10K/X
2
+3V3_BUS 1
UNNAMED_19_MOSP_I147_G
R208
i
2
Q204 0R/X
+3V3_BUS DNI
AO3415L
2
3
1
+3V3_BUS
DNI DNI
1
PERST#_BUF 1 21
R255 3,15,19,23,24,28 Q220 R209
f
IN DNI C255 20K
R210
10K/X MMBT3904T/X 2.61K/X
1
U202 0.1uF/X
DNI 16V 1% 26 PWM_B
OUT
2
2
DNI R211
7 OE1 VCC 8
2
10K
6
UNNAMED_19_NC7WB66K8X_I240_1B
3 OE2 1B 2
3
Q201A
FANOUT_T 26 1 1A 2B 6 R212 1 2 20K 2 MMDT3904-7
2
IN FAN_EN UNNAMED_19_NPN_I141_B CTF_OUT
FAN_OUT 23,28 5 2A GND 4 R213 1 2 UNNAMED_19_NPN_I131_C
0R 2 5 R214 1 2 2.2K 23 24 26
IN
A
n
Q203A
1
D201 MMDT3904-7 Q203B
NC7WB66K8X/X BAT54KFILM TO SHUTDOWN FAN IN BACO
4
MMDT3904-7
PX_EN R216 13,23,24,26 2 20K 2 Q202A C205
IN
C
MMDT3904-7
R261 1DNI 2 0R/X 0.1uF/X
6.3V
R258 1 2 0R TO PREVENT DNI
3
FAN RUNNING
FULL SPEED AT Q_OUT Q202B
1 2 5
o
23 R217 20K
MMDT3904-7
POWER UP
4
PERST#_BUF 3,15,19,23,24,28
IN
y
CRITICAL TEMPERATURE FAULT
C
+3V3_BUS
p
1
+3V3_BUS
R218
20K/X
2 DNI
1
e o
2
UNNAMED_19_PNP_I49_B
1 C211
Q206
MMBT3906/X 0.1uF
DNI 6.3V
3
2
3
t
CTF_FAN Q201B
R221 1 DNI 2 0R/X R222 1 2 2.2K 5 U200
MMDT3904-7
1
UNNAMED_19_PNP_I49_C
3 5
A VCC
1
1
UNNAMED_19_74AUP1G57_I199_Y
C206 1 4 MR236 1 223,260R FAN_IN_ASIC
OUT
4
B Y
R224 R225 100nF 6 2
20K/X 20K/X C GND
C
10V
DNI DNI
1
74AUP1G57GM
y
2
CTF_THERM C9348
IN 26
1n/4/NPO/50V/J
3
50V
DNI
2
CTF UNNAMED_19_RES_I32_B CTF_TRIP
R226 1 DNI 2 4.7K/X R227 1 DNI 2 47K/X 1 R236 1 DNI 2 0R/X
IN 23
1
Q208
MMBT3904/X
1
t
C207 DNI TO MAXIMIZE FAN OUTPUT +3V3_BUS +12V_BUS_B
D203
2
C A R228 DURING CTF TRIGGER
b
PERST#_BUF 3,15,19,23,24,28 0.01uF/X
IN 100K/X 10V
DNI DNI
2
1
BAT54KFILM/X +3V3_BUS
2
DNI
R229 R230
10K/X 10K
DNI
J200
1
o
2
2
R231 FAN_PWM
4
a
5.1K FAN_IN
HEADER IS 2MM
R232 1 2 1K 1% TACH 3
FANOUT_P
IT DOES NOT FOLLOW
3
2 2.54MM SPACING AS 4-PIN
1
R233 1 2 2.2K CTF_OUT R234 1 2 1K 1 Q209 1
24,26 OUT PWM FAN SPECIFICATION
MMBT3904 C208 R235 C209
3.83K
CTF BYPASS 1000pF/X 1% 10uF/X
2
JW/1*4/WH/2.0/VA/D
n
50V 16V
g
DNI DNI
2
FOR 4-WIRE FAN
i
G Do
23
移移pump connect和和和和和 by diho 2019.9.3
Differential Routing
23
改常用螺絲孔
BK
MOS SINK MOS SINK GPU SINK
MEC12
BOARD STIFFENER MH-C236D125-10
MEC26
COMMON
9 connected mounting pins
MEC32 MEC19 BOARD STIFFENER
MH-C236D125-10
BOARD STIFFENER BOARD STIFFENER
1
2
3
4
5
6
7
8
9
10
MH-C236D118-10 MH-C236D118-10 9 connected mounting pins COMMON

COMMON COMMON
9 connected mounting pins 9 connected mounting pins
1
2
3
4
5
6
7
8
9
10
MEC35
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
BOARD STIFFENER
MH-C236D125-10
9 connected mounting pins COMMON
GND
1
2
3
4
5
6
7
8
9
10
GND MEC23
GND GND BOARD STIFFENER
MH-C236D125-10
MEC17 MEC22
1
2
3
4
5
6
7
8
9
10
BOARD STIFFENER BOARD STIFFENER GND
MH-C236D118-10 MH-C236D118-10
COMMON COMMON
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GND
MEC24
BOARD STIFFENER
GND GND BKT1 MH-C236D125-10
SCREW201
BRACKET
1
2
3
4
5
6
7
8
9
10
MEC18 MEC30 SCREW
DUAL
MH-C236D118-10 MH-C236D118-10
COMMON COMMON 7020001700G
802005610AG
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GND
MEC25
BOARD STIFFENER
MH-C236D125-10
COMMON
GND GND 9 connected mounting pins
MEC31 MEC33
1
2
3
4
5
6
7
8
9
10
MH-C236D118-10 MH-C236D118-10
COMMON COMMON
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GND
GND GND
Title
MECHNICAL
Custom
GV-R55XTOC-4GD 1.0
l
(27) POWER MANAGEMENT
it a
COLAY改改改和消消改 by diho 20190832
+12V_BUS
+12V_BUS_B
L1002
1 2
0.47uH/X
1
C102
L1903 0.22uH/40A/S/X
10uF
16V
2
L1904 1uH/11A/S +3V3_BUS
SMD_078X072 COMMON
1
BUS 12V AND AUX A POWER UP SEQ +3V3_BUS R1004
10K POWER ENABLE CONTROL
n
To Enable 1V8
2
1
+12V_EXT +12V_BUS_B
COLAY改改改和消消改 by diho 20190831 3,22 INPUT_RAILS_UP
R1009 OUT
5.11K
L1902 0.47uH/28A/S/X ADD by diho 1%
3
+12V_EXT_A +12V_BUS_B
SMD_12X8 COMMON
2
J1000 12V_UP
R1011 1
L1000 11.3K Q1001
1
1 1 2 MMBT3904 +3V3_BUS
+12V 1%
e
1
1
2 C1000
+12V 0.47uH/X
2
12V_BUS_UP +3V3_BUS
+12V 3 C1002
L1900 2 Q1000A 0.1uF PLACE CLOSE
RS1014 1V8_PWRGD 22,24R1021 1 2
21,24 0R 0V75_EN
10K IN OUT
1
MMDT3904-7 16V
47pF TO ITS CTLR
2
1
3
C1003 50V C9353 C9354 C9355 +12V_EXT_A RS1012
0.36uH/30A/S C9352
2
2.32K
1
R1015 +3V3_BUS +12V_BUS_B
10uF 0.1u/4/X7R/16V/K 10u/8/X5R/16V/K10u/8/X5R/16V/K 10u/8/X5R/16V/K/X 1% 5 Q1028B
1K
6
16V 16V 16V 16V R1005
1% MMDT3904-7
2
10K
1
GND 4 2 Q1028A
1
GND
6 L1901 0.22uH/40A/S/X R1018 MMDT3904-7
+3V3_BUS
+1V8 DNI DNI
To Enable 0V75
2
1
11.3K R1006 MR1006 0V75_EN
d
21,24
1
1% 10K/X 100K/X OUT
3
RS1013
2
SENSE_GND 12V_EXTA_UP 1K
3
Sense 5 24 5 Q1000B 1% DNI DNI
2
6P_SENSE 0V75_RAIL_EN#
1 R1001 2 MMDT3904-7 MR1010 R1010 R1008 1 DNI 2 5.1K/X 5 Q1004B
2
10K 10K/X
1
DNI MMDT3904-7/X
APW/2*3/BK/OC/P/4.2/RA/SN/REV/X 0R/X
4
i
6
+3V3_BUS
DNI R1020 DNI DNI
4
1 MR1001 2 1K 1V8_PWRGD 22,24 R1012 1 2 5.1K/X 2 Q1004A
1% IN
1
MMDT3904-7/X
0R DNI
1
MJ1000 C1001
C1
1
+12V
1 47pF 1uF/X R1013
50V CTF_OUT_B 6.3V 10K
f
+12V 2 R1038 1 DNI 2 0R/X DNI
2
+12V
3 R1039 1 2 0R
2
VDDGFX_SOC_EN
SENSE_GND 15,24 OUT
24
3
To Enable VDDCR_GFX
8P_SENSE
INTERNAL CTF LATCH - VDD_18 REQUIRED R1016 1 2 5.1K 5 Q1005B
and VDDCR_SOC
1
5 +12V_BUS_B MMDT3904-7
GND
GFX_SOC_VPP_RAIL_EN#
3
7 +3V3_BUS C1038
GND
4
GND 8 CTF_OUT R1040
23,26 1 2 2.2K 1 Q1009 1uF/X
IN
n
MMBT3904 6.3V +3V3_BUS
DNI
2
1
1
DNI
SENSE_1 6 PLACE CLOSE
2
+3V3_BUS
SENSE_2
4 T O IT S CT LR R1019 MR1019
10K/X 100K
1
LED_VCC
R1024
APW/2*4/BK/OC/P/4.2/RA/SN/REV
2
10K
1
R1022 RS1006 1 DNI 2 5.1K/X To Enable VPP
2
1K
1
R1144 VPP_EN
o
22,24
MVDD_VDDCI_EN OUT
6
5.1K/4/1/X C1039 R1017 1 DNI 2 1K/X
19,24
2
EXT8P_A_Detect OUT
1
C4556 0.1u/4/X7R/16V/K/X 0V75_PWRGD 21,24 R1025 1 2 5.1K 2 Q1005A 1uF/X DNI
28 IN
1
OUT 6.3V
1V8_PWRGD RS1008
22,24 1 2 0R/X MMDT3904-7
DNI 5 Q1006B
C1037 VPP_PG to Enable
IN
2
DNI
C1004 MMDT3904-7/X 1uF/X MVDD/VDDCI
1
+12V_EXT_A 6.3V
A 1uF/X DNI
2
放放J1000後正 R377 R379 6.3V
DNI
2
+3V3_BUS
LED1
GND
LED/W/6/S/X
9.09K/4/1/X 1K/4/1/X
1
C 3
D Q602 0V75_PWRGD R1028 1 2 0R VPP_EN RS1016
IN 21,24 22,24 OUT 10K
C
EXT8P_A_Detect_LED 1G 1G1D1S
28
2
OUT
S 2 HW default power up sequence VPP_PWRGD MR1017 1 2 0R
p
22
IN
GND
3V3_AUX
+12V_BUS_B
e o
1
RS1025
100K
5V
2
t
+12V_EXT_A +VDDGFX_SOURCE1 +12V_EXT_A +MVDD_SOURCE +12V_EXT_A +VDDSOC_SOURCE
+12V_EXT_A +VDDCI_SOURCE
RS1033 1 DNI 222 0R 5V_EN
1V8 OUT
DNI DNI DNI
3
R1099 1 2 0R/X DNI R1090 1 2 0R R1089 1 2 0R/X
1 2 R1092 1 2 0R/X R1091 1 2 0R R1088 1 2 0R/X 0V75 RS1018 1 2 5.1K 1
C
R1098 0R/X Q1029
R1093 1 2 0R/X MMBT3904
DNI DNI DNI
VDDGFX_PH1 OPTIONAL1 DNI +MVDD SOURCE OPTIONAL1 VDDSOC OPTIONAL1
2
y
+VDDCI SOURCE OPTIONAL1
VDDCR_GFX
IN BACO MODE(BAMACO_EN=0,PX_EN=1)
+12V_BUS_B +VDDGFX_SOURCE1 +12V_BUS_B +MVDD_SOURCE +12V_BUS_B +VDDSOC_SOURCE TURN OFF VDDCR_GFX, VDDCR_SOC, VDDCI, VPP and MVDD
+12V_BUS_B +VDDCI_SOURCE VDDCR_SOC
MR1099 1 2 0R MR1090 1 2 0R/X MR10891 2 0R IN BAMACO MODE(BAMACO_EN=1,PX_EN=1)
VPP_EN
MR1098 1 2 0R MR1092 1 2 0R MR1091 1 2 0R/X MR10881 2 0R TURN OFF VDDCR_GFX, VDDCR_SOC, VDDCI(turn off by SVI2)
22,24
t
OUT
MR1093 1 2 0R
1
VPP
b
VDDGFX_PH1 OPTIONAL2 +MVDD SOURCE OPTIONAL2 VDDSOC OPTIONAL2
3
RS1040
+VDDCI SOURCE OPTIONAL2 PX_EN_BAMACO_EN 0/X
PX_EN R1029
3,23,26 1 2 5.1K RS1021 1 2 5.1K 5 Q1007B DNI
MVDD IN MMDT3904-7
2
1
4
6
3
R1031
VDDCI BAMACO_EN R1030 1 2 10K/X 2 10K 1
o
4,25,26 Q1007A Q1034
IN
1
MMDT3904-7 MMBT3904/X
2
C1006
2
+0V75 FB MVDD BOOT 1uF/X
6.3V
0V75_FB 21 DNI
2
IN
FB_MVDD_VR 19
IN VDDGFX_SOC_EN
15,24 OUT
1
+12V_BUS_B
1
3
MVDD_VDDCI_EN
R1050
12K R762 RN700B
PX_EN_GFX_SOC_EN# 19,24 OUT
1 2 5
n
R1033 5.1K Q1008B
1% 100R/X
1
806R MMDT3904-7
g
0.1% +5V_VR
2
0.1%
1
DNI RS1039 RS1041
0V75_SENSE_N 21
IN
2
4
10K/X 0R/X
R1034 DNI
10K
1
FB_MVDD_VSS_VR 19
IN
2
RS1037
2
51K/X
3
1%
6
5 Q1033B
2
2 Q1033A
MMDT3904-7/X
VPP_EN_MOS_GND
MMDT3904-7/X
4
1
1
RS1038
10K/X
1
G Do
1%
6
R1036
2
0R
PERST#_BUF R1035
3,15,19,23,28
1 2 10K/X 1% 2 Q1008A
IN MMDT3904-7
2
1
1
R1037
10K/X
1% Make sure 5V power on before Enable is active when w/ EN 5V VR
2
Add MOS VRHOT CIRCUIT
+12V_BUS_B
VDDC Thermal Protection

PWM_B PWM_B
23,24
OUT
Q6225 Q6226 Q6227
C6223
R6330 MMBT3904/SOT23/200m A/30 MMBT3904/SOT23/200m A/30 MMBT3904/SOT23/200m A/30 0.1u/4/X7R/16V/K
3
4.7K/4/1 3 2 3 2 3 2 1K/4/1
+5V_VR
R6273 1 Q6221
MMBT3904/SOT23/200m A/30
R6282 R6283 R6329
8
R5352 R5349 R5353

1
2
R6383 3 +3V3_BUS
U4822A
0/4 + 1
5%
0402
11K/4/1 100K/1/4/S 100K/1/4/S 100K/1/4/S
2 VDDC Thermal Protection
0402
11K/4/1 0402
11K/4/1 0402
-
COMMON
R6276
4
LM358DR2G/SO8 1K/X
+5V_VR
R10864
R10863 1K/4/1/x C6222 LM358DR2G/SO8
VDDGFX_SOC_EN
4
1K/4/1/x 0.1u/4/X7R/16V/K R6277 0/4 IN 14,21
3
6 - 1K/4/1
7 R6266 1 Q6220
PTC 5 + MMBT3904/SOT23/200m A/30
VREF_PTC
2
C6219
8
0.1u/4/X7R/16V/K U4822B
R6263
1K/4/1
R6275
1K/X
R6258
1K/4/1
Near
R6800 0/4
Title
POWER MANAGEMENT
Size Docum ent Num ber Rev
VDDC
Cus tom GV-R55XTOC-4GD 1.0

Date: Tues day, Decem ber 10, 2019 Sheet 24 of 28
each
high
side
MOS
l
(28) SVI2
it a
+1V8 +1V8_SVI2_MACO
+VPP +1V8
VDDCR_GFX/SOC VOLTAGE CONTROL Overlap pad
R1051 1 2 0R
1
NR1051 1 DNI 2 0R/X
R1053 R1054
10K 10K/X
DNI VPP can be applied only if VPP power on is before MVDD/VDDCI Enable
2
SVC_GFX_SOC 4,15
IN
SVD_GFX_SOC 4,15
BI
n
1
1
SVI2 BOOT UP VOLTAGE (VDDGFX/VDDC)
R1057 R1058
Resistor could be placed inside the analog switch.
10K/X 10K
SVC SVD
VOLTAGE DNI R1059 1 DNI 2 0R
2
e
0 0 1.1V
+3V3_BUS +1V8_SVI2_MACO
0 1 1.0V
1 0 0.9V
1 1 0.8V
1
C1019 U1001
R1060
0.1uF/X 8 7 10K/X
d
VCC OE1
16V
SVT_MVDD_VDDCI 4 2 1B OE2 3
2
IN
6 2B 1A 1 SVT_MVDD_VDDCI_VR
19 OUT
4 5
i
GND 2A
NC7WB66K8X/X
f
Isolation for SVT when 1.8V to GPU is off during BOMACO
n
Resistor could be placed inside the analog switch.
R1061 1 DNI 2 0R
R1062 1 DNI 2 0R
+1V8_SVI2_MACO
+3V3_BUS
o
1
1
MVDDC/VDDCI_MEM VOLTAGE CONTROL
y
C1020 U1002
R1063 R1064
0.1uF/X 8 7 10K 10K/X
VCC OE1
16V
SVC_MVDD_VDDCI 4 2 1B OE2 3
2
IN
SVD_MVDD_VDDCI 4 6 2B 1A 1 SVC_MVDD_VDDCI_VR
19
IN OUT
C
4 GND 2A 5 SVD_MVDD_VDDCI_VR
19 BI
p
+3V3_BUS R1065 R1066
100R/X 10K/4 NC7WB66K8X/X
DNI
2
1
+3V3_BUS
6
3
R1067
10K
Q1012A
o
2
5 SVI2 BOOT UP VOLTAGE (VDDCI_MEM/MVDD)
e
2N7002DW
1
Q1012B
2
2N7002DW
R1068
SVC SVD
VOLTAGE
4
10K/X
6
t
T=~40us 0 0 1.1V
2
Q1011B MACO_EN#
MVDD_VDDCI_PWROK 19 R1070 1 2 UNNAMED_20_CAP_I9_A
5.1K/X 1% 2 0 1 1.0V
IN 2N7002DW/X
1
3
1 0 0.9V
1
C1021 BAMACO_EN R1071 4,24,261 2 0R/X 5 Q1011A

1 1 0.8V
1
IN
1
C
R1072 2N7002DW/X
0.01uF/X
10K/X
1
25V C1022
DNI
y
2
4
R1073 22pF/X SVC/SVD need to pull high during MACO mode
2
10K/X 50V
DNI
2
2
b t
R1074 1 2 0R/X
1
DNI
1 Q1015
R1076
2N7002E/X 0R/X
o 1
2
a
R1077
100K/X
2
i g
G Do n
Title
SVI2
l
(29) DEBUG CIRCUIT
it a
+1V8
+1V8
1
DEBUG
1
R4000
DEBUG DEBUG DEBUG DEBUG 1K/X
JTAG
1
C4000 R4001 R4002 R4003 R4004 R4005 R4006
1K/X 1K/X 1K/X 1K/X 1K/X 1K/X
R4007 R4008 R4009 R4010 0.1uF/X DNI DNI DNI DEBUG
2
10K 10K 10K 10K 6.3V
R4011 1 2 33R/X
2
2
2
n
U1C
BP_0 GPU_TCK J4001 DEBUG
AJ6 BP_0 symbol3 TCK J2 2 1
GPU_TMS
TMS G2 4 3
BP_1 GPU_TDI
AK5 BP_1 TDI G3 6 5
GPU_TDO
TDO F1 8 7
BP_2 GPU_TRST_L HDT_TRST_L
AL4 J1 10 9
e
BP_2 TRST_L
12 11
BP_3
AL5 BP_3 DEBUG 14 13
GPU_DBREQ_L HDT_DBREQ_L
DBREQ_L M4 R4016 1 2 33R/X 16 15
DIECRACKMON GPU_TESTEN
R4017 1 2 0R AL13 DIECRACKMON TESTEN F2 18 17
20 19
1
Navi14 Rev0.90
DEBUG DEBUG DEBUG HEADER_2X10/X
d
C4001 R4018 C4002
1K/X
0.01uF/X 0.01uF/X
6.3V 16V
2
移移SW4000 by diho 2019.9.3
fi
SWITCHES
Default: ON
CTF_OUT 23,24,26
IN
BYPASS CTF
n
Default: ON
PWM_B 23
IN
MAXIMIZE FAN
Co p y
+3V3_BUS
VTMM J4007 DEBUG
1 2
GFX_VTMM FB_VTMM
FB_VDDCR_GFX 6,15R4031 1 DEBUG 2 0R/X 3 4 R4033 16,15
DEBUG 2 0R/X FB_VSS_A
IN SOC_VTMM IN
o
FB_VDDCR_SOC 6,15R4032 1 DEBUG 2 0R/X 5 6
e
IN SCL_VTMM SDA_VTMM
REG_SCL R4030
4,15,18,19 1 DEBUG 2 0R/X 7 8 R4035 14,15,18,19
DEBUG 2 0R/X REG_SDA
IN IN
9 10
SOCKET_2X5/X
THERMAL SENSOR FOR GDDR6
b y t
+3V3_BUS
t C
1
o
I2C ADDRESS(8bit): 0X90
1
a
I2C ADDRESS(7bit): 0X48 C4005
0.1uF/X
R4065 16V
4.7K/X DEBUG
2
DEBUG
5
U4000 LMSMCLK R4083 1 DEBUG 2 0R/X

IN 3
2
V+
DEBUG
DDCVGACLK R4070
4,26,28 1 DEBUG 2 0R/X 1 SCL ADD0 4 R4078 1 DEBUG 2 0R/X LMSMDATA 3 R4085 1 DEBUG 2 0R/X
IN IN
n
U4001 +3V3_BUS
g
LMS_MCLK LM_TCRIT#
DDCVGACLK 4,26,28 R4071 1 DEBUG 2 100R/X 10 SMBCLK DEBUG TCRIT 1 R4044 1 23 DNI 2 0R/X CTF_THERM
UNNAMED_22_RES_I473_B IN OUT
DDCVGADATA R4080
4,26,28 1 DEBUG 2 0R/X 6 SDA ALERT 3
BI UNNAMED_22_RES_I483_A LMS_MDATA
R4081 1 DEBUG 2 0R/X PROCHOT_L DDCVGADATA R4076 1 DEBUG 2 100R/X 9 2
GND
23,26 OUT IN 4,26,28 SMBDAT VDD
1
TMP102A/X FAN_IN_ASIC 23 8 TACH D+ 3 23 GPU_D+
IN IN
2
C4003
TH_ALERTB
PROCHOT_L 23,26 R4046 1 DNI 2 0R/X 7 ALERT D- 4 23 GPU_D- 1uF/X
OUT IN 6.3V
DEBUG
2
G Do
LM_PWM
6 GND PWN 5 R4047 23 1 DNI 2 33R/XFANOUT_T
OUT
+3V3_BUS
THMPAD 11
DEBUG TACH CONNECTION IS FOR TESTING +3V3_BUS
R40391 2 10K/X AND RPM MEASUREMENT ONLY LM96163CISD/X
8bit address: 0x98
7-BIT I2C ADDRESS: 0x4c R4072 1 DNI 2 2.61K/X 1%
LM96163 FOR BACKUP THERMAL CONTROL
移移AMD LED lights by diho 2019.9.3
LED LIGHTS
CTF_OUT 23,24,26
IN
LED RED "ON" INDICATES CTF FAULT
PX_EN 3,23,24
IN
LED YELLOW "ON" INDICATES FANOFF (BACO) MODE
BAMACO_EN 4,24,25
IN
LED YELLOW "ON" INDICATES BAMACO STATE
+3V3_BUS
1
DEBUG
R4022
10K
1%
2
GPIO4_GFX_PCC# 4,15,18
IN
LED RED "ON" INDICATES PCC triggerred
Title
DEBUG CIRCUITS
Custom
GV-R55XTOC-4GD 1.0
it a l
n
1.00 00A 08/09/2018 Initial s chem atic
12/28/2018 change all 4172010501G parts to 4172010500G
1.00 00B 04/16/2019 ADD D1752 D1802 D1852 D1952
e
ADD R795 AND CHANGE MVDD LOCAL SENSE PONIT
ADD R1092 R1093 MR1092 MR1093 and reas s ign gfx phas e1-3 input s ource
ADD R4653 R4654 R4655 C4689
Change 701: 0.33uH/5260116000G R749: 909R/3160909000G NR704:30K/3160300200G R743: 18K/3160180200G C747:470pF/4170047100G C748:220pF/4 170022100G
n fi d
Co p y
y te C o
g a b n o t
i
G Do
Title
REVISION HISTORY
l
LED 12V M_3.3V
+12V_BUS_B
LED_VCC
ADD Page35: LED Control MCU circuit by diho 20190619 +12V_EXT_A +3.3V_BUS
R5030 220/8/3A/S/X
it a
1
0.400 R5031 220/8/3A/S/X CR3 CON1
+12V_BUS_B +3.3V_BUS 12V
LED_VCC M_3.3V R4999 R5000 20MIL
11.3K 1K/4 R5002 0.1u/4/X7R/16V/K/X 5
1% 1% 5
3
1 2 INPUT_PEX8P_A_DT1_R C4525 C4526 4
2
12V_EXTA_UP_DT Q4024 C4518 10uF/X 10u/8/X5R/16V/K C4527 C4528 C4529 C4530 4
1 SWCLK 3
R4990 390/6/X ADC_Vref R4989 0/6 0.1u/4/X7R/16V/K 16V 16V 0.1u/4/X7R/16V/K 10u/8/X5R/16V/K 4.7uF/X 0.1u/4/X7R/16V/K 3
MMBT3904 1K/4
SWDIO 2
20% 10% 2
1
C4514 16V 16V 6.3V 16V
1%
X5R X5R
Reset 1
2
R4991 1.5K/6/1/X R4992 10u/6/X5R/6.3V/M 10% 10% 20% 10% 1
INT, 27KHz R5005 X7R 603 805 X7R X5R X7R
3.4K/4/1/X 1K
C4515 C4516 402 COMMON COMMON 402 603 402 JW/1*5/WH/2.0/RA/D/X
1%
ADD by diho 20191008 COMMON COMMON COMMON COMMON
2
1u/4/X5R/6.3V/K/X SW-DP
U4503 10u/6/X5R/6.3V/M/X
n
2
GND LED_VCC GND CON1 排針不上件
1
0 SOT23 +3.3V_BUS +3V3_BUS
GND
SOT23
APL431L/SOT23/150m A/X
COMMON FAN_OUT
INPUT_PEX8P_A_DT1_R
R4993
XTIN XTOUT C4543
e
2.37K/4/1/X OUT 23 R5080 R5081 10u/8/X5R/16V/K
R10870 0/6 0/8/X 0/8/X
R5032
1M/4/X
12M/20p/30ppm/3.2*2.5/80/S/X
d
Y3 GND GND GND GND
ADC_Vref
XTAL_4PIN_SMD-E3SB270000F18S3B Windforce_LED
i
CR2 4-pin GPU fans ink
CR1 0/4/X R4995
U4504 GND J4105 1PWM
f
10p/4/NPO/50V/J/X 10p/4/NPO/50V/J/X INS16796513 TACH +3.3V_BUS
R4994 2
MALE
HT32F52241/LQFP48/S/X GND
2.0MM 3 12V R5087 0/8/X
VERTICAL 4GND
GPU R5091 0/8/X R5092
COMMON
10K/4/X
48
47
46
45
44
43
42
41
40
39
38
37
C4517 3
D
n
Q4036
PB8
PB7
PB6
PC3
PC2
PC1
PS5
PS4
PB3
PB2
VSSA
VDDA
0.1u/4/X7R/16V/K/X
MCU_R R4998 0/4/X 1 36 1G1D1S G1 R5096 0/4 MCU_R
PA0/ADC_INT2/GT_CH0 VSS_2 GND
2 S
FAN Stop LED MCU_G R5001 0/4/X 2
PA1/ADC_INT3/GT_CH1 VDD_2
35
M_3.3V
+3.3V_BUS R5101
100K/4/X
C4546
o
MCU_B R5003 0/4/X 3 34 R5102 0/8/X 0.1u/4/X7R/16V/K/X
PA2/ADC_INT4/GT_CH2 PB1
R5106
EXT8P_A_Detect R5004 0/4/X 4 33 R5105 0/8/X 10K/4/X
24 PA3/ADC_INT5/GT_CH3 PB0
y
OUT
12V Sense 3
5 32 Q4040 D
GND GND
PA4/ADC_INT6/GT_CH0 PA15
0/4/X R5007 OUT INT, 200Hz
6 31 FAN_IN_ASIC 1G1D1S G1 R5112 0/4 MCU_G
PA5/ADC_INT7/GT_CH1 PA14
C
C4519 2 S
GPIO Windforce_LED R5009 0/4/X 7 30 R5010 0/4/X SWDIO 1n/4/X7R/50V/K/X +3.3V_BUS R5114 C4550
28 PA6/ADC_INT8/GT_CH2 SWDIO/PA13
p
OUT
100K/4/X
FAN_STOP_LED R5011 0/4/X 8 29 R5012 0/4/X SWCLK 0.1u/4/X7R/16V/K/X
28 OUT PA7/ADC_INT9/GT_CH3 SWCLK/PA12
R5119
9 28 R5120 0/8/X 3 10K/4/X
PC4/ADC_INT10 PA11 D
Q4042
EXT8P_A_Detect_LED R5013 0/4/X
o
10 27 GND R5122 0/8/X GND GND
e
24 OUT PC5/ADC_INT11 PA10 MCU_B
GPIO 1G1D1S G1 R5124 0/4
XTALOUT/PB14
X32KOUT/PB11
RTCOUT/PB12
XTALIN/PB13
X32KIN/PB10
11 26 2 S
PC6 PA9_BOOT
R5127 C4552
+3.3V_BUS
t
VDD_1
12 25 100K/4/X
VSS_1
CLDO
nRST
PB15
PC7 PA8
PC0
PB9
0.1u/4/X7R/16V/K/X
R5129
13
14
15
16
17
18
19
20
21
22
23
24
10K/4/X
C
3
Q4044 D 5%
GND GND
y
402
0/4/X R5018 4,26 DDCVGADATA COMMON
BI
XTOUT
C4520 C4521 0/4/X R5019 4,26 DDCVGACLK MCU Slave 1G1D1S G1 Windforce_LED
OUT 28
XTIN
OUT
Reset
2 S
1u/4/X5R/6.3V/K/X 1u/4/X5R/6.3V/K/X GND
C4555
t
0.1u/4/X7R/16V/K/X
b
M_3.3V LED_VCC
GND C4523 R5027 0/4 R5028 3,15,19,23,24
100/4/X PERST#_BUF
IN
GND GND
o
1u/4/X5R/6.3V/K/X
a
C4524 R5029 C4542
R5078 R5079
0.01u/4/X7R/25V/K/X 100K/4 10u/8/X5R/16V/K/X
0/8/X 0/8/X
GND 1% 5%
603 603
DNI COMMON
g n
GND M_3.3V
M_3.3V M_3.3V GND
i
COLAY HT23F52220 for costdown by diho.su 20190902 J4104
4-pin GPU fans ink
1PWM
R10853 R10854 INS16798172 TACH
2
G Do
MALE +3.3V_BUS
10K/4/1/x 10K/4/1 2.0MM 3 12V
VERTICAL 4GND R5089 0/8/X
GPU
COMMON
R5094 0/8/X R5090
10K/4/X
U4022 3
D
DDCVGACLK R10788 0/4 1 24 Q4035
PB7 PB4
MCU Slave DDCVGADATA R10784 0/4 2 23 0/4 R10860 EXT8P_A_Detect_LED
PB8 PB3
3 22 0/4 R10861 FAN_STOP_LED M_3.3V
1G1D1S G1 R5098 0/4/X MCU_R
MCU_G VDDA PB2
R10777 0/4 4 21 0/4 R10862 FAN_IN_ASIC 2 S
MCU_B PA0 PB1 INPUT_PEX8P_A_DT1_R +3.3V_BUS
R10782 0/4 5 20 R5100 C4545
MCU_R PA1 PB0
R10776 0/4 6 19 0/4 R10781 SWDIO 100K/4/X
Windforce_LED PA2 SWDIO
R10783 0/4 7 18 0/4 R10792 SWCLK R5103 0/8/X 0.1u/4/X7R/16V/K/X
EXT8P_A_Detect PA3 SWCLK
R10858 0/4 8 17 R10856 C9345 R5108
M_3.3V PA4 PA9_BOOT
9 16 10K/4/1/x C2301 R5107 0/8/X 10K/4/X
PA5 XTALOUT
C9346 10 15 1u/4/X5R/6.3V/K 3
CLD0 XTALIN D
11 14 R10855 10u/6/X5R/6.3V/M Q4039 GND GND
VDD PB12
0.1u/4/X7R/16V/K C2336 12 13 Reset 10K/4/1
VSS nRST 1G1D1S G1 MCU_G
R5113 0/4/X
0.1u/4/X7R/16V/K C9342 C9343 2 S
+3.3V_BUS
HT32F52220/24SSOP/S/X R5116 C4549
GND 1u/4/X5R/6.3V/K 1u/4/X5R/6.3V/K GND 100K/4/X
0.1u/4/X7R/16V/K/X
GND GND R5118
GND GND R5117 0/8/X 3 10K/4/X
Q4041 D
GND
Reset
R5123 0/8/X GND GND

1G1D1S G1 R5125 0/4/X MCU_B
2 S
R5126 C4551
+3.3V_BUS 100K/4/X
0.1u/4/X7R/16V/K/X
R5128
10K/4/X
3
D 5%
C9322 Q4045
402
GND GND
0.01u/4/X7R/50V/K COMMON
1G1D1S G1 FAN_STOP_LED
28 OUT
2 S
C4554
GND 0.1u/4/X7R/16V/K/X
GND GND
Title
MCU_LED

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it a l

1 TOC 26 DEBUG CIRCUITS

6 NAVI14 - POWER and GND

11 GDDR6 x16 - MEM CH CD

15 REG VDDGFX/SOC CONTL

19 REG VDDCI/MVDD CNTL

23 MECHANICAL AND THERMAL

From +12V_BUS TMDPE

From +3.3V Direct:

and Control Circuit NAVI14 D332 110W TGP

+3V3_BUS DNI DO NOT

These termination should be as short as possible, never exceed 500mil

B77 A44 PERN6 C43 1 20.22uF 6.3V AH20 PCIE_TX6N

A5 JTAG2 PERp8 A52

PERn9 A57 device to internal bump.

DGPU_PWR_EN_PCIE A19 A76

x16 GEN4 PCIe

R53 1 DNI 2 10K/X

1: Audio for DisplayPort only

1: Enable the external BIOS ROM device

改改改改by diho 2019..8.27

R10867 R10865 R10866 5

XTRIG* are for debug purpose

symbol18 symbol19 symbol15

10uF - 0402 x81 10uF 0402 x5

DQA0_[0..15] 10 symbol11 10 DQA1_[0..15] DQB0_[0..15] 10 symbol12 10 DQB1_[0..15]

CAA0_[9..0] 8 8 CAA1_[9..0] CAB0_[9..0] 8 8 CAB1_[9..0]

CKEA0 G10 M10 8 CKEB0 G10 M108

C2124 C2125 C2126 C2127 C2128

10uF 1uF 1uF 1uF 1uF

CAC1_[9..0] 9 9 CAC0_[9..0] CAD1_[9..0] 9 9 CAD0_[9..0]

CKEC1 G10 M10 9 CKED1 G10 M109

HDT_TCK +MVDD +MVDD

DNI DNI DNI DNI DNI

C2324 C2325 C2326 C2327 C2328

Navi14 Rev0.90 2N7002DW +12V_BUS_B

10K 10K 2.2K 2.2K DPB_GND

47pF/X 47pF/X +3V3_BUS

ESD8004/X ESD8004/X ESD8004/X ESD8004/X

OPTIONAL ESD PROTECTION DIODES

0603 0.22uF 0603 1 BOOT HI_GATE 10

16V 16V DNI

C609 C610 C611 C612 C613 LFPAK D 5

4 9 R604 SMD 11.5*10.3*4.2mm DCR=0.5 ± 7%

C634 C635 R606 2 2 C636

R781 C781 19 1 2 1 2 C746

1 TSR702 2 R758 R759

VDDCI_CSSUM R715 VDDCI_ISENP1

20 1 R789 2 FB_MVDD_VSS_VR 1 2 47K/4/1

20 1% DNI OUT VDDCI_CSCOMP

1000pF 10uF 10uF 10uF 10uF 10uF 10uF

4G Isat=31A Irms=16A, 0805 Colay 0603 by diho 2019.8.28

10K 1% SMD 11.5*10.6*4 DCR=1.05m+/-7% 2 1

C988 0.0056uF 16V

0V75_EN 5 Q905A 49.9K 2.2n/4/X7R/50V/K

2N7002DW DNI Ref=0.6V

+3V3_BUS 1206 1/2W 0805 Colay 0603 by diho 2019.8.28

1% FBR4 DNI 402 1%

DNI 402 1% 2 Q301A

U302 改改改10GL6-017805-10R 消消消diho 20190831

TS_A 50V U201

23 TEMPIN PERST#_BUF R202

C A R228 DURING CTF TRIGGER

4 9 R604 SMD 11.510.34.2mm DCR=0.5 ± 7%

10K 1% SMD 11.510.64 DCR=1.05m+/-7% 2 1