MICROPROCESSOR SYSTEMS NOTES - Copy-1

NATIONAL YOUTH SERVICE ENGINEERING INSTITUTE
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING
MODULE III
MICROPROCESSOR SYSTEMS
STUDY NOTES
© N. Koech 2021 Microprocessor Systems 1st Ed.

MICROPROCESSOR ARCHITECTURE
A microprocessor is a semiconductor IC manufactured by large-scale integration technique.
It is a program controlled device which fetches, decodes and execute instructions.
It consists of the ALU, register arrays and control unit on a single chip.
Microprocessor Manufactures:
Intel Zilog Toshiba Rockwell etc.
Motorola Fairchild Signetics
Difference between microprocessor, microcomputer and microcontroller.
Microprocessor is a CPU on a single chip. E.g. Intel 8085.
Microcomputer is designed using a microprocessor as its CPU, along with input devices, output
devices and memory.
Microcontroller is designed to include all the features found in a microprocessor along with
memory, I/O signal lines on a single chip using VLSI technology.
Classification of microprocessors
Microprocessors are specified by its ‘word size’, (the size of its data bus). E.g. 4-bit, 8-bit etc.
4-bit Microprocessors - 1st generation
Intel 4004 Fairchild PPS-25
Intel 4040 Rockwell PPS-4
8-bit Microprocessors - 2nd generation
Intel 8008 Intel 8085 Rockwell PPS-8
Intel 8080 Motorola M6800 Zilog Z-80
Characteristics of 8-bit microprocessors
Large chip size.  Ability to address more I/O ports.
40-pins  More powerful Instruction set
More number of on-chip decoded  Faster operation
timing signals.  Better interrupt handling capabilities.
 Ability to address larger memory
space.
16-bit Microprocessors - 3rd generation
Intel 8086 Intel 8088 Intel 80186 Intel 80286

Motorola 68000 Motorola 68010 Zilog z-8000 Toshiba TLC-12
Characteristics of 16-bit microprocessors
 40/48/64 pins
 High speed and very strong processing capability
 Easier to program.
 Allow for dynamically re-locatable programs
 Size of internal registers were 8/16/32 bits
 These microprocessors had the multiply/divide/ arithmetic hardware
 Physical memory space was from 1 to 16MB.
 Flexible I/O port addresses
 More powerful interrupt and hardware capabilities
32-bit Microprocessors - 4th generation
Intel 80386 Motorola MC 88100 Motorola M-68030
Intel 80486 Motorola M-68020
Advantages of microprocessor based systems.
 Simplifies system design.
 Reduces development time, cost and size.
 Flexible in operation.
Microprocessor Architecture
A microprocessor consists of the following basic units/functional blocks:
i. Arithmetic Logic Unit (ALU) subsystem
ii. Memory subsystem
iii. Input/output subsystem
iv. Control unit
Schematic arrangement of a microprocessor
Control unit
Register file Control bus
ALU
Data bus

Arithmetic and Logic Unit (ALU)
 It perform integer arithmetic and logic operation.
 Arithmetic operations include: addition and subtraction.
 Logic operations include: AND, OR, NAND, NOR, XOR
Memory sub-system
Buffer Register – It interfaces the microprocessor with its memory system. It consists two
registers:
Memory Address Register (MAR) - It hold the memory address of the data or instruction to be
accessed.
Memory Data Register (MDR) – It stores all data written to and read from memory.
Block diagram of a memory sub-system
LM Memory Address CP
Register (MAR) 88 88 LP
CLK
Program Counter CLK
(PC) EP
88
CLR
W/R Random Access

Memory (RAM) 88 X not Zero X minus
ME
88
Memory Data INX

LD
88 88 DEX
Register (MDR)
CLK
Index Register CLK
LX
(XR)
EX
Program counter: It is a 16-bit reg. It stores the address of the next instruction to be executed.
Index Register: It is used to point at blocks of data in memory
Input / Output sub-system
Input devices includes:

 Keyboard  Switches  Mouse
 Teletype writer  Sensors  Light pen
 Magnetic tape  Tape recorders  Microphone etc.
 A/D converters  Scanners
Output devices includes:
 Printers  Speakers  LEDs  Alarms
 Monitors  Projectors  LCDs  Actuators
Block diagram of an input/output sub-system
8 A/D
8
Bus
L1 CLK
8 (8) 8
CLK Input Register Output Register
LO
E1
Control Unit:
It directs various sub-systems/units to act in a desired way. It coordinates and synchronizes their
functioning. It consists of the:
 Instruction register  Timing and control unit
 Instruction decoder
Block diagram of the control unit
LC Instruction register
CLR A/D
8
CLK
Bus
EC
8 (8)
Instruction decoder
Timing and control unit
Clock pulses
© N. Koech 2021signals
Control Microprocessor Systems 1st Ed.
Instruction register: it stores the code of the instruction currently being executed
Instruction decoder: it decodes the instructions received from the instruction register and
directs the control unit to produce necessary control signals.
Control and timing unit: it produces the control signals required for the operation of various
sub-systems.
Other registers
Stack pointer
Stack: it is a set of memory locations reserved by a programmer for saving the address in the
program counter.
Stack pointer: it stores the address of a memory location belonging to the most recent entry in
the stack. It is used to save data of another general purpose register during execution of a sub-
routine or when an interrupt is serviced.
General purpose registers (B, C, D, E, H and L)
They are used to store data and address information. This enhance the processing speed of a
microprocessor by avoiding a large number of external memory read/write operations. Each
register can hold 8-bit data. They can also work as register pairs to hold 16 bit data. Their pairing
combination is: B-C, D-E and H-L
Temporary registers (W and Z)
They are used when data have to be stored during the execution of a machine instruction.
Accumulator (Register A)
It stores the result of an operation. During arithmetic and logic operation, one of the operands is
always taken into the accumulator.
Flag Register/Status register
It stores the status outputs of the result of an operation and gives additional information about the
result of an ALU operation. Flag register is an 8-bit register. Intel 8085 has five flags as shown:
D7 D6 D5 D4 D3 D2 D1 D0
S Z XX AC XX P XX CY
i. S – Sign flag: when the MSB of result is 1, it is set to 1, otherwise it is reset to 0.

ii. Z – Zero flag. It is set to 1 if the result is of an operation is zero, otherwise reset to 0.
iii. AC – Auxiliary carry- when there is a carry at D3 and carried to D4, AC is set to 1,
otherwise it is reset to 0.
iv. P – Parity flag: For even no. of 1’s, P is set to 1. For odd no of 1’s, it is reset to 0.
v. CY – Carry flag: when an operation has a carry/borrow at D7, it is set to 1.
vi. XX – means unused.

Microprocessor Bus organization
Buses – it is a group of connecting wires or lines over which electrical signals are transmitted.
The three buses are:
i. Address bus
ii. Data bus
iii. Control bus
Bus structure/ organization
Address bus
Memory Input unit Output unit
Microprocessor
Data bus
Control bus
Address bus:
It is used to carry and address signals of memory location or I/O devices.
It is unidirectional.
Data bus
It is used for sending and receiving data by a microprocessor to & from memory and I/O devices.
It is bidirectional.
Control bus
It is used for transmitting and receiving control signals between the microprocessor and other
devices. E.g. memory read, I/O read, memory write and I/O write.

Intel 0885 microprocessor
Features of Intel 8085 microprocessor

It is an 8-bit microprocessor. I.e. its data bus has 8 bits
Its address bus has 16 bits. Therefore it has 216 = 65536 = 64kB memory locations.
It is a 2nd generation microprocessor using N-MOS technology designed by Intel in 1977.
It has 40 pins and requires a single battery of +5V D.C
Its clock speed is about 3MHz.

Schematic/Functional/Architectural/ Block diagram of Intel 8085 Microprocessor
The descriptions of various pins are as follows:
Address Bus and Data Bus
o A8 - A15 (Output): These are address bus and are used for the most significant bits of
the memory address or 8-bits of I/O address.
o AD0 - AD7 (Input/output): These are time multiplexed address/data bus i.e. they serve
dual purpose. They are used for the least significant 8 bits of the memory address or I/O
address during the first cycle. Again they are used for data during 2nd and 3rd clock
cycles.
Control and Status Signals

o ALE (Output): ALE stands for Address Latch Enable signal. ALE goes high during
first clock cycle of a machine cycle and enables the lower 8-bits of the address to be
latched either into the memory or external latch.
o IO/M (Output): It is a status signal which distinguishes whether the address is for
memory or I/O device.
o S0, S1 (Output): These are status signals sent by the microprocessors to distinguish the
various types of operation given in table below:
Status codes for Intel 8085
S1 S0 Operations
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
o RD (Output): RD is a signal to control READ operation. When it goes low, the

selected I/O device or memory is read.
o WR (Output): WR is a signal to control WRITE operation. When it goes low, the data
bus' data is written into the selected memory or I/O location.
o READY (Input): It is used by the microprocessor to sense whether a peripheral is ready
to transfer a data or not. If READY is high, the peripheral is ready. If it is low the
microprocessor waits till it goes high.
Interrupts and Externally Initiated Signals
o HOLD (INPUT): HOLD indicates that another device is requesting for the use of the
address and data bus.
o HLDA (OUTPUT): HLDA is a signal for HOLD acknowledgement which indicates
that the HOLD request has been received. After the removal of this request the HLDA
goes low.

o INTR (Input): INTR is an Interrupt Request Signal. Among interrupts it has the
lowest priority. The INTR is enabled or disabled by software.
o INTA (Output): INTA is an interrupt acknowledgement sent by the microprocessor
after INTR is received.
o RST 5.5, 6.5, 7.5 and TRAP (Inputs): These all are interrupts. When any interrupt is
recognized the next instruction is executed from a fixed location in the memory as given
below:
Line Location from which next instruction is picked up
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
RST 7.5, RST 6.5 and RST 5.5 are the restart interrupts which cause an internal restart to be
automatically inserted.
The TRAP has the highest priority among interrupts. The order of priority of interrupts is as
follows:
o TRAP (Highest priority)

o RST 7.5
o RST 6.5
o RST 5.5
o INTR (Lowest priority).
Reset Signals
o RESET IN (Input): It resets the program counter (PC) to 0. It also resets interrupt enable
and HLDA flip-flops. The CPU is held in reset condition till RESET is not applied.
o RESET OUT (Output): RESET OUT indicates that the CPU is being reset.
Clock Signals

o X1, X2 (Input): X1 and X2 are terminals to be connected to an external crystal oscillator
which drives an internal circuitry of the microprocessor. It is used to produce a suitable
clock for the operation of microprocessor.
o CLK (Output): CLK is a clock output for user, which can be used for other digital ICs.
Its frequency is same at which processor operates.
Serial I/O Signals
o SID (Input): SID is data line for serial input. The data on this line is loaded into the
seventh bit of the accumulator when RIM instruction is executed.
o SOD (Output): SOD is a data line for serial output. The seventh bit of the accumulator
is output on SOD line when SIM instruction is executed.
Power Supply
VCC: +5 Volts supply
VSS: ground reference

2.0 INTRODUCTION TO ASSEMBLY LANGUAGE
PROGRAMMING
Program: is a sequence of instructions, written for the purpose of performing a desired task. It is
made up of two parts:
 Instructions
 Data
An instruction of computer is a command given to the computer to perform a specified

operation on given data. Some instructions of Intel 8085 microprocessor are: MOV, MVI, LDA,
STA, ADD, SUB, RAL, INR, MVI, etc. An instruction consists of two parts:
Opcode (Operation code) and Operand.
Opcode: The 1st part of an instruction which specifies the task to be performed by the computer.
Operand. The 2nd part of the instruction is the data to be operated on, and it is called The
Operand (or data) given in the instruction may be in various forms such as 8-bit or 16-bit data, 8-
bit or 16-bit address, internal registers or a register or memory location.
Instruction Word Size
A digital computer understands instruction written in binary codes (machine codes). The binary
codes of all instructions are not of the same length.
According to the word size, the Intel 8085 instructions are classified into the following three
types:
1. One byte instruction

2. Two byte instruction
3. Three byte instruction
1. One-byte instruction: Examples of one byte instructions are:
o MOV A, B - Move the content of the register B to register A.

o ADD B - Add the content of register B to the content of the accumulator.
All the above two examples are only one byte long. All one-byte instructions contain information
regarding operands in the opcode itself.
2. Two-byte instruction: In a two byte instruction the first byte of the instruction is its opcode
and the second byte is either data or address.

Example:
MVI B, 05; 05 moved to register B.
06, 05; MVI B, 05 is in the code form.
The first byte 06 is the opcode for MVI B and second byte 05 is the data which is to be moved to
register B.
3. Three-byte instruction: The first byte of the instruction is its opcode and the second and third
bytes are either 16-bit data or 16-bit address.
Example:
LXI H, 2400H; Load H-L Pair with 2400H
21, 00, 24; LXI H, 2400H in the code form
The first byte 21 is the opcode for the instruction LXI H. The second 00 is 8 LSBs of the data
(2400H), which is loaded into register L. The third byte 24 is 8 MSBs of the data (2400H), which
is loaded into register H.
Instruction Cycle
The time required to fetch an instruction and necessary data from memory and to execute it, is
called an instruction cycle. Or the total time required to execute an instruction is given by:
Instruction Cycle = Fetch Cycle + Execute Cycle
Phases in execution of an instruction
i. Fetch Cycle
Microprocessor places the contents of the program counter on the address bus and gets
instruction code, opcode from the addressed memory location. The microprocessor then saves
the opcode in the instruction register. The whole operation of fetching an opcode takes three
clock cycles. A slow memory may take more time.
ii. Decode Cycle
The opcode fetched from the memory goes to the data register, DR and then to instruction
register, IR. The opcode in the instruction register is decoded with the help of the instruction
decoder to generate appropriate control signals to execute the instruction
iii. Execute Cycle

The microprocessor generates appropriate control signals and execute the instruction. If the
operand is reside the general purpose registers, execution is immediately performed. The time
taken in decoding and execution of an instruction is one clock cycle.
In some situations, an execute cycle may involve one or more read or write cycles or both.
Read Cycle: If an instruction contains data or operand address which are in the memory, the
CPU has to perform some read operations to get the desired data. In case of a read cycle the
instruction received from the memory are data or operand address instead of an opcode.
Write Cycle: In write cycle data are sent from the CPU to the memory or an output device.
Basic Instruction Cycle
Start
Fetch the next instruction Fetch cycle
Decode the instruction Decode cycle
Execute the instruction Execute cycle
Stop
Timing Diagram for Instruction Cycle
Machine Cycle and State
Machine Cycle: It is the time required to access the memory or an I/O device. It is measured in
T-states (a clock period). The 8085 µP has seven machine cycles:

i. Opcode fetch iv. I/O read vi. Interrupt
ii. Memory read v. I/O write acknowledge
iii. Memory write vii. Bus idle
T-state: is one sub-division of an operation performed in one clock cycle. In short, one clock cycle of the
system clock is referred to as a state.
Timing Diagrams
The necessary steps carried out in a machine cycle can be represented graphically using a timing diagram.
Timing Diagram for Opcode Fetch Cycle:
Timing Diagram for Memory Read

Timing Diagram for Memory Write
Timing Diagram for I/O Read

Timing Diagram for I/O Write
In the above diagrams, the basic used parameters are:
ALE: ALE indicates the availability of a valid address on the multiplexed address/data lines. When it is high or
1, then it acts as an address bus and when low or 0, then it acts as a data bus.
RD (low active): If it is high or 1, then no data is read by the microprocessor. If signal is low or 0, then data is
read by the microprocessor.
WR (low active): If it is high or 1, then no data is written by the microprocessor. If signal is low or 0, then data
is written by the microprocessor.
IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0 indicates memory
operation.
S0, S1: S0 and S1 Indicate the type of machine cycle in progress.
The below table, shows the status of different control signal for different operation:
Instruction format:
An instruction in assembly language program includes the following four fields:
i. Label field
ii. Mnemonic field/opcode field
iii. Operand field
iv. Comment field.
Labels
It contains a sequence of letters and digits e.g. START, HERE etc.
It is used to identify the statement before which it occurs.
A label is separated from the rest of the statement by a colon.
Mnemonic/opcode
It is a sequence of characters used to represent an operation in a microprocessor. E.g. ADD, MOV, LXI etc.
Operands
It is a binary number on which an operation is to be carried out as per the instructions. It may be data or an
address.
e.g. MOV A, C
Opcode Operand
Comments
It gives a narrative description of the task which an instruction is supposed to take. This helps in understanding
the program.
A semicolon is used to separate a comment from the rest of the instructions.
An assembler ignores comment field during translation. It is only useful to the programmer and not the
microprocessor.
Assembler Delimiters
They are used to separate the four fields in an instruction. Typical delimiters are:
 Spaces: used between fields
 Commas: used between addresses in an operand field
 Semicolon: used before a comment
 Colon: used for a label.

Microprocessor programming languages:
They are typically divided into three:
i. Machine language Low level languages
ii. Assembly language
iii. High level languages e.g. C, C++ etc.
Machine language
It is a sequence of instructions written in binary numbers (1s & 0s) to which the computer understands directly.
Advantages of machine language
 Faster execution: no translation is required
Disadvantages:
 Difficult to remember machine code
 Very tedious and time consuming to write machine code
 Very difficult to detect errors
 It is dependent on the type of computer and its design.
Assembly language
It uses mnemonics (memory aids). This improves the readability of the program.
Assembly language is translated to machine language using an assembler.
Advantages of assembly language
 Executes faster than an equivalent high level language program.
 Occupy less space in memory compared to compilers.
8085 INSTRUCTION SET
8085 instructions are classified into the following groups:

i. Data transfer instructions
ii. Arithmetic instructions
iii. Logical instructions
iv. Branching instructions
v. Machine control instructions
vi. Input/output instructions
vii. Stack operations
Data Transfer Group

Instructions which are used to transfer the data from a register to another register, from memory to register or
register to memory come under this group.
Instruction Set Explanation States Flags Addressing Machine Example
Cycles
MOV r1, r2 Move the content 4 none Register 1 MOV A, B

[r1] ← [r2] of the one register
to another
MOV r, M Move the content 7 none Register 2 MOV B, M

[r]←[[H-L]] of memory to Indirect
register
MOV M, r Move the content 7 none Register 2 MOV M, C

[[H-L]]←[r] of register to Indirect
memory
MVI r, data 8 Move immediate 7 None Immediat 3 MVI M, 08

[r] ←data data to register e Register
LXI rp, data 16 Load Register pair 10 None Immediat 3 LXI H, 2500H
[rp] ←data 16 immediate data e
bits, [rh] ←8
MSBs, [rl] ←8
LSBs of data
LDA addr Load 13 None Direct 4 LDA 2400 H

[A] ←[addr] Accumulator
direct
STA Addr Store accumulator 13 None Direct 4 STA 2000H

[addr] ←[A] direct
LHLD addr Load H-L pair 16 None Direct 5 LHLD 2500H

[L] ←[addr], [H] direct
← [addr + 1 ]

SHLD addr Store H-L pair 16 None Direct 5 SHLD 2500 H
[addr] ←[L], direct
[addr +1] ← [H]
LDAX rp Load accumulator 7 None Register 2 LDAX B

[A] ←[[rp]] indirect Indirect
STAX rp Store accumulator 7 None Register 2 STAX D

[[rp]] ←[A] indirect Indirect
XCHG Change the 4 None Register 1

[H-L] ↔[D-E] contents of H-L
with D-E pair
Programming examples
1. Write an assembly language program to store the number D5H in register B.
Soln. MVI B, D5H

HLT
2. Write an assembly language program to load the accumulator with data F2H, transfer this data to
register C.
Soln. MVI A, F2H

MOV C, A
HLT
3. Write an assembly language program to load the accumulator with contents of memory location
F230H, transfer these contents to register B.
Soln. LDA, F230H

MOV B, A
HLT

4. Write instructions of 8085 microprocessor that:
i. Copies the data in B-C register pair to D-E register pair.
ii. Moves the data in memory to A register and vice versa. (4mks)
Soln. i. MOV D, B ii. MOV A, M
MOV E, C MOV M, A
5. Indicate three ways to represent decimal value 10 as an immediate data type.

i. MVI A, 0AH
ii. MVI A, 10D
iii. MVI A, 1010B
Arithmetic Group
The instructions of this group perform arithmetic operations such as addition, subtraction, increment or
decrement of the content of a register or a memory.
Instruction Set Explanation States Flags Addressing Machine Example

Cycles
ADD r Add register to 4 All Register 1 ADD E

[A] ←[A]+[r] accumulator
ADD M Add memory to 7 All Register 2 ADD M

[A] ← [A] + [[H-L]] accumulator indirect
ADC r Add register with 4 All Register 1 ADC B

[A] ← [A] + [r] + carry to accumulator
[CS]
ADC M Add memory with 7 All Register 2 ADC M

[A] ← [A] + [[H-L]] carry to indirect
[CS] accumulator

ADI data Add immediate data 7 All Immediate 2 ADI 55H
[A] ← [A] + data to accumulator
ACI data Add with carry 7 All Immediate 2 ACI 55H

[A] ← [A] + data + immediate data to
[CS] accumulator
DAD rp Add register paid 10 CS Register 3 DAD B

[H-L] ←[H-L] + [rp] to H-L pair
SUB r Subtract register 4 All Register 1 SUB C

[A] ←[A]-[r] from accumulator
SUB M Subtract memory 7 ALL Register 2 SUB M

[A] ← [A] - [[H-L]] from accumulator indirect
SBB r Subtract memory 7 All Register 2 SBB D

[A] ←[A]-[H-L]] - from accumulator indirect
[CS] with borrow
SUI data Subtract immediate 7 All Immediate 2 SUI 55H

[A] ←[A]-data data from
accumulator
SBI data Subtract immediate 7 All Immediate 2 SBI 04H

[A] ←[A]-data-[CS] data from accumulator
with borrow
INR r Increment register 4 All Register 1 INR B

[r] ←[r]+1 content except
carry
flag
INR M Increment memory 10 All Register 3 INR M

[[H-L]] ←[[H-L]]+1 content except indirect

carry
flag
DCR r Decrement register 4 All Register 1 DCR L

[r] ←[r] -1 content except
carry
flag
DCR M Decrement 10 All Register 3 DCR M

[[H-L]] ← [[H-L]]-1 memory content except indirect
carry
flag
INX rp Increment memory 6 None Register 1 INX B

[rp] ←[rp]+1 content
DCX rp Decrement register 6 None Register 1 DCX D

[rp] ←[rp]-1 pair
DAA Decimal adjust 4 1 DAA

accumulator
Notes
DAA – the contents of the accumulator is adjusted to change 8-bit binary number into two 4-bit BCD number.
DAD – the contents of the register pair is added to that of the H-L pair. The result I stored in H-L pair.
1. Write an assembly language program to add two numbers: 25H and 52H and store the result in
the memory location 2050H.
Soln. MVI A, 25H OR MVI A, 25H
ADI 52H MVI B, 52H
STA 2050H ADD B
HLT STA 2050H
© N. Koech 2021 Microprocessor Systems HLT 1st Ed.

2. Write an assembly language program to subtract the number 43H from 78H and store the result
in memory location 2050H.
SUI 43H MVI B, 43H
STA 2050H SUB B
HLT STA 2050H

HLT
3. Write an assembly language program to multiply a number in memory location 2000H by 4 and
store the result in location 2008H.
Soln. LDA 2000H OR LXI H, 2000H
ADD A MOV A, M
ADD A ADD A
STA 2008H ADD A
HLT STA 2008H

HLT
4. Write an assembly language program to perform the following sequentially: Sum the numbers 48
and 17; multiply the result by 2; subtract 22 from the result; store the answer in memory location
2016H. (6mks)
Soln. MVI A, 48D OR MVI A, 30H
ADI 17D ADI 11H
ADD A ADD A
SUI 22D SUI 16H
STA 2016H STA 2016H
HLT HLT

5. Write an assembly language program to perform the following: 59 X 4 + 13 (4mks)
Soln. Converting to hex: 59 = 3BH; 13 = 0DH
MVI A, 3BH
ADD A
ADD A
ADI 0DH
HLT
6. Write an assembly language program segment to perform each of the following:
i. 27 + 15 MVI A, 27D MVI A, 69D

ii. 69 – 14
ADI 15 SUI 14D
iii. 12 x 4
iv. 18 ÷ 2 HLT HLT
MVI A, 12D
XRA
ADD A
MVI A, 18D
ADD A
RAR
HLT
HLT
7. Write an assembly language program segment to solve each of the following

i. y = 23x; where x is an 8-bit integer less than 11. (5mks)
ii. z = Q/4 where Q is an 8-bit number. (3mks)
Soln.
MVI A, X ADD A MVI A, Q
MOV B, A ADD A RRC
ADD A ADD D RRC
MOV C, A ADD C HLT
ADD A ADD B
MOV D, A HLT

8. Write an assembly language program segment to perform each of the following
i. (3948)16 + (4ACE) 16 (3mks)
ii. 2510 x 1610 (5mks)
iii. (109)10 ÷ 410 (4mks)
Soln.
MVI A, 19H
LXI H, 3948H
MVI A, 6DH
ADD A
LXI B, 4ACEH
RAR
ADD A
DAD B
ORA A
ADD A
HLT
RAR
ADD A
HLT
HLT
9. Starting at address 3000H, write an assembly language program that will add two decimal
numbers 36748 located at memory address starting 3500H and 38117 located at memory address
starting 3502H. The result is stored in memory starting at 3504H. (8mks)
Soln.
Converting: 3674810 = 8F8CH
ORG 3000H OR 3811710 = 94E5H
XRA A
LDA 3500H
ORG 3000H
LXI H 3502H
XRA A
ADD M
MVI A, 8CH
STA 3504H
ADI E5H
LDA 3501H
STA 3504H
INX H
MVI A, 8FH
ADC M
ACI 94H
STA 3505H
STA 3505H
HLT
HLT

Logical Group
The instructions in this group perform logical operation such as AND, OR, XOR, Complement, Compare,
Rotate, etc.
Instruction Set Explanation States Flags Addressing Machine

Cycles
ANA r AND register with 4 All Register 1

[A] ←[A]∧[r] accumulator
ANA M AND memory with 4 All Register 2

[A] ←[A]∧[[H-]] accumulator indirect
ANI data AND immediate data 7 All Immediate 2

[A] ← [A] ∧ [data] with accumulator
ORA r OR-register with 4 All Register 1

[A] ←[A]∨[r] accumulator
ORA M OR-memory with 7 All Register 2

[A] ←[A]∨[[H-L]] accumulator indirect
ORI data OR -immediate data 7 All Immediate 2

[A] ← [A] ∨ [data] with accumulator
XRA r XOR register with 4 All Register 1

accumulator
[A] ← [A]∀[r]
XRA M XOR memory with 7 All Register 2

accumulator indirect
[A] ← [A] ∀ [[H-L]]
XRI data XOR immediate data 7 All Immediate 2

with accumulator
[A] ←[A] ∀ [data]

CMA Complement the 4 None Implicit 1
accumulator
[A] ←[A]
CMC Complement the carry 4 CS 1

[CS] ←[CS] status
STC Set carry status 4 CS 1

[CS] ← 1
CMP r Compare register 4 All Register 1

[A]-[r] with accumulator
CMP M Compare memory 7 All Register 2

[A] - [[H-L]] with accumulator indirect
CPI data Compare immediate 7 All Immediate 2

[A] - data data with accumulator
RLC Rotate accumulator 4 Cs Implicit 1

[An+1] ←[An], [A0] ←[A7], [CS] left
←[A ] 7
RRC Rotate accumulator CS Implicit 1

[A7] ←[A0], [CS] ←[A0], [An] right
←[An+1]
RAL Rotate accumulator CS Implicit 1

[An+1
] ←[A ], [CS] ←[A ], [A ]
n 7 0
left through carry
←[CS]
RAR Rotate accumulator CS Implicit 1

[An] ←[An+1], [CS] ←[A0], [A7] right through carry
←[CS]

10. Write an assembly language program to reset (clear) the carry flag.
Soln. STC
CMC
HLT
11. Write an assembly language program to find the 2’s complement of data 16H
CMA CMA
ADI 01H INR A
HLT HLT
12. Write an assembly language program to carry out the arithmetic below using 2’s complement
method. 42H – 18H
MVI A, 18H
Soln. MVI A, 18H OR
CMA
CMA INR A
ADI 01H MVI B, 42H
ADI 42H ADD B
HLT HLT
13. Write an assembly language program to perform: 101001012 AND 23H
Soln. MVI A, A5H OR MVI A, A5H
ANI 23H MVI B, 23H
HLT ANA B
HLT

Branch Control Group
This group contains the instructions for conditional and unconditional jump, subroutine call and return, and
restart.
They alter the normal sequential program flow. Conditional flags are not affected by this group. They are
classified as:
Unconditional transfer: simply perform a specified operation on the program counter.
Conditional transfer: examine the condition of one of the processor flags to determine if the specified branch
is to be executed.
Unconditional Jump

Cycles
JMP addr (label) Unconditional jump: jump to the 10 None Immediate 3

[PC] ← Label instruction specified by the address
Conditional Jump
Instruction Set Explanation States Machine Cycles
Jump addr Conditional jump: jump to the 10, if true and 3, if true and
(label) instruction specified by the address if 7, if not true 2, if not true
[PC] ← Label the specified condition is fulfilled
Instruction Set Explanation Status States Flags Addressing Machine

Cycles
JZ addr (label) [PC] ← Jump, if the Jump if 7/10 None Immediate 2/3
address (label) result is zero Z=1
JNZ addr (label) Jump if the Jump if 7/10 None Immediate 2/3
[PC] ← address (label) result is not zero Z=0

JC addr (label) Jump if there Jump if 7/10 None Immediate 2/3
[PC] ← address (label) is a carry CS =1
JNC addr (label) Jump if there Jump if 7/10 None Immediate 2/3
[PC] ← address (label) is no carry CS =0
JP addr. (label) Jump if result Jump if 7/10 None Immediate 2/3

[PC] ← address (label) is plus S=0
JM addr (label) Jump if result Jump if 7/10 None Immediate 2/3

[PC] ← address (label) is minus S=1
JPE addr (label) Jump if even The parity 7/10 None Immediate 2/3
[PC] ← address (label) parity status P =1
JPO addr (label) Jump if odd The parity 7/10 None Immediate 2/3
[PC] ← address (label) parity status P =0
Unconditional CALL

Cycles
CALL addr (label) Unconditional CALL: 18 None Immediate 5

[SP]-1] ← [PCH] ,[[SP-2] ← Call the subroutine /register
[PCL], [SP] ← [SP]-2, [PC] ← identified by the address
addr(label)
Conditional CALL
CALL addr (label) Unconditional CALL: Call 18, if true and 5, if true and
[SP]-1] ← [PCH] , [[SP-2] the subroutine identified by 9, if not true 2, if not true

← [PCL], [PC] ← addr the address if the specified
(label), [SP] ← [SP]-2 condition is fulfilled
Instruction Explanation Status States Flags Addressing Machine Cycles

Set
CC addr Call subroutine if CS =1 9/18 None Immediate 2/5

(label) carry status CS=1 /register
CNC Call subroutine if CS =0 9/18 None Immediate 2/5

addr carry status CS=0 /register
(label)
CZ addr Call Subroutine if Zero status 9/18 None Immediate 2/5

(label) the result is zero Z=1 /register
CNZ addr Call Subroutine if Zero status 9/18 None Immediate 2/5
(label) the result is not Z=0 /register
zero
CP addr Call Subroutine if Sign status 9/18 None Immediate 2/5

(label) the result is plus S=0 /register
CM addr Call Subroutine if Sign status 9/18 None Immediate 2/5

(label) the result is minus S= 1 /register
CPE addr Call subroutine if Parity 9/18 None Immediate 2/5

(label) even parity Status P=1 /register
CPO addr Call subroutine if Parity Status 9/18 None Immediate 2/5
(label) odd parity P= 0 /register

Unconditional Return

Cycles
RET Unconditional 10 None Indirect 3

[PCL] ← [[SP]], [PCH] ← [[SP] + 1], RET: Return
[SP] ← [SP] + 2 from subroutine
Conditional Return
RET Conditional RET: 12, if true and 3, if true and 1, if not

[PCL] ← [[SP]], Return from 6, if not true true
[PCH] ← [[SP] + 1], subroutine
[SP] ← [SP] + 2
Instruction Explanation Status States Flags Addressing Machine

Set Cycles
RC Return from subroutine CS =1 6/12 None Register 1/3

if carry status is zero. indirect
RNC Return from subroutine CS = 0 6/12 None Register 1/3

if carry status is not indirect
zero.
RZ Return from subroutine Zero status 6/12 None Register 1/3

if result is zero. Z=1 indirect
RNZ Return from subroutine Zero status 6/12 None Register 1/3
if result is not zero. Z= 0 indirect

RP Return from subroutine Sign Status 6/12 None Register 1/3
if result is not plus. S= 0 indirect
RM Return from subroutine Sign Status 6/12 None Register 1/3

if result is not minus. S= 0 indirect
RPE Return from subroutine Parity Status 6/12 None Register 1/3
if even parity. P= 1 indirect
RPO Return from subroutine Parity Status 6/12 None Register 1/3
if odd parity. P= 1 indirect
Restart

Cycles
RST Restart is a 12 None Register 3

[[SP]-1] ← [PCH], [[SP]-2] ← [PCL], one word Indirect
[SP] ← [SP] - 2, CALL
[PC] ← 8 times n instruction.
The restart instructions and locations are as follows:
Instruction How to calculate Restart Locations
RST 0 0x8 0000
RST 1 1x8 0008
RST 2 2x8 0010
RST 3 3x8 0018

RST 4 4x8 0020
RST 5 5x8 0028
RST 6 6x8 0030
RST 7 7x8 0038
PCHL

Cycles
PCHL Jump address 6 None Register 1

[PC] ← [H-L], specified by H-L
[PCH] ←[H], [PCL] ←[L] pair
1. Write an assembly language program to decrement data 05H stored in register B to zero.
MVI B, 05H
LOOP: DCR B
JNZ LOOP
HLT
2. Write an assembly language program to add the series elements: 5 + 4 + 3 + 2 + 1
Soln. XRA A
MVI B, 05H
LOOP: ADD B
DCR B
JNZ LOOP
HLT

Input/Output Group
This group contains the instructions for input/output ports
Instruction Set Explanation States Flags Addressing Machine Cycles
IN port - address Input to accumulator from 10 None Direct 3

[A] ← [Port] I/O port
OUT port-address Output from accumulator to 10 None Direct 3

[Port] ← [A] I/O port
Machine Control Group

This group contains the instructions for machine control.
Instruction Set Explanation States Flags Addressing Machine Cycles
EI Enable Interrupts 4 None 1
DI Disable Interrupts 4 None 1
SIM Set Interrupts Masks 4 None 1
RIM Read Interrupts Masks 4 None 1
NOP No Operation 4 None 1
HLT Halt 5 None 1

Stack Operations Group
This group contains the instructions for stack.

Cycles
PUSH rp Push the content of 12 None Register(source)/ 3

[[SP] - 1] ← [rh], register pair to register Indirect
[[SP] - 2] ← [rh], stack (destination)
[SP] ← [SP] - 2
PUSH PSW Push processor 12 None Register(source)/ 3

[SP]-1] ← [A], word register Indirect
[[SP] -2] ← PSW, (destination)
[SP] ← [SP] - 2
POP rp Pop the content of 10 None Register(source)/ 3

[rl] ← [ [ SP ] ], register pair, which register Indirect
[rh] ← [[SP]+1], was saved, from (destination)
[SP] ← [SP] + 2 the stack
XTHL Exchange top stack 16 None Register indirect 5

[L] ↔ [[SP]], with H-L
[H] ↔ [[SP] + 1]
SPHL Moves the contents 6 None Register 1

[H-L] → [SP] of H-L pair to
stack pointer

Hand coding:
It is converting a program from assembly language to hexadecimal code or vice versa using a table.
Example 1: Hand code the following program starting from address 2001H. (7mks)
MVI A, 32H
MVI B, 20H
MVI C, 42H
ADD B
ADD C
HLT
Soln.
Address Mnemonic Machine code
2001H MVI A, 32H 3E
2002H 32
2003H MVI B,20H 06
2004H 20
2005H MVI C, 42H 0E
2006H 42
2007H ADD B 80
2008H ADD C 81
2009H HLT 76
Example 2: The table below shows an 8085 hexadecimal machine code program. Using the 8085 instruction
set, convert the program into 8085 mnemonic program. (6mks)
Address Machine code Soln. LXI H, 3000H
2000H 21
2001H 00 LXI B, 4000H
2002H 30
DAD B
2003H 01
2004H 00 HLT
2005H 40
2006H 09
2007H 76

Example 3: The table below shows an 8085 assembly language program.
i. Convert the assembly language program into hexadecimal code
ii. Determine the contents of register A at the end of the program execution. (10mks)
LXI H, 0870H
MOV A, L
MOV B, H
ADD B
ADD A
HLT
Soln.
Address Mnemonic Machine code
0000H MVI A,C8H 3E
0001H C8
0002H LXI B, 5640H 01
0003H 40
0004H 56
0005H ANA C A1
0006H ORA B B0
0007H RLC 07
0008H LXI H, 2000H 21
0009H 00
000AH 20
000BH SHLD 3000H 22
000CH 00
000DH 30
000EH HLT 76
Example 4: Given the program listing 1 below and Intel 8085 instruction set, hand-code it using hexadecimal.
Listing 1 ORG 0000H (8mks)
MVI A, C8H
LXI B, 5640H
ANA C
ORA B
RLC
LXI H, 2000H
SHLD 3000H
HLT
Soln. Register contents
Address Mnemonic Machine code A H L B
0000H LXI H 0870H 21 xx 08 70 xx
70
08
0004H MOV A, L 7D 70 08 70 xx
0005H MOV B, H 44 70 08 70 08
0006H ADD B 80 78 08 70 08
0007H ADD A 87 F0 08 70 08
0008H HLT 76 F0 08 70 08
ADDRESSING MODES
These are the various techniques used to specify the data or addresses to be operated on by the instruction.
8085 microprocessor has the following address modes: direct, register, indirect, immediate and implied.
1. Direct addressing mode
The address of the operand is specified in the instruction itself. E.g. LDA 2000H, SHLD 3000H etc.
2. Register addressing mode
The source, destination operand or both are contained in the µP register. E.g. MOV A, B; SPHL, ADD C etc.
3. Register Indirect addressing mode
The memory address where the data is located is specified by the contents of a register pair. E.g. LDAX B,
MOV M, A etc.
4. Immediate addressing mode
The 8 or 16-bit data is specified as part of the instruction. E.g. MVI A, 20H, MVIM 30H, LXI SP, 2700H,
LXI D, 10FFH. Etc.
5. Implied/implicit addressing mode:
The opcode specifies the address of the operands. E.g. CMA, RAL etc.
6. Relative addressing mode
The address field of the instruction is added to the contents of program counter (PC) to evaluate the effective
address. E.g. JR 20H Address = PC +20
7. Absolute addressing mode
The address of data is part of the instruction. E.g. SHLD, LDA 2000H, LHLD, STA 4000H etc.
8. Indexed addressing mode
The contents of an index register is added to the address part of an instruction to obtain the effective addressing
mode. E.g. ADD A, (I X + 5) I X = Index Register
9. Stack addressing mode:
Instruction consists of action (e.g. PUSH or POP) and register or actual data being sent or retrieved from stack.
E.g. PUSH B, POP D etc.
Assembler Directives / Pseudo instructions

They are used to direct the assembler to take an action.
1. DS directive (Define Storage)
It orders the assembler to reserve a specified number of consecutive bytes in memory location.
e.g. P : DS 24H - it reserves 24 bytes of memory space sequentially .
P = address of the first byte.
2. DB directive (Define Byte)
It directs the assembler to reserve one byte of memory at a specified address and initialize it with a specified
value.
e.g. E : DB 0F8H - it reserves one bytes of memory space at location E and initializes it with to value F8.
3. DW directive (Define Word)
It reserves two bytes of memory space and initializes it with the desired value.
e.g. K : DW 208FH
4. EQU directive (Equate)
It directs the assembler to equate the specified constant to a symbol.
e.g. P : EQU 2000H - it ask the assembler to treat P to be equal to 2000.
5. ORG directive (Origin)
It directs the assembler to assign specified address to the succeeding data items or instructions in a program.
e.g. ORG F028H - directs the assembler to assign the address F208H to the next
data/instruction in the program.
6. END
It shows the end of assembly program. When the assembler encounters it, it stops assembling because no other
instruction is expected below END.
Example 1: For the program shown below:
i. Identify the labels
ii. Identify the pseudo ops
iii. Produce the corresponding machine code
iv. Draw a symbol table
v. Determine the number of bytes occupied by the program
ORG START
MVI C, COUNT

LOOP: MVIA, DATA 1
MVI B, DATA 2
ADD B
STA MEM
DCR C
JNZ LOOP
HLT
START: EQU 4000H
COUNT: EQU 0AH
DATA 1: EQU 02H
DATA 2 EQU 03H
MEM: EQU 6000H
END
Soln.
i. Labels: START, COUNT, DATA 1, DATA 2, MEM, LOOP.
ii. Pseudo ops: ORG, EQU, END
iii. HAND CODING:
PC MACHINE CODE
4000 0E 0A
LOOP: 4002 3E 02
4004 06 03
4006 80
4007 32 00 60
400A 0D
400B C2 02 40
400E 76
iv. Symbol table

It is a table which shows the labels in a program and their equivalent numerical values.
START = 4000
DATA 1 = 02
DATA 2 = 03
MEM = 6000
LOOP = 4002
COUNT = 0A
v. Number of bytes
400E
4000
+ 1
000F
Flow charts
It is a diagrammatic method of writing a program. Unless a program is relatively easy, it is always advisable to
draw a flow chart first. When drawing flow charts, some standard symbols are used as shown below:
Name Symbol Meaning
1. Arrow - It indicates the direction of program execution.
2. Oval - It indicates the beginning (START) or ending (END)
of a program or segment.
3. Rectangle - It represent a process or an operation. All arithmetic and

data movement instructions are shown by this symbol.
4. Parallelogram - It indicates input or output operations.
5. Diamond - It represent a decision making block. It is used when a

decision has to be made and branching to one or two
more alternative points is possible.
6. Circle with - It indicates a condition (an entry or an exit) to a different

an arrow stage. It is also called a connector; when a flow chart
becomes too long to fit in a single page and continuation
has to be carried out on the next page, a connector is used.

Example
With an aid of a flow chart, write an assembly language program that adds the series 19H + 18H + 17H
+ - - - - + 01H.
Soln.
Start
Program
- Clear the accumulator
- Move count 19H to register B
XRA A
MVI B, 19H
- Add contents of A to B
- Decrement count (register B) LOOP: ADD B
DCR B
JNZ LOOP
Is count HLT
Zero?
NO
YES
Stop
SUBROUTINES
It is a program which is used to carry out a similar sub-task like addition, subtraction, multiplication etc.
Subroutines are applicable in cases where a sequence like addition may be required several times within a
program. It will be better to write a subroutine which is called every time the addition sequence is require, other
than writing addition sequence every time addition is needed. Below shows a flow diagram of a main program
and a subroutine. Subroutine
Main Program JOE
CALL JOE RET
CALL JOE

The instructions used with subroutines are CALL addr.(label) and RET
Nested subroutines
It is where a subroutine calls another subroutine. The LIFO (Last In First Out) always ensures that the correct
address is on top of stack memory when RET instruction is executed.
Nested subroutines are used when solving related problems such as determination of cosec x sin x. Where one
subroutine will find sin x while the other will find cosec x of the result obtained.
Nested subroutine is also used in time delay required between processes.
Below show a diagram of a nested subroutine.
Main Program PAT SAM
Subroutine
for sin x
Find cosec x sin x Subroutine
for cosec x
CALL PAT CALL SAM
RET RET
Parameter passing
The values operated on by a subroutine commonly known as parameters or augments may clearly change every
time the subroutine is called. For instance, for a subroutine that carries out addition between two values, the
values to be added may change each time the subroutine is called. Therefore, there should be a mechanism of
sending or passing these parameters to the subroutine for processing and also a way of getting back the results
obtained.
Note that subroutine does not contain values (parameters) but these values are held in the main program but are
pasted to the sub routine for processing.
Methods of parameter passing:

i. By use of register
ii. By use of memory
iii. By use of stack
Advantages of subroutine
i. It saves on memory by enhancing short programs through avoiding repetition of similar programs
ii. Encourages modular programming – where a large program is subdivided into module (subroutines)
to be developed and tested by different programmers.
iii. It is easier to modify a subroutine rather than a program sequence that appears severally in a main
program.
Disadvantages of subroutine
i. Two more instructions are added into the instruction set: CALL and RET.
ii. Programs with some subroutines are complex to develop.
iii. Programs with some subroutines runs slower.
NB Since subroutine requires use of the stack memory, the stack memory must first be
initialized to become usable. This is done by loading the stack pointer SP with the higher address of the given
stack range. E.g. given the stack range 3000H – 40FFH, the SP is loaded with address 40FF as:
LXI SP, 40FFH
Example
i. Write a program in assembly language to add two values 06H and 39H and store the result in
memory address 7000H.
ii. Convert the program into a main program and a subroutine. Assume that the stack memory has the
range 3000H to 5FFFH.
iii. Write a main program utilizing the above subroutine to add values 45H and D8H and store the sum
in memory address 8000H.
Soln.
i. MVI A, 06H MVI A, 06H
MVI B, 39H OR
MVI B, 39H
ADD B ADD B
STA 7000H LXI H, 7000H
HLT MOV M, A
HLT
ii. Main program Subroutine
LXI SP, 5FFFH PETER: ADD B

MVIA, 06H MOV M, A
MVI B, 39H RET
LXI H, 7000H
CALL PETER
HLT

iii. LXI SP, 5FFFH
MVIA, 45H
MVI B, D8H
LXI H, 8000H
CALL PETER
HLT

4.0 Interrupts
Interrupts are the signals generated by the external devices to request the microprocessor to perform
a task. There are 5 interrupt signals in intel 8085, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt: − In this type of interrupt, the interrupt address is known to the processor. For
example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt: − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt: − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, and RST5.5.
 Non-Maskable interrupt: − In this type of interrupt, we cannot disable the interrupt by writing
some instructions into the program. For example: TRAP.
 Software interrupt: − In this type of interrupt, the programmer has to add the instructions into
the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1,
RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP,
RST7.5, RST6.5, RST5.5, INTA.
Note − INTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP
has the highest priority, then RST7.5 and so on.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting source is
called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled
until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory.
This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt
is executed, the processor saves the content of the PC register into the stack and branches to 003CH
address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 0034H
address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 002CH address.
INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting
the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction and
sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
Computer Architecture: Interrupts

Data transfer between the CPU and the peripherals is initiated by the CPU. But
the CPU cannot start the transfer unless the peripheral is ready to communicate
with the CPU. When a device is ready to communicate with the CPU, it generates
an interrupt signal. A number of input-output devices are attached to the
computer and each device is able to generate an interrupt request.
The main job of the interrupt system is to identify the source of the interrupt.
There is also a possibility that several devices will request simultaneously for CPU
communication. Then, the interrupt system has to decide which device is to be
serviced first.
Priority Interrupt
A priority interrupt is a system which decides the priority at which various
devices, which generates the interrupt signal at the same time, will be serviced by
the CPU. The system has authority to decide which conditions are allowed to
interrupt the CPU, while some other interrupt is being serviced. Generally, devices
with high speed transfer such as magnetic disks are given high priority and slow
devices such as keyboards are given low priority.
When two or more devices interrupt the computer simultaneously, the computer
services the device with the higher priority first.

Types of Interrupts:
Following are some different types of interrupts:
Hardware Interrupts
When the signal for the processor is from an external device or hardware then
this interrupts is known as hardware interrupt.
Let us consider an example: when we press any key on our keyboard to do some
action, then this pressing of the key will generate an interrupt signal for the
processor to perform certain action. Such an interrupt can be of two types:
 Maskable Interrupt
The hardware interrupts which can be delayed when a much high priority
interrupt has occurred at the same time.
 Non Maskable Interrupt
The hardware interrupts which cannot be delayed and should be processed

by the processor immediately.
Software Interrupts
The interrupt that is caused by any internal system of the computer system is
known as a software interrupt. It can also be of two types:
 Normal Interrupt
The interrupts that are caused by software instructions are called normal
software interrupts.
 Exception
Unplanned interrupts which are produced during the execution of some

program are called exceptions, such as division by zero.

Daisy Chaining Priority
This way of deciding the interrupt priority consists of serial connection of all the
devices which generates an interrupt signal. The device with the highest priority is
placed at the first position followed by lower priority devices and the device
which has lowest priority among all is placed at the last in the chain.
In daisy chaining system all the devices are connected in a serial form. The
interrupt line request is common to all devices. If any device has interrupt signal
in low level state then interrupt line goes to low level state and enables the
interrupt input in the CPU. When there is no interrupt the interrupt line stays in
high level state. The CPU respond to the interrupt by enabling the interrupt
acknowledge line. This signal is received by the device 1 at its PI input. The
acknowledge signal passes to next device through PO output only if device 1 is
not requesting an interrupt.
The following figure shows the block diagram for daisy chaining priority system.

5.0 Direct Memory Access (DMA)
It is an efficient way of transferring data from the memory to the I/O devices or vice versa without involving the
CPU. It is suitable for large data transfers e.g. data transfer from magnetic disk or optical disk to memory.
Advantages of DMA
i. Since it transfer data directly to and from memory it relieves congestion on the bus system.
ii. Very fast
iii. It relieves CPU from undertaking I/O operation.
Disadvantages of DMA
i. Complex to both implement and program
ii. Requires extra circuitry
iii. May block CPU from responding to urgent interrupts.
How DMA Operations are performed:

Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory, the device has to send
DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses between
the CPU, memory, and I/O devices.
DMA Controller 8257

It is a programmable DMA controller.
DMA Controller Modes of operation

The device 8257 is operated in two modes:
i. Slave mode: when the device is accessed by the CPU. It is treated as an I/O device. This mode is
used to load necessary data into the DMA controller before the actual DMA operations.
ii. Master mode: when the device actually executes DMA operation.
DMA Operations:
i. Read Operation: to transfer data from memory to an I/O device.
ii. Write Operation: to transfer data from an I/O device to memory.
iii. Verify Operation: to check the validity of the data that has been transferred.
DMA Controller cycles:

i. DMA idle cycle: when no channel is requesting service.
ii. DMA active cycle: when the DMA service takes place.

8257 Pin Configuration
Data bus (D0 – D7) – are bidirectional tri-state signals connected to the system data bus.
Address bus (A0 – A3 and A4 – A7) A0 – A3 are bidirectional tri-state signals.
Address strobe (ADATB) – this is used to demultiplex higher byte address and data using external latch. It
functions like ALE in 8085.
Address Enable (AEN):
it is active high. It enables 8-bit latch containing upper 8 address bits onto the system address bus. It is used to
take control of the address bus from the CPU.

Memory Read (MEMR):
It is used to access data to the addressed memory location during DMA write or memory to memory transfer.
Memory Write (MEMW):
It is used to write data from the addressed memory location during DMA read or memory to memory transfer.
I/O Read (IOR) and I/O Write (IOW)
In idle cycle, they are input signal used by the CPU to read/write the control registers.
Chip Select (CS):
Used to select 8257 as an I/O device during the idle cycle. It allows the CPU to communicate with 8257.
Reset:
It clears the command, status, request and temporary registers. It also clears the first/last flip-flop and sets the
master register. After reset, the device is in the idle cycle.
Ready:
This input is used to extend the memory read and write signals from the 8257 to interface slow memories or
I/O devices.
Hold Request (HRQ):
Any valid DREQ causes 8257 to issue a HRQ. It is used for requesting the CPU to get the control of the system
bus.
Hold Acknowledge (HLDA): from the CPU indicates that the CPU has relinquished control of the system bus.
DREQ0 – DREQ3: These are DMA request lines from I/O devices.
DACK0 – DACK3: Are used to indicate peripheral devices that the DMA request is granted.
Terminal Count (TC):
It is concerned with the completion of DMA service. It is activated at the end of DMA service. i.e. when the
present cycle is a last cycle for the current data block.
MARK: This output notifies the selected peripheral that the current DMA cycle is the 128th cycle since the
previous MARK output.
A DMA controller contains the following blocks:

 DMA channels
 Data bus buffer
 Read/Write logic
 Control logic
 Mode Set Register
 Status Word Register.

Block Diagram of 8257 DMA Controller.
DMA Channels
8257 has four identical channels: CH0 to CH4. Each channel has two sixteen bit registers:
i. DMA address register
ii. Terminal count register
DMA address register
It specifies the address of the first memory location to be accessed.
A14 A13 A12 A11 A10 A9 A8 A7 --- A0
Terminal count register:

It specifies the number of DMA cycles minus one before the terminal count output is activated. The most
significant two bits specifies the type of DMA operation.
T1 T0 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

T1 T2 Type of operation
0 0 DMA verify cycle
0 1 DMA write cycle
1 0 DMA read cycle
1 1 illegal
Priority Resolver
It resolves peripheral requests. We have two modes of priorities:
i. Fixed priority mode
Channel 0 has the highest priority and channel 3 has the lowest.
ii. Rotating Priority mode

The priority of channels has a circular sequence. The channels being serviced gets the lowest priority and
the channel next to it gets the highest priority.
DMA Mode of data transfer:
During the DMA active cycle, data is transferred in the following modes:
i. Burst mode/ Block transfer mode:
In this mode, the entire block of data is transferred in one contiguous sequence. Once the DMA controller is
granted access to the system bus by the CPU, it transfers all the bytes of data in the data block before releasing
control of the system buses back to the CPU.
Disadvantages:
It renders the CPU inactive for long periods of time
ii. Cycle stealing mode/ Single transfer mode

It is used in systems in which the CPU should not be disabled for the length of time. In this mode, the DMA
controller obtains access to the system bus the same way as in burst mode, using bus request and bus grant
signals. However, after one byte of data transfer, the control of the system bus is deserted to the CPU via bus
grant. It is then continually requested again via bus request, transferring one byte of data until the entire block
of data has been transferred. This mode is useful in controllers that monitor real time.
iii. Transparent mode/ Hidden DMA data transfer mode:

The DMA controller transfer data only when the CPU is performing operations that do not use system buses.
Advantages:
The CPU never stops executing its programs.
Disadvantages:
It is complex: since the hardware needs to determine when the CPU is not using system buses.
Possible kinds of transfer:

i. Peripheral to memory
ii. Memory to peripheral
iii. Peripheral to peripheral
iv. Memory to memory.

6.0 INTERFACING DEVICES
Functions of an I/O interface:
i. Synchronization of speed of I/O with that of CPU.
ii. Format data e.g. serial – to – parallel and vice versa, digital to analog etc.
iii. Voltage level conversions. E.g. from high voltage to low level and vice versa.
Modes of data transfer:
There are two basic modes:
i. Parallel ii. Serial
Parallel data transfer:
Multiple bits are sent simultaneously on different channels. They are synchronous.
0 0
1 1
2 2
: :
7 7
An example is data between a computer and a printer.
Advantages
 Fast
Disadvantages
 It support short distance
 Uses more wires hence costly.
Serial transmission
One bit is transferred at a time over a single line. It is used for long distance transmission.
Advantages
 It uses less number of wires hence cheaper.
 It supports long distance data transmission.
 Simple interface since it uses less wires.
Disadvantages
 Slower speed of transmission.
Serial communication occurs either in the following two formats:
 Synchronous
 Asynchronous
In synchronous format, a receiver and a transmitter are synchronized.

In asynchronous format, timing signals are added to each character of data. It is generally used for low
speed transmission.
Serial mode of data transfer can be divided into three groups namely:
i. Simplex method
ii. Half duplex method
iii. Duplex (full duplex) method.
Simplex mode:
Data flows on a single channel only in one direction. (Unidirectional). E.g. in radio and TV.
Transmitter Receiver
Channel
Half Duplex mode

Data flow on a single channel in both directions but not simultaneously. E.g. in walky – talky
Duplex mode:
Flow of data takes place in both directions at the same time through two different channels. E.g. mobile phone.
Universal Asynchronous Receiver Transmitter:

It consists of:
 A serial receiver (Rx) – to receive serial input and to convert it to parallel data format and store in
receiver data register (RxDR) for transmission to the microprocessor.
 A serial transmitter (Tx) – to receive parallel data from the transmitter data register (TxDR) and to
convert it to serial form for transmission to serial I/O device.
 Bidirectional data bus buffer to pass parallel data from the microprocessor to the TxDR or from the
RxDR to the microprocessor system bus.
 Externally applied clock inputs; RxCLK and TxCLK.
Block diagram of UART

Microprocessor
Serial I/O devices
Data Sssss Recei

Receiver
RxDR
Bus Rx Serial
Buffer data
TXDR
Transmitter
Tx
Interfacing UART with 8085 Microprocessor
Rx/Tx Rx/Tx
Rx/Tx Rx/Tx
Intel TxC/RxC TxC/RxC
UART
8085 Reset Reset
µP CLK CLK
RD RD
WR WR
D0 D0
D7 D7
CLK CLK
How data is transmitted:

The transmitter accepts parallel data from the microprocessor and converts them into serial data.
The data is buffered to hold 8-bit data and the receiver accepts serial data converting it into parallel data.
UART performs asynchronous serial data communication.
RS 232C Standard
It is used for serial asynchronous data transmission:

a. Over telephone lines equipped with modems
b. In digital systems in which the total cable distance is less than 50ft.
RS 232C connector has 25 pins. It uses three wires for data transmission. All other wires (22) are used
for control purposes.
Transmitted data
DTE Pin 2 2 DCE
Received data
Data 3 3 Data
Terminal Communication
Signal Ground
Equipment 7 7 Equipment1st Ed.
© N. Koech 2021 Microprocessor Systems
IEEE 488 Standard
It is a document that indicate the rules and specifications that an instrument connected to the bus must adhere to.
It consists of 16 lines. The lines are divided into three groups:
1. Data lines (8) – carry data, address and universal commands.
2. Hand shake lines (3) – are required because of asynchronous nature of operation of the bus.
3. Bus management lines (5) – ensure an orderly flow of data across the bus interface.
There are four categories of instruments that can be connected to an IEEE 488 bus. These are:
1. Listeners: are those instruments which receive data. E.g. a printer or a recorder.
2. Talkers: send data to listeners e.g. a digital voltmeter.
3. Talkers/listeners: are able to receive or send data. E.g. digital multi-meter, network analyzers etc.
4. Controllers: Manages all operations of the instrument connected to it and direct data flow from one to
another. E.g. a computer or a programmable calculator
Block diagram of IEEE 488 bus connected system.

7.0 TOOLS IN ASSEMBLY LANGUAGE PROGRAMMING
The software tools used by a programmer in system development includes:
i. Editor iv. Linker vii. Simulator
ii. Assembler v. Loader viii. Emulator
iii. Compiler vi. Debugger
Text editor
It is a software program used to create/type, modify source programs. It runs interactively with the user. It is
used for making corrections during program development. It helps the user to construct an assembly language
program in the right format.
Assembler
It is a program that converts assembly language instruction into corresponding machine language instruction.
It also assigns appropriate values to labels and symbols. It also checks syntax errors and provide error messages.
It enables software application developer to access, operate and manage a computer’s hardware architecture and
components.
Assembly language Assembler Machine language
Types of assemblers
i. Load and go iv. Macro-assembler vii. Meta-assembler
ii. One pass v. Cross assembler
iii. Two pass vi. Resident assembler
Load and go assembler
It is the simplest assembler program. It accepts as input a program whose instructions are essentially one to one
correspondence with those of the machine language, but with symbolic codes used for op-codes and operands.
The output of the assembler is the machine language, which is loaded directly in memory and executed.
One pass module assembler
This assembler goes through an assembly language program once and translates it into a machine language
program. It is suitable for small machines.
Two pass module assembler
It scans an assembly language program twice. In the first pass, it creates a symbol table (consists of labels and
addresses assigned to them). On the second pass, the assembler translates the assembly language into machine
code. It is more desirable and much easier to use.
Macro-assembler
It translates a program written in macro-language into machine language.
A macro is a group of instructions that perform one task.

Cross assembler
It is an assembler which converts instructions into machine code for different types of CPU than the one the
assembler in running on. It is usually written in higher level language.
Resident assembler
It assembles programs for a processor in which it is resident. It may slow down operation of the processor on
which it runs.
Meta-assembler
It can assemble programs for many different types of processors.
Compiler
It is a program used to translate a source program (mostly in high level language) into a complete machine code
(object code) program before execution.
It will also check syntax errors and provide error messages.
Linker/ Linkage editor
It is a program that joins smaller executable programs together to form a large program. It also links subroutines
with the main program. It creates a memory map where the linked object modules will be loaded in memory.
Loader
It is a program that places programs into main memory and prepares them for execution.
Locator
It is a program that locate memory locations and carries out loading. Usually loader, locator and linker are
combined together and called a loader.
Debugger
It is a program used to find errors (bugs) in other programs and debug (correct/fix) the errors.
It allows a programmer at any point to examine and change the values of variables.
Simulator
It is a program which run on the development system to simulate the operation of a newly designed system. It
executes a program and display the results. It can be used to evaluate the performance of a microprocessor
which is absent.
Emulator
It is a combination of hardware and software. It tests the hardware and software of a newly designed program.
Summary of assembly language development tools:

1. First step: define the problem carefully.
2. Develop algorithm of the program.
3. Make the source file with the help of editor and assembler.
4. Remove all errors, if no error, link the programs with the help of linker and locator.

5. Load the emulator and debugger
6. Run the program.
Flow chart for assembly language development tools:
Start
Define problem
Develop algorithm
Make source file with

Correct the errors editor and assembler
Any
error?
Link the program
External
system?
Load debugger Load emulator
Test and run the Test and run the

program program
Any
error?
Use emulator
Use debugger tools for errors
tools for errors
Stop

8.0 CONTROL STRUCTURES
The main purpose of the control unit is to translate or decode instructions and generate appropriate enable
signals to accomplish the desired operation. The control unit performs two basic operations:
i. Instruction interpretation ii. Instruction sequencing
Instruction interpretation
The control unit reads (fetches) an instruction from the memory address by the contents of the program counter
into the instruction register.
The control unit inputs the contents of the instruction register it recognizes the instruction type, obtains the
necessary operands and routes them to the appropriate functional units (registers and ALU).
The control unit then issues the necessary signals to execution unit to perform the desired operation and routes
the results to the destination specified.
Instruction sequencing
The control unit generates the address of the next instruction to be executed and loads it into the program
counter (PC).
Control unit design

There are two methods of designing a control unit:
i. Hardwired control ii. Micro programmed control
Hardwire control
The circuit is built by physically connecting components such as gates and flip flops. Synchronous sequential
circuit design procedures are used in designing the control unit. The general hardwired control unit organization
is shown below:

Advantages of hardwire control
i. Very fast in execution
ii. Compact and small in size.
Disadvantages
i. Once implemented, no alterations can be effected.
ii. Expensive.
Micro-programmed Control / Firmware
The control instructions are store in ROM/EPROM inside the control unit. This memory is called the control
memory. The words in this memory are called control words.
The control words specify the control functions to be performed by the control unit. The control words are
fetched from the control memory and the bits are routed to appropriate functional units to enable various gates.
An instruction is thus executed. The general micro-programmed control unit organization is shown below:
Advantages of micro-programmed control

i. Flexible: alteration can be made simply by changing the micro-program in the control memory.
Disadvantage:
i. It is more expensive than using hardwire control.
ii. Slower than hardwire control; since the contents of the control memory must be read.
9.0 MICROCOMPUTER DEVELOPMENT SYSTEMS
While designing a µP based system, two design aspects have to be kept in mind:
i. Hardware design
ii. Software design
The two aspects can be done concurrently to save time.
Flow chart showing microprocessor system development stages.
User requirements
Product specification
Software specification Hardware specification
Software development Hardware development
Simulation tests Circuit tests
In - Circuit Emulation
ICE
Implementation
(Prototype tests)
The designer will get the system requirements from the client.
From the requirements, he will come up with the product specifications. This will consist of both hardware and
software specifications. The development of both hardware and software are done simultaneously.
In-circuit emulation (ICE) is crucial as it provides the necessary support to help in testing either hardware
and/or software development before the prototype board is ready for testing.

Hardware design
It consist of selecting suitable devices to meet the system requirements. E.g. memory capacity, timing, power
rating, speed etc.
These devices are interconnected together using a breadboard for testing. The final circuit is built on a printed
circuit board (PCB).
Microprocessor Development System (MDS)
It is a laboratory equipment that consist of peripherals, large capacity memories, mass storage medium e.g.
floppy disks, printers, CRT etc.
It is very costly.
It also provide facility of software debugging.
Other hardware design aids
 Teletype writers: comprises of a keyboard, printer etc.
 Floppy disks
 Compact disks
 Pen drives
 Magnetic tapes
EPROM programmer:
It is used to ‘burn’ experimental programs into the EPROM. The IC to be programmed is inserted into the
EPROM programmer and voltage levels varied to create a logic ‘0’ or ‘1’ into each cell being programmed.
UV- eraser:
It is used to delete experimental programs on the EPROM. It produces ultra-violet light which is shone through
a window into the EPROM cells. These UV energy erases any previous program.
Software design
The software is designed in assembly language. The program is entered in a development system by means of a
keyboard, after testing the software is debugged and then translated into machine language, corresponding to
the microprocessor used in the system, by means of a cross-assembler. It is then tested on the microprocessor
system built on the breadboard.
Software development aids
They include:
 Assembler/cross assembler
 Emulator
 Compiler
 Debugger
 Loaders
 Linkers
 Text editors etc.
In-Circuit Emulator (ICE) Board.
The ICE is designed to emulate the microprocessor being used in the system under development.
The ICE reads the program from the targeted system memory and then generates the correct bus signals during
execution.
It keeps a record in the MDS RAM of the sequence of actions of the targeted processor – which can be
examined later to locate any possible errors.
ICE substitutes the prototype CPU, memory and I/O ports at different stages of the prototype development.
Advantages / features of ICE
i. It allows downloading: programs can be transferred between software development system or
computer and the emulator.
ii. It allows resource sharing: the system under test can share emulator memory and I/O ports.
iii. It can be used as a debugging tool for troubleshooting in program.
Important debugging aids

Single stepping: - allows execution of one instruction at a time observing the results after each instruction.
Break points: permits the execution of a program in sections (segments).
Real time trace: bus operations, memory addresses and data conditions can be displayed on the screen.
In line assembly: allows the user to change data/instructions while the software is in the emulator.
Disassembly: when instructions are changed in the emulator, memories can be written in software.
Register display: register contents can be displayed after executing instructions.
Factors considered when writing a program for a microprocessor:

i. Reliability
ii. Speed
iii. Hardware cost
iv. Programming time and cost
v. Ease of use
vi. Error tolerance
vii. Extendibility
Operating system
It is a system software that manages computer hardware and software resources.
It acts as an interface between software and hardware.
Types of operating systems
 DOS
 Windows
 Linux

Functions of operating system:
i. Program execution
The operating system loads a program into memory, executes it and runs the program.
ii. Error detection
Errors may occur in the user program, CPU, memory or in the I/O devices. The OS monitors and takes action.
iii. Coordination
The OS co-ordinates in assigning, compiling, assembling the utility programs to the various users of the
computer system. It co-ordinates between I/O.

10.0 MICROPROCESSOR APPLICATIONS
Microprocessors find applications in many fields. They are used in PCs, consumer products, industrial
products and control systems.
Some of the applications includes:
i. Traffic lights
ii. Weighing machine
iii. Level control
iv. Timing etc.

11.0 MICROPROCESSOR FAULT DIAGNOSIS
There are three basic steps of fixing a digital microprocessor that has a fault:
i. Fault detection: Observe the system operation and compare it with the expected correct operation.
ii. Fault isolation: Perform tests and make measurements to isolate the fault.
iii. Fault correction: Replace the fault component, repair the fault connection, remove the shorted part etc.
Logical method of fault tracing in microprocessor based system

i. Physically inspect the system for any obvious defects and faults.
ii. Observe and measure power supply, clock, bus activity (Reset, HOLD, READY, R/W etc.).
iii. Free run system; check address bus pattern.
iv. Test memory and I/O decoders. vi. Test I/O devices.
v. Test memories: RAM and ROM
Microprocessor fault diagnosis flow chart
Start
Physically inspect the system for any obvious defects and faults
No
OK? Locate and rectify fault
Yes
Observe and measure power supply, clock,
bus activity, reset, hold, ready, R/W etc.
No
Yes
Free run system. Check address bus pattern.
No
Yes
Test memory, decoder, I/Os
No
Yes
Stop

Test equipment
Certain test equipment have been devised to enable fault to be more readily isolated in digital and
microprocessor based system. The equipment include:
1. Logic probes
It is a hand held instrument which is used to detect and indicate High and Low logic test levels in all types of
logic circuit including TTL and CMOS. Logic probes have lamp indicators. Power for the logic probe is
normally taken from the circuit under test. The probe can also be used to detect open and short circuits.
2. Logic pulser
It is a hand held instrument which is used to stimulate digital circuit by injection of controlled pulses. It can
generate a short duration pulses manually by pressing a push button. In use, the pulse tip is applied to the circuit
node and a button is pressed on the pulse body to generate the pulse. You can apply pulses at one point in a
circuit with the pulser and check another point for resulting pulses with a logic probe.
3. Current tracer
It is used to detect a changing current in a wire or a printed circuit board track without breaking the circuit. It is
normally used to locate the source of a low impedance path (short circuit).
4. Cathode Ray Oscilloscope (CRO)
It is a laboratory equipment that consist of peripherals, large capacity memories, mass storage medium and
facility for debugging. The CRT edits the input data and debugs programs.
The CRT terminal has a keyboard for inputting and the monitor may be operated in local or line mode.
In line-mode, the CRT displays the data from the computer. In local mode, the computer is disconnected from
the monitor and this terminal has its own microprocessor to control its operation.
CRO
It consists of five main parts:
i. Electron gun: Source of accelerated, energized and focused beam of electrons.
ii. Deflection system: vertical and horizontal for sweeping the beam.
iii. Fluorescent screen: consists of phosphorus layer that glows when electron beam strikes it.
iv. Glass envelop
v. Base: for amplifying electron beam.
5. Logic Analyser
It is a multi-trace digital oscilloscope designed for use with microprocessor based system. The timing
relationships of several signals can be observed with respect to a triggering event. It displays data in
hexadecimal or binary format. It has a 40 pin probe and auxiliary probe to gather information and it has a RAM
to store data from the prototype, a ROM to store instructions related to the logic analyser and a microprocessor
to monitor the data gathering. A keyboard is provided to enter data in Hex or octal format and specify
operations. It samples the real-time information at a specific trigger and stores it in its RAM to display on the
CRT.

6. Signature Analyser
It converts the serial data stream present at the intersection of logic circuits called nodes into a 4-digit code
called the signature. A signature is similar to a voltage level specified on the schematic diagram of an analogue
equipment. It is useful in troubleshooting in the microprocessor systems in the field or during production.
ROM Testing
Method 1: Using a ROM tester.

A ROM tester checks the correctness of the stored data by reading each data word from the ROM under test and
comparing it with reference ROM.
Disadvantages of the above method:

i. It requires a reference ROM for each different ROM to be tested.
ii. A failure in the reference ROM can produce a fault indication.
Block diagram
Reference
ROM
under ROM
test EN
EN
Data Ref. Data

Enable
ROM Tester
Address

Flow chart for the ROM testing
Start
Select 1st address (n = 0)
Read data byte from address n of ROM and Ref. ROM
Compare data
No Indicate fault
Do data bytes agree?
Yes
Next address No
Last address?
n = n+1
Yes
Stop
Method 2: Checksum Method

The contents of all the ROM addresses is stored in a designated ROM address when the ROM is programmed.
To test the ROM, the contents of all the addresses except the checksum are added. The result is compared with
the checksum stored in the ROM. If there is a difference, then there is a fault. If the checksums agree, then the
ROM is good.
e.g.
Address Data
0 0 0 1 0 0 1 1 0 1 0
0 0 1 1 0 1 0 0 1 1 1
0 1 0 0 0 0 1 1 0 1 0
0 1 1 0 0 1 0 1 1 0 0
1 0 0 1 1 0 1 0 0 0 1
1 0 1 1 0 0 0 0 0 1 1
1 1 0 0 1 0 1 1 0 0 1 Checksum
The checksum test can be implemented with a special test instrument or it can be written as a sub-routine
program. The ROM test routine is automatically run on system start-up.

Flow chart for a basic checksum test
Start
Set n = 0
Set sum = 0
Read address n
XOR contents of address n with previous sum.

Update sum
Next address No
Last address?
n = n+1
Yes
Read checksum address
Compare checksum with final XOR

sum of data
No
Do they agree? Indicate fault
Yes
Stop
RAM Testing
Method 1: All-0s-all-1s test (Basic test)

First 0s are written into all cells in each address and then read out and checked. Next, 1s are written into all the
cells in each address and then read and checked.
Advantages
 It can detect a cell that is stuck in either a 1 state or a 0 state.
Disadvantages
 It cannot detect a fault if two adjacent cells are shorted, (they will always be in the same state)
Method 2: Checkerboard pattern test
The RAM is checked with a pattern of 1s and 0s. The pattern is then reversed (0s and 1s) as shown below:
Address Data Address Data
0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0
0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0
0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1
(a) (b)
The procedure can be implemented with a software in microprocessor based system.
Flow chart for basic RAM checkerboard test.
Start
Store checkboard pattern at all addresses
Check all addresses
No
All ok? Indicate fault
Yes
Reverse the pattern at all addresses
Check all addresses
No
Yes
Set n = 0
Reverse the pattern in address n
Check all other addresses
No
Yes
No
Next address
Stop
Last address?
n = n+1
Yes
Stop

MICROPROCESSOR SYSTEMS NOTES - Copy-1

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MICROPROCESSOR SYSTEMS NOTES - Copy-1

Uploaded by

Copyright:

Available Formats

NATIONAL YOUTH SERVICE ENGINEERING INSTITUTE

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING

© N. Koech 2021 Microprocessor Systems 1st Ed.

© N. Koech 2021 Microprocessor Systems 1st Ed.

Register file Control bus

© N. Koech 2021 Microprocessor Systems 1st Ed.

W/R Random Access

Memory Data INX

© N. Koech 2021 Microprocessor Systems 1st Ed.

Block diagram of an input/output sub-system

Timing and control unit

i. S – Sign flag: when the MSB of result is 1, it is set to 1, otherwise it is reset to 0.

© N. Koech 2021 Microprocessor Systems 1st Ed.

Memory Input unit Output unit

© N. Koech 2021 Microprocessor Systems 1st Ed.

Features of Intel 8085 microprocessor

© N. Koech 2021 Microprocessor Systems 1st Ed.

The descriptions of various pins are as follows:

Address Bus and Data Bus

Control and Status Signals

© N. Koech 2021 Microprocessor Systems 1st Ed.

Status codes for Intel 8085

o RD (Output): RD is a signal to control READ operation. When it goes low, the

Interrupts and Externally Initiated Signals

© N. Koech 2021 Microprocessor Systems 1st Ed.

Line Location from which next instruction is picked up

RST 5.5 002C

RST 6.5 0034

RST 7.5 003C

o TRAP (Highest priority)

© N. Koech 2021 Microprocessor Systems 1st Ed.

Serial I/O Signals

VCC: +5 Volts supply

VSS: ground reference

© N. Koech 2021 Microprocessor Systems 1st Ed.

An instruction of computer is a command given to the computer to perform a specified

Opcode (Operation code) and Operand.

Instruction Word Size

1. One byte instruction

1. One-byte instruction: Examples of one byte instructions are:

o MOV A, B - Move the content of the register B to register A.

© N. Koech 2021 Microprocessor Systems 1st Ed.

MVI B, 05; 05 moved to register B.

06, 05; MVI B, 05 is in the code form.

LXI H, 2400H; Load H-L Pair with 2400H

21, 00, 24; LXI H, 2400H in the code form

Instruction Cycle = Fetch Cycle + Execute Cycle

Phases in execution of an instruction

ii. Decode Cycle

iii. Execute Cycle

© N. Koech 2021 Microprocessor Systems 1st Ed.

Basic Instruction Cycle

Fetch the next instruction Fetch cycle

Decode the instruction Decode cycle

Execute the instruction Execute cycle

Timing Diagram for Instruction Cycle

Machine Cycle and State

© N. Koech 2021 Microprocessor Systems 1st Ed.

Timing Diagram for Opcode Fetch Cycle:

Timing Diagram for Memory Read

© N. Koech 2021 Microprocessor Systems 1st Ed.

Timing Diagram for I/O Read

© N. Koech 2021 Microprocessor Systems 1st Ed.