Differential Amplifier Circuit

The BJT Differential Pair

A differential amplifier is an amplifier that produces outputs that are a function of the difference between
two input voltages. The differential amplifier has two basic modes of operation: differential (in which the
two inputs are different) and common mode (in which the two inputs are the same). The differential
amplifier is important in operational amplifiers because it is the input stage of designing op-amps.

Figure 1 shows the basic BJT differential-pair configuration. Two identical transistors, Q1 and Q2, whose
emitters are connected together, share the emitter resistor RE with another to produce two amplifiers, as
shown in Figure 1. RE is connected to a negative supply voltage − VEE. The collectors of Q1 and Q2 are
connected through resistors RC to a positive supply voltage + VCC. We can assume that the two transistors
and the collector resistances are identical. This can be achieved as this circuit is usually fabricated in IC
form; hence the components are fabricated at the same time with the same conditions. By design, transistors
Q1 and Q2 are to remain biased in the forward-active region. As we mentioned, we assume that the two
collector resistors RC are equal, and that Vi1 and Vi2 are ideal sources, meaning that the output resistances of
these sources are negligibly small.

Fig.1 Basic differential amplifier circuit.

It is customary to assign one of the two outputs of the differential amplifier as non-inverting output and the
other as inverting output. Suppose output 1 is assigned as non-inverting output, then output 2 will be
inverting output. Further, the non-inverting output is represented by the plus (+) sign and the inverting
output by the minus (−) sign.

DC Analysis
Let’s first consider the dc bias operation of the circuit of Fig. 1. With ac inputs obtained from voltage
sources, the dc voltage at each input is essentially connected to 0 V, as shown in Fig. 2. With each base
voltage at 0 V, the common-emitter dc bias voltage is

VE = 0 V - VBE = -0.7 V

The emitter dc bias current is then

It is assumed that the transistors are identically matched by careful process control during manufacturing so
that their dc emitter currents are the same when there is no input signal. Thus,

IE1 = IE2

Since both emitter currents combine through RE,

Fig.2 DC bias of differential amplifier circuit.

Based on the approximation that IC  IE, we obtain:

resulting in a collector voltage of

Next, input 2 is left grounded, and a positive bias voltage is applied to input 1, as shown in Figure 3. The
positive voltage on the base of Q1 increases IC1 and raises the emitter voltage to VE = VB - 0.7 V.

This action reduces the forward bias (VBE) of Q2 because its base is held at 0 V (ground), thus causing IC2 to
decrease. With a bit of reasoning we can see that Q1 will be on and conducting all of the current IE and that
Q2 will be off. The net result is that the increase in IC1 causes a decrease in VC1, and the decrease in IC2
causes an increase in VC2, as shown in Fig. 3.
 Fig. 3 Bias voltage on input 1 with input 2 grounded

Let us now change input 1 to negative value. Again with some reasoning we can see that Q1 will turn off,
and Q2 will carry all the current IE. The collector voltages will be VCl = VCC and VC2 = VCC — IC2RC2.

Fig. 4 Bias voltage on input 2 with input 1 grounded

Finally, input 1 is grounded and a positive bias voltage is applied to input 2, as shown in Figure 4. The
positive bias voltage causes Q2 to conduct more, thus increasing IC2. Also, the emitter voltage is raised. This
reduces the forward bias of Q1, since its base is held at ground, and causes IC1 to decrease. The result is that
the increase in IC2 produces a decrease in VC2, and the decrease in IC1 causes VC1 to increase, as shown.

If we change input 2 to negative value, again we can see that Q2 will turn off, and Q1 will conduct and carry
all the current IE. The collector voltages will be VC1 = VCC — IC1RC1 and VC2 = VCC.

From the foregoing, we see that the differential pair certainly responds to difference-mode (or differential)
signals. In fact, with relatively small difference voltages we are able to steer the entire bias current from one
side of the pair to the other.
 VEE

Fig. 5 the differential pair with a small differential input signal vi. Note that we have assumed the bias
current source I to be ideal (i.e., it has an infinite output resistance) and thus I remains constant with the
change in the voltage across it.

To use the BJT differential pair as a linear amplifier, we apply a very small differential signal (a few
millivolts), which will result in one of the transistors conducting a current of I/2+I; the current in the other
transistor will be I/2  I, with I being proportional to the difference input voltage (see Fig. 5). The output
voltage taken between the two collectors, vod, will be 2I Rc, which is proportional to the differential input
signal vi.

Modes of Signal Operation

A number of input signal combinations are possible:

1. If an input signal is applied to either input with the other input connected to ground, the operation is
referred to as “single-ended.”
2. If two opposite-polarity input signals are applied, the operation is referred to as “double-ended.”
3. If the same input is applied to both inputs, the operation is called “common-mode.”

Single-Ended Differential Input

In single-ended operation, a single input signal is applied. However, due to the common emitter connection,
the input signal operates both transistors, resulting in output from both collectors. When a diff-amp is
operated with this input configuration, one input is grounded and the signal voltage is applied only to the
other input, as shown in Fig. 6. In the case where the signal voltage is applied to input 1 as in Fig. 6, an
inverted, amplified signal voltage appears at output 1 as shown. Also, a signal voltage appears in phase at
the emitter of Q1. Since the emitters of Q1 and Q2 are common, the emitter signal becomes an input to Q2,
which functions as a common-base amplifier. The signal is amplified by Q2 and appears, noninverted, at
output 2. This action is illustrated in Fig.6.

In the case where the signal is applied to input 2 with input 1 grounded, as in Fig. 7, an inverted, amplified
signal voltage appears at output 2. In this situation, Q1 acts as a common-base amplifier, and a noninverted,
amplified signal appears at output 1.
 Fig. 6 Single-ended differential input operation (input at node 1).

Fig. 7 Single-ended differential input operation (input at node 2).

Double-Ended Differential Inputs

In double-ended operation, two input signals are applied, the difference of the inputs resulting in outputs
from both collectors due to the difference of the signals applied to both inputs. In this input configuration,
two opposite-polarity (out-of-phase) signals are applied to the inputs, as shown in Fig. 8. Each input affects
the outputs, as you will see in the following discussion. Fig. 8 (b) shows the output signals due to the signal
on input 1 acting alone as a single-ended input. Fig. 8 (c) shows the output signals due to the signal on input
2 acting alone as a single-ended input. Notice in parts (b) and (c) that the signals on output 1 are of the same
polarity. The same is also true for output 2. By applying the superposition theorem and summing both output
1 signals and both output 2 signals, you get the total output signals, as shown in Fig. 8 (d).

Common-Mode Inputs

One of the most important aspects of the operation of a diff-amp can be seen by considering the common-
mode condition where two signal voltages of the same phase, frequency, and amplitude are applied to the
two inputs, as shown in Fig. 9 (a). Again, by considering each input signal as acting alone, you can
understand the basic operation.

Fig. 9 (b) shows the output signals due to the signal on only input 1, and Fig. 9 (c) shows the output signals
due to the signal on only input 2. Notice that the corresponding signals on output 1 are of the opposite
polarity, and so are the ones on output 2.
 Fig. 8 Double-ended differential operation.

When the input signals are applied to both inputs, the outputs are superimposed and they cancel, resulting in
a zero output voltage, as shown in Fig. 9 (d). This action is called common-mode rejection. Its importance
lies in the situation where an unwanted signal appears commonly on both diff-amp inputs.

Fig. 9 Common-mode operation of a differential amplifier.

Common-mode rejection means that this unwanted signal will not appear on the outputs and distort the
desired signal. Common-mode signals (noise) generally are the result of the pick-up of radiated energy on
the input lines from adjacent lines, the 60 Hz power line, or other sources.

To summarize, in common-mode operation, the common input signal results in opposite signals at each
collector, these signals canceling, so that the resulting output signal is zero. As a practical matter, the
opposite signals do not completely cancel, and a small signal results.

The main feature of the differential amplifier is the very large gain when opposite signals are applied to the
inputs as compared to the very small gain resulting from common inputs. The ratio of this difference gain to
the common gain is called common-mode rejection.

AC Analysis
An ac connection of a differential amplifier is shown in Fig. 10. Separate input signals are applied as Vi1 and
Vi2, with separate outputs resulting as Vo1 and Vo2. To carry out AC analysis, we redraw the circuit in Fig.
11. Each transistor is replaced by its ac equivalent.

Fig. 10 AC connection of differential amplifier.

Fig. 11 AC equivalent of differential amplifier circuit.

Single-Ended AC Voltage Gain

To calculate the single-ended AC voltage gain, Vo/Vi, apply signal to one input with the other connected to
ground, as shown in Fig. 12. The AC equivalent of this connection is drawn in Fig. 13.
The AC base current can be calculated using the base 1 input Kirchhoff voltage loop (KVL) equation. If one
assumes that the two transistors are well matched, then

Ib1 = Ib2 = Ib

ri1 = ri2 = ri = re

Fig. 12 Connection to calculate AV1 = Vo1>Vi1.

Fig. 13 AC equivalent of circuit in Fig. 12.

Fig. 14 Partial circuit for calculating Ib.

With RE very large (ideally infinite), the circuit for obtaining the KVL equation simplifies to that of Fig. 14,
from which we can write
 Vi1 - Ibri - Ibri = 0

so that

Example 1

Calculate the DC voltages and currents in the circuit of Fig. 15.

Fig. 15 Differential amplifier circuit for Example 1.

Solution:
Example 2

Calculate the single-ended output voltage Vo1 for the circuit of Fig. 16.

Fig. 16 Circuit for Examples 2 and 3.

Solution:

The DC bias calculations provide

The AC voltage gain magnitude can be calculated using gain Eq.:

providing an output AC voltage of magnitude: Vo = AvVi = (87.4)(2 mV) = 174.8 mV = 0.175 V

Double-Ended AC Voltage Gain

A similar analysis can be used to show that for the condition of signals applied to both inputs, the
differential voltage gain magnitude is

where Vd = Vi1 - Vi2.

Common-Mode Operation of Circuit

Whereas a differential amplifier provides large amplification of the difference signal applied to both inputs,
it should also provide as small an amplification of the signal common to both inputs. An AC connection
showing common input to both transistors is shown in Fig. 17. The AC equivalent circuit is drawn in Fig.
18, from which we can write

Fig. 17 Common-mode connection.

Fig. 18 AC circuit in common-mode connection.

As β ≫ 1 and RE ≫ re then we can approximate the gain as

R c R c Rc
AC = = ≈
ri + 2( + 1)R E 𝛽re + 2( + 1)R E 2R E

Differential Amplifier Configuration Type Gain Equation

Rc
the single-ended input/single-ended output gain Av =
2re
Rc
The single ended input/differential output gain Av =
re
Rc
The differential input/differential output gain Av =
re
Rc
The differential input/ single-ended output gain Av =
re
R c
The common mode input/single-ended output gain AC =
ri + 2( + 1)R E
The common mode input/ differential output gain AC = 0

Fig. 19 Differential Amplifier Configuration Type.

Example 3

Calculate the common-mode gain for the amplifier circuit of Fig. 16.

Solution:

Example 4

Using the circuit of Figure 10, determine the single-ended input/differential output and single-ended
input/single-ended output voltage gains. Use the following component values: VCC =15V, VEE =-8V,
RE=10kΩ, RC=8kΩ.

Solution:

VEE − 0.7 8 − 0.7

IET = = = 0.73 mA
RE 10

IET 0.73
IET = = = 0.365 mA
2 2
26mV 26
re = = = 71.2 
IE 0.365

For the single ended output gain,

RC 8 k
AV = = = 56.18
2re 2 × 71.2 

The differential output gain is twice this value, or 112.36.

Common Mode Rejection Ratio

The component of voltage, which is identical at the two inputs, is usually an unwanted signal; therefore, the
common mode gain is made as small as possible. The parameter used to express this quality of an amplifier
is the common mode rejection ratio (CMRR). CMRR is defined as

Signal Gain (differential output)

𝐶MRR =
Common ModeNoise Gain
For the circuit shown in Fig. 20, for the differential outputs the CMRR is

Signal Gain (differential output) R C /2re

CMRR = = =∞
Common ModeNoise Gain 0
The CMRR is infinitive. For the single-ended output the CMRR is

Signal Gain (differential output)

CMRR =
Single ended output Voltage Gain

R C /2re R E
CMRR = =
R C /2R E re
To maximize the CMRR we need a large RE, without affecting the bias of the transistor. A possible solution
is the circuit shown in Fig. 21. The emitter resistor is replaced by a circuit with a transistor, T3 biased by
three resistors and the connection of the collector of T3 replaces the emitter resistor RE.

This circuit behaves as a current source, where the current required to bias the transistor T1 and T2 is set as
the collector current of transistor T3. In this circuit, any fluctuation of voltage at the collector of T3 will not
affect the biasing current. For the fluctuation of signal voltage we have what is effectively an infinite
resistance RE. This will increase the CMRR without affecting the bias for T2 and T1. Then we have an
amplifier with high CMRR, high gain, and amplification from dc to high frequencies. All these
characteristics form the basis for an ideal amplifier, which can be implemented as a unit in integrated form
and create an operational amplifier (Op-Amp).

Fig. 21 Differential amplifier with a noise source at both inputs.

Fig. 21 Differential amplifier with emitter resistance replaced by a current source.

Example 5

For the differential amplifier shown in Fig. 22, calculate the output voltage at A, VOA, output voltage at B,
VOB, and the voltage between A and B, VAB, when an input voltage of 10 mV is applied and the emitter
current is 4 mA. If a small noise signal is contained in the input signal, and it is applied to both inputs,
calculate the CMRR for a single ended output of this amplifier. State any assumption made.

Fig. 22 Circuit diagram for a long pair amplifier use in Example 18.1.

Solution:

We can assume that both transistors are identical, β ≫ 1 and the amplifier is used at room temperature of
300° K. The emitter resistance, re can be determined as

26mV 26
re = = = 6.5 
IE 4

and the voltage gain for the single output at A is

R𝐶 520
AVA = − =− = −40
2re 2 × 6.5

Then, the output voltage at output A is

VoA = AvA × Vin = − 40 x10 = − 400 mV

and the voltage gain for the single output at B is

R𝐶 520
AVB = = = 40
2re 2 × 6.5

Then the output voltage at output B is

VoB = AvB × Vin = 40 x10 = 400 mV

and the voltage gain between A and B, AVAB is

R𝐶 520
AVAB = − =− = −80
re 6.5
Then, the output voltage between A and B, VoAB is

VoAB = AVAB × Vin = −80 x10 = −800 mV

If noise is introduced into both inputs, the CMRR for the single-ended output is

Signal Gain (differential output)

CMRR =
Single ended output Voltage Gain

R C /2re R E 10 k
CMRR = = = = 1538.46
R C /2R E re 6.5 

JFET Differential Amplifier

Figure 23 shows a basic JFET differential pair biased with a constant-current source. If a pure differential-
mode input signal is applied such that vG1 = +vd/2 and vG2 = −vd/2, then drain currents ID1 and ID2 increase
and decrease, respectively.

Fig. 23 Basic JFET differential pair configuration

Fig. 24 Small-signal equivalent circuit, JFET differential amplifier

We can determine the differential-mode voltage gain by analyzing the small-signal equivalent circuit. Figure
24 shows the equivalent circuit, with the output resistance of the constant-current source and the small-
signal resistances of Q1 and Q2 assumed to be infinite. The small-signal equivalent circuit of the JFET diff-
amp is showing for the case when the current-source output resistance is infinite. A KCL equation at the
common-source node, in phasor notation, is

gmVgs1 + gmVgs2 = 0

or

Vgs1 = − Vgs2

The differential-mode input voltage is

Vd ≡ V1 − V2 = Vgs1 − Vgs2 = −2Vgs2

A one-sided output at Vo2 is given by

Vo2 = −gmVgs2 RD = −gm (−Vd/2) RD

and the differential-mode voltage gain is

Ad = Vo2 / Vd = + gm RD / 2

If the constant-current source output resistance is finite, we can determine the basic relationships for the
differential-mode gain, common mode gain, and common-mode rejection ratio from an analysis of the
small-signal equivalent circuit. Figure 25 shows the small-signal equivalent circuit of the JFET differential
pair configuration. We assume the transistors are matched, and that the constant-current source is
represented by a finite output resistance Ro. All voltages are represented by their phasor components. The
two transistors are biased at the same quiescent current, and gm1 = gm2 ≡ gm.

Fig. 25 Small-signal equivalent circuit, JFET differential amplifier.

Writing a KCL equation at node Vs, we have

gmVgs1 + gmVgs2 = Vs / Ro

From the circuit, we see that Vgs1 = V1 − Vs and Vgs2 = V2 − Vs. The above equation then becomes
 gm (V1 + V2 − 2Vs) = Vs / Ro

Solving for Vs we obtain

V1 + V2
VS =
2 + gm1Ro

For a one-sided output at the drain of Q2, we have

Vo = Vd2 = −(gm Vgs2) RD = −(gm RD)(V2 − Vs)

Substituting equation for Vs into above equation and rearranging terms yields

1
V2 (1 + g ) − V1
m Ro
VO = −g m R D [ ]
2 + gm1Ro

Based on the relationships between the input voltages V1 and V2 and the differential- and common-mode
voltages, (Vcm = (V1+V2) /2 and Vd = V2 – V1) as given by

V1 = Vcm + Vd / 2

and V2 = Vcm – Vd / 2

gmRD gmRD
VO = Vd − V
2 1 + 2g m R o cm

We can write the output voltage in the general form

Vo = Ad Vd + Acm Vcm

Comparing the two equations, we develop the relationships for the differential-mode gain,

gm RD
Ad =
2
and the common-mode gain

gmRD
Acm = −
1 + 2g m R o

We again see that for an ideal current source, the common-mode gain is zero since Ro = ∞.

From the above two equations Ad and Acm, the common-mode rejection ratio, CMRR is found to be

Ad 1
CMRR = | | = (1 + 2g m R o )
Acm 2

This demonstrates that the CMRR for the MOSFET diff-amp is also a strong function of the output
resistance of the constant-current source.

Voltage Gain of Double-ended Differential Amplifier

If we consider the two-sided output of an ideal JFET differential amplifier and define the output voltage as
Vo = Vd2 − Vd1, we can show that the differential-mode voltage gain is given by

Ad = gm RD
and the common-mode voltage gain is given by

Acm = 0

The result of Acm = 0 for the two-sided output is a consequence of using matched devices and elements in
the diff-amp circuit.

Example 6

In the JFET differential amplifier circuit of Fig. 26, IDSS = 4 mA and pinch-off voltage VP = - 4 V.

Calculate the following:

1. DC output voltage. 2. Transconductance.

3. Gain of single-ended amplifier. 4. Gain of double-ended amplifier.

[VDS = 34 V]

Fig. 26 JFET Differential Amplifier.

Solution:
I D RD
Current through RS: KVL  VDD = + VDS + ID R S − VDD
2

4VDD −2VDS 80 − 68
ID = = = 2 mA
R D + 2R S 4 k + 2 k

1. DC voltages at drain terminals of FET devices

ID R D 2×4
VD1 = VD2 = VDD − = 20 − = 16 V
2 2

2IDSS I 2×4 2
2. Transconductance: gm = |VP |
√I D = |4|
√ = 1.414 m℧−1 = 1.414 mS
DSS 4

3. Voltage gain of single-ended amplifier Ad = + gm RD / 2 = (1.414x4)/2 = 2.828

4. Gain of double-ended amplifier Ad = gm RD = 1.414x 4 = 5.656