Total No. of Questions : 4] SEAT No.

8
23
P8498 [Total No. of Pages : 1

ic-
Oct.-22/BE/Insem-91

tat
3s
B.E. (E & TC) (Semester - VII)

7:4
02 91
VLSI DESIGN AND TECHNOLOGY

3:3
0
(2019 Pattern) (404182)

21
Time : 1 Hour]
4/1 13 [Max. Marks : 30
0
0/2
Instructions to the candidates:
.23 GP

1) Attempt Q. No. 1 or Q. No. 2 and Q. No. 3 or Q. No. 4.

E

2) Neat diagrams must be drawn wherever necessary.

80

8
C

23
3) Figures to the right indicate full marks.

ic-
4) Assume suitable data, if necessary.
16

tat
8.2

3s
.24

7:4
Q1) a) What is meant by concurrent and sequential statements in VHDL? Describe
91
49

with two examples of each. [5]

3:3
30
21

b) What is meant by synthesizable and non-synthesizable statement? Give

two example of each. [5]
01
02
0/2

c) Write VHDL code for 4:1 Mux using behavioral modeling style. [5]
GP
4/1

OR
CE
80

8
Q2) a) Write VHDL Code for full adder and its test bench. [10]

23
.23

b) Explain in brief different modeling styles supported by VHDL.

ic-
[5]
16

tat
8.2

3s
.24

7:4

Q3) a) What is Clock Skew? What are techniques to minimize it? [5]
91
49

3:3

b) Draw state diagram and write VHDL code and its test bench for sequence
30
21

detector 101. [10]

01
02

OR
0/2
GP

Q4) a) What is meant by Meta-stability? Explain any one solution in detail. [5]
4/1

b) Explain clock Distribution Techniques in detail. [5]

CE
80

c) Write Short note on Power Optimization. [5]

.23
16
8.2


.24
49