Total No. of Questions : 8] SEAT No.

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PA-938 [Total No. of Pages : 2

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B.E. (Electronics & Telecommunication Engineering)

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VLSI DESIGN & TECHNOLOGY

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(2019 Pattern) (Semester - VII) (404182)
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Time : 2½ Hours] [Max. Marks : 70
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Instructions to the candidates :

1) Solve Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
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2) Neat diagrams must be drawn wherever necessary.
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3) Figures to the right indicate full marks.

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4) Use of electronic pocket calculator is allowed.

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5) Assume sitable data, if necessary.

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Q1) a) Draw and explain the architecture of CPLD. Explain Macrocell in detail.[10]
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b) What are the technologies supported by FPGA? Explain any two of it

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detail. [8]
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Q2) a) List and Explain in brief various Simulation and Synthesis Tool. [6]
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b) Draw and Explain the following for FPGA : [12]

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i) Logic Cell
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ii) Programmable Switch Matrix

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iii) I/O Block
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Q3) a) Design CMOS logic for F = AB + C(D+E). [5]

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b) Draw 2:1 Mux using CMOS as well as TG. Comment on the savings of
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transistors using TG and CMOS method. [12]

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Q4) a) Define Scaling and Explain any one type of scaling and its effect on at
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least 4 parameters. [9]

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b) Explain the following terms : [8]

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i) Velocity Saturation
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ii) Hot Electron Effect

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Q5) a) Which Lambda rules are used for CMOS Layout? Give its significance.[6]

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b) Explain the steps involved in fabrication of CMOS transistor with suitable

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Q6) Draw the block diagram of half adder and its truth table. Draw it CMOS

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transistor level circuit. Draw Euler’s Path for both networks. Draw the stick

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diagram for sum and Carry (outputs) of HALF ADDER. [18]

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Q7) a) Explain different types of faults existing in VLSI chips. [8]
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b) Explain Controllability. Observability and Predictability in testability. [9]

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Q8) a) Explain Path sensitization method. [8]

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b) Explain JTAG boundary Scan, Explain all the pins involved. [9]
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