CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

DESIGN OF FLASH CONTROLLER USING

VERILOG

A graduate project submitted in partial fulfillment of the requirements

For the degree of Master of Science in Electrical Engineering

By

Artish R Nervatla

August 2005
The graduate project of Artish R Nervatla is approved:

Prof ,Atlmad fulrfaraz / Datl

Prof Ramin Roosta Date

Prof Geng Xiaojun, Chair Date

California State University, Northridge

II
DEDICATED

TO

MY PARENTS

iii
 TABLE OF CONTENTS

Signature --------------------------------------------------------------- ---- 11

Dedication ----------------------------------------------------------- --------- 111

List Of Tables ------------------------------------------------------------------ v1

List Of Figures ----------------------------------------------------------------- v11

Abs tract ------------- ----------------------------------------------------- x1

CHAPTER Introduction ----------------------------------------------------- 1

1.1 Memory Storage Devices ------------------------------------ 1

1.2 Verilog Programming 1

CHAPTER 2 Different Types Of Memory ------------------------------- 2

2.1 Memory In Computer -------------------------------- 2

2.2 ROM(Read Only Memory) -------------------------------- 2

2.3 Different Types OF ROM --------------------------------- 2

2.4 Description Of Memory Cell -------------------------------- 5

2.5 RAM (Random access Memory) ------------------------------ 6

CHAPTER 3 Flash Memory Description ----------------------------------- 7

3.1 Nand Flash Memory ----------------------------------- 7

3.2 General Description ----------------------------------- 8

3.3 Almy Organization And Functional Descripiton ----------- 10

3 .4 Pin Description -------------------------------------------------- 12

3.5 Nand Flash Technical Description --------------------------- 14

IV
 3 .6 Invalid Block ------------------------------------------------- 24

3.7 EITor In W1ite Or Read Operation ------------------------ 26

3. 8 Page Program ------------------------------------------------ 31

3. 9 Block Erase -------------------------------------------------- 32

3 .10 Read Stat us -------------------------------------------------- 32

3 .11 Read Id ------------------------------------------------------ 33

3 .12 Reset --------------------------------------------------------- 34

3 .13 Ready/Busy ------------------------------------------------- 34

CHAPTER 4 N and Flash Controller --------------------------------------- 35

4.1 Task ----------------------------------------------------------- 35

4.2 Description of verilog module ------------------------------ 36

Reference --------------------------------------------------------------------- 39

Appendix A --------------------------------------------------------------------- 40

Appendix B ----------------------------------------- ---------------------------- 48

Appendix C ------------------------ -------------------------------------------- 52

v
 LIST OF TABLES

3.4 Pin Description ----------------------------------------- 11

3. 5 Mode Selection ---------------------------------------- 14

3.4 AC Timing Characteristics For Command I Address 15

Data Input

3.14 AC Characteristics For Operation ------------------------ 19

3 .18 EITor In Write Or Read Operation ------------------------ 26

3.27 Status Register Definition --------------------------------- 33

3. 30 Device Status ------------------------------------------------ 34

VI
 LIST OF FIGURES

2.1 Flash Memory Cell ------------------------------------- 3

2.2 Flash Memory ------------------------------------------- 4

2.3 Circuit of Nand Gate I Nor Gate ---------------------- 4

3.1 Functional Block Diagram ------------------------------ 9

3 .2 Array Organization --------------------------------------- 9

3 .3 Pin Configuration ----------------------------------------- 10

3. 7 Command Latch Cycle ----------------------------------- 16

3.8 Address Latch Cycle -------------------------------------- 17

3 .9 Input Data Latch Cycle ----------------------------------- 18

3 .11 Sequential out cycle After Read ------------------------- 20

3 .12 Status Read Cycle ------------------------------------------ 20

3.13 Readl Operation(Read One Page) ----------------------- 21

3.14 Readl Operation (intercepted by CE) ------------------- 22

3.15 Sequential Row Read Operation ------------------------ 23

3 .16 Page Program Operation --------------------------------- 24

3.17 Flow Chart To Create Invalid Block Table----------- 25

3.19 Program Flow Chart -------------------------------------- 27

3.20 Erase Flow Chart ------------------------------------------ 28

3.21 Read Flow Chart ----------------------------------------- 29

3. 22 BI ock Replacement -------------------------------------- 29

3.23 Block Erase Operation --------------------------------- 30

Vll
3.24 Manufacture & Device ID Read Operation --------- 30

3 .25 Program & Read Status Operation ------------------- 31

3.26 Block Erase Operation --------------------------------- 32

3.28 Read ID Operation ------------------------------------- 33

3 .29 Reset Operation ----------------------------------------- 34

4.1 State Machine ---------------------------------------------- 38

Vlll
 ABSTRACT

DESIGN OF FLASH CONTROLLER USING

VERILOG

By

Artish R Nervatla

Master of Science in Electrical Enginee1ing

This project discusses the way to control the flash memory using a flash controller.
Flash controller is designed using a set of verilog codes which can be used to access the
flash devices.

IX
 CHAPTER 1

Introduction

1.1 Memory Storage Devices:

A basic computer consists of input/output devices , memory devices and cpu (central
processing unit). Memory is the an important part of a cpu. Memory is a place where all
the data ,files are stored. CPU uses some of these files when started which are called as
back up files. Main Memory of the system is called as hard drive , apart from this there
are many secondary memmies such flop drive, disk, USB etc.

1.2 Verilog Programming :

After the advent of LSI (Large scale integration) ,designer could put thousands of gate on
a single chip. This made design process complicated. So designers felt the need of
automate these processes. Computer Aided Design(CAD) techniques began evolving
The Very High Speed Integrated Circuit(VHSIC) Hardware Desc1iption Language
(VHDL) was developed in the early 1980 's under a US Depaitment of Defense(DOD)
contract. The first public release of VHDL, version 7.2 was made available in 1985and in
1987 the institute of Electrical Electronics Engineers(IEEE) approved and enhanced
versions of VHDL and released it as an IEEE Standard,IEEE 1076-1987.

VHDL was 01iginally conceived as a language to describe and document the behavior of
digital system.It can be used to describe these system at many different level.

Later in 1983 at Gateway Design Automation Verilog HDL was developed.

This became popular than the VHDL because of its similar in syntax to C programming.
It can be used to describe the system at many different levels , ranging from a purely high
level behavioral desc1iption to a detailed gate level implementation with precise timing
information .verilog has expanded to become widely used in digital circuit and system
simulation and design .

One of the most exciting developments in the use of Verilog has been its increasing use
in the synthesis of digital circuits. From a behavioral description of a circuit, it is now
possible to generate a gate -level design suitable for manufacturing integrated
circuits(IC) , in fact a single line of Verilog code can be now be used to generate a
circuit function comprising over a hundred gates.Digital circuit could be described at
register transfer level(RTL) using Verilog, this helps the designer to specify data flows
between the registers This process of describing a design in Verilog, simulating the
Verilog description and synthesizing it into gates has allowed to increase in design
productivity compared to previous standard technique of schematic design entry.

1
 CHAPfER 2

Different Types Of Memory

2.1 Memory In Computer

Memory of a computer is analogous to human brain, where most of its data is stored.

Memory is capable of retaining digital information under ce1tain conditions . This

retained mate1ial might be operational code or data files or combination of two.

2.2 ROM (read only memory)

ROM is used as a storage medium in computers , because it cannot be easily be written

to . ROMs are used in the computer because it does not loose its memory if the power is
cut off. Early microprocessors lacked the ROM ,so they had to enter the bootstrap
program or some time the whole program which the program wants to run
Its main use is in the distribution of firmware. Home computers of early 1980 came with
complete operating system in ROM. ROMs are widely used in embedded systems.

Features of ROM :
Mature, high-density, reliable, low cost, time-consuming mask required, suitable for
high production with stable code

2.3 Different types of ROMs

EPROM (erasable programmable read-only memory)

EPROM's can be erased by exposure to ultraviolet light then rew1itten with a EPROM
programmer. EPROM's are rated ink-bits where k is equal to 1024 .EPROM number
genrerally (but not always) reflects the size .Size of EPROM is always in terms of
k-bytes.
EPROM cell use floating gate technology. A floating gate is a gate with a special
capacitor which takes on an electrical charge. This quantum physics effect is called
tunneling The presence of charge determines the value (1 or 0) of the memory cell.

Most of the EPROM's have 8 data lines (bits DO-D7) forming a byte wide data bus, some
have 16data lines (bits DO-D 15) which make it a word wide data bus. Enabling both CE
and OE causes all the bits to appear on the data lines. The data of the bytes or word ,
appears on theses lines as O's (about .4 volts) or (about 4 volts ). The data lines of an
Eprom are bi-directional , they are outputs when you are reading the EPROM and input
when you are programming it. The address lines from an address bus made of inputs that
together select which location you want to read or program. Address lines start at AO the
LS (least significant) going up (Al,A2,A3 . ..) with the address space doubling in size
with each additional pin

2
Features of EPROM
High-density memory, must be exposed to ultraviolet light for erasure

EEPROM(electrical erasable programmable Read-only memory)

EPROM's are similar to EPROM but erasure is done using an electrical field instead of
UV li ght source. These EEPROM's require a programmer or special voltage to program
it.

Features of EEPROM
Elect1ically byte-erasable , lower reliability , higher cost , lowest density

Flash

A flash EPROM is similar to a EEPROM except that flash EPROM' s are erased all at
once while the regular EEPROM's can erase one byte at a time . This is possible because
no special voltage is used for erase operation , instead a special application software
routines are used.
Flash memory is a nonvolatile memory using NOR and NAND technology, which allows
the user to elect1ically program and erase information. Flash programming occurs when
electrons are placed on the floating gate. The charge is stored on the floating gate , with
the oxide layer allowing the cell to be electrically erased through the source

Features of flash memory

Low-cost , high-density , high-speed architecture , low-power, high reliability

Fig 2.1 Flash Memory:

EPROM + EEPROM Flash Memory

*Dual Po·-Ner(5V and ·12V) *Single Po·i ver(3.3V or 5V) "' Single 1Jr Dual Power
* Removal by ultraviolet * removal by eledricity * remova l by electricit y
* ·1Tr ·1 Cell "' 2Tr 1 Cell " ·1Tr1 Cell

The above gives a better picture of features of an flash memory. The flash memory
Have features that of an a EPROM and EEPROM. The flash memory can use dual power
As that of EPROM or single power that of EEPROM.
Flash memory is made of either NOR or NAND gates. The names refer to the type of
logic gate used in each storage cell. In NAND flash memory the inputs A and B are
connected parallel ,where as in NOR flash memory they are connected in se1ies.

3
Fig 2.3 Circuit of Nand Gate and Nor gate

NANO Gate sv NOR Gate 5V

GND

Nor flash memory : NOR flash memory was first developed by intel in 1988. This is used
to for instruction storage and execution . the life span is about lOOk w1ite cycles .erasing
and writing takes several seconds, but reading is fast.

Fig 2.4 Flash Memory Cell

Individual ETOX™
Flash Memory Cell

Wordline

00 Bitlin e
Tunnel Oxide

Drain
n+

P - Substrate

4
2.3 Descripiton of Flash Memory Cell

In NOR flash each cell looks simj Jar to a standard Mosfet transistor , except that it has
two gates instead of ojust one. One gate is the control gate (CG) like in other MOS
transistor , but the second is a floating gate (FG) that is insulated all around by an oxide
layer as shown in the above fig. The FG is between the CG and the substrate. Because the
FG is isolated by its insulating oxide layer , any electrons placed on it get trapped there
and thus store information.(ref figure 2.4).

When electrons are on the FG, they modify (partially cancel out) the electric field corillng
from the CG, which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is
"read" by placing a specific voltage on the CG, electrical current will either flow or not
flow, depending on the V 1 of the cell, which is controlled by the number of electrons on
the FG. This presence or absence of current is sensed and translated into l's and O's,
reproducing the stored data. In a multi-level cell device, which stores more than 1 bit of
information per cell, the amount of cmrent flow will be sensed, rather than simply the
presence or absence of current, in order to determine the number of electrons stored on
the FG.

A NOR flash cell is programmed (set to a specified data value) by starting up electrons
flowing from the source to the drain, then a large voltage placed on the CG provides a
strong enough elect1ic field to suck them up onto the FG, a process called hot-electron
injection. To erase (reset to all l's, in preparation for reprogramming) a NOR flash cell, a
large voltage differential is placed between the CG and source, which pulls the electrons
off through Fowler-Nordheim tunneling, a quantum mechanical tunneling process. Most
modern NOR flash memory components are divided into erase segments, usually called
either blocks or sectors. All of the memory cells in a block must be erased at the same
time. NOR programming, however, can generally be performed one byte or word at a
time.

NAND flash memory:

NAND flash memory was developed by Samsung and Toshiba in 1989. It has faster erase
and write times higher density and lower cost per bit that NOR flash .NAND flash uses
tunnel injection for w1iting and tunnel release for erasing. However its I/O interface
allows only sequential access to data. This makes its suitable for mass-storage device
such as PC cards and various memory cards.

5
2.4 RAM(random-access memory):

RAM refers to read and write memory,since we can read and write to the memory easily.
Most RAMs are volatile, which means it requires a steady flow of electricity to maintain
its contents. As soon as the power is turned off, the date on the RAM is lost

SRAM(static random-access memory)

Static RAM does not need to be refreshed, which makes it faster and it's also more
expensive than dynamic RAM
Features of SRAM
Highest speed, high-power , low-density memory , limited density drives up cost

DRAM(dynamic random access memory)

Dynamic memory needs to be refreshed thousand of times per second
Features of DRAM
High-density , low-cost , high-speed , high-power

6
 CHAPfER 3

Flash Memory Description

3.1 Nand Flash Memory:

Use of Nand flash memory is growing very rapidly because of its density, performance
and cost. Nand flash memory is now widely used in most of the multimedia system
products. Because of it large storage capacity it is widely used in digital cameras ,
camcorders, PDAs, MP3 players, digital consumer equipment including 30 cell phone,
and removable storage media like USB disk and Flash Cards.

The following are the characters of Nand flash memory :

The performance character of Nand flash memory are fast write (or program) speed and
fast erase speed. For high performance data storage requirements , such as storing digital
photos , downloading music and other advanced features popular in today's cell phone
the write /erase speed of Nand provide a distinct performance advantage

Illustrating the performance of Nand and Nor flash devices , for example To erase a
64 KB unit of memory , Nand requires 17 milliseconds and Nor requires 2.4 seconds. In
system application , this difference is large enough to bring down the system performance
considerably.
Although Nor flash offers a slight advantage in random read access time, Nand offers
significantly faster program and erase time.

Nand flash memory is reliable for its eITor cotTecting code(ECC) and controller which
maps around bad memory areas. All controllers for Nand flash have a built in ECC to
automatically coITect bit eITors

Nand flash memory can be accessed through command sequences instead of direct
application of an address to the address lines. Nand has indirect or I/O like access. Nand
flash also has internal command, address and data registers . Most of the Nand flash can
be integrated into the system by using Nand controllers and software drives.

Interface the Nand flash using other devices appears to be cumbersome than direct
interface of Nor flash , but we would have great advantage in ease upgrading to a higher
chip density.
The maximum available density for a MLC (multi level cell) Nor is 256MB ,where as
for a MLC Nand flash is cuITently 4Gb, and highest capacity available for SLC Nand is
2GB.

7
3.2 General Description

The K9F1608WOA is a 2M(2,097,152)x8bit NAND Flash Memory with a spare

64K(65,536)x8bit. Its Nand cell provides the most cost-effective solution for the solid
state mass storage market. A program operation programs the 264-byte page in typically
250µs and an erase operation can be pcrfo1med in typically 2ms on a 4K-byte block. Data
in the page can be read out at 80ns cycle time per byte. The I/O pins serve as the ports for
address and data input/out-put as well as command inputs. The on-chip write controller
automates all programs and erases system functions, including pulse repetition, where
required, and internal verify and margining of data.

The write-intensive systems can take advantage of the K9F1608WOA extended reliability
of 1,000,000 program/erase cycles by providing either ECC(Error Correction Code) or
real time mapping out algorithm . These algorithms have been implemented in many mass
storage applications and also the spare 8bytes of a page combined with the other 256
bytes can be utilized by system-level ECC. The K9F1608WOA is an optimum solution
for large nonvolatile storage application such as solid state storage, digital voice recorder,
digital still camera and other portable applications requiring no volatility.

Features:

Voltage supply: 2.7V - 5.5V

Organization
Memory Cell Array : (2M + 64K)bit x 8bit
Data Register : (256 + 8)bit x 8bit
Automatic Program and Erase
Page Program: (256 + 8)Byte
Block Erase : (4K + 128)Byte
264-Byte Page Read Operation
Random Access: lOµs(Max.)
Serial Page Access: 80ns(Min.)
Fast Write Cycle Time
Program time : 250µs(typ.)
Block Erase time : 2ms(typ.)
Command/Address/Data Multiplexed I/O port
Hardware Data Protection
Program/Erase Lockout Dming Power Transitions
Reliable CMOS Floating-Gate Technology
Endurance: IM Program/Erase Cycles
Data Retention : lOyears
Command Register Operation
44(40) - Lead TSOP Type II (400mil/0.8mm pitch)
Forward Type

8
Fig 3.1 Functional Block Diagram

Aa - Ai o X-Buffers ~

- Latches
& Decoders
16M + 512K Bit
NAND Flash
ARRAY
Ao-A1 Y-Buffers
Latches 1-
(256 + 8)Byte x 81 92
& Decod ers

L ..___.
Page Reg ister & SIA
Y-Gating
Co mmand •
.I
·1 Com mand
-
~
1/0 Buffers & Latches

rr=
Register '

~:
VccQ
Vss
CE Co ntrol Logi c
,_ '
RE & High Vo ltage , _ _I --.110 0
WE Generator Global Buffers
I 110 7

i i i
CLE ALE WP

Fig 3.2 Amiy Organization

·1 Block(=16 Row)
/ (4K + 128)Byte

1 Page = 264 Byte

1 Block = 264 B x -is Pages
16M : 8K Row = (4K + 128) Bytes
(=51 2 Block) ·1 Device= 2648 x ·16Pages x 5·12 Blocks
"If----- = 16.5· Mbits
\' +-----------+--f ·a bit
. . . __ ----- 2568 Column _______ . . .BB Column

,_,_____ _ _ Page Register - - - , - --!<-

----- - 256Byte ____ __, SByte

1/00 1/01 1/02 1/0 3 1/04 1/0 5 1/06 1/0 7

·1st Cycle Ao A1 A2 Ai A4 A5 Ao A1 Column Address
2nd Cycle AB Ag A10 A11 A i2 A1 3 Ai 4 A 5 Row Address
(Page Address)
3rd Cycle A 1a A11 Aie Aig A20 ·x ·x ·x
NOTE : A 12 to A20 : Block fl.ddress .. : X can be V1L or Vin.

9
3.3 Aarry Organization And Functional Description

The K9F1608WOA is a 16.5Mbit(l 7,301,504 bit) memory organized as 8192 rows by

264 columns . Spare eight columns are located from column address of 256 to 263. A
264-byte data register is connected to memory cell arrays accommodating data transfer
between the IJO buffers and memory during page read and page program operations. The
memory array is made up of 16 cells that are serially connected to form a NAND
structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array
organization is shown in Figure 3.2. The program and read operations are executed on a
page basis, while the erase operation is executed on block basis. The memory airny
consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by
bit erase operation is prohibited on the K9F1608WOA (refer to fig 3.2).

The K9F1608WOA has addresses multiplexed into 8 I/0¢s. This scheme dramatically
reduces pin counts and allows systems upgrades to future densities by maintaining
consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE.
Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex
command and address respectively, via the IJO pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and
another for erase-execution after block address loading. The 2M byte physical space
requires 21 addresses, there by requiring three cycles for byte-level addressing : column
address, low row address and high row address, in that order. Page Read and Page
Program need the same three address cycles following the required command input. In
Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register.
Table 1 defines the specific commands of the K9F1608WOA

10
Fig 3.3 Pin Configuration

V&-?. ~ 210
CL=
44 ~ Vcc
43 GE
AL E 42 R~
WE 41
WP 4{)
·LC 2..g
N .C 38
N.C 37
N.C 3'6
·LC 35
34
33
N .C 32
·LC 31
LC 30
·LC w
LC 28
1100 27
1101 2e
1102 25
1/03 24
VS'J 23

44(40) TSOP (II)

STAN OAR D TYP E

Fig 3.4 Pin Description

Pin Name Pin Fun ct ion

1/00 - 1/07 Data Inputs/Outputs
CLE Com m~m d Latch Enable
ALE Add ress Latch Enable
CE Chip Enable
-
RE Read Enable
-
WE Write Enable
WP Write Protect
GND Ground Input
-
R/8 Ready/Busy output
Vee Power(2.7V-5 .5V)
VceQ Output Butter Power( 2.7V-5 .5V)
Vss Ground
N.C No Con nection

11
3.4 Pin Description

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register.
When active high, commands are latched into the command register through the I/O ports
on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the path activation for address and input data to the internal
address/data register.
Addresses are latched on the rising edge of WE with ALE hi gh, and input data is latched
when ALE is low.

Chip Enable(CE)
The CE input is the device selection control. When CE goes high dming a read operation
the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is
ignored, and does not return the device to
standby mode.

Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on
the rising edge of the WE pulse.

Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O
bus. Data is valid TREA after the falling edge
of RE which also increments the internal column address counter by one.

1/0 Port : 1/0 0 - 1/0 7

The I/O pins are used to input command, address and data, and to outputs data during
read operations. The I/O pins float to high-z
when the chip is deselected or the outputs are disabled.

12
Write Protect (WP)
The WP pin provides inadvertent write/erase protection during power transitions. The
internal high voltage generator is reset when
the WP pin is active low .

Ready/Busy(RIB)
The RIB output indicates the status of the device operation. When low, it indicates that a
program, erase or random read operation is
in process and return to high state upon completion. It is an open drain output and does
not float to high-z condition when the chip is
deselected or outputs are disabled.

Power Line(VCC & VCCQ)

The VCCQ is the power supply for I/O interface logic. It is electrically isolated from
main power line(VCC=2.7-5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.

13
3.5 Nand Flash Technical Descriptions

Fig 3.5 Mode Selection

CLE ALE CE WE RE WP Mode

H L L l-S H x Comm~rnd Input
Read Mode
L H L Lr H x Address lnput(3clock )
H L L l__f" H H Command Input
Write Mode
L H L l-S H H Add ress lnput(3clock)
L L L LS H H Data Input
L L L H t.___J x Sequential Read & Data Ou tpu t
L L L H H x During Read(Busy)
x x x x x H During Program(Busy)
x x x x x H During Erase( Busy)
x XP l x x x L Write Protect
x x H x x OVNcc12> Stand-by

The above figure 3.5 shows the status of the pins when the operations are set to be
pe1formed.
For example for a Nand flash controller to do a read operation the pins CLE must be
high, ALE must be low ,-CE (CE not) must be low, -RE (RE not) must be high and
-WE (WE not) must have a rising edge, similarly for write operation ALE should be low
with other pins status same as read mode.

Similarly for other mode of operations such as data input , sequential read & data output,
Read busy ,program busy ,erase busy, w1ite protect and stand by, the following setting
should be performed.

14
F.1g 36 ACTlllllilg
. Charactens
. f1cs For Command I Address I Data Input
Pnrnmeter Symbol Min Mnx Unit
CLE Set-up Time tCLS 20 - 115
CLE Hold Time lCLH 40 - 115
CE Setup Time tcs 20 - ns
CE Hold Time ICY 40 - ns
WE Pulse Width t\NP 40 - 115
ALE Setup Time IAL5 20 - 115
ALE Hold Time tALH 40 - 115
Data Setup Time tos 30 - ns
Data Hold Time !OH 20 - ns
Write Cycle Time twc BO - ns
WE High Hold Time lWH 20 - ns

The above figure 3.6 gives the symbolic representation of the pins and their minimum
time in nanoseconds for which the opertions can respond.(refering to fig 3.11)
CLE set up time - Tels is the time measured from change of state of CLE to the falling
edge of-WE.
CLE hold time - Tclh is the time measured from rising edge of the -WE to the change of
stateof CLE ..
-CE set up time - Tes is the time taken from falling edge of -CE to falling edge of -WE
-CE hold time - Tch is the time taken from rising WE to the falling edge of -CE
-WE pluse width -Twp is time between falling edge to rising edge of -WE
ALE set up time - Tals is the time taken from change of state on ALE to the falling edge
of-WE.
ALE hold time - Talh is the time taken from 1ising edge of -WE to change of state of
ALE.
Data setup time - Tds is the time taken between the data out on input/output bus to the
rising edge of -WE .
Data hold time - Tdh is the time taken between the rise of -WE to completion of data on
to the input/output bus

Write cycle time -Twc is the time taken for a complete cycle of -WE ie fall edge to the
next falling edge.
-WE high hold time -Twh is the time between the 1ising edge to the falling edge of
-WE

15
Fig 3. 7 Command Latch Cycle

CLE
------~ ~ICLS
t
ICL H_.j ~------------

tcs !CH
CE

IWP
WE

l ALS lA LH
ALE

rtos- - .--to· 1
~--------~X command~~------------~
110 0 - 7

The above figure 3.7 gives the timing diagram of command latch cycle. It shows timing
sequence when the command is pushed on the input/output bus.
For the command instruction to be out on input/output bus , we need to have CLE
high,-CE low and ALE low.-WE is used to calculate data set up time Tds and data hold
time Tdh. According to the specifications give the Tds is set up to 30ns and Tdh is set up
to be 20ns.

16
Fig.3.8 Address Latch Cycle

------ 1 4---tCL.S ~
CLE

tcs-- - 1 - - - twc------>- twc

CE

WE

lALS lALH

ALE

tos toH IDS• !DH

110 0 ' 7 A o-A7 A1 6-A20

The above timing diagram 3.8 shows the timing sequence of address latch bus. Similar to
data latch cycle, the manfactures gives the timing sequence when the address bits can be
pushed on the input /output bus . As shown in the above fig for the address to be on the
input /output bus ,we need to have the CLE low, -CE low, and ALE must be high. And
depending on timing - WE the address bits are poped out on to the input/output bus.

17
Fig .3.9 Input Data Latch Cycle

CLE

le
CE

- ---,]- to.Ls twe

ALE

WE

• IDS lDH
IDS

1/0 0 .. 7 DIN 0 DIN 255

The above figure 3.9 gives the timing sequence for the input data flash controller can be
on the input/output bus.
Similar to that of address and command latch, for the data that has to be input for flash
controller can be on input/output bus, if CLE is low ,-CE is low and ALE is also low.
And depending on timing sequences of -WE Tds and Tdh is calculated.

18
Fig 3.10 AC Characteristics For Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 10 ps
ALE to RE Delay IA« 150 - 115

ALE to RE Delay(read ID) IAR1 200 - ns

CE to RE Delay( ID read) !CR 200 - 115

Ready to RE Low !RR 20 - 115

WE High to Busy tl\18 - 200 115

Read Cycle Time tRC 80 - 115

RE Access Time lREA 45' ,ns
RE High to Output Hi-Z tRHZ 5 20 115

CE High to Output Hi-Z tCHZ - 30 ns

RE High Hold Time !REH 20 - 115

Output Hi-Z to RE Low t1R 0 ns

Last RE High to Busy( at sequenti al read) !RB - 200 ns
CE High to Ready(in case of interception by CE at read)!'l !CRY 1OO+tr( RIB )t2l ns
CE High Hold Time(at the last serial read)i31 ICEH 250 - 115

RE Low to Status Output tRSTO - 45 ns

CE Low to Status Output !CSTO 55 115

RE High to WE Low IRHW 0 - ns

WE High to RE Low l'NHR 50 - ns
Device Resetting Time(Read/Program/Erase) tRST 51101500 ~IS

The above table 3.10 illustrates the timing symbols , minimum and maximum time for the
operations to be perfomated by the flash memory after it receives the instructions from
the flash controller.

19
Fig 3.11 Sequential Out Cycle After Read

IRC---+<
CE ICHZ'
~-------+-----,-R-EH--+-----------~1

RE
- - - - --.i ~r I rJ lf---a-\)~j f-l--+-----~

110 0' 7

!RR
Dout Oout J Do~d-
R/8

The above figure3.11 gives the timing sequence when the data can be out from the flash
memory to controller .when data is out on input/output bus then the R/-B (ready /busy)
Will be high , showing an operation is being performed ie data from flash memory is
written on to falsh controller

Fig 3.12 Status Read Cycle

The above timing diagram 3.12 gives the timing sequence when the read operation can be
pe1iormed by the flash memory.

20
Fig 3.13 Readl Operation(Read One Page)

CLE

ALE

RE

1/0 0 - 7

RIB

The above figure 3.1 3 gives the timing sequence for reading one page by the flash
memory.

21
The following timing diagram gives the different types of read operations to be perfomed
by the flash memory

Fig 3.14 Readl Operation (intercepted by CE)

CLE

CE

WE
!C HZ
!AR

ALE

tR

RE
!RR

1/0 0 - 7

R/B Busy

22
Fig 3.15 Sequential Row Read Operation

CLE

CE

WE

ALE

RE

)~
1/0 0 - 7 ~

R/ B

The above timing sequences 3.15 is to petfom sequential row read operation

23
Fig 3.16 Page Program Operation

CLE

CE

WE
IWB

ALE

RE

1/0 0' 7
Read Statu s
Command

RIB
l/Oo =O Succe ssful Progm m
l/Oo =1 Error in Pro gram

The above timing diagram 3.16 shows the timing signals for the page read operation. ie
reading the whole page of the flash memory.

3.6 Invalid Blocks(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose
reliability is not guaranteed. Typically, an invalid block will contain a single bad bit. The
information regarding the invalid block(s) is called as the invalid block information.
The invalid block information is written to the 1st or the 2nd page of the invalid block(s)
with OOh data. Devices with invalid block(s) have the same quality level or as devices
with all valid blocks and have the same AC and DC characteristics. An invalid block(s)
does not affect the petformance of valid block(s) because it is isolated from the bit line
and the common source line by a select transistor.

The system design must be able to mask out the invalid block(s) via address mapping.
The 1st block of the NAND Flash, however,
is fully guaranteed to be a valid block.

24
All device locations are erased(FFh) except locations where the invalid block info1mation
is written prior to shipping. Since the invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been
erased. Therefore, the system must be able to recognize the invalid block(s) based on the
original invalid block info1mation and create the invalid block table via the following
suggested flow chart. Any intentional erasure of the original invalid block information is
pro hi bi ted. (ref to figure 3 .17)

Fig 3.17 Flow Chart To Create Invalid Block Table.

Start

Set BlocK Address = O

Increment Blocl< Address

Create (or update) No

_ _ .----- - - - - - 0
<:-____ChecK "FFH"? ---:>
Checl< "FFH" on the 1st and 2nd page

Invalid Blocl<(s) Table --- .---

No ---- -----
~------------<: L:istBlocK? __ :::>

] Yes
/-----.'\
( End }
\ __ j

25
3. 7 Error In Write Or Read Operation

Over its life time, the additional invalid blocks may occur. Through the tight process
control and intensive testing, Samsung minimizes the additional block failure rate, which
is projected below 0.1 % up until I million program/erase cycles. Refer to the qualification
report for the actual data.The following possible failure modes should be considered to
implement a highly reliable system. In the case of status read failure after erase or
program, block replacement should be done. To improve the efficiency of memory space,
it is recommended that the read or ve1ification failure due to single bit error be reclaimed
by ECC without any block replacement. The said additional block failure rate does not
include those reclaimed blocks.

Fig 3.18 Error in Write Or Read Operation

Failure Mode Detection and Countermeasure sequ en ce
Erase Fa ilure Status Read after Erase --> Block Replace 111ent

Write Status Re;,id ;.ifter Program --> Blo ck Replacement

Prog ram Failu re Read back ( Verify after Progra111) --> Bl ock Replace 111ent
or ECC Correction
Read Single Bit Failure Ve ri fy ECC -> ECC Correction

26
FIG 3.19 Program Flow Chart
r---------------------------~

!f 5CC is used, this verificZtt!on

/ _. operation is not needed.
'\
'\_ Start _)
-
Write OOH
Weill SOH
Write Address
Write Address

Write Data Wait for tR Time

Write 10H ---- ·-.. - No I

0 °""
-·< __ Verify Data ____ _:-.> --..i,, Program Erro.')

Write 70H I -------- - -~-1·-~=-~----------------

Yes
1 -· - "'
\_ Program Completed )

0 :the
If program operation results in an error, map out

·8 J__~es block including the page in error and copy the

target data to another block.
.,.. .-·
,. -.._ No ---. ___
1~ Progr~m Error ~...__ ---- SR . 0 = 0?
- /

Yes

27
Fig 3.20 Erase Flow Chart

-\
( Start )

Write Block Address

Write DOH

Write 70H

</.
'····-~.
S-~. ~ =-~? _o_J
or RIB = 1 ? __.. /
·----..

·-·- ............ _ _.,..,..,.

0 _J;~·s
- -- ----· No _./-- ----...
( .. Erzise Error °';....._-.::~:----·· SR. O = O ? ---·-:::.>
'\._ _./ --- .-

(~ : If ernse operzition results in zin error, mzip out

- the fziiling block zind replzice it with zinotlier block.

28
Fig 3.21 Read Flow Chart

\A!r!te OO H

Write Address

ECC Generation

Fig 3.22 Block Replacement

Buffer
error occurs
rne11101y ,.. '-.,

'~t---: -t-----i
f- Block A

~ ",'-_I-:----+-----<
~>---.- ·1
>----------< J Block B

When the en-or happens in block "A" try to write the data into another block "B" by
reloading from an external buffer .then ,prevent further system access to block "A"(by
creating a "invalid block" table or other appropriate scheme .

29
Fig 3.23 Block Erase Operation

CLE ,__/\~_ ______._/_,___/_\>........L../_ _\~(\'-----'-/_ _

CE

WE

!\.vs +--! SE RS
ALE

RE

'- ,,
Slack
A.ddress
RIB Busy

Auto Block E rns~ S~tu p Cornn and Erase Con11n and Read Status l/Oo= O Successful Erase
Command I/Ou= 1 Error in Erase

The following timing sequence (ref to figure 3.23) should be created by the flash
controller for a block erase operation

Fig 3.24 Manufacture & Device ID Read Operation

CLE

CE

WE

ALE

RE

110 0-1

30
3.8 Page Program

The device is programmed basically on a page basis. But it also allows multiple partial
pages programming of a byte or consecutive bytes up to 264 may be programmed in a
single page program cycle. The number of paitial page programming operation in the
same page without an intervening erase operation must not exceed ten. The addressing
may be done in random order in a block. A page program cycle consist of a serial data
loading period in which up to 264 bytes of data must be loaded into the device, and
nonvolatile programming pe1iod in which the loaded data is programmed into the
appropriate cell. The sequential data loading period begins by inputting the Serial Data
Input command(80H), followed by the three cycle address input and then serial data
loading. The bytes other than those to be programmed do not need to be loaded.
In order to program the bytes in the spare columns of 256 to 263, the pointer should be
set to the spare area by writing the Read 2 command(50H) to the command register. The
pointer remains in the spare area unless the Read 1 command(OOH) is entered to
rectum to the main area.

The Page Program confirms command(lOH) initiates the programming process. Writing
lOH alone without previously ente1ing the se1ial data will not initiate the programming
process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. Once the
program process starts, the Status Register may be read RE and CE low after the Read
Status command(70H) is written to it. The CPU can detect the completion of program
cycle by monitoring the RIB output, or the Status bit(I/06) of the Status Register. Only
the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/00) may be
checked. The internal w1ite verify detects only errors for ''l''s that are not successfully
programmed to "O"s. The command register remains in Read Status command mode until
another valid command is written to the command register.

Fig 3.25 Program & Read Status Operation

- - -- - - -- -- - - - - - ,4 - - - - -IPROG-__.. - - - - - - - - - - -
R/B

1/0 0 ·-7 Addrc$S & Dnta Input

Ao - A7 & A3 - A;o
264 Byie Data Fail

31
3.9 Block Erase
The Erase operation is done on a block(4K Byte) basis. Block address loading is
accomplished in two cycles initiated by an Erase Setup comrnand(60H). Only address
Al2 to A20 is valid while A8 to All is ignored. The Erase Confirm command(DOH)
following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution command ensures that memory contents are not
accidentally erased due to external noise conditions . At the rising edge of WE after the
erase confirm command input, the internal write controller handles erase, erase-verify
and pulse repetition where required. When the erase operation is complete, the W1ite
Status Bit(I/00) may be checked.

Fig 3.26 Block Erase Operation

~-------------.+--! B ER S --+.-------------
RIB

1/0 0 ' 7 Address lnput(2Cyc'e) Paos

Block Add. : Al ' Az;

Fail

3.10 Read Status

The device contains a Status Register which may be read to find out whether program or
erase operation is complete, and whether the program or erase operation is completed
successfully. After writing 70H command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each
device in multiple memory connections even when RIB pins are common-wired. RE or
CE does not need to be toggled for updated status. Refer to table 2 for specific Status
Register definitions. The command register remains in Status Read mode until further
commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(OOH or 50H) should be given before sequential page read cycle.

32
Fig 3.27 Status Register Definition

SR Status Defi nitio n

"O" : Successful Prog ram I Erase
i/Oo Prograrn I Erase
"f': Error in Prog ram I Erase
1/0 1 "O"
1 /0 ~ "O"
Reserved for Future
1/0 3 Use "O"
1/0• "O"
1/05 "O''
l/Oa Device Ope ration "O" : Busy "1": Ready
1/0 7 Write Protect "O" : Protected "1" : Not Protected

3.11 Read ID

The device contains a product identification mode, initiated by writing 90H to the
command register, followed by an address input of OOH. Two read cycles sequentially
output the manufacture code(ECH), and the device code (EAH) respectively. The
command register remains in Read ID mode until further commands are issued to it.

Fig 3.28 Read ID Operation

CLE

~------tcR--.
CE

WE

~----------- IAR l
ALE

RE

1/0 0 .. 7 90H Address. 1 cycle Dout(ECH) Dout(EAH)

A.o - A1 :' O" Maker code Device code

33
3.12 Reset
The device offers a reset feature, executed by writing FFH to the command register.
When the device is in Busy state during random read, program or erase mode, the reset
operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value COH
when WP is high . Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register.
The RIB pin transitions to low for tRST after the Reset command is written. Reset
command is not necessary for normal operation.

Fig 3.29 Reset Operation

- - - - - - - - - - - - - - tRST - - - - o , c - - - - - - - - - - - - - - -
RIB

110 0 ·- 7 FFH >------------------------------

Fig 3.30 Device Status

After Power -up After Reset

Operation Mode Read "I \Nailing for next command

3.12 Ready/Busy
The device has an RIB output that provides a hardware method of indicating the
completion of a page program, erase and random read completion. The RIB pin is
normally high but transitions to low after program or erase command is written to the
command register or random read is started after address loading. It returns to high when
the internal controller has finished the operation. The pin is an open-drain driver thereby
allowing two or more RIB outputs to be Or-ti ed. An appropriate pull-up resister is
required for proper operation and the value may be calculated

34
 CHAPTER 4

Nand Flash Controller

4.1 Nand Flash Controller

Nand flash controller is a device which is used by the user for an easy interface of a flash
memory. Flash devices are accessed through complicated sequences of command ,
address , data and confirmation protocol.

In the following verilog code we will write the commands to access the flash memory
using a flash controller . At certain clock signals we try to create timing signals which are
required by the flash memory to perform certain operations such as to read the command
And address latch .

Nand flash controller occupies a small part of the system memory without scarifying
system performance. Timing parameters of the controller is fully programmable so
different memory speeds are supp01ted regardless of the operating frequency of the
controller.It has a separate address and data buses and command signals burst transfer
and wait state in se1tions. The controller acts as a target or slave on these buses.
With these standard bus interfaces , it can be integrated with systems

4.2 Task

To writing a verilog program to interface Nand Flash Memory - K9F1608WOA.

The verilog program is used to create the timing signals which the memory chip -
K9F1608WO uses. For example to access a particular address on the memory chip, we
have to create the same timing signals using verilog as command latch cycle which the
manufacture has provided and send the data from the host to output of nand flash
controller .To create same timing signals we use all the information of the chip which the
manufacture has provided us with.

35
4.2 Description Of Verilog Module

We create a nand flash controller with following input pins from host (test bench)

Host _elk :
This pin is used to send clock signals from host to the flash controller.
Clk signal is used to trigger an operation to start.
Host_rst:
This pin is used to reset the flash controller by the host
Host_data_in:
This pin is used to send data bits from host to the flash controller
Host_addr:
This pin is used to send address bits from host to the controller
Host_ wr_rd:
This pin is used to read and w1ite from host to the flash controller
Host_start:
This pin is used to stait the flash controller
Nd_flsh_cntrl_cs:
Chip select from host to the flash controller

The following are the output pins from nand flash controller and input to flash memory .
Using these pins we create the timing signals for which the flash memory can respond.

Nd_flsh_ce_b :
This is a chip enable pin from the flash controller to the flash memory
Nd_flsh_we_b:
This is a write enable pin from the flash controller to the flash memory
Nd_flsh_re_b:
This is a read enable pin from the flash controller to the flash memory
Nd_flsh_ale:
Ale enable from flash controller to flash memory
Nd_flsh_cle
Cle enable pin from the flash controller to the flash memory
Nd_flsh_cmd_addr_data_out:
Command or address is out from the flash controoler on the flash memory on this pin
Nd_flsh_cmd_addr_data_oe:
output enable for 8bit bidirectional i/o bus between flash controller & flash memory

36
The following pin is the output from nand controller to host

Host_slave_rdy:
This pin sends the message to the host saying that controller is ready to receive
instructions.

The following pins are output pin from flash device to flash controller

Nd_flsh_busy_b:
When the flash device is busy this pin will be high , indicating to the flash controller that
its busy with another ope1tion
Nd_flash_data :
This pin is used to send data from the flash memory to flash controller.

We create 4 state machines to generate the required timing signals (refer appendix 1)

ND_CTRL_IDLE
ND_CTRL_ALE_ OR_CLE_RISE_TO_WE_F ALL
ND_CTRL_WE_LOW_DURATION
ND_CTRL_WE_RISE_TO _ALE_ OR_CLE_FALL

At the positive edge of the host_clk & host_rst ,we trigger our module .
In first loop we double synchronize the nd_flsh_busy_b ,then we set host_slave_rdy and
ale_or_cle_start_enbl to 1 when host_addr is ready.

We then initialize our registers cnt_ale_or_cle_1ise_to_we_fall, cnt_we_low_width,

cnt_we_rise_to_cle_or_ale_fall to 0.

Now that we are all set with our registers we start our state machine.

In the first state ND_CTRL_IDLE:

We create timing signal cnt_ale_or_cle_rise_to_we_fall which is tcs (ref to fig . 3.7)
By loading it with nd_ctl_setup_time and move on to the second state

In the second state ND_CTRL_ALE_OR_CLE_RISE_TO_WE_FALL ,we decrement

cnt_ale_or_cle_rise_to_ we_fall. When its 1 we load the next timing signal
cnt_we_low_width with nd_cntl_pluse_width which is twp(ref to fig.3.7) and move on
the third state .

37
In the third state ND_CTRL_ WE_LOW _DURATION we decrement cnt_we_low_width
and when its l we load the cnt_ we_rise_to_cle_or_ale_fall with nd_ctl_hold_time which
is tch (ref. 3. ll)and switch to the last state.

In the fourth state ND_CTRL_WE_RISE_TO_ALE_OR_CLE_FALL we decrement the

cnt_we_rise_to_cle_or_ale_fall and when its 1 we switch back to first state again
bringing all the timing register to 0 again.

Now we are ready to write the data out on to nd_flsh_cmd_addr_data_out.

In this way the data from host_data_in is send out from nd_flsh_cmd_addr_data_out.

FIG .4.1 . State Machine

Nd_ctrl_idle
STATE 1 _rise_to_ we_fall
ST ATE 2 Tcs=tcs-1

Tcs=l
Tch=l

Nd_ctrl_ we_rise_to_ale_
Twp=l
or_cle_fall Duration
STATE 4 Tch=tch-1 STATE 3 Twp=twp-1

38
 REFERENCES

(1) Samir palnitkar ,Verilog HDL ,A Guide To Digital Design And Synthesis,
Published by Pearson Education .

(2) Nand Flash Device ,Samsung Semiconductors Global ,

1995-2005 Samsung Digitall

(3) Intel Flash Memory, Intel Corporation .

39
 APPENDIX A

Verilog Module Of Flash Controller

//////////II/////////////////////////////////////////////////////////////////////
11 Module Description:
II This is a NAND FLash Controller module containing NAND Control state
II machine (for ALE/CLE cycles).
II It also contains register writes to NAND control reg,
II NAND command/address reg, NAND control (ALE/CLE) timing
II reg.
////////////////////////////////////////////////////////////////////////////////

II state values
'define ND_CTRL_IDLE 2'b00
' define ND_CTRL_ALE_OR_CLE_RISE_TO_ WE_FALL 2'b01
'define ND_CTRL_ WE_LOW_DURATION 2'b10
'define ND_CTRL_WE_RISE_TO _ALE_ OR_CLE_FALL 2'bll

module nd_flsh_ctrl(
II outputs
nd_flsh_ce_b, II chip enable pin from nand flash controller to flash device
nd_flsh_re_b, II read eanble pin from nand flash controller to flash device
nd_flsh_ we_b, 11 write enable pin from nand flash controller to flash device
nd_flsh_ale, //ale eanble pin from nand flash controller to flash device
nd_flsh_cle, II cle enable pin from nand flash controller to flash device
nd_flsh_cmd_addr_data_out, //command or address out from flash controller to
//flash device
nd_flsh_cmd_addr_data_oe, II olp enable for 8bit bidirectional i/o bus b/w flash
II controller & device
II if its 1 -->data from controller is d1ived flash device and viceversa

II inputs to flash controller from to test bench to start the task

host_clk, //elk used a input to controller from test bench
host_rst, II reset from test bench to the controller
host_data_in,// data input from test bench to controller
host_addr, // addr input from test bench to controller
host_ wr_rd, II write and read from test bench to controller
host_start, II start from test bench to controller
nd_flsh_ctrl_cs, II chip select for nand controller driven from host i/f testbench

II output from nand controller to host interface testbench

host_slave_rdy, //output

40
 II inputs driven from nand flash device
nd_flsh_busy_b,
nd_flash_data
);

II output signals to NAND flash device

output nd_flsh_ce_b; II NAND flash device chip enable(active low)

output nd_flsh_re_b; II read enable for NAND flash device(active low)

output nd_flsh_ we_b; II w1ite enable for NAND flash device(active low)
output nd_flsh_ale; II address latch enable for NAND flash device (active hi gh)
II indicating address byte being written to NAND flash
II device
output nd_flsh_cle; II It is the command latch enable (active high) indicating
II command byte being written to NAND flash device
output [7 :0] nd_flsh_cmd_addr_data_out; II output 8-bit bus used to send command or
II address or write data from NAND
II controller to NAND flash device
output nd_flsh_cmd_addr_data_oe; II output enable for 8-bit bus used for command
II or address or write data
II sent to NAND flash device

II host bus interface signals

input host_clk, II host clock
host_rst; II host async reset
input [31 :O] host_data_in; II host write data in
input [3:0] host_addr; 11 host address
input host_wr_rd; II host bus write or read; write =l, read= 0
input host_start; II host bus starting a bus cycle
input nd_flsh_ctrl_cs; II NAND controller's chip select for host bus cycles

output host_slave_rdy; II NAND controller completed host bus cycle for register
read or write

II inputs driven from nand flash device

input nd_flsh_busy_b; II NAND flash device's RDY/BUSY _b; when NAND flash
II device is busy, this signal is low (l 'bO) else it is high
II (l'bl) (indicating it is ready)

input [7:0] nd_flash_data; II input 8-bit bus from NAND flash device to NAND
II controller
II output net declarations
wire nd_flsh_ce_b;
wire nd_flsh_re_b ; II read enable strobe for NAND(active low)

41
wire nd_flsh_we_b; II write enable strobe for NOR(active low)
wire nd_flsh_ale; //address latch enable for NAND(active
II high)
II NAND: Active high signal to indicate an
II address byte being w1itten into the
II NAND flash
wire nd_flsh_cle; II It is the command latch enable.
II It is the active high signal
II to indicate a command byte being written
II into the NAND flash.

wire [7:0] nd_flsh_cmd_addr_data_out; //Output bus of NAND flash

II flash controller. Command, address and
II data are sent on this bus.
wire nd_flsh_cmd_addr_data_oe; //output enable for the flash
II command or address or data being
II sent to the 1/0 pads
reg host_slave_rdy; // NAND controller completed host bus cycle for register
11 read or write

II local net declarations

reg [2:0] nd_flsh_ctrl_reg; II NAND Flash Controller's Control (addr: 4'h0)
II register
reg [7:0] nd_flsh_cmd_or_addr_reg; II NAND Flash Controller's cmd/addr reg (addr:
4'hl)
reg [11:0] nd_flsh_ale_cle_tim_reg; // NAND control (ALE/CLE) timing register
II register (addr: 4'h2)
wire [7:0] nd_flsh_ctrl_status_reg; // NAND Flash Controller's Status
II register (addr: 4'h3) - READ ONLY

reg nd_flsh_busy_b_sl, II first stage delayed version of nd_flsh_busy_b

nd_flsh_rdy; //second stage delayed version of nd_flsh_busy_b
reg ale_or_cle_start_enbl; //CLE or ALE start enable
reg [2:0] cnt_ale_or_cle_ri se_to_ we_fall, II count for CLE or ALE to WE falling edge
cnt_we_low_width, II count for we strobe pulse(active low)
cnt_we_rise_to_cle_or_ale_fall //count for we rising to CLE or ALE
reg [7 :0] nd_flsh_addr_cmd_out; II NAND Flash's command, address
reg nd_flsh_addr_cmd_out_enbl ; II Output enable for NAND Flash's
11 command, address
reg [1:0] nd_ctrl_state; II NAND control state
reg nd_ctrl_sm_busy; II NAND control state machine's busy
reg nd_ctrl_we_b; II Write enable strobe for NAND
II Flash's command and address
wire [2:0] nd_ctl_setup_time, II NAND control setup time

42
 nd_ctl_pulse_ width, II NAND control pulse width
nd_ctl_hold_time; II NAND control hold time

II nd_flsh_busy_b being double synchronized

II to align according to the clock
always @( posedge host_clk or posedge host_rst)
begin
if ( host_rst )
begin
nd_flsh_busy_b_sl <= 1'bO;
nd_flsh_rdy <= 1'bO;
end
else
begin
nd_flsh_busy_b_sl <= nd_flsh_busy_b;
nd_flsh_rdy <= nd_flsh_busy_b_s 1;
end
end

II generation of host_slave_rdy
always @(posedge host_clk or posedge host_rst)
begin
if ( host_rst )
host_slave_rdy <= l 'bO;
else if ( host_start & nd_flsh_ctrl_cs )
begin
case (host_addr[3 :O])
4'h0,
4'hl,
4'h2,
4'h3:
host_slave_rdy <= l'bl;
default:
host_slave_rdy <= 1'bO;
endcase
end
else
host_slave_rdy <= 1'bO;
end

II generation of the start enable for NAND CLE or ALE state machine
II when host bus write is done to nd_flsh_cmd_or_addr_reg
//this cycle tell us when to start the state machine after the host read write,

43
II host_slave_rdy and chip enable are host address is high then start enable is started
always @( posedge host_clk or posedge host_rst)
begin
if ( host_rst )
ale_or_cle_start_enbl <= 1'bO;
else if ( host_wr_rd & host_slave_rdy & nd_flsh_ctrl_cs)
begin
if ( host_addr[3:0] == 4'hl )
ale_or_cle_start_enbl <= 1'b1;
else
ale_or_cle_start_enbl <= l 'bO;
end
else
ale_or_cle_start_enbl <= 1'bO;
end

II NAND control state machine for CLE or ALE bus cycles

always @( posedge host_clk or posedge host_rst)
begin
if ( host_rst ) //begin a cycle when host_rst is started
begin
cnt_ale_or_cle_rise_to_we_fall <= 3 'bOOO; lite s from 1-7 cycles
cnt_we_low_width <= 3'b000; //twp from 1-7 cycles
cnt_we_rise_to_cle_or_ale_fall <= 3'b000; /Itch from 1-7 eye
nd_flsh_addr_cmd_out <= 8'h00; //command or address 8bit value (VO)
nd_flsh_addr_cmd_out_enbl <= 1'bO; //enable when the data is vailed
nd_ctrl_state <= 'ND_CTRL_IDLE; //state variable is set to IDLE state
nd_ctrl_sm_busy <= 1'bO; //ale or cle sm is busy or not
nd_ctrl_we_b <= l'bl; //write enable for command or address
II cycles

end
else if ( -nd_flsh_ce_b ) II chip enable (active low) programmed
II through nd_flsh_ctl_reg[2]
begin
case(nd_ctrl_state)
'ND_CTRL_IDLE:
if ( ale_or_cle_start_enbl & nd_flsh_rdy) // ale_or_cle_start_enbl goes high when
II write is done to
II nd_flsh_cmd_or_addr_reg; when
II nd_flsh_rdy is 1'bl then
II nand flash device is ready else it is busy
begin
nd_ctrl_sm_busy <= l'bl; // nand control state machine is busy
cnt_ale_or_cle_1ise_to_we_fall <= nd_ctl_setup_time; //load nand control setup
II time register value

44
 II from nd_flsh_ale_cle_tim_reg[2:0] into counter
II used to count setup time of we_b w.r.t CLE or ALE rise
nd_ctrl_state <= ' ND_CTRL_ALE_OR_CLE_RISE_TO_WE_FALL;
II state transition to state 1
end
else
begin
nd_ctrl_sm_busy <= 1'bO; //assigning the status is not busy;
nd_flsh_addr_cmd_out <= 8'h00; //assigning 8-bit value of command or
11 address to zero
nd_flsh_addr_cmd_out_enbl <= 1'bO; II di sabling cmd or address (8bit value)
end
' ND _CTRL_ALE_OR_CLE_RISE_TO_WE_FALL:
if ( cnt_ale_or_cle_rise_to_we_fall == 3'b001)
11 check for cnt_ale_or_cle_rise_to_ we_fall to be 1'b1 (tel s)
begin
nd_ctrl_we_b <= l'bO; II we_b take it to low (l'bO)
cnt_we_low_width <= nd_ctl_pulse_width; //load pulse width counter (tWP)
II with we_b width register value
II from nd_flsh_ale_cle_tim_reg[5:3]
nd_flsh_addr_cmd_out <= nd_flsh_cmd_or_addr_reg; II d1ive cmd or addr value
II to nd fish controller's data bus
nd_flsh_addr_cmd_out_enbl <= l'bl; II cmd or addr (8bit) is valid to be sent to
II nd fish device
nd_ctrl_state <= ' ND_CTRL_WE_LOW_DURATION;
II state transition to state2
end
else
begin
cnt_ale_or_cle_rise_to_ we_fall <= cnt_ale_or_cle_rise_to_we_fall - 1'b1;
II keep decrementing this counter
II until it is l'bl
end
'ND_CTRL_ WE_LOW _DURATION:
if ( cnt_we_low_width == 3'b001)
begin
nd_ctrl_we_b <= l'bl ;
cnt_we_rise_to_cle_or_ale_fall <= nd_ctl_hold_time ;
nd_ctrl_state <= ' ND_CTRL_WE_RISE_TO_ALE_OR_CLE_FALL;
end
else
cnt_we_low_width <= cnt_we_low_width - l'bl;
' ND_CTRL_WE_RISE_TO _ALE_ OR_CLE_FALL:
if ( cnt_ we_rise_to_cle_or_ale_fall == 3'bOO1 )
begin
nd_ctrl_state <= ' ND_CTRL_IDLE;

45
 end
else
cnt_we_rise_to_cle_or_ale_fall <= cnt_ we_rise_to_cle_or_ale_fall - l 'b 1;
endcase
end
else
begin
cnt_ale_or_cle_rise_to_we_fall <= 3'b000;
cnt_we_low_width <= 3'b000;
cnt_we_rise_to_cle_or_ale_fall <= 3 'bOOO;
nd_flsh_addr_cmd_out <= 8'h00;
nd_flsh_addr_cmd_out_enbl <= 1'bO;
nd_ctrl_state <= 'ND_CTRL_IDLE;
nd_ctrl_sm_busy <= 1'bO;
nd_ctrl_we_b <= 1'bl ;
end
end

II generation of NAND Controller's Command or Address or Data out to

II external NAND Flash devices
assign nd_fl sh_cmd_addr_data_out = nd_ctrl_sm_busy ? nd_flsh_addr_cmd_out: 8'h0;

II generation of NAND Controller's Command or Address or Data output enable

assign nd_flsh_cmd_addr_data_oe = nd_ctrl_sm_busy ? nd_flsh_addr_cmd_out_enbl :
l'bO;

II generation of NAND Controller's write enable to external NAND Flash

II devices

assign nd_flsh_ we_b = nd_ctrl_sm_busy ? nd_ctrl_we_b : 1'b1;

assign nd_flsh_re_b = l 'b 1;
II WRITES TO REGISTERS
II w1iting into NAND Flash Control register
always @( posedge host_clk or posedge host_rst)
begin
if ( host_rst )
nd_flsh_ctrl_reg <= 3'b100;
else if ( host_wr_rd & (nd_flsh_ctrl_cs) & host_start)
begin

46
 if ( host_addr[3:0] == 4'h0)
nd_flsh_ctrl_reg <= host_data_in[2:0];
end
end

assign nd_flsh_cle = nd_flsh_ctrl_reg[O] ;

assign nd_flsh_ale = nd_flsh_ctrl_reg[ 1] ;
II generation of NAND Controller's chip selects to external NAND Flash
II devices
assign nd_flsh_ce_b = nd_flsh_ctrl_reg[2];

II writing into NAND command or address register

always @( posedge host_clk or posedge host_rst)
begin
if ( host_rst )
nd_flsh_cmd_or_addr_reg <= 8'h00;
else if ( host_ wr_rd & (nd_flsh_ctrl_cs) & host_start )
begin
if ( host_addr[3:0] == 4'hl )
nd_flsh_cmd_or_addr_reg <= host_data_in[7:0];
end
end

II writing into NAND ALE/CLE control timing register

always @(posedge host_clk or posedge host_rst )
begin
if ( host_rst)
nd_flsh_ale_cle_tim_reg <= 12'h777;
else if ( host_ wr_rd & host_start & nd_flsh_ctrl_cs )
begin
if (host_addr[3:0] == 4'h2)
nd_flsh_ale_cle_tim_reg <= host_data_in[ll :OJ;
end
end

assign nd_ctl_hold_time = nd_flsh_ale_cle_tim_reg[ 10: 8];

assign nd_ctl_pulse_ width = nd_flsh_ale_cle_tim_reg[6:4];
assign nd_ctl_setup_time =nd_flsh_ale_cle_tim_reg[2:0];

II nand controller status register - READ ONLY

assign nd_flsh_ctrl_status_reg = {6'b0000_00,nd_flsh_rdy,nd_ctrl_sm_busy};

endmodule

47
 APPENDIX B

Test Bench Of Flash Controller

//'timescale Ins I 100 ps

module test_nd_flsh ();

reg host_elk;
wire nd_flsh_ce_b,
nd_flsh_cle,
nd_flsh_ale,
nd_flsh_ we_b,
nd_flsh_re_b,
nd_flsh_busy _b;

wire [7:0] nd_flsh_io,

nd_flsh_cmd_addr_data_out,
nd_flash_data;

reg host_rst;
reg [3:0] host_addr;
reg [31 :O] host_data_in;
reg host_ wr_rd,
host_start;
reg nd_flsh_ctrl_cs;

wire [7:0] nd_flsh_data_rd_reg;

wire [2:0] nd_flsh_ctrl_reg;

wire [7:0] nd_flsh_cmd_or_addr_reg,
nd_flsh_ctrl_status_reg;
wire [27:0] nd_flsh_data_tim_reg;
wire [ 11 :O] nd_flsh_ale_cle_tim_reg;

initial
host_clk = l 'bO ;
always
#20 host_clk = ~host_clk;
I*
km29w040 sam_fl_dev
(
.ceb(nd_flsh_ce_b ),
.cle(nd_flsh_cle ),
.ale(nd_flsh_ale ),

48
 .web(nd_flsh_ we_b ),
.reb(nd_flsh_re_b ),
.io(nd_flsh_io ),
.gnd(l 'bO),
.wpb(l 'bl),
.rbb(nd_flsh_busy_b)
);
*I

nd_flsh_ctrl nd_flsh_ctrl (

.nd_flsh_ce_b(nd_flsh_ce_b),
.nd_flsh_re_b(nd_flsh_re_b),
.nd_flsh_we_b(nd_flsh_ we_b ),
.nd_flsh_ale( nd_fl sh_ale ),
.nd_flsh_cle(nd_flsh_cle ),
.nd_flsh_cmd_addr_data_out(nd_flsh_cmd_addr_data_out),

.nd_flsh_cmd_addr_data_oe(nd_flsh_cmd_addr_data_oe),

.host_clk(host_clk),
.host_rst(host_rst),
.host_data_in(host_data_in),
.host_addr(host_addr),
.host_ wr_rd(host_ wr_rd),
.host_start(host_start),
.host_slave_rdy(host_slave_rdy),
.nd_flsh_ctrl_cs(nd_flsh_ctrl_cs),

II uncommented below 2 lines if samsung flash device instance above is used and
//comment last two lines in this port list
II .nd_flsh_busy_b(nd_flsh_busy _b ),
II .nd_flash_data(nd_flash_data)

.nd_flsh_busy_b(l 'b 1),

.nd_flash_data(8'h0)
);

assign nd_flsh_io = nd_flsh_cmd_addr_data_oe ? nd_flsh_cmd_addr_data_out : 8'hz;

II uncommented below line if samsung flash device instance above is used
//assign nd_flash_data = nd_flsh_io;

initial
begin
host_rst <= 1'bO;

49
 nd_flsh_ctrl_cs <= l 'bO;
host_rst <= #10 I 'bl;
host_rst <= #50 1'bO ;

II write nd_flsh_ctrl_reg with bit 2 (ce_b) to l'bO, bit 1 (ale) to l'bO, bit 0 (cle) to l'bO
nd_flsh_ctrl_cs <= #50 l 'b 1;
host_addr <= #50 4'h0;
host_data_in <= #50 32'h0000_0000;
host_wr_rd <= #50 l'bl;
host_start <= #62 1'b1;
host_start <= #102 1'bO;
host_wr_rd <= #142 l'bO;

II write nd_flsh_ctrl_reg with bit 2 (ce_b) to l'bO, bit 1 (ale) to l'bO, bit 0 (cle) to l'bl
host_addr <= #170 4'h0;
host_data_in <= #170 32'h0000_0001;
host_wr_rd <= #170 l'bl;
host_start <= #182 l'bl;
host_stm1 <= #222 1'bO;
host_ wr_rd <= #262 1'bO;

II write nd_flsh_cmd_or_addr_reg with 80 hex (sequential data input command from

samsung spec)
host_addr <= #290 4'hl;
host_data_in <= #290 32'h0000_0080;
host_wr_rd <= #290 l'bl;
host_start <= #302 1'b1;
host_sta11 <= #342 1'bO;
host_wr_rd <= #382 l'bO;

II wait until nd_flsh_ctrl_busy is low to program CLE low (bit 0 of nd_flsh_ctrl_reg)

CE_b = 1'bO, ALE = 1'bO
II wait for 25 host_clk cycles (25 * 40 (clock period)= 1000)
host_addr <= #1350 4'h0;
host_data_in <= #1350 32'h0000_0000;
host_wr_rd <= #1350 l'bl;
host_start <= #1362 l'bl;
host_start <= #1402 l 'bO;
host_wr_rd <= #1442 l'bO;

II write to nd_flsh_ctrl_reg with CLE=O, ce-b = 0, ALE= 1

host_addr <= #1470 4'h0;
host_data_in <= #1470 32'h0000_0002;
host_wr_rd <= #1470 l'bl;
host_start <= #1482 1'bl;
host_start <= #1522 1'bO;

50
 host_wr_rd <= #1562 l'bO;

II write to nd_flash_cmd_or_addr_reg with nand flash device address= 44 hex

host_addr <= #1590 4'hl ;
host_data_in <= #1590 32'h0000_0044;
host_wr_rd <= #1590 l'bl ;
host_start <= #1602 l'bl;
host_start <= #1642 l 'bO;
host_wr_rd <= #1682 l'bO;

II write to nd_flash_cmd_or_addr_reg with nand flash device address = 66 hex

host_addr <= #2630 4'hl;
host_data_in <= #2630 32'h0000_0066;
host_wr_rd <= #2630 l'bl ;
host_start <= #2642 l 'b 1;
host_start <= #2682 1'bO;
host_ wr_rd <= #2722 1'bO;

II write to nd_flash_cmd_or_addr_reg with nand flash device address= 88 hex

host_addr <= #3670 4'hl;
host_data_in <= #3670 32'h0000_0066;
host_wr_rd <= #3670 l'bl;
host_start <= #3682 l 'b 1;
host_start <= #3722 l 'bO;
host_wr_rd <= #3762 l'bO;

II write to nd_flsh_ctrl_reg with ALE= 0, CLE= 0, CE_B = 0

host_addr <= #3670 4'h0;
host_data_in <= #3670 32'h0000_0000;
host_wr_rd <= #3670 l'bl;
host_start <= #3682 l 'b 1;
host_start <= #3722 1'bO;
host_ wr_rd <= #3762 1'bO;

end

initial
begin
II $fsdbAutoSwitchDumpfile(250, "verilog.fsdb", 100);
$dumpvars(3,test_nd_flsh);
#4000 $finish;
end

endmodule

51