Formal Verification Formality

What is Formal Verification?
Formality Flow
Formality Terminology
Formal Equivalence Checking

Formality
Ahmed Abdelazeem
Department of Electronics and Communications Engineering (ECE)

Zagazig University
12 Nov 2022
Ahmed Abdelazeem Formal Equivalence Checking

Formality Flow
Outline
Introduction to Equivalence Checking
Using Formality
Flow Overview
Formality Flow
Fundamental Formality steps
Key Equivalence Checking Concepts
Formality Flow 0: Guidance
Formality Flow 1: Reading the Designs
Formality Flow 2: Match
Breaking Design Into Cones and Points
Match Compare Points
Classic Matching
Classic Matching -2
What is Formal Verification? Introduction to Equivalence Checking
Formality Flow Using Formality
Formality Terminology Flow Overview
FORMAL Verification
Definition
▶ Logic Equivalence Checking.

▶ Formal Verification is an alternative to verification through
simulation.
▶ As design become larger and more complex and require more
simulation vectors, regression testing with traditional
simulation tools becomes a bottleneck in the design flow.
▶ A 100% coverage.
▶ It verifies the logical equivalence of RTL, gate or transistor
level netlist to each other.
▶ Ignores timing information
▶ Only Boolean Equivalence.
▶ Verifies logic function independent of technology and timing
therefore no timing check.
What is the Formality?

▶ The purpose of Formality is to detect unexpected differences
that might have been introduced into a design during
development.
▶ It uses a formal verification comparison engine to prove or
disprove the equivalence of a given design and presents any
differences for follow-on detailed analysis.
▶ Employs formal, mathematical techniques.
▶ Proves two version of a design are or are not functionally
equivalent.

Formality Flow
▶ There are four basic steps in equivalence checking:
▶ Read
▶ Match
▶ Verification
▶ Debug

What is Formal Verification? Formality Flow 0: Guidance
Formality Flow Formality Flow 1: Reading the Designs
Formality Terminology Formality Flow 2: Match
Formality Flow 3: Verify
Formality Flow 4: Debug

▶ Steps to verify design:
▶ Set the SVF
▶ Read RTL into reference container
▶ Read gate level netlist into implementation container
▶ Verify the design

Two Key Concepts
▶ A design contains Logic Cones and Compare Points:

▶ Compare Point
▶ Primary output
▶ Register or latch within the circuit
▶ Input of a black-box
▶ Logic Cone
▶ A block of combinational logic which drives a compare point

Two Key Concepts - schematic

A design contains Logic Cones and Compare Points:

Step 0: Guidance
▶ SVF- Automated Guidance Setup file

▶ Guidance passed from Design Compiler to Formality:
▶ Automatically generated by Design Compiler
▶ Contains both setup and guidance information
▶ Reduces user setup effort and errors
▶ Removes unnecessary verification iterations
▶ SVF data is implicitly or explicitly proven in Formality,
or it is not used (rejected)
▶ Using the SVF flow is recommended
▶ Required when verifying a netlist containing retiming, register
merging, or register inversions

The Design Read Cycle
Breaks Designs into Logic Cones

Breaking Design Into Cones and Points
▶ Breaks the two logic circuits up into Compare points each

with it’s own logic cone:
▶ End points (compare points) are primary outputs, registers,
and black box inputs

Match Compare Points
▶ Compare points are then aligned:

▶ This process is called “compare point matching”
▶ End points of logic cones (compare points) are primary
outputs, registers, and black box inputs

Matches Corresponding Points between Designs
▶ Most compare points match by name. For those compare

points that do not need guidance information, matching is
performed manually or by compare rules

Matches Corresponding Points between Designs

Step 5: Verify
▶ Run Formality’s verification algorithms

▶ By default all points are verified
▶ Four possible results:
▶ Succeeded: implementation is equivalent to the reference
▶ Failed: implementation is not equivalent to the reference
▶ Logic difference or setup problem
▶ Inconclusive: no points failed, but analysis incomplete.
▶ Analysis incomplete due to timeout or to complexity
▶ Not run: a problem earlier in the flow prevented verification
from running at all

Step 5: Verify - Example
Verifies logical equivalence for each logic cone

Step 6: Debug
▶ If verification fails, you need to determine the cause:
▶ An incorrect setup?
▶ A logical design difference between the two designs?
Isolates implementation errors

Formality Flow
▶ Reference Design
▶ The “golden” design under test
▶ Frequently RTL (Verilog, SystemVerilog, VHDL)
▶ Simulated and known to be good
▶ Implementation Design
▶ The modified design being checked against the golden
reference
▶ Containers
▶ Formality database for designs and libraries
▶ Default reference container is named “r”
▶ Default implementation container is named “i”
▶ Can be saved and read using any version of Formality

Formality Flow
Summary
▶ The seven-step Formality flow

▶ Specify Guidance File
▶ Read Reference
▶ Read implementation
▶ Setup
▶ Match
▶ Verify
▶ Debug

Formal Verification Formality

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What is Formal Verification?

Formal Equivalence Checking

Department of Electronics and Communications Engineering (ECE)

Ahmed Abdelazeem Formal Equivalence Checking

▶ Logic Equivalence Checking.

What is the Formality?

Ahmed Abdelazeem Formal Equivalence Checking

Ahmed Abdelazeem Formal Equivalence Checking

Fundamental Formality steps

Ahmed Abdelazeem Formal Equivalence Checking

Two Key Concepts

▶ A design contains Logic Cones and Compare Points:

Ahmed Abdelazeem Formal Equivalence Checking

Two Key Concepts - schematic

Ahmed Abdelazeem Formal Equivalence Checking

▶ SVF- Automated Guidance Setup file

Ahmed Abdelazeem Formal Equivalence Checking

The Design Read Cycle

Breaks Designs into Logic Cones

Ahmed Abdelazeem Formal Equivalence Checking

Breaking Design Into Cones and Points

▶ Breaks the two logic circuits up into Compare points each

Ahmed Abdelazeem Formal Equivalence Checking

Match Compare Points

▶ Compare points are then aligned:

Ahmed Abdelazeem Formal Equivalence Checking

Matches Corresponding Points between Designs

▶ Most compare points match by name. For those compare

Ahmed Abdelazeem Formal Equivalence Checking

Matches Corresponding Points between Designs

Ahmed Abdelazeem Formal Equivalence Checking

▶ Run Formality’s verification algorithms

Ahmed Abdelazeem Formal Equivalence Checking

Step 5: Verify - Example

Verifies logical equivalence for each logic cone

Ahmed Abdelazeem Formal Equivalence Checking

Isolates implementation errors

Ahmed Abdelazeem Formal Equivalence Checking

Ahmed Abdelazeem Formal Equivalence Checking

▶ The seven-step Formality flow

Ahmed Abdelazeem Formal Equivalence Checking

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