Verification Short Course

Introduction to Verification

Centre for Development of Advanced Computing

Hyderabad
Need for Verification

What is Verification
Need For Verification
Cost of bugs over time


Design Reuse


Importance of Verification
70% of design effort


80% of written code



Major Challenges
Enormous designs


Detecting incorrect behavior



Time and Human Factor



Centre for Development of Advanced Computing

Hyderabad
Verification

The challenges are achieved through

Simulation based verification


Formal Verification


Verification can be approached as

Black box


White box


Grey box


Centre for Development of Advanced Computing

Hyderabad
Formal Verification

Act of proving/disproving the correctness of a



system w.r.t a certain formal specification

Mathematically prove the correctness of the


design – called equivalence checking

Ex: RTL to post synthesis gates , Gates


to Post PD gates
Consumes enormous computer


resources

Proves that a assertion or protocol or design

rule holds true for all possible cases of design

Centre for Development of Advanced Computing

Hyderabad
Levels of Verification

Designer level


Unit Level
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Core Level
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Chip Level
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Board or System level



Hardware/software co-verification
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Usually 2 or more levels of verification are followed



Lower the level, more is the controllability and observability



Centre for Development of Advanced Computing

Hyderabad
Verification Planning

Very crucial
Specific tests and methods
Required tools
Completion criteria
Resources
Functions to be verified

Centre for Development of Advanced Computing

Hyderabad
Directed vs Random Verification

Directed Verification
– separate test cases to achieve a specific state of design
– possibility of missing out some cases
– time consuming
Random Verification
– provide certain constraints on inputs.
Balance is required for effective verification

Centre for Development of Advanced Computing

Hyderabad
Assertion Driven Verification

Use of assertions to describe the properties that must be true

Properties can sometimes fully describe the specification of a design
Kind of Formal Verification- Sanity check
Performed by Designers/Verification engineers

Centre for Development of Advanced Computing

Hyderabad
Coverage Driven Verification

Code Coverage
Quantitative measure of DUT code execution


Functional Coverage
Measures whether the features of DUT code are executed


Relies on randomization


Provides feedback and confirmation of what the verification



environment has exercised in the DUV

Two coverage approaches are complementary
Self-checking verification environments are critical

Centre for Development of Advanced Computing

Hyderabad
Bus Function & Reference Models

BFM


useful for bus based designs



quick and easy way to simulate a sub-section of design without



simulating entire system

Reference Models


Developed for easy integration with the verification environment



Used to compare the design results



Usually coded in high level language



Centre for Development of Advanced Computing

Hyderabad
Systemverilog

For complex designs , developing a verification environment is tedious



and consumes a lot of time

Major extension to verilog -2001


Introduction of OOP techniques and new constructs



Handles increased complex tasks effectively



Reusability due to inherent flexibility of OOP



The course covers the systemverilog language & techniques for using


systemverilog in verification, introduction to verification methodologies

and a brief on UVM

Centre for Development of Advanced Computing

Hyderabad
Verification Short Course

Thank You !

Centre for Development of Advanced Computing

Hyderabad