S E M I C O N D U C T O R HIP4081

80V/2.5A Peak, High Frequency

November 1996 Full Bridge FET Driver

Features Description
• Independently Drives 4 N-Channel FET in Half Bridge The HIP4081 is a high frequency, medium voltage Full
or Full Bridge Configurations Bridge N-Channel FET driver IC, available in 20 lead plastic
• Bootstrap Supply Max Voltage to 95VDC SOIC and DIP packages. The HIP4081 can drive every pos-
• Drives 1000pF Load at 1MHz in Free Air at 50oC with sible switch combination except those which would cause a
Rise and Fall Times of Typically 10ns shoot-through condition. The HIP4081 can switch at fre-
quencies up to 1MHz andssssss is well suited to driving
• User-Programmable Dead Time
Voice Coil Motors, high-frequency Class D audio amplifiers,
• On-Chip Charge-Pump and Bootstrap Upper Bias and power supplies.
Supplies
For example, the HIP4081 can drive medium voltage brush
• DIS (Disable) Overrides Input Control
motors, and two HIP4081s can be used to drive high perfor-
• Input Logic Thresholds Compatible with 5V to 15V mance stepper motors, since the short minimum “on-time”
Logic Levels can provide fine micro-stepping capability.
• Very Low Power Consumption
Short propagation delays of approximately 55ns maximizes
Applications control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
• Medium/Large Voice Coil Motors in rapid, precise control of the driven load.
• Full Bridge Power Supplies
A similar part, the HIP4080, includes an on-chip input com-
• Class D Audio Power Amplifiers
parator to create a PWM signal from an external triangle
• High Performance Motor Controls wave and to facilitate “hysteresis mode” switching.
• Noise Cancellation Systems
See Application Note AN9325 for HIP4081, Harris Answer-
• Battery Powered Vehicles FAX, (407) 724-7800, document #99325. Harris web home
• Peripherals page: http://www.semi.harris.com
• U.P.S. Similar part HIP4081A includes undervoltage circuitry which
does not require the circuitry shown in Figure 30 of this data
Ordering Information sheet.
PART TEMP. PKG.
NUMBER RANGE (oC) PACKAGE NUMBER
HIP4081IP -40 to 85 20 Lead Plastic DIP E20.3
HIP4081IB -40 to 85 20 Lead Plastic SOIC M20.3

Pinout
HIP4081
(PDIP, SOIC)
TOP VIEW

BHB 1 20 BHO

BHI 2 19 BHS

DIS 3 18 BLO

VSS 4 17 BLS

BLI 5 16 VDD

ALI 6 15 VCC

AHI 7 14 ALS
HDEL 8 13 ALO
LDEL 9 12 AHS
AHB 10 11 AHO

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 3556.7
Copyright © Harris Corporation 1996
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 HIP4081

Application Block Diagram

80V

12V

BHO

BHS
LOAD
BHI BLO
BLI
HIP4081

ALI ALO

AHI AHS
AHO

GND GND

Functional Block Diagram (1/2 HIP4081)

HIGH VOLTAGE BUS ≤ 80VDC

AHB
10
DRIVER AHO
CHARGE LEVEL SHIFT
11 CBS
PUMP AND LATCH

AHS
VDD 16 12

AHI 7 TURN-ON
DELAY
TO VDD (PIN 16)
DBS
DIS 3
VCC
15

DRIVER +12VDC
ALO
TURN-ON 13 BIAS
ALI 6 DELAY SUPPLY
CBF
ALS
14

HDEL 8

LDEL 9

VSS 4

2
 HIP4081

Typical Application (PWM Mode Switching)

80V

1 BHB BHO 20
12V 2 BHI BHS 19
LOAD
DIS 3 DIS BLO 18
4 VSS BLS 17
PWM
5 BLI VDD 16
INPUT
6 ALI VCC 15 12V
7 AHI ALS 14
8 HDEL ALO 13
9 LDEL AHS 12
10 AHB AHO 11

GND

TO OPTIONAL -
CURRENT CONTROLLER +

6V

GND

3
 HIP4081

Absolute Maximum Ratings Thermal Information (Typical, Note 1)

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65oC to 150oC
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC
Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25oC to 125oC) Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) (For SOIC - Lead Tips Only)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Thermal Resistance, Junction-Ambient
Voltage on AHB, BHB . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +16V SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W
Voltage on ALO, BLO . . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W
Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All voltages are relative to pin 4, VSS, unless otherwise
specified.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . +6V to +15V Voltage on AHB, BHB . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA
Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC

Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
and TA = 25oC, Unless Otherwise Specified

TJS = -40oC
TJ = 25oC TO 125oC
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS

SUPPLY CURRENTS AND CHARGE PUMPS

VDD Quiescent Current IDD All Inputs = 0V 7 9 11 6 12 mA

VDD Operating Current IDDO Outputs Switching f = 500kHz 8 9.5 12 7 13 mA

VCC Quiescent Current ICC All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 µA

VCC Operating Current ICCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA

AHB, BHB Quiescent Current - IAHB, IBHB All Inputs = 0V, IAHO = IBHO = 0 -50 -30 -15 -60 -10 µA
Qpump Output Current VDD = VCC = VAHB = VBHB = 10V

AHB, BHB Operating Current IAHBO, IBHBO f = 500kHz, No Load 0.5 0.9 1.3 0.4 1.7 mA
AHS, BHS, AHB, BHB Leakage Current IHLK VAHS = VBHS = VAHB = VBHB = 95V - 0.02 1.0 - 10 µA

AHB-AHS, BHB-BHS Qpump VAHB-VAHS IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V
Output Voltage VBHB-VBHS
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V

High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V

Input Voltage Hysteresis - 35 - - - mV

Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA

High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

TURN-ON DELAY PINS: LDEL AND HDEL

LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100µA 4.9 5.1 5.3 4.8 5.4 V

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V

High Level Output Voltage VCC -VOH IOUT = -100mA 0.8 .95 1.1 0.5 1.2 V

4
 HIP4081

Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
and TA = 25oC, Unless Otherwise Specified (Continued)

TJS = -40oC
TJ = 25oC TO 125oC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS

Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A

Peak Pulldown Current IO- VOUT = 12V 1.7 2.4 3.3 1.3 3.6 A

Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF

TJS = 40oC
TJ = +25oC TO 125oC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS

Lower Turn-off Propagation Delay TLPHL - 30 60 - 80 ns

(ALI-ALO, BLI-BLO)

Upper Turn-off Propagation Delay THPHL - 35 70 - 90 ns

(AHI-AHO, BHI-BHO)

Lower Turn-on Propagation Delay TLPLH - 45 70 - 90 ns

(ALI-ALO, BLI-BLO)

Upper Turn-on Propagation Delay THPLH - 60 90 - 110 ns

(AHI-AHO, BHI-BHO)

Rise Time TR - 10 25 - 35 ns

Fall Time TF - 10 25 - 35 ns

Turn-on Input Pulse Width TPWIN-ON 50 - - 50 - ns

Turn-off Input Pulse Width TPWIN-OFF 40 - - 40 - ns

Disable Turn-off Propagation Delay TDISLOW - 45 75 - 95 ns

(DIS - Lower Outputs)

Disable Turn-off Propagation Delay TDISHIGH - 55 85 - 105 ns

(DIS - Upper Outputs)

Disable to Lower Turn-on Propagation Delay TDLPLH - 35 70 - 90 ns

(DIS - ALO and BLO)

Refresh Pulse Width (ALO and BLO) TREF-PW 160 260 380 140 420 ns

Disable to Upper Enable (DIS - AHO and BHO) THEN - 335 500 - 550 ns

TRUTH TABLE

INPUT OUTPUT

ALI, BLI AHI, BHI DIS ALO, BLO AHO, BHO

X X 1 0 0

1 X 0 1 0

0 1 0 0 1

0 0 0 0 0

NOTE: X signifies that input can be either a “1” or “0”.

5
 HIP4081

Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA
pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be con-
trolled by the low-side input.
3 DIS Disable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.
4 VSS Chip negative supply, generally will be ground.
5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels
of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven.
6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels
of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven.
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA
pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be con-
trolled by the low-side input.
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on de-
lay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guar-
antees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is
approximately 5.1V.
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap
diodes.
16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

6
 HIP4081

Timing Diagrams
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
TLPHL THPHL

DIS = 0

XLI

XHI

XLO

XHO

THPLH TLPLH TR TF
(10% - 90%) (10% - 90%)

FIGURE 1. INDEPENDENT MODE

DIS = 0

XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

FIGURE 2. BISTATE MODE (10% 90%) (10% 90%)

TDLPLH TDIS

TREF-PW
DIS

XLI

XHI

XLO

XHO

THEN

FIGURE 3. DISABLE FUNCTION

7
 HIP4081

Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified

11.0
14.0
IDD SUPPLY CURRENT (mA)

10.5
12.0

SUPPLY CURRENT (mA)

10.0
10.0

8.0 9.5

6.0 9.0

4.0 8.5

2.0 8.0
6 8 10 12 14 0 100 200 300 400 500 600 700 800 900 1000
VDD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (kHz)

FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs
SUPPLY VOLTAGE FREQUENCY (kHz)

30.0 5.0
FLOATING SUPPLY BIAS CURRENT (mA)

125oC

75oC
ICC SUPPLY CURRENT (mA)

25.0 4.0
25oC
20.0
0o C
3.0
-40oC
15.0
2.0
10.0

1.0
5.0

0.0 0.0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs
FREQUENCY (LOAD = 1000pF) FREQUENCY (kHz) TEMPERATURE

-90
FLOATING SUPPLY BIAS CURRENT (mA)

1.8
LOW LEVEL INPUT CURRENT (µA)

1.4
-100

1.0

0.6
-110

0.2

-0.2 -120
0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125
SWITCHING FREQUENCY (kHz) JUNCTION TEMPERATURE (oC)

FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL
CURRENT vs FREQUENCE vs TEMPERATURE

8
 HIP4081

Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)

15.0 80
NO-LOAD FLOATING CHARGE PUMP

PROPAGATION DELAY (ns)

14.0 70
VOLTAGE (V)

13.0 60

12.0 50

11.0 40

10.0 30
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION
VOLTAGE vs TEMPERATURE DELAY TDISHIGH vs TEMPERATURE

400 80
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)

380 70

360 60

340 50

320 40

300 30
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 12. DISABLE TO UPPER ENABLE TUEN FIGURE 13. DISABLE TO UPPER ENABLE TUEN
PROPAGATION DELAY vs TEMPERATURE PROPAGATION DELAY vs TEMPERATURE

375 80
REFRESH PULSE WIDTH (ns)

70
PROPAGATION DELAY (ns)

325
60

275 50

40
225
30

175 20
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH
TEMPERATURE PROPAGATION DELAY vs TEMPERATURE

9
 HIP4081

Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)

80 80

70 70
PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

60 60

50 50

40 40

30 30

20 20
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs
vs TEMPERATURE TEMPERATURE

80 80

70 70
PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

60 60

50 50

40 40

30 30

20 20
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs
vs TEMPERATURE TEMPERATURE

13.5 13.5
GATE DRIVE FALL TIME (ns)

12.5 12.5
TURN-ON RISE TIME (ns)

11.5 11.5

10.5 10.5

9.5 9.5

8.5 8.5
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)

FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE

10
 HIP4081

Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)

6.0 1500
HDEL, LDEL INPUT VOLTAGE (V)

1250
5.5

VCC - VOH (mV)

1000

5.0 750 -40oC

0oC
500
4.5 25oC

75oC
250
125oC
4.0
0
-40 -20 0 20 40 60 80 100 120 6 8 10 12 14
JUNCTION TEMPERATURE (oC) BIAS SUPPLY VOLTAGE (V)

FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs
BIAS SUPPLY AND TEMPERATURE AT 100mA

1500 3.5

-40oC
GATE DRIVE SINK CURRENT (A)

1250 3.0
0o C
2.5
1000
VOL (mV)

2.0
750
1.5
500
25oC 1.0

250 75oC
0.5
125oC
0 0.0
6 8 10 12 14 6 7 8 9 10 11 12 13 14 15 16
BIAS SUPPLY VOLTAGE (V) VDD , VCC , VAHB , VBHB (V)

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY
SUPPLY AND TEMPERTURE AT 100mA VOLTAGE

3.5 500
10,000pF
LOW VOLTAGE BIAS CURRENT (mA)

200
GATE DRIVE SINK CURRENT (A)

3.0
100 3,000pF
2.5 50 1,000pF
20 100pF
2.0
10

1.5 5

2
1.0
1
0.5
0.5
0.2
0.0 0.1
6 7 8 9 10 11 12 13 14 15 16 1 2 5 10 20 50 100 200 500 1000
VDD , VCC , VAHB , VBHB (V) SWITCHING FREQUENCY (kHz)

FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS
VOLTAGE QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE

11
 HIP4081

Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)

150
1000

500
LEVEL-SHIFT CURRENT (µA)

120
200

DEAD-TIME (ns)
100
90
50

20
60
10 80V

5 60V
30
40V
2
20V
1 0
1 2 5 10 20 50 100 200 500 1000 10 50 100 150 200 250
SWITCHING FREQUENCY (kHz) HDEL/LDEL RESISTANCE (kΩ)

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE
FREQUENCY AND BUS VOLTAGE

HI4081 Power-up Application Information

The HIP4081 H-Bridge Driver IC requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-bridge power MOS- R1 1 BHB BHO 20
15K
FETs may be exposed to shoot-through current, possibly 2 BHI BHS 19
leading to MOSFET failure. Following the instructions below 3 DIS BLO 18
will result in reliable start-up. ENABLE 4 VSS BLS 17
R2
The HIP4081 has four inputs, one for each output. Outputs 3.3K 5 BLI VDD 16
ALO and BLO are directly controlled by input ALI and BLI. 6 ALI VCC 15
By holding ALI and BLI low during start-up no shoot-through 7 AHI ALS 14
conditions can occur. To set the latches to the upper drivers
8 HDEL ALO 13
such that the driver outputs, AHO and BHO, are off, the DIS
9 LDEL AHS 12
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown 10 AHB AHO 11
below in Figure 30. As the VDD /VCC supply ramps from zero
FIGURE 30A.
up, the DIS voltage is below its input threshold of 1.7V due
to the R1/R2 resistor divider. When VDD /VCC exceeds
approximately 9V to 10V, DIS becomes greater than the
VDD 12V, FINAL VALUE
input threshold and the chip disables all outputs. It is critical
that ALI and BLI be held low prior to DIS reaching its thresh- 8.5V TO 10.5V (ASSUMES 5% RESISTORS)
old level of 1.7V while VDD /VCC is ramping up, so that shoot ALI, BLI
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
DIS

1.7V

t1

NOTES:
2. ALI and/or BLI may be high after t1, whereupon the ENABLE pin
may also be brought high.
3. Another product, HIP4081A, incorporates undervoltage circuitry
which eliminates the need for the above power up circuitry.
FIGURE 30B. TIMING DIAGRAM FOR FIGURE 30A

12
 IN2 IN1 +12V POWER SECTION
B+

Q1 2 C8
CONTROL LOGIC R21
+ DRIVER SECTION 1
SECTION R29 CR2
C6
2

JMPR5
HIP4080/81 3 Q3
JMPR1 U1C4 1
1 2 OUT/BLI
U2 1 BHB BHO 20 R22
2 HEN/BHI BHS 19 3
CD4069UB 3 DIS L1
BLO 18
AO
JMPR2 4 V BLS 17
13 12 IN+/ALI SS Q2 2
+12V L2
U2 5 OUT/BLI V 16
DD R23 C1 BO
1
6 IN+/ALI VCC 15
CD4069UB 7 IN-/AHI C2
ALS 14
JMPR3 3
5 6 HEN/BHI 8 HDEL ALO 13
U2 9 LDEL Q4 2
AHS 12
10 AHB R24 1
CD4069UB R33 R34 AHO 11
3 3
JMPR4 3
11 10 IN-/AHI 2 2 CR1
U2
CW CW

13
1 1 C3
CD4069UB R30 R31
CX CY
HIP4081

C5
COM
ENABLE IN
3 4 O
I U2
ALS BLS
15K
R32
CD4069UB
TO DIS PIN
3.3K
9 8
U2 O

CD4069UB

NOTES:
4. Device CD4069UB PIN 7 = COM, Pin 14 = +12V.
5. Components L1, L2, C1, C2, CX, CY, R30, R31, not supplied. refer to Application Note for description of input logic operation to determine
jumper locations for JMPR1 - JMPR4.
FIGURE 31. HIP4081 EVALUATION BOARD SCHEMATIC
 GND +12V
B+ COM

C8

R29
R27
R28
R26
C1

C7
CR2

C6

JMPR5
+ + AO
Q1 Q3

R32
C4 R22 1 1
U1
BHO
R24
C2

U2 DIS BLO
BO
L1
L2

IN1 BLS
I JMPR1
JMPR2

HIP4080/81
O Q2 Q4
JMPR3 ALS R23

14
IN2 JMPR4 ALO 1 1
R21
HIP4081

O AHO
LDEL
C3 C5

HDEL
ALS CR1
CX
CY

R33 R34
BLS
R30
R31

FIGURE 32. HIP4081 EVALUATION BOARD SILKSCREEN

 HIP4081

Supplemental Information for HIP4080
and HIP4081 Power Application
The HIP4080 and HIP4081 H-Bridge Driver ICs require
external circuitry to assure reliable start-up conditions of the
upper drivers. If not addressed in the application, the
H-bridge power MOSFETs may be exposed to shoot-
through current, possibly leading to MOSFET failure. Follow-
ing the instructions below will result in reliable start-up.
HIP4081
The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 33. As the VDD/VCC supply ramps from zero
up, the DIS voltage is below its input threshold of 1.7V due to
the R1/R2 resistor divider. When VDD/VCC exceeds approxi-
mately 9V to 10V, DIS becomes greater than the input
threshold and the chip disables all outputs. It is critical that
ALI and BLI be held low prior to DIS reaching its threshold
level of 1.7V while VDD/VCC is ramping up, so that shoot
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
HIP4080
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a com-
parator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accom-
plished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 34. Pulling
LDEL to VDD will indefinitely delay the lower turn-on delays
through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e., DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 33.

ENABLE
R1 1 BHB BHO 20 1 BHB BHO 20
15K R1
2 BHI BHS 19 15K 2 BHI BHS 19
3 DIS BLO 18 3 DIS BLO 18
ENABLE 4 VSS BLS 17 4 VSS BLS 17
R2 R2
3.3K 5 BLI VDD 16 3.3K 5 BLI VDD 16
6 ALI VCC 15 6 ALI VCC 15
7 AHI ALS 14 7 AHI ALS 14
8 HDEL ALO 13 8 HDEL ALO 13
9 LDEL AHS 12 9 LDEL AHS 12
10 AHB AHO 11 10 AHB AHO 11

FIGURE 33.

1 BHB BHO 20
VDD VDD 2 HEN BHS 19
ENABLE 3 DIS BLO 18
4 VSS BLS 17
56K
5 OUT VDD 16
2N3906
6 IN+ VCC 15
56K
RDEL 7 IN- ALS 14
VDD
8.2V 100K 8 HDEL ALO 13
100K
9 LDEL AHS 12
0.1µF RDEL
10 AHB AHO 11

FIGURE 34.

15
 HIP4081

Timing Diagrams

VDD 12V, FINAL VALUE

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)
VDD 12V, FINAL VALUE
8.5V TO 10.5V (ASSUMES 5% RESISTORS) DIS

ALI, BLI
LDEL

5.1V
DIS
=10ms
1.7V t1 t2

NOTE: NOTE:
6. ALI and/or BLI may be high after t1, whereupon the ENABLE pin 7. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin
may also be brought high. to go through one complete cycle (transition order is not impor-
tant). If the ENABLE pin is low after the undervoltage circuit is
satisfied, the ENABLE pin will initiate the 10ms time delay during
which the IN+ and IN- pins must cycle at least once.
FIGURE 35. FIGURE 36.

16
 HIP4081

Dual-In-Line Plastic Packages (PDIP)

N
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.55 1.77 8
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.980 1.060 24.89 26.9 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
eA 0.300 BSC 7.62 BSC 6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eB - 0.430 - 10.92 7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated N 20 20 9
in JEDEC seating plane gauge GS-3. Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

17
 HIP4081

Small Outline Plastic Packages (SOIC)

N M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX 0.25(0.010) M B M
AREA H
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0926 0.1043 2.35 2.65 -
1 2 3 A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.4961 0.5118 12.60 13.00 3
D A h x 45o
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.050 BSC 1.27 BSC -
α
e H 0.394 0.419 10.00 10.65 -
A1
C h 0.010 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 20 20 7
α 0o 8o 0o 8o -
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.

All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.

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18