RV College of

Engineering

Unit 3
Hardware of 8051 Microcontroller
1
 Unit 3
 Introduction to Embedded system,Comparison of Microprocessor and
Microcontroller, Intel MCS 51 family, Architecture and Pin Functions of 8051
Microcontroller, CPU Organization, Program Counter, Timing and Machine Cycles,
Internal Memory Organization, Registers, Stack, Input/ Output Ports, Counters
and Timers, Interrupts, Power Saving Modes.

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Reference Books
1. Kenneth J. Ayala; “The 8051 Microcontroller Architecture, Programming
&Applications”;Thomson Learning; 2nd Edition, 2004.
2. Muhammad A Mazidi; ”The 8051 Microcontroller and Embedded Systems”;
Pearson Education; 2nd Edition, 2009.
3. Intel 8051 Technical Reference Manual

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Embedded System
Input Output
CPU

SENSOR ACTUATOR
t
x(t) y(t)
Response Time

 The embedded system is a combination of hardware and software

integrated in an optimal way to perform predefined set of functions.

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Comparison of Microprocessor and Microcontroller
 A microprocessor contain no RAM,ROM or no peripherals.
 A system designer must add peripherals externally to make a
processor functional, hence commonly referred as general purpose
microprocessors.
 A Microcontroller contain CPU in addition to fixed amount of RAM,
ROM & peripherals on a chip.
 The peripherals are integrated in microcontroller, ideally suited for
specific applications.

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 Microprocessor (MP) & Microcontroller (MC)
MP
 A silicon chip representing a Central
Processing Unit (CPU), which is capable of
performing arithmetic as well as logical
operations according to a pre-defined set
of Instructions.
 It is a dependent unit. It requires the
combination of other chips like Timers,
Program and data memory chips etc.
for functioning.
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MC
• A microcontroller is a highly integrated
chip that contains a CPU, RAM, On Chip
ROM/FLASH memory for program
storage, Timer and Interrupt control units
and dedicated I/O ports.
 It is a self contained unit and it doesn’t
require external, Timer, UART etc. for
its functioning.
Microprocessor (MP) & Microcontroller (MC)
MP
 Doesn’t contain a built in I/O port. The I/O
Port functionality needs to be implemented
with the help of external Programmable
Peripheral Interface chips like 8255.
 Most of the time general purpose in design
and operation.
 Limited power saving options compared to
microcontrollers.
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MC
 Most of the controllers contain multiple built-
in I/O ports which can be operated as a single
8 or 16 or 32 bit Port or as individual port
pins.
 Mostly application oriented or domain
specific.
 Includes lot of power saving features.
Microprocessor (MP) & Microcontroller (MC)

Data Pgm Data Pgm

Memory Memory Memory Memory

 E.g:8086  E.g:8051

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  Which is computationally intensive(capable of performing
complex operations)?
Processor
or
Controller

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Intel 8051 Features:
 40- pin DI package(DIP).
 Harvard Architecture.
 8-bit Arithmetic Logic Unit.
 On-chip oscillator:1–16MHz operating frequency.
 16-bit address bus :216 = 65,536 = 64K bytes of Locations.
 8-bit data bus.
 4K ROM: Program Memory.
 128 bytes of RAM: Data Memory (32 REGs,+16 bytes of Bit addressable RAM+80 bytes
user RAM).
 Two 16 bit timers/counters with interrupts.
 Four 8 bit parallel ports.
 1 serial port with interrupt facility.
 2 external Interrupts( total - 6 Interrupts including RESET).
 Micro programmed control unit.
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 Questions
 What is scratch pad memory organization of registers?
 What is an external & Internal interrupt?
 Differentiate between serial data transfer & parallel data transfer.
 Differentiate between counter & timer operation.

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 Block Diagram of Intel 8051

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MCS-51 family
MC Features
8031 Intel's: 0K–ROM, 128-Bytes RAM, 32-
I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts.
8051 Intel's: 4K–ROM, 128-Bytes RAM, 32-
I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts.
8052 Intel's: 8K–ROM, 256-Bytes RAM, 32-
I/O pins, 32-Regs, 3-Timers, 1-Serial
port, 7–Interrupts.

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 MCS-51 family
AT89C51 Atmel's: 4K–Flash, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-
Timers, 1-Serial port, 6-Interrupts,Vcc =5V.

AT89LV51 Atmel's: 4K–Flash, 128-Bytes RAM, 32- I/O pins,32-Regs, 2-

Timers, 1-Serial port, 6-Interrupts,Vcc =3V.

DS5000 Dallas's: 8K–ROM, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-

Timers, 1- Serial port, 6-Interrupts,Vcc =5V.
(ROM: Non volatile RAM)

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 MCS-51 family

8751 •4 K bytes of on chip of UV-EPROM

•PROM burner and UV-EPROM erase the contents
•Takes 20 mins to erase

OTP 8051 •One-Time- Programmable

•Cheaper(price/unit)
•Long life time

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 AT89C51ED2(MCU used in lab)
 80C52 Architecture Compatible
– 8051 Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bitTimer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
 ISP (In-System Programming) Using StandardVCC Power Supply
 64K Bytes On-chip Flash Program Memory
 On-chip 1792 bytes Expanded RAM (XRAM)
 On-chip 2048 Bytes EEPROM Block for Data Storage
 SPI(Serial Peripheral ) Interface (Master/Slave Mode)
 Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
 HardwareWatchdog Timer
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 Questions
 What is instruction set compatibility?
 Why AT8951ED2 MC is used in lab?
 What is the advantage of using FLASH as program memory?

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 Intel 8051 chip: Pin Diagram
40 pin IC: Most of the pins are used to connect to I/O devices or external data
and code memory.

 4 I/O ports take 32 pins(4 x 8 bits) plus a pair of XTALs pins for crystal
clock.
 A pair of Vcc and GND pins for power supply (the 8051 chip needs +5V
500mA to function properly).
 ALE, PSEN and EA for memory interface.
 One Reset pin for reboot purpose.

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 P1.0 1 40 Vcc

P1.1 2 39 P0.0(AD0)

P1.2 3 38 P0.1(AD1)

P1.3 4 37 P0.2(AD2)

P1.4 5 36 P0.3(AD3)
Ext
Memory
P1.5 6 8051 35 P0.4(AD4) Address
P
I P1.6 P0.5(AD5)
7 34

N P1.7 8 33 P0.6(AD6)

RST 9 32 P0.7(AD7)

D (RXD) P3.0 10 31 EA/VPP

I
(Serial)
Ext Memory
(TXD) P3.1 11 30 ALE/PROG Access Control

A (INT0) P3.2 12 29 PSEN

G interrupt
(INT1) P3.3 13 28 P2.7(A15)
R
(T0) P3.4 P2.6(A14)
A
14 27
Timer

M (T1) P3.5 15 26 P2.5(A13)

(WR) P3.6 16 25 P2.4(A12)

Ex M W/R
(RD) P3.7 17 24 P2.3(A11) Ext Memory
Address

XTAL 2 18 23 P2.2(A10)
clock
XTAL 1 19 22 P2.1(A9)

19 MGRJ,ECE,RVCE GND 20 21 P2.0(A8)

 8051 pins…

 PSEN (Program Store Enable)

 This is a dedicated control line on pin 29 and is used to enable
external program (code) memory.
 This pin usually connects to an EPROM’s Output Enable (OE) pin.

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 8051 pins…

On-Chip Oscillator Inputs

 Pin 18, 19 (XTAL2, XTAL1)
 Clock frequency:1 to 16MHz)
 Typically driven by a crystal. Normal crystal frequency is 11.0592 MHz
to generate standard baud rates.
 Minimum frequencies imply that some internal memories are dynamic
and must always operate above a minimum frequency or data will be
lost.

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 8051 pins…
Crystal Connection

C1, C2 = 30 pF 10 pF for Crystals

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 Clock cycle, Machine cycle, Instruction cycle
 Clock cycle = time of one cycle of clock (oscillator)
 Machine cycle =12 clock cycles for 8051
 Instruction cycle = period for executing one instruction.
 Most instructions need only one machine cycle to complete. While
others can be executed in 2 and 4 machine cycles.

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 Instruction Vs Clock cycle

S1 S6
Clock cycles P12
P1 P2

Machine
Cycle

• 12 clock cycles are called One machine cycle and One or more machine
cycles gives Instruction Cycle.
• Instruction cycle depends on how many machine cycles an instruction is
taking for execution.
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 8051 pins…
Reset
 The reset input is the RST pin, which is a input to initiate reset operation.
 A reset is accomplished by holding the RST pin high for at least two
machine cycles(24 oscillator periods), while the oscillator is
running.
 The external reset signal is asynchronous to the internal clock.
 The internal reset algorithm writes 0s to all the *SFRs except the port
latches, the Stack Pointer.
 The program counter is loaded with 0000H.

*SFR: Special Function Registers

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 Architecture of 8051…
Program Memory
EA=1 EA=0

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 Program memory…

 After reset, the CPU begins execution from location 0000H.

 if the EA pin is strapped to Vcc, then program fetches to
addresses 0000H through 0FFFH are directed to the internal ROM.
Program fetches to addresses 1000H through FFFFH are directed to
external ROM.
 If the EA pin is strapped to Vss(ground), then all program
fetches are directed to external ROM. The ROM less parts must
have this pin externally strapped to Vss to enable them to execute
properly.

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 Architecture of 8051…
128 bytes of Internal RAM structure(lower address space)

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 Architecture of 8051…
Working registers
 32 bytes form address 00h-1Fh make up 32 working registers.
 Organized into 4 register banks numbered from Bank 0 to Bank 3 and are made
up of eight registers named R0 to R7.
 At any time one bank is active, based on status of RS0 and RS1 bits of
PSW(program status word).
 Default is Bank0 (RS0=RS1=0)
 Registers can be accessed either by RAM address or name(when its bank is
selected).
 E.g. R0 of bank 3 is R0(if bank 3 is currently selected RS1=1,RS0=1) or address
18h( whether bank 3 is selected or not)

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 Working registers

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 Architecture of 8051…

Bit addressable locations

 A bit addressable area of 16 bytes occupies RAM byte address 20h to
2Fh, forming a total of 128 addressable bits.
 An addressable bit may be specified by its bit address of 00h to 7Fh or 8
bits may be form any byte address from 20h to 2Fh.
 Addressable bits are useful when the program need only remember a
binary event (switch on, light of, etc…)

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 Bit addressable locations

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128 bytes of Internal RAM structure(Upper address space)

 The RAM locations above are mapped

into special function registers(SFR).

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 Architecture of 8051
Stack & Stack Pointer SP
 RAM locations are used of stack operations
 SP points to the data item currently on the top of stack.
 Push data onto stack: PUSH :
 (SP) <- (SP) + 1
 ((SP)) <- (direct)
 Pop data from the stack: POP :
 (direct) < ((SP))
 (SP) <- (SP) – 1
 The stack pointer in the 8051 is only 8 bits wide, which means that it can take
value 00 to FFH.When 8051 powered up, the SP register contains value 07.
 The stack uses locations form 08h to 7Fh.

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 Architecture of 8051
Example:
MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4
POP 4

0BH
0BH 0BH 0BH 0BH

0AH
0AH 0AH 0AH 0AH F3

09H 12
09H 09H 09H 12 09H 12

08H 25
08H 08H 25 08H 25 08H 25

SP=09H
Start SP=07H SP=08H SP=09H SP=0AH

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 Architecture of 8051

Accumulator(A) & B CPU registers

 8 bit registers, hold results of many arithmetic and logical instructions.
 Both are bit addressable

 Accumulator bits can also be addressed as follows.

ACC.7 for MSB……..acc.0 for LSB

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 Program Counter(PC)

 PC is 16 bit register points to next instruction to be executed.

 The PC is automatically incremented after every instruction
byte is fetched and may also be altered by curtain instructions.
 The PC in only register that does not have an internal address.

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 Data Pointer( DPTR)
 The DPTR is made up of two 8-bit registers, named DPH and DPL.

DPH DPL

 RAM address

 The DPTR can be used as single 16 bit register or two separate 8 bit registers.

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 Program status word(PSW)
F1

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 Architecture of 8051

Details of PSW
 status register of 8 bit wide at address 0D0h
 CY =1 when Addition>0 or subtraction<0
 AC =1 when low nibble affects high nibble
 F0 = User flag
 RS1 = Register bank select bit 1
 RS0 = Register bank select bit 0
 OV is used to detect errors in signed arithmetic operations.
 F1 = User flag
 P = 1 when ACC has odd no. of ones.
 Bit addressable(D7/PSW.7 – D0/PSW.0)
 Zero flag is not there in PSW but it is in Jump instructions as JZ(Jump is zero).
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 How to switch Register Bank?
RS1 (PSW.4) RS0(PSW.3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1

• Each bank has 8-registers(R0 –R8) but by default Bank 0 is selected

and accessed.
• Cleared after reset and changed by software.
E.g. SETB RS1
SETB RS0
MOV A, R7 ;use bank3

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 I/O Port Structure
•Each port of 8051 has bidirectional capability.

•Port 0 is called 'true bidirectional port' as it floats (tristated) when

configured as input.

•Port-1, 2, 3 are called 'quasi bidirectional port’.

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•PORT 0 Pin Structure
Port -0 has 8 pins (P0.0-P0.7).
The structure of a Port-0 pin is as shown below.

O/P
Buffer
LATCH

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 Port- 0…

 Port-0 can be configured as a normal bidirectional I/O port or it can be used for
address/data interfacing for accessing external memory.
 When control is '1', the port is used for address/data bus memory interfacing.
 When the control is '0', the port can be used as a normal bidirectional I/O port.

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 Port- 0…
Address/ Data Bus
1. Control=1, port 0 = Address/Data Interfacing.
2. When Control =1, address/data bus controls the output driver
MOSFETs.
3. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the
lower MOSFET is 'on'.The output becomes '0'.
4. If the address/data bus is '1', the upper transistor is 'on' and the lower
transistor is 'off'. Hence the output is '1'.
5. Port-0 latch is written to with 1's when used for external memory
access.

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 Port- 0…

I/O Operation
 Let us assume that control is '0'. When the port is used as an input port, '1' is
written to the latch.
 In this situation, both the output MOSFETs are 'off'. Hence the output pin floats
(high impedance). This high impedance state of the pin can be masked by external
device by making pin low or high.

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 Port- 0……
 When the port is used as an output port, a '1' written to the latch again turns 'off' both the
output MOSFETs and causes the output pin to float. An external pull-up is required to
output a '1'.
Vcc
10
K
P0.0

Port
P0.1
P0.2
P0.3
P0.4 0
P0.5
P0.6
P0.7
8051

 But when '0' is written to the latch, the pin is pulled down by the lower MOSFET.
Hence the output becomes zero.
 Output port does not require configuration.
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49
 Questions
 How to configure a port as input?
 What is the default direction of the ports?
 What is the driving capability of port 0?

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 Port-1 Pin Structure

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 Port-1…

 Port-1 does not have any alternate function i.e. it is dedicated solely for
I/O interfacing.
 For output port, the pin is pulled up or down through internal pull-up.
 To use port-1 as input port, '1' has to be written to the latch.
 Due to internal pull-up there is limited current driving capability.

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 Question
 Design 8051 system to connect LED and switch. Write a C program to read switch
and display status on LED.
 Design 8051 system to realize 2 digit BCD counter on seven segment interface. Write
a program to read a button event to start BCD counter.
Seven segment display codes: Common Anode type
03H,9FH,25H,0DH,99H,49H,41H,1FH,01H,09H,
Segment values to display 3:

Segment A B C D E F G H
Bit 7 6 5 4 3 2 1 0
Input 0 0 0 0 1 1 0 1
Hex Code 0 D

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 Question
 The diagram below shows an interface card with eight DIP switches with status indicating
LEDs D1 & D8. The card also features 8 LEDs (D9-D16) controlled by external devices.
Design a suitable scheme to interface card to 8051.Write a program to read the
status of switches & display the same on LEDs D9-D16.

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 Question
 The diagram below shows an interface that provide two digit seven segment display driven
by the outputs of two cascaded serial-in-parallel-out shift registers. Data to be displayed is
transmitted serially (first segment H).Each bit is clocked into the shift registers by
providing common clock. Data in first shift register appears at second after eight clock
pulses. Provide a push button to start the counting operation.

Vcc

MGRJ,ECE,RVCE Data CLK

55
  The seven segment type is common anode type. The display codes are
obtained as follows.
Segment values to display 3
Segment A B C D E F G H
Bit 7 6 5 4 3 2 1 0
Input 0 0 0 0 1 1 0 1
Hex Code 0 D

 Seven segment display codes:

03H,9FH,25H,0DH,99H,49H,41H,1FH,01H,09H,
Design 8051system interface seven segment display & realize two digit BCD
counter.

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 Port-2 Pin Structure

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 Port-2…

 Port-2 is used for higher external address byte or a normal input/output port.
 The I/O operation is similar to Port-1.
 Port-2 latch remains stable when Port-2 pin are used for external memory access.
 In this port, due to internal pull-up there is limited current driving capability.

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 Port-3 Pin Structure

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 Port-3…
 Each pin of Port-3 can be individually programmed for I/O operation or for alternate
function.
 The alternate function can be activated only if the corresponding latch has been written to
'1'.
 To use the port as input port, '1' should be written to the latch. This port also has internal
pull-up and limited current driving capability.
 Alternate functions of Port-3 pins:
 When used as IO pin, the alternate output
signal is held high by control circuit.

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 Reading a port (port-pins) Vs reading a latch
 Reading a latch: Usually the instructions that read the latch, read a value, possibly
change it, and then rewrite it to the latch. These are called "read-modify-write"
instructions.
 Examples of a few instructions are-
ORL P2, A; P2 <-- P2 or A
 Reading a Pin: Examples of a few instructions that read
port pin, are-
MOV A, P0 ; Move port-0 pin values to A
MOV A, P1; Move port-1 pin values to A

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 8051 port current ratings

 P0
IOL=3.2 mA

 P1, P2 and P3
IOL=1.6 mA
IOH=60 µA

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Exam Questions

a. Differentiate between a microprocessor and microcontroller.

b. List the salient features of 8051.
c. Explain memory organization in 8051
d. Mention the difference between
 Assembly coded program and high level language program.
 Directive and Instructions

e. Draw a block diagram that represents 8051 Microcontroller and brief on

the Functionalities of some important blocks

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 Question
 Design 8051 based system to display a stringin first row of 2x16 LCD. The figure
below shows interfacing diagram.

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 2 x 16 LCD Interface:
 The LCD driver used in lab requires 3 control lines as well as either 4 or 8 I/O lines
for the data bus.
 The user may select whether the LCD is to operate with a 4-bit data bus or an 8-bit
data bus.
 If 4-bit data bus is used, the LCD will require a total of 7 data lines (3 control lines
plus the 4 lines for the data bus).
 If 8-bit data bus is used, the LCD will require a total of 11 data lines (3 control lines
plus the 8 lines for the data bus).
 The three control lines are referred to as EN, RS, and RW.

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 Pin description of PIN FUNCTION
LCD 1 Vss
2 Vcc
3 VEE – Contrast Control Supply
4 RS – 0- Command reg (clear,
cursor at home, etc)
1-Select Data reg
5 R/W’
6 EN – Latch Enable
7 DB0
8 DB1
9 DB2
10 DB3 Data Lines
11 DB4
12 DB5
13 DB6
66 MGRJ,ECE,RVCE 14 DB7
 LCD control Signals

 The RS line is the "Register Select" line.

 When RS is low (0), the data is to be treated as a command or special
instruction (such as clear screen, position cursor, etc.).
 When RS is high (1), the data being sent is text data which should be
displayed on the screen.
 The RW line is the "Read/Write" control line.
 When RW is low (0), the information on the data bus is being written
to the LCD.
 When RW is high (1), the program is effectively querying (or reading)
the LCD. (The Status of RS=0 while reading).

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 LCD Control Signals
 Only one instruction ("Get LCD status") is a read command. All others are write
commands.
 The busy status of the LCD is indicated by a logic 1 on D7 bit.
 Enable(EN): 1 to 0 transition while writing LCD and 0 to 1 transition while
reading LCD.
 To display a character on LCD, equivalent ASCII values must be sent on data bus.

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 LCD Commands: Examples
 0x38 // 8 BIT DATA , 2LINE, 5X7 DOT MATRIX
 0x0F // DISPLAY ON, CURSOR ON, BLINK
 0x01; //CLEAR DISPLAY
 0x80; // Address of FIRST LINE (2x16 LCD)

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Question
Design & implement 8051 based system to convert analog DC voltage in the range
0-5V to digital value. Interface ADC 0808/0809 to GPIOs. Send digital value to
LCD connected to port 1. Use following pins to interface ADC.
Start of conversion(SOC)=P2.7
Output Enable(OE)=P2.6
Address Latch Enable(ALE)=P2.7
Address lines=P2.2-P2.0
End of conversion(EOC)=P0.7
Data lines(D0-D7)=P0.0-P0.7

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 Pin Diagram: ADC 0809

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Interfacing ADC 0809:Features
• 8-bit analog-to-digital converter.
• successive approximation as the conversion technique.
• 8-channels (IN1- IN18)
• 3 user programmable address lines (ADD A-ADD C)
• REF(+) & REF(-) set the reference voltage.
• If REF(+) =5 V and REF(-)=GND, the step size is 19.53 mv(5/256). The input analog
voltage can be varied between 0(00H) to 5V(FFH).
• ALE to latch in the address.
• Start(SOC) is for start of conversion.
• EOC(end of conversion) and OE(output enable) is to read the 8 bit digital value (Refer
timing diagram).
• 50 KHz clock
• Conversion time is 100µS.

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 Timing diagram: ADC 0809

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 Timers/Counters
 Two 16-bit timers/counters: T0 and T1 in 8051
 8052 has a third timer: T2
 Used as interval timer (fosc/12) or event counter (External clock
T0-P3.4, T1 -P3.5 pins)
 4 operation modes for T0, T1
 Up-counting timer/counter
 TMOD (89H), and TCON (88H) to set/control timer modes and
operation.
 TL0 (8AH), TH0 (8CH), TL1 (8BH), TH1 (8DH) hold timer current
count value.

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Timer Special Function Registers
Timer SFR Purpose Address Bit-addressable

TCON Control 88H Yes

TMOD Mode 89H No
TL0 Timer 0 low-byte 8AH No
TL1 Timer1 low-byte 8BH No
TH0 Timer0 high-byte 8CH No
TH1 Timer1 high-byte 8DH No

75 MGRJ,ECE,RVCE
 TCON (88H)

76 MGRJ,ECE,RVCE
 TMOD(89H)

77 MGRJ,ECE,RVCE
 Timer Control Logic:

Tx

CK
PULSES

78 MGRJ,ECE,RVCE
 Mode 0
 In this mode, the timer is used as a 13-bit UP counter as follows.
 The 13-bit counter can hold values between 0000 to 1FFFh in THx – TLx.
 The lower 5 bits of TLx and 8 bits of THx are used for the 13 bit count.
Upper 3 bits of TLx are ignored. When the counter rolls over from all 1's
to all 0's,TFx flag is set and an interrupt is generated.

79 MGRJ,ECE,RVCE
 Timer 1 in mode 0(with control logic)

80 MGRJ,ECE,RVCE
 Mode 1
 In this mode, the timer is used as a 16-bit UP counter as
follows.
 The 16-bit counter can hold values between 0000 to FFFFh
in THx – TLx.
 When the counter rolls over from all 1's to all 0's, TFx flag is
set and an interrupt is generated.

81 MGRJ,ECE,RVCE
Mode 1:16 bit mode (with control logic)

82 MGRJ,ECE,RVCE
 Timer Programming:
Timer clock frequency & period:

Crystal o/p Time

frequency frequency period
12 MHz 1MHz 1μS
11.0592 MHz 921.6KHz 1.085μS
16 MHz 1.333MHz 0.75μS
Timer Modes:
TMOD = xxxx xx01 – Timer 0, Mode 1
TMOD = xxxx xx00 – Timer 0, Mode 0
TMOD = xx01 xxxx – Timer 1, Mode 1
COUNT TO BE LOADED: If the delay is 10 μS,
then load (65536 – 10)=65526 in to the timer.
Timer counts 10 clock pulses & creats a delay
of 10 μS, with a crystal frequency of 12MHz.
83 MGRJ,ECE,RVCE
 Timer programming
1. Load TMOD register with mode value.
2. Load TH & TL registers with initial count value.
3. Start Timer using TR bit.
4. Monitor TF flag till it is SET.
5. Clear TF flag for next iteration.
6. Go to Step 2 for repetition

84 MGRJ,ECE,RVCE
Question
 Write a program to generate delay of 0.5 msec using timer0 and
complement pin P1^0 (Assume clock of 12MHz) in mode 1.

Timer I/P freq=clock/12=1MHz

Time period= 1us
No of counts=0.5m/1 u=500
Initial count=65536-500=65036=FE0Ch
Note: Header file reg51.h contains all registers declaration
Timer Registers:TMOD,TCON,TH0,TL0,TH1,TL1
Control Bits:TR0,TR1,TF1
85 MGRJ,ECE,RVCE
 C Program:
#include<reg51.h>
sbit pin=P1^0;

void main()
{
pin=0;
TMOD=0x01; //timer 0 in mode 1
while(1)
{
TH0=0xFE; // Loading Initial Count
TL0=0x0C; // Loading initial count
pin=~pin;
TR0=1; // Starting timer
while(TF0==0); // monitoring overflow flag
TF0=0;
TR0=0;
}
}

86 MGRJ,ECE,RVCE
 Question
 Write a program to generate square wave of frequency 4 KHz on pin
P2.0.(XTAL=11.0592 MHz).

Timer I/P freq=0.9216 MHz

No of counts=0.125 m/1.085 u=115.20
Initial count=65536-115=65036=FF8Dh

87 MGRJ,ECE,RVCE
 Program:
#include<reg51.h>
sbit pin=P2^0;

void main()
{
pin=0;
TMOD=0x01; //timer 0 in mode 1
while(1)
{
TH0=0xFF; // Loading Initial Count
TL0=0x8d; // Loading initial count
pin=~pin;
TR0=1; // Starting timer
while(TF1==0); // monitoring overflow flag
TF0=0;
TR0=0;
}
}

88 MGRJ,ECE,RVCE
 Question
 Write a program to generate delay of 1 sec using timer 1
(XTAL=12 MHz).

Max delay in mode 1=65536 u sec

For 1 sec delay, 15.25*65536 u =1sec

89 MGRJ,ECE,RVCE
 Program:
#include<reg51.h>
void main()
{
unsigned char x=15;
TMOD=0x10; //timer 1 in mode 1
TR1=1; // Starting timer
while(x>0)
{
while(TF1==0); // monitoring overflow flag
TF1=0;
x--;
}
while(1);
}

90 MGRJ,ECE,RVCE
 Note: The execution time for different C statements in previous
programs is not considered while calculating delay.
 The Development IDEs comes with tools which allows us to
find the execution time of C statements.
E.g: Keil: Cycle Tracer & Execution Profiler

91 MGRJ,ECE,RVCE
 Question
 The block diagram below shows 8051 based pulse width measurement system in
polled mode.The measured pulse width is displayed on LCD (in milliseconds).

 For accurate measurement of pulse width, a timer is used. At some point of time,
the displayed pulse width is 17.The count value of timer for this width
is_____________________.
92 MGRJ,ECE,RVCE
 Question
 Design & Implement 8051 based system to convert analog DC voltage in the range 0-
5v to digital value with following specifications. Interface ADC 0809 to GPIOs.
Generate PWM wave on pin P3.1 & vary duty cycle in accordance with analog input
voltage.
Pins for ADC interface:
Start of conversion(SOC)=P2.7
Output Enable(OE)=P2.6
Address Latch Enable(ALE)=P2.7
Address lines=P2.2-P2.0
End of conversion(EOC)=P0.7
Data lines(D0-D7)=P0.0-P0.7

93 MGRJ,ECE,RVCE
 Question: Dice
 In the diagram shown below, the seven LEDs are mounted to emulate the dots on
real dice. The pattern displayed for different numbers is shown. As in real dice,
first row can have up to two LEDs on (Corresponding to two dots on a dice),
second row have up to three LEDs on and third row have up to two LEDs on.

94 MGRJ,ECE,RVCE
 Question: Dice
 A random dice number is obtained by scanning push button switch as
follows. If the switch is not pressed, the number is incremented between 1
and 6.When ever the push button is pressed, the current value of the
number is read and this value is used as new dice number. The new number
is displayed on LED for 2 seconds.
Design 8051 system with above specifications and write C program to
emulate dice operations.

95 MGRJ,ECE,RVCE
 Dice: Algorithm

96 MGRJ,ECE,RVCE
 Question
 Design 8051 based 4 digit BCD counter on seven segment display interface card with
schematics as shown below. The 74LS164 is an edge-triggered 8-bit (stage) shift register
with serial data entry and an output from each of the eight stages. Data is entered serially
through serial I/P. Each LOW-to-HIGH transition on the Clock (CLK) input shifts the data
1 bit right and enters into output to which a segment of seven segment display & I/P of
the next stage is connected.
 To the output of first stage of shift register, segment ‘a’ is connected. It can be seen from
the interfacing diagram that, first bit after 8 clock pulses is available at h output of the shift
register S1 and thus controls the h segment of D3. Similarly, first bit, after 16 clock pulses,
is available at h output of the shift register S2 and thus controls the h segment of D2. The
seven segment display is of type common anode, with display codes for 0 to 9 is as given
below (the MSB is value of segment h).
 Show the implementation by writing connection diagram with 8051 & program in C.

97 MGRJ,ECE,RVCE
 Seven segment display codes: (Common anode type :LSB is h segment)
03H,9FH,25H,0DH,99H,49H,41H,1FH,01H,09H

98 MGRJ,ECE,RVCE
Mode 2: 8-bit Auto-Reload
 This is a 8 bit counter/timer operation. Counting is performed
in TLx while THx stores a constant value.
 In this mode, when the timer overflows i.e. TLx becomes FFH,
not only sets TFx, but also reloads TLx with value stored in THx.
 For example, if we load THx with 50H then the timer in mode
2 will count from 50H to FFH. After that, 50H is again reloaded
(hardware reload).

99 MGRJ,ECE,RVCE
 Mode 2: Timer1 in 8-bit Auto-Reload

100 MGRJ,ECE,RVCE
 Mode 3: Split-Timer Mode
 Mode 3 applicable only for Timer 0
 Timer 1 in mode-3 simply holds its count. The effect is same as
setting TR1=0.
 Timer0 in mode-3 establishes TL0 and TH0 as two separate
counters.
 Control bits TR1 and TF1 are used by Timer-0 higher 8 bits (TH0) in
Mode-3 while TR0 and TF0 are available to Timer-0 lower 8
bits(TL0).

101 MGRJ,ECE,RVCE
 Mode 3: Split-Timer Mode

102 MGRJ,ECE,RVCE
 Mode 3…
 When Timer 0 is in Mode 3, Timer 1 can be turned on
and off by switching it out of and into its own Mode 3.
 Timer 1 can be used to generate the baud rate for serial
communication or any application not requiring an
interrupt.

103 MGRJ,ECE,RVCE
 Question
 Write a program using Timer0 in mode 2 to create a 10KHz
PWM wave with 50% duty cycle on P1.0 (XTAL =12 MHz)

Clock period of square wave=100 u sec

Ton= 50 u sec, Toff=50 u sec
Timer I/P frequency=1 MHz
Timer clock period=1u sec
Initial count=256-50=206

104 MGRJ,ECE,RVCE
 program:
#include<reg51.h>
sbit PWM=P1^0;
void main()
{
TMOD=0x02;
TH0=TL0=-50;
TR0=1;
while(1)
{
while(TF0==0);
PWM=~PWM;
TF0=0;
}
}

105 MGRJ,ECE,RVCE
 Questions
 WAP for generating time delay of 38ms.
 WAP for generating delay of 5ms square wave on P3.4 continuously.
 Assuming that XTAL = 11.0592Mhz, write a program to generate PWM
wave of 2KHz frequency with duty cycle 60% on pin P1.5.
 Assuming that XTAL = 11.0592Mhz, write a program to generate a square
wave of 30 Hz frequency on pin P3.5?

106 MGRJ,ECE,RVCE
Counter Operation
 In the “Counter” function, the register is incremented in
response to a l-to-0 transition at its corresponding external
input pin,T0,T1.

 The external input is sampled during S5P2 of every machine cycle.

 When the samples show high in one machine cycle and a low in the
next machine cycle, the count is incremented.
107 MGRJ,ECE,RVCE
 Counter Operation…

 The new count value appears in the register during S3P1of

the cycle following the one in which the transition was
detected.
 Since it takes 2 machine cycles (24 oscillator periods)to
recognize a l-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency.
 There are no restrictions on the duty cycle of the external
input signal, but ensure that a given level is sampled at least
once before it changes.

108 MGRJ,ECE,RVCE
Serial Port of 8051
110 MGRJ,ECE,RVCE
111 MGRJ,ECE,RVCE
112 MGRJ,ECE,RVCE
113 MGRJ,ECE,RVCE
114 MGRJ,ECE,RVCE
 Asynchronous: Transmission of 5Dh

STOP 0 1 0 1 1 1 0 1 START
BIT BIT

MSB LSB

115 MGRJ,ECE,RVCE
 8051 serial port
 The serial port is full duplex, meaning it can transmit and
receive simultaneously.
 Separate TxD & RxD lines
 The serial port receive and transmit registers are both accessed
at Special Function Register SBUF.
 Writing to SBUF loads the transmit register, and reading SBUF
physically access separate receive register.

116 MGRJ,ECE,RVCE
 Registers of serial port
 SBUF register
-RAM address:99h
-For a byte of data to be transferred via TxD line, it must
be placed in SBUF register.
MOV SBUF,#4Dh
MOV SBUF,#’d’ :ASCII value
MOV SBUF,A
SBUF=‘A’;
- SBUF hold the byte of data received over RxD line
MOV A,SBUF
temp=SBUF;

117 MGRJ,ECE,RVCE
 SCON register(Bit addressable)
•RAM address:98h

SCON .7 SCON .0
•SM0,SM1 :serial mode bits

118 MGRJ,ECE,RVCE
  SM2: Multiprocessor communication enable bit in modes 2 and 3.
 REN: Receive enable bit
1=Enable reception
0=Disable reception
 TB8 is the 9th bit that will be transmitted in modes 2 and 3.
-set/cleared by software as desired
 RB8 is the 9th bit received in modes 2 and 3.

119 MGRJ,ECE,RVCE
  TI: Transmit interrupt flag
-Set by H/W at the end of the 8 bit in mode 0 or at the beginning
of stop bit in other modes.
-Must be cleared by S/W
 RI: Receive interrupt flag
-Set by H/W at the end of the 8 bit reception in mode 0
-Set by H/W at halfway through stop bit reception in other modes.
-Must be cleared by S/W
 NOTE:Neither of these flags are cleared by hardware when the service routine is
vectored to.

120 MGRJ,ECE,RVCE
 PCON register
 RAM address:87h

Not implemented

 SMOD : Serial baud modify bit

-Set to 1 by program to double baud rate in modes
1, 2 and 3
 GF1: General purpose flag bit 1
 GF0: General purpose flag bit 0
 PD: Power down mode bit 0
 IDL: IDLE mode bit
121 MGRJ,ECE,RVCE
 Data transmission
 Transmission begin any time data is written into SBUF.
 TI is set to 1 when data has been transmitted & signifies that SBUF
is empty and another byte can be send.
Transferring character ‘A’ continuously
while(1){
SBUF=‘A’;
while( TI==0);
TI=0;
}

122 MGRJ,ECE,RVCE
 Data reception
 REN must be enabled to start data reception for all modes.
 For mode 0, RI must be cleared to 0.
Reading serial port continuously
Unsigned char data;
REN=1;
while(1){
while(RI==0);
data=SBUF;
RI=0;
}
123 MGRJ,ECE,RVCE
 Mode 0:Shift Register Mode
 Serial data enters and exits through RXD.
 TXD outputs the shift clock.
 8 bits are transmitted/received(LSB first).
 The baud rate is fixed at 1/12 the oscillator frequency.
 The transmission is enabled any time SBUF is the destination of write
operation, regardless of state of TI flag bit of SCON.
 The receiver is enabled when REN of SCON is enabled by software and RI bit
is set 0.
 Enabling reception also enables the clock pulses that shift the received data into
the receiver.
 A serial data transmission interrupt is generated at end of the transmission or
reception if interrupts are enabled.
124 MGRJ,ECE,RVCE
 Mode 0

125 MGRJ,ECE,RVCE
 Serial Data Mode 1:Standard UART
 10 bits are transmitted (through TXD) or received( through
RXD) : a start bit (0), 8 data bits (LSB first), and a stop
bit (l).
 On receive, the stop bit goes into RB8 in SCON.
 The baud rate variable.
 Each bit interval is inverse of the baud rate frequency.
 Transmission is initiated by any instruction that uses SBUF as a
destination register.
126 MGRJ,ECE,RVCE
 Mode 1…

 The following figure shows the way the bits are transmitted/ received.


127 MGRJ,ECE,RVCE
  In receiving mode, data bits are shifted into the receiver at the
programmed baud rate.
 The data word (8-bits) will be loaded to SBUF if the following
conditions are true.
1.RI must be zero. (i.e., the previously received byte has
been cleared from SBUF) and
2. Mode bit SM2 = 0 or stop bit = 1.
 In mode-1, if SM2 is set to 1, no receive interrupt (RI) is
generated unless a valid stop bit is received.
128 MGRJ,ECE,RVCE
 Baud rate for mode 1
 Timer-1 is used to generate baud rate for mode-1 serial
communication by using overflow rate of the timer.
 The baud is determined by, timer 1 overflow frequency & SMOD bit
of PCON register as follows.

 The Timer 1 itself can be configured for either “timer” or “counter”

operation, and in any of its 3 running modes.

129 MGRJ,ECE,RVCE
 Baud generation Mode 1…

 Frequently, the Timer 1 is configured in auto-reload mode.

 In this case, baud rate is calculated as follows.

130 MGRJ,ECE,RVCE
 Mode 1…
Example:
 If standard baud rates are desired, then 11.0592 MHz crystal is
selected.
 To get a standard 9600 baud rate, the setting of TH1 is calculated as
follows.
 Assuming SMOD to be '0' .

131 MGRJ,ECE,RVCE
 Mode 1…..
Programming 8051 for serial transfer of data in mode 1:

1. Load TMOD register with 20h (Timer1, mode-2).

2. Load TH1 with baud rate selector.
3. Load SCON register with 40h (mode-1, 8 bit data,1 start bit.
1 stop bit).
4. Start timer-1 (TR1=1).
5. Clear TI flag.
6. Write data into SBUF register.
7. Monitor TI flag continuously to transfer data completely.
8. Go to step-5 to transfer next data.
132 MGRJ,ECE,RVCE
 Question:
WAP to transfer character ‘A’ serially at a baud of 9600
#include <reg51.h>
void main() {
TMOD=0x20; //Timer 1 in auto reload mode
TH1= - 0x3; //baudrate of 9600
SCON=0x40; //Standard UART mode
TR1=1;
while(1) {
SBUF=‘A’;
while(TI==0);
TI=0;
}
}

134 MGRJ,ECE,RVCE
 Question:

#include <reg51.h>
void send(unsigned char);
void main() {
unsigned char string[]=“RVCE”,i=0;
TMOD=0x20;
TH1= - 0x3;
SCON=0x40;
TR1=1;
while( string[i]!=0){
send(string[i]); void send (unsigned char x)
i++; {
} SBUF =x;
while (TI == 0);
}
TI=0;
}
136 MGRJ,ECE,RVCE
 Mode 1…

Programming 8051 for serial reception of data in mode 1:

1. Load TMOD register with 20h (T1, mode-2).

2. Load TH1 with baud rate selector.
3. Load SCON register with 50h (mode-1, 8 bit data,1 start bit. 1 stop
bit, REN=1).
4. Start timer-1 (TR1=1).
5. Clear RI flag.
6. Monitor RI flag continuously to receive data completely; if RI is SET
then save SBUF in to destination after clearing RI.
7. Go to step-5 to receive next data.

137 MGRJ,ECE,RVCE
 Question:
WAP to Receive characters serially at baud rate of 4800
#include <reg51.h>
void main() {
unsigned char temp;
TMOD=0x20;
TH1= - 6;
SCON=0x40;
TR1=1;
REN=1;
While(1) {
While(RI==0);
RI=0;
temp=SBUF;
P1=temp;
}
}
139 MGRJ,ECE,RVCE
 Question
Design 8051 system to monitor switch and display status on serial port.

#include <reg51.h>
sbit SW=P1^7;
void send(unsigned char *);
void main() {
unsigned char msg1[]=“ON”,msg2[]=“OFF”; void send (unsigned char *x)
TMOD=0x20; {
TH1= - 0x3; while(*x!=0){
SCON=0x40; SBUF =*x;
TR1=1; while (TI == 0);
SW=1; TI=0;
while(1) {
x++;
if(SW==1)
send(msg1);
}
else }
send(msg2)
}
140 MGRJ,ECE,RVCE
}
 Mode 1…..

 One can achieve very low baud rates with timer 1 by leaving the Timer
1interrupt enabled and configuring the Timer to run as a 16-bit timer, and
using the timer 1 interrupt to do a software reload.
 The baud is obtained as follows:

141 MGRJ,ECE,RVCE
 Question
Design & implement 8051 based system to convert analog DC voltage in the
range 0-5V to digital value. Interface ADC 0808/0809 to GPIOs. Display the
digital value in serial window. Demonstrate polled mode of I/O support. Use
following pins to interface ADC.
Start of conversion(SOC)=P2.7
Output Enable(OE)=P2.6
Address Latch Enable(ALE)=P2.7
Address lines=P2.2-P2.0
End of conversion(EOC)=P0.7
Data lines(D0-D7)=P0.0-P0.7

142 MGRJ,ECE,RVCE
Question
 Design 8051 based system to receive a string on serial port & display in first
row of 2 x16 LCD. The figure below shows interfacing
diagram.(Baud:9600,8bits of data, 1 start bit & 1 stop bit)

143 MGRJ,ECE,RVCE
 Question: Key pad interface
 Design & Implement 8051 based system to connect 4 x 4 hex key board to GPIOs.
Display key value in serial window.

144 MGRJ,ECE,RVCE
 Question
 The rows are connected to an input port and columns are connected to output port. If
no key is pressed, the reading the input port results in 1s for all rows. If a column is
grounded and a key is pressed, one of the row will have 0(zero) since the key pressed
provides the path to ground. It is the function of the microcontroller to scan the
keyboard continuously to detect and identify the key being pressed.

145 MGRJ,ECE,RVCE
 Mode 2:Multiprocessor mode
 11 bits are transmitted (through TXD) received( through RXD):
a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a
stop bit (l)
 On Transmit, the 9th data bit (TB8 in SCON)can be assigned the value of 0 or 1.
E.g.The parity bit (P, in the PSW) could be moved into TB8.
 On receive, the 9th data bit goes into RB8 in Special Function
Register SCON.
 The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency.
 Both start & stop bits are discarded

146 MGRJ,ECE,RVCE
 Mode 2...
 Transmission is initiated by any instruction that uses SBUF as a
destination register.
 The baud rate of mode 2 is programmed as follows:

147 MGRJ,ECE,RVCE
 Mode 3:
Multiprocessor mode with variable baud rate
 Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable.
 The baud rate is programmed as follows:

148 MGRJ,ECE,RVCE
Operation in Multiprocessor mode
 8051 operates in multiprocessor mode for serial communication Mode-2
and Mode-3.
 In multiprocessor mode, a Master processor(8051) can communicate
with more than one slave processors(8051).
 The Master communicates with one slave at a time. 11 bits are
transmitted by the Master, viz, One start bit ( '0'), 8 data bits (LSB first),
TB8 and a stop bit ( '1').

149 MGRJ,ECE,RVCE
 Connection diagram
 TB8
-'1' for an address byte
- '0' for a data byte
- Software addressing
scheme

150 MGRJ,ECE,RVCE
  It should be noted that in Mode 2&3, receive interrupt flag RI is set if
REN=1, RI=0 and the following condition is true.
1.SM2=1 and RB8=1 and a valid stop bit is received.
Or
2. SM2=0 and a valid stop bit is received.
Sequence of operations:
 If the Master wants to communicate with certain slave, it first sends the
address of the slave with TB8=1.
 This address is received by all the slaves. Slaves initially have their SM2 bit
set to '1'.
 All slaves check this address and the slave who is being addressed, responds
by clearing its SM2 bit to '0' so that the data bytes can be received.

151 MGRJ,ECE,RVCE
  After the communication between the Master and a slave has
been established, the data bytes are sent by the Master with
TB8=0.
 Hence, other slaves do not respond /get interrupted by this
data as their SM2 is pulled high (1).

152 MGRJ,ECE,RVCE
 Power saving modes of operation

 8051 has two power saving modes. They are -

1. Idle Mode
2. Power Down mode.
 The structure of PCON register is as follows.

153 MGRJ,ECE,RVCE
 Schematic diagram for 'Power down' mode and 'Idle' mode

154 MGRJ,ECE,RVCE
 Idle Mode
 Idle mode is entered by setting IDL bit to 1 ( IDL =0).
 The clock signal is gated off to CPU, but not to the
interrupt, timer and serial port functions.
 The CPU status is preserved entirely. SP, PC, PSW,
Accumulator and other registers maintain their data during
IDLE mode.
 The port pins hold their logical states they had at the time
Idle was initiated. ALE and PSEN are held at logic high
levels.

155 MGRJ,ECE,RVCE
 Ways to exit Idle Mode:

1.Activation of any enabled interrupt will clear PCON.0 bit and hence
the Idle Mode is exited.
- The program goes to the Interrupt Service Routine (ISR). After
RETI is executed at the end of the ISR, the next instruction will
start from the one following the instruction that enabled Idle Mode.
2. A hardware reset exits the idle mode. The CPU starts from the
instruction following the instruction that invoked the 'Idle' mode.

156 MGRJ,ECE,RVCE
 Power Down Mode
 The Power down Mode is entered by setting the PD bit to 1.
 The internal clock to the entire microcontroller is stopped (frozen).
However, the program is not dead.
 The Power down Mode is exited (PCON.1 is cleared to 0) by Hardware
Reset only.
 The CPU starts from the next instruction where the Power down Mode
was invoked. Port values are not changed in power down mode.
 VCC can be reduced to as low as 2V in Power Down mode. However,
VCC has to be restored to normal value before Power Down mode is
exited.
157 MGRJ,ECE,RVCE
 8051 - Interrupts :

Interrupt Name Vector Location Priority Level

INT0 0003h Highest
TF0 000Bh
INT1 0013h
TF1 001Bh
RI &TI 0023h Least

169 MGRJ,ECE,RVCE
 Reset
When reset pin is activated, the 8051 jumps to
address location 0000h(PC).
Reset in non maskable interrupt.

170 MGRJ,ECE,RVCE
Processing Interrupts
 When an interrupt occurs and is accepted by the CPU, the main program is
interrupted.The following actions occur:
 The current instruction completes execution.
 The PC is saved on the stack.
 The current interrupt status is saved internally.
 Interrupts are blocked at the level of the interrupt.
 The PC is loaded with the vector address of the ISR
 The ISR executes.
 The ISR finishes with an RETI instruction, which retrieves the old value of PC from
the stack and restores the old interrupt status. Execution of the main program
continues where it left off.

171 MGRJ,ECE,RVCE
Interrupt Enable(IE) register

8052
Architecture

172 MGRJ,ECE,RVCE
 Priority level structure
 Each interrupt source can also be individually programmed
to one of two priority levels by setting or clearing a bit in
Special Function Register IP.
 A low-priority interrupt can itself be interrupted by a high-
priority interrupt but not by another low-priority interrupt.

174 MGRJ,ECE,RVCE
 Interrupt priority(IP) register

175 MGRJ,ECE,RVCE
 Polling Sequence
 If two interrupts of the same priority occur simultaneously, a fixed polling sequence
determines which is serviced first.
 The polling sequence is External 0 > Timer 0 > External 1 > Timer 1 > Serial Port
 Mapping of interrupts in C51 compilers:

External Interrupt 0 interrupt 0

Timer 0 overflow interrupt 1
interrupt
External Interrupt 1 interrupt 2
Timer 1overflow interrupt 3
interrupt
Serial port interrupt 4

176 MGRJ,ECE,RVCE
 Timer interrupts
Timer0 interrupt vector:
TF0

1 000Bh

Timer1 interrupt vector:

TF1

1 001Bh

•When a timer interrupt is generated, the flag that generated it is cleared by the
on-chip hardware when the service routine is vectored to.

177 MGRJ,ECE,RVCE
 A 10-KHz Square Wave on P1.0 Using Timer Interrupts: Clock
Frequency 12 MHz (50% Duty Cycle)
Time period=0.1 msec Ton=Toff=50 usec
No. counts=50
Initial count=256-50 (Timer in mode 2) Without using interrupts

#include<reg51.h> #include<reg51.h>
sbit out=P1^0; sbit out=P1^0;
void main() {
void complement() interrupt 1
TMOD=0x02;
{ TH0=-50;
out=~out; TL0=-50;
} TR0=1;
void main() {
TMOD=0x02; while(1) {
TH0=-50; out= ~out;
TL0=-50; while(TF0==0);
EA=1; TF0=0;
}
ET0=1;
}
TR0=1;
for(;;){
180 MGRJ,ECE,RVCE PCON=0x01;
}
 Question
 A system operating in a computer network is indicating active status
by posting a character ‘*’ on its UART pin at 9600 baud, 8 data bits,
1 start bit and 1 stop bit. It is learnt that, the system must be
monitored at a rate of 3 sec. Design optimized 8051 system by
connecting LEDs & Buzzer.

181 MGRJ,ECE,RVCE
 Serial interrupt

RI
RI
0023h
TI

•TI & RI flags doesn’t clear upon ISR entry.

182 MGRJ,ECE,RVCE
 * Program to transfer a message serially
#include<reg51.h>
char *ptr;
void InitialUART(int BaudRate)
{
SCON = 0x40;
TMOD = 0x20;
TH1 = 256-(28800/BaudRate); /*11.059M/384=28800*/
TR1 = 1; //SMOD=0//
}
const char msg1[ ]=“UART interrupt message!!”;
void main(void)
{
InitialUART(9600);
EA = 1; /*enable all interrupt */
ptr = msg1;
ES = 1; /*enable SP interrupt */
SBUF=*ptr++;
185 MGRJ,ECE,RVCE while(1); /*wait for SP interrupt*/
}
 void SCON_int(void) interrupt 4 /*Serial port ISR*/
{
if(TI==1)
{
TI=0;
if(*ptr!=‘\0’) /*string ends with ‘\0’ character*/
{
SBUF=*ptr;
++ptr;
}
else
ES=0; /*complete a string tx, clear ES
}
}
186 MGRJ,ECE,RVCE
 External Interrupts

•INT0 (P3.2 )- Level triggered, edge triggered

TCON

187 MGRJ,ECE,RVCE
 INT1 (P3.3 )- Level triggered, edge triggered

188 MGRJ,ECE,RVCE
  Low-level trigger (IT0 or IT1 =0): Interrupt when INT0 or INT1 is 0 at least for
12 clock periods.
 The external source has to hold the request active until the requested interrupt is
actually generated. Then, it has to deactivate the request before the interrupt
service routine is completed or else another interrupt will be generated.
 Negative edge trigger (IT0 or IT1 = 1): Interrupt if sense high on /INT0 or
/INT1 in one machine cycle and low in next machine cycle.
 IE0 and IE1 are automatically cleared when CPU is vectored to the ISR.

189 MGRJ,ECE,RVCE
 Interrupt handling:
 The INT0 & INT1 levels are inverted and latched into the interrupt
flags IE0 and IE1 at S5P2 of machine cycle.
 The Serial Port flags RI and TI are set at S5P2 of machine cycle.
 The Timer0 and Timer1flags,TF0 and TF1, are set at S5P2 of the
cycle in which the timers overflow.
 The values are then sampled by the circuitry in the S5P2 of next
cycle.
 If the flags are set, an CALL is made to appropriate ISR.
 This call operation takes 2 machine cycles.

190 MGRJ,ECE,RVCE
 Response Time
A minimum of three complete machine cycles elapse between activation of an interrupt
request(setting of flags) and the beginning of execution of the first instruction of the service
routine.

Response time would increase because of,

 An interrupt of equal or higher priority level is already in progress.
 The current machine cycle is not the final cycle in the execution of the instruction in
progress.
 The instruction in progress is RETI(after RETI at least one other instruction of
interrupted program will be executed) or instruction writing IP or IE.

193 MGRJ,ECE,RVCE
 Interrupt Response Timing Diagram: Fastest (3 Machine cycles)

194 MGRJ,ECE,RVCE
 Interrupt Response Timing Diagram: Longest (8 Machine Cycles)

Level 0 ISR Main program Level 1 ISR

RETI MUL AB Save PC ISR

8 cycles
Level 1 interrupt
occurs here

•Thus, in 8051 the response time is always more than 3 cycles and less than 9 cycles.

195 MGRJ,ECE,RVCE
 Furnace Controller
8051
HOT = 0 if T > 21C INT0
1 = solenoid engaged (furnace on) if T < 19C
P1.7 0 = solenoid disengaged (furnace off) if T > 21C
COLD = 0 if T < 19C INT1

T = 21C
T = 20C
T = 19C

HOT

COLD

P1.7
197 MGRJ,ECE,RVCE