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15 February 2020 1441 ‫ جمادى الثانية‬21

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Digital IC Design

Lecture 22
SOI and Subthreshold Design

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
 Silicon-on-Insulator (SOI)
❑ A subject of research for decades
❑ Commercially important since adopted by IBM for PowerPC microprocessors in 1998

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 SOI Cross-Section
❑ A thin layer of SiO2 buried beneath a thin single-crystal silicon layer
❑ Shallow trench isolation is used to surround each transistor by an oxide insulator
❑ Transistor source, drain, and body are surrounded by insulating oxide rather than the
conductive substrate or well
❑ Most of the capacitance of diffusion regions is eliminated
❑ But the body is floating!

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 Fully vs. Partially Depleted SOI
❑ A depletion region empty of free carriers forms in the body beneath the gate
❑ Partially depleted (PD) SOI: the body is thicker and its voltage can vary depending on how
much charge is present
▪ Floating body effect
▪ Varying body voltage in turn changes Vt through the body effect
❑ Fully depleted (FD) SOI: the body is thinner than the channel depletion width, so the body
charge is fixed and thus the body voltage does not change
▪ More difficult to manufacture because of the thin body

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 GF FD-SOI Technology

22: SOI and Subthreshold Design [GF FD-SOI] 5

 SOI Advantages
❑ A major advantage of SOI is the lower diffusion capacitance
▪ Smaller parasitic delay
▪ Lower dynamic power consumption
❑ Less threshold voltage process variations
▪ Nominal 𝑉𝑡 can be lower
▪ Thus faster transistors, especially at low VDD
❑ Lower subthreshold slope (i.e., transistor turns off more
abruptly)
▪ 𝑆 = 𝑛𝑉𝑇 ln 10 ≈ 2.3𝑛𝑉𝑇
▪ 𝑛 is a process dependent parameter
• Bulk CMOS: 𝑛 ≈ 1.5 → 𝑆 ≈ 90𝑚𝑉/𝑑𝑒𝑐𝑎𝑑𝑒
• SOI: 𝑛 < 1.5 → 𝑆 ≈ 75 − 85𝑚𝑉/𝑑𝑒𝑐𝑎𝑑𝑒
❑ Immune to latchup
22: SOI and Subthreshold Design [GF FD-SOI] 6
 SOI Disadvantages
❑ Higher manufacturing cost
▪ Now cost-effective compared to FinFET!!
❑ Self-heating: the oxide is a thermal insulator
▪ Heat accumulates
❑ PD SOI suffers from the floating body effect
❑ A BJT with floating base is present within each transistor
❑ The unusual transistor behavior complicates circuit design

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 Additional Topics
❑ Design and layout in FD-SOI 22nm technology
▪ https://www.globalfoundries.com/resources/technical-webinar-series/analog-design-
workshop-22fdx-22nm-fd-soi-technology-part-one
▪ https://www.globalfoundries.com/resources/technical-webinar-series/analog-design-
workshop-22fdx-22nm-fd-soi-technology-part-two
▪ https://www.globalfoundries.com/resources/technical-webinar-series/top-5-design-
guidelines-successfully-implement-22fdx-fd-soi-technology

02: CMOS Layout 8

 Subthreshold Circuit Design
❑ In many applications, performance requirements are minimal and battery life is paramount
▪ Implanted biomedical devices, e.g., pacemaker
▪ One of the buzz words in this decade: IoT

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 Min Power vs. Min Energy
❑ Minimum power is not an interesting objective because it is achieved as the delay
approaches infinity
❑ A better metric is minimizing the energy for a given operation (PDP), or the energy delay
product (EDP)
❑ Minimum energy point typically occurs at VDD < Vt
▪ Subthreshold regime
▪ All the transistors OFF, but some are more OFF than others!
▪ If S = 100 mV/decade, a transistor with Vgs = 0.3 will nominally leak 1000 times more
current than a transistor with Vgs = 0

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 Supply Voltage
❑ In subthreshold, delay varies exponentially with VDD
❑ Reducing VDD reduces the switching energy but causes the OFF transistors to leak for a
longer time (because gates are slower)
❑ The minimum energy point is where the sum of dynamic and leakage energies is smallest.
❑ This point is typically at a supply close to 300–500 mV
▪ Near-threshold operation
▪ A somewhat higher voltage is preferable when leakage dominates (e.g., at low activity
factor or high temperature).
❑ At this voltage, static CMOS logic operates at kHz or low MHz frequencies and consumes an
order of magnitude lower energy per operation than at typical voltages.

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 VDD and 𝑽𝒕 Selection
❑ Contours of normalized energy (blue) and delay (black) for 𝛼 = 1 (left) 𝑎𝑛𝑑 0.1 (right) for
ring oscillator in 180nm process
❑ At or near threshold: operating frequency increases exponentially as VDD increases or 𝑉𝑡
decreases
❑ At 𝛼 = 0.1, switching energy is less important, so the circuit can run at a higher supply
voltage

22: SOI and Subthreshold Design 12

 VDD Selection
❑ A logic gate must have a slope steeper than -1 in its DC ccs to
achieve restoring behavior and maintain noise margins
❑ In subthreshold, circuits are exponentially sensitive to
variations
❑ In the worst case corners (usually SF or FS), the supply
voltage may need to be 300 mV, or higher for complex gates,
to guarantee proper operation.
❑ Gates with multiple series and parallel transistors require a
higher supply voltage
▪ Must ensure the ON current through the series stack
exceeds the OFF current through all of the parallel
transistors.
❑ Must take power distribution network drops into account

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 Gate Selection
❑ Subthreshold circuits should use simple gates (no more complicated than an AOI22 or
NAND3)
❑ Static structures with many parallel transistors such as wide multiplexers do not work well
at low voltage
▪ The leakage through the OFF transistors can exceed the current through the ON
transistor, especially considering variation
❑ Ratioed circuits do not work well at low voltage because of exponential sensitivity to
variation
❑ Dynamic circuits are not robust in subthreshold operation because leakage easily disturbs
the dynamic node

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 Transistor Sizing
❑ If you need higher performance
▪ Transistor sizing offers at best a linear performance benefit
▪ Supply voltage (in subthreshold) offers an exponential performance benefit
❑ As a general rule, minimum energy under a performance constraint is thus achieved by
using minimum width transistors
▪ Raise the supply voltage if necessary from the minimum energy point until the
performance is achieved (assuming the performance requirement is low enough that
the circuit remains in the subthreshold regime)
❑ Wider transistors might become advantageous to reduce 𝑉𝑡 variability
❑ Upsizing the critical path for speed might be better than raising the supply voltage to the
entire circuit

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 Thank you!

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