ES 204 Digital Systems

LAB 1

Naga Sheshu Reddy [22110178]

Srivathsa Vamsi Chaturvedula [22110260]

Structural Code

`timescale 1ns / 1ps

module lab1(
input a,
input b,
input c,
input d,
output out
);

and a1(g,~a,~b,c);
and b1(f,~a,b,d);
and c1(h,b,~c,d);
and d1(e,~b,c,d);
or e1(out,g,f,h,e);

endmodule

Continuous Assignment

`timescale 1ns / 1ps

module lab1(
input a,
input b,
input c,
input d,
output out
);

assign out = (~a & ~b & c) | (~a & b & d) | (b & ~c & d) | (~b & c & d);

endmodule
Test Bench Code

`timescale 1ns / 1ps

module lab1b();

reg a,b,c,d;
wire out;

lab1 uut(a,b,c,d,out);

initial
begin
a = 0; b = 0; c = 0; d = 0;
#10;
a = 0; b = 0; c = 0; d = 1;
#10;
a = 0; b = 0; c = 1; d = 0;
#10;
a = 0; b = 0; c = 1; d = 1;
#10;
a = 0; b = 1; c = 0; d = 0;
#10;
a = 0; b = 1; c = 0; d = 1;
#10;
a = 0; b = 1; c = 1; d = 0;
#10;
a = 0; b = 1; c = 1; d = 1;
#10;
a = 1; b = 0; c = 0; d = 0;
#10;
a = 1; b = 0; c = 0; d = 1;
#10;
a = 1; b = 0; c = 1; d = 0;
#10;
a = 1; b = 0; c = 1; d = 1;
#10;
a = 1; b = 1; c = 0; d = 0;
#10;
a = 1; b = 1; c = 0; d = 1;
#10;
a = 1; b = 1; c = 1; d = 0;
#10;
a = 1; b = 1; c = 1; d = 1;
#10;

end
endmodule
Simulation Output