ECE102P-DIGITAL SYSTEMS DESIGN

LAB-ASSIGNMENT-2

Student Name: DAGUMATI HARSHA VARDHAN

Student ID: 21BCE2879

Lab Slot: L47+L48

Date of Submission: 27/8/2022

Aim: To understand the functionality of basic Half-Adder, Full-Adder, HalfSubtractor and Full-
Subtractor devices, and design them using ModelSim.

Tools used: ModelSim

1)HALF ADDER:

Boolean function:
Truth table and k-map:
Verilog program (using if-else loop):
 Simulated result:

2)HALF SUBTRACTOR
Boolean function:
Truth table and k-map:
Verilog program using test bench method:
Simulated result:
3)FULL ADDER: Boolean function:
Truth table and k-map:
Verilog program using test bench method:

Simulated result:
4)FULL SUBTRACTOR Boolean function:

4)FULL SUBTRACTOR
Boolean function:
Truth table and k-map:
VERILOG PROGRAM USING TEST BENCH:
STIMULATED RESULTS: