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  • Assignment I

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    win papasan
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    The document contains four sections. Section I describes a sequential circuit assignment to design a circuit with inputs X and outputs S, V. The circuit calculates the 4-bit number N+2 and sets V=1 if it is too large. Section II asks about the difference between a CPLD and FPGA. Section III asks about disadvantages of SRAM FPGAs. Section IV asks about disadvantages of antifuse FPGAs.

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    The document contains four sections. Section I describes a sequential circuit assignment to design a circuit with inputs X and outputs S, V. The circuit calculates the 4-bit number N+2 and sets V=1 if it is too large. Section II asks about the difference between a CPLD and FPGA. Section III asks about disadvantages of SRAM FPGAs. Section IV asks about disadvantages of antifuse FPGAs.

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    6 views1 page

    Assignment I

    Uploaded by

    win papasan
    The document contains four sections. Section I describes a sequential circuit assignment to design a circuit with inputs X and outputs S, V. The circuit calculates the 4-bit number N+2 and sets V=1 if it is too large. Section II asks about the difference between a CPLD and FPGA. Section III asks about disadvantages of SRAM FPGAs. Section IV asks about disadvantages of antifuse FPGAs.

    Copyright:

    © All Rights Reserved
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    Assignment I

    I. A sequential circuit has one input (X) and two outputs (S and V). X
    represents a 4-bit binary number N, which is input least signicant bit rst.
    S represents a 4-bit binary number equal to N 1 2, which is output least
    signicant bit rst. At the time the fourth input occurs, V 5 1 if N 1 2 is too
    large to be represented by 4 bits; otherwise, V = 0. The value of S should
    be the proper value, not a don’t care, in both cases. The circuit always
    resets after the fourth bit of X is received.
    (a) Derive a Mealy state graph and table with a minimum number of
    states (6 states).
    (b) Try to choose a good state assignment. Realize the circuit using D
    -ip--ops and NAND gates. Repeat using NOR gates. (Work this part
    by hand.)

    II. What is difference between a CPLD and an FPGA?

    III. What are the disadvantages of SRAM FPGAs?

    IV. What are the disadvantages of antifuse FPGAs?

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