SpyGlass Get Started Lab Book 2019.06

Getting Started with SpyGlass®
Hands-on Training
SpyGlass_vL-2019.06
Hands-on Training
Table of Contents
1 INTRODUCTION.........................................................................3
1.1 Nomenclature............................................................................3
2 SPYGLASS ENVIRONMENT SETUP....................................................3

2.1 Environment Variables................................................................3
2.1.1 SPYGLASS_HOME.................................................................3
2.1.2 PATH..................................................................................4
2.1.4 EDITOR...............................................................................4
3 LAB DESIGN OVERVIEW...............................................................5

3.1 Organization of Lab Structure......................................................6
4 SPYGLASS OVERVIEW (LAB #1)....................................................7

4.1 Reading the Design into SpyGlass................................................7
4.2 Running Analysis with SpyGlass.................................................10
5 DESIGN READ IN SPYGLASS (LAB #2)...........................................14

5.1 Specifying Files to Read From Source File List..............................14
5.2 Pre-compiled Library.................................................................17
6 GOALS SETUP, RUN AND REVIEW RESULTS (LAB#3)..........................18

7 SPYGLASS VIOLATION DEBUGGING (LAB #4)...................................21
7.1 Launch SpyGlass GUI mode for debugging...................................21
7.2 Reports...................................................................................21
7.3 W415 Errors: Multiple drivers....................................................23
7.4 SYNTH_5159 Warning...............................................................26
7.5 UndrivenInTerm-ML Errors........................................................27
7.6 Waiving Violations....................................................................31
8 GENERATING DASHBOARD/DATASHEET...........................................33
9 SHARING YOUR STATUS (LAB #5).................................................35
9.1 Block Hand-off.........................................................................35
10 TOOLS...............................................................................36
© Copyright Synopsys Inc., 2017 Page 2

Hands-on Training
1 Introduction
This document is the companion to the Getting Started with SpyGlass training. This
document provides instructions on running SpyGlass through different design stages to
gain hands-on experience on SpyGlass setup and debugging/analysis of SpyGlass
results.
This document is a pre-requisite for other SpyGlass product labs. It covers multiple
hands-on exercises and each hands-on exercise is dependent on the previous hands-on
exercise being completed. Additional details are provided in section “Organization of
Lab Structure” on the hands-on exercise directory structure.
1.1 Nomenclature
The following nomenclature is used throughout this document:
Command-line instructions are shown in bold with gray background, for example:
%> spyglass –project Project-1.prj
Tcl commands are shown with gray background, for example
set_option designread_enable_synthesis yes
Use of pull-down menus is shown in bold, for example:
File  Open Project
2 SpyGlass Environment Setup

2.1 Environment Variables
The following environment variables should be set up for SpyGlass to function
correctly:
2.1.1 SPYGLASS_HOME
This variable is not mandatory to be set to run software but is useful for supporting
functions, such as path setup, moving to the top of the install hierarchy, and so on.
(csh)
setenv SPYGLASS_HOME <install_path>/SPYGLASS_HOME
(sh, bash)

Hands-on Training
export SPYGLASS_HOME=<install_path>/SPYGLASS_HOME
2.1.2 PATH
This variable assumes that the SPYGLASS_HOME variable has already been set (as
above).
(csh)
set path = ($SPYGLASS_HOME/bin $path)
(sh, bash)
export PATH=“$SPYGLASS_HOME/bin:$path”
2.1.3 EDITOR
You can invoke your favorite text editor directly from the SpyGlass environment. To
set up the text editor, set the EDITOR environment variable as follows:
(csh)
setenv EDITOR <full-path-name-to-editor>
(sh, bash)
export EDITOR=<full-path-name-to-editor>
3 Lab Design Overview

The following figure is the block diagram of the design that is being used for the labs.
The design has a USB controller (USB) and an audio decoder core (IMA_ADPCM)
which are compliant to Wishbone bus. These components connect to the Wishbone
connection matrix (WB_Conmax) which in turn connects to the AMBA Bus using
Wishbone-to-Amba bridge (wb2ahb). The design is of type mixed-RTL as uses both
Verilog and VHDL as indicated in the block diagram below
USB Controller IMA ADPCM

(Verilog) (VHDL)
WB Connmax
(Verilog)
AHB2WB
(Verilog)
WB_Subsystem
Hands-on Training
The design is assembled using blocks available from open source as below:
Block Name Source Unit Name Language

Audio Controller www.opencores.org ima_adpcm VHDL
USB www.opencores.org usbf_top Verilog
WishBone Conmax www.opencores.org wb_conmax Verilog
AHB2WB Bridge www.opencores.org ahb2wb Verilog

Hands-on Training
3.1 Organization of Lab Structure

Extract the training files
%>gtar –zxvf SpyGlass-Get-Started_Lab-Files_1906.tar.gz
The lab design directory is organized as follows:
rtl RTL Files associated with the design
All SpyGlass runs will be performed in

spyglass this directory
Training_labs
doc Contains the lab document (this one)
Other scripts that will be used in the

tools training
For the purposes of this lab, the design is built as follows to highlight specific features
in SpyGlass:
 Top level USB controller block is available as a regular RTL but all of its
design files are read as a Verilog library component
 IMA_ADPCM block is pre-compiled into its own work library
(ima_adpcm_lib) and then get referenced at the top level of the design
 Rest of the components are read as normal RTL files

Hands-on Training
4 SpyGlass Overview (Lab #1)

The objective of this hands-on exercise is to quickly get you started with SpyGlass
where you can run the analysis and look at the results. As this test case will be
common to other subsequent labs, it’s recommended to save the project file developed
here for later usage.
In Lab #1, we are using the GUI as a simple path to get to a project file to start with,
and then we will continue in batch using project file.
4.1 Reading the Design into SpyGlass

Please follow the steps below:
1. Go to directory “spyglass”
% cd Getting_Started_with_SpyGlass_1906
% cd Training_labs/spyglass
2. Start SpyGlass GUI with the command below:
% spyglass &
3. You will now see the following main environment window:
4. Click on GUI option “Add File(s)”. This will open up the ‘SpyGlass: Add File(s)’
window and add the following RTL files from the ‘rtl’ directory as shown below:

Hands-on Training
../rtl/ahb2wb.v
../rtl/wb_subsystem.v
5. Now select GUI option ‘Set Options’ and enter the top level design unit name for
the block (wb_subsystem) as shown below:
6. Now Select Tab “Read Design” and click on option “Run Design Read” to start the
design read. Once the SpyGlass run is completed, let’s review the design read
errors reported by SpyGlass as shown below.

Hands-on Training
There are three errors reported for the design (wb_subsystem), read by SpyGlass.
You will notice that these all errors are of same type and are reported by SpyGlass
rule ErrorAnalyzeBBox, which indicates that SpyGlass did not find a definition of
the block and hence marked it as a blackbox. (Note: For complete design analysis
using SpyGlass, all black boxes should be resolved first and for that reason you
may additionally like to select checkbox ‘Synthesize Netlist’ while running design
read.)
The ‘Design Setup’ step enables you to start your analysis while the blocks are still
being defined. The Module View marks the blocks as follows:
 Green to indicate that the block is ready for analysis but not yet internally
synthesized
 Black to indicate that the block can’t be analyzed (black boxes)
 White to indicate that the block is synthesizable and you can select that
DU and open modular schematic to see the structure (with ‘Synthesize
Netlist’ option enabled in design read)
4.2 Running Analysis with SpyGlass

Please follow the steps below:
1. Click on “Goal Setup” tab and select “lint -> lint_rtl”. The purpose of the selected
goal can be read from the Help window adjacent to goal selection window. As you
can see from the help that “lint_rtl” checks basic connectivity issues in the design,
such as floating input, width mismatch, etc.
Note: ‘lint_rtl’ goal help will be visible only when you select the lint_rtl goal. (By
making that goal highlighted with a blue bar and you can highlight only one at a time

Hands-on Training
during setting up goal, whereas you can enable multiple goals just by enabling (by
adding a tick) the checkboxes towards left of the goal name and they will be executed
sequentially.)
2. Click on “Run Goal(s)”. Once the run completes, the tool will automatically take
you to “Analyze Results”.
Expand the ERROR messages first. They reports the same black boxes being reported
from the design read stage.
Select and expand the InferLatch ERROR.
Double-click the first violation message. Note how the related line of RTL code is
highlighted in the HDL viewer above the results display, as shown in the window
below.

Hands-on Training
Carefully analyze this rule. You can further probe this issue as follows:
First, the message tells you that a latch has been inferred for certain signal.
As you can see there is a NAND gate symbol attached with the violation message,
which indicates that violation message also has some debug information in terms of
schematic data. You can open the associated schematic data by pressing key <i> or by
clicking button for Incremental Schematic on above of the Message view window.
The incremental schematic window will look as follows:

Hands-on Training
In this particular example situation, you can see that signal ‘hready’ is getting assigned
inside if statement without an else part and that seems to be the valid reason for latch
inference during synthesis. If design requires hready signal to be latched w.r.t strobe
signal ‘stb_o’, then this is not an unintended structure. For the purposes of this lab we
will assume that these latches are intentional and so you may like to waive the
violation.
On the other hand, if you needed to fix the problem, you can click the relevant HDL
source-code line in the RTL View and press the <e> key on the keyboard (or select
‘open Editor’ from the right click pop-up menu). Then, SpyGlass will open the RTL
source file using the default text editor, as defined by the EDITOR environment
variable, with the cursor on the line that is selected in the RTL View window. You are
now ready to edit the source file and save the modified file and can rerun the goal.
3. Save the project file (File-> “Save Project” and then put wb_subsystem as file
name) and exit (File -> Exit).
4. Let us have a look at the project file (wb_subsystem.prj) generated from this lab.
We will use this project file in our next lab for our reference. Note that the
GuideWare2.0 (GuideWare2.0 is renamed as 2016.06(latest) in SpyGlass 2016.06-
SP1) is the default methodology in SpyGlass, and it is defined as
active_methodology in the project file. ‘read_file’ command provides the various
types of files to be read during SpyGlass run.
The ‘language_mode’ option is used to specify the operating language for the
current SpyGlass run. The default value is ‘mixed’, means, tool will process either
Verilog designs, VHDL designs, or mixed language designs. The ‘projectwdir’
option is used to specify a project working directory
For better readability, you need to add design input files/options in the ‘Data
Import Section’ and data read/tool options in the ‘Common Options Section’ of the
project file as shown below. In the next lab, you have to add suggested
commands/options in this project file.

Hands-on Training
With that we have completed first hands-on exercise of the training.

Hands-on Training
5 Design Read in SpyGlass (Lab #2)

This hands-on exercise will cover the various aspects of reading a design into
SpyGlass and will build on top of the previous lab. In this lab, we will run SpyGlass in
the batch mode using –batch option. The same operation can be done in GUI mode as
well.
5.1 Specifying Files to Read From Source File List
1. Invokes SpyGlass in batch mode with the setup from wb_subsystem.prj file and
runs design read process
% spyglass -project wb_subsystem.prj -designread -batch

Result Summary on terminal shows 3 blackbox errors as below.
Check for moresimple report generated at

location:-./wb_subsystem/wb_subsystem/Design_Read/spyglass_reports/
moresimple.rpt as shown below:

Hands-on Training
Messages in the moresimple report are sorted in the order of Severity Class,
Severity Label, Rule Name, File Name, and Line Number. This report provides
sufficient information to identify the violation in the source file.
2. In an external text editor, examine the following source file list for the ‘usb’ and
‘wb_conmax’ blocks
../rtl/usb/file.list
../rtl/wb_conmax/file.list
Now, add these source file lists in the project file (wb_subsystem.prj) as
mentioned below and save the project file.
read_file -type sourcelist ../rtl/usb/file.list
read_file -type sourcelist ../rtl/wb_conmax/file.list
3. Run design read again and this time provide the following option in the project file
to enable Synthesize during design read. For better readability, add this option
under ‘##Common Options Section’ in project file and save it
set_option designread_enable_synthesis yes
4. Repeat the step #1 to re-run the design read
5. You will notice that adding of above source files have resolved the blackboxes
errors for USB and WB_Conmax blocks, but has still generated more blackbox
errors for cells instantiated inside the USB block as shown in the moresimple
snapshot below.

Hands-on Training
They appear to be standard cells being instantiated but somehow their definition is
not provided. It is quite likely that these cells are to be passed using –y/-v option
and so let’s explore the directory inside ‘usb’ to see if there are any missing library
file. We get to see that usb_lib directory is present inside ‘usb’ directory, but no –
y has been specified with it as part of file.list.
6. Let’s specify the Verilog library path and extension to read the missing definitions
in the design. Specify the Libraries directory containing libraries
‘../rtl/usb/usb_lib’ and
Specify Library File Extension: ‘.v’
Add the following commands in the project file
set_option y { ../rtl/usb/usb_lib }
set_option libext { .v }
7. Repeat the step #1 to re-run the design read to see if all the USB black boxes are
resolved. Only one blackbox error seen in the result summary on the terminal
8. Please add enableSV option to read the System Verilog files
set_option enableSV yes
9. Configure types of reports using “report” option:
set_option report {summary count moresimple sign_off }
10. Pass list of Black-Boxes with “stop” option:

set_option stop { list of modules }

Hands-on Training
Find more details in the moresimple report as shown below:
Note that we are left with just one black-box error and which is coming for block
‘IMA_ADPCM_top’.
5.2 Pre-compiled Library
1. To pre-compile HDL library, you have to specify the list of files to be precompiled
in the logical library, and the mapping between logical library and physical
directory. Let us examine the file list i.e. ‘../rtl/ima_adpcm/file.list’
You will notice that the ‘file.list’ includes the -libhdlfiles option along with the logical
library mapping where the HDL files are to be compiled into. This file also defines the
mapping of logical library with physical location using option “-lib”. Read this source
file list into project file as mentioned below:

Hands-on Training
read_file -type sourcelist ../rtl/ima_adpcm/file.list
2. Rerun design read to see if that resolves the blackbox errors coming from
‘IMA_ADPCM_top’ using following command:
% rm –rf wb_subsystem
% spyglass –project wb_subsystem.prj –designread –batch
You will see the result summary that we resolved all the black-box errors.
With that we have completed second hands-on exercise of the training.
6 Goals Setup, Run and Review Results

(Lab#3)
In this lab, the project file ‘wb_subsystem.prj’ (project file built during Lab#2
execution) will be used to run the goal and review the run results
1. To get the list of available goals, use the following command
% spyglass –project wb_subsystem.prj -showgoals
Goal status summary can be viewed any point of time using this command

Hands-on Training
2. Let us run the first goal i.e. “lint/lint_rtl” in the list above, using following
command:
% spyglass -project wb_subsystem.prj -goals lint/lint_rtl -batch
The selected goal should be a part of the currently active methodology, which is
the methodology currently selected by the ‘current_methodology’ command or
default methodology in setup file in case not set explicitly. The GuideWare is the
default and latest methodology in SpyGlass.
Note that multiple methodologies can be specified in the project file, but one
methodology will be active at a time.
3. Once the run is complete, Review the results in the Result Summary generated on
run completion on the terminal as shown below:

Hands-on Training
4. After looking at Result Summary, you might want to see the details on the
violations. Open moresimple report generated during run @
./wb_subsystem/wb_subsystem/lint/lint_rtl/spyglass_reports/moresimple.rpt.
Snapshot below for your reference
With that we have completed third hands-on exercise of the training.

Hands-on Training
7 SpyGlass Violation Debugging (Lab #4)

In this hands-on exercise, we will analyze the violations produced during lint
goal run. We can use various debugging tools in SpyGlass GUI to understand the
violations, debug its root causes in the RTL code and see how to fix those violations in
the SpyGlass environment itself.
For this lab, you can either choose to make changes in the RTL/setup after each
section and rerun goal to confirm the fixes or make all the changes and then rerun goal
to validate the results.
Generally the debugging of different goal results are expected to be in the order
as they are listed inside the methodology and hence in the order as shown in the ‘Run
Goal’ box in ‘Analyze Results’ tab but still as part of this training lab, we shall be
debugging them in some random order.
7.1 Launch SpyGlass GUI mode for debugging

The use-model in the GUI mode is intended for debugging violations, though the
debugging can also be done in the batch mode using reports. As we already run the lint
goal in batch mode, now we can simple load the already run goal in the GUI to debug
few violations.
Open SpyGlass GUI with the following command and the last run goal
(lint/lint_rtl) will be loaded automatically
% spyglass –project wb_subsystem.prj &
Note that ‘-batch’ option is not needed while running GUI mode.
7.2 Reports
Multiple reports are generated corresponding to each goal run, which can be accessed
from the Reports section of menu bar as shown below:

Hands-on Training
Click on the moresimple report under More Reports, to get the starting point to analyze
the violations. The moresimple report looks like:
This report provides all the pointers with a violation to debug it easily.

Hands-on Training
Let us go through all the violations reported by SpyGlass lint goal run picking one
violation at a time. We can analyze these violations either in GUI mode or batch mode.
7.3 W415 Errors: Multiple drivers

Check the analyze window tab as shown below and set the violation message
displayed with ‘Group by: Severity’ in this lab to analyze all the violations.
From the message window you can see violation for rule W415. This rule identifies
nets which can be simultaneously driven by 2 or more drivers in the design.
 Expand the W415 rule folder in the message window and look at the underlying
violation message. The violation message indicates that net “WB_master_data_o” is
driven by multiple drivers in top-level of the design ‘wb_subsystem’. Let’s debug
this issue and find out the root cause in the RTL code.
 Select the violation message by double clicking on it. This will correspondingly
highlight RTL line in the File View window, but highlighted line does not provide
sufficient reason for the structural problem reported by rule message, so we need
more design information to check the correctness of the violation and which can be
obtained/viewed from one of the very useful SpyGlass debugging feature i.e.
‘incremental schematic’ viewer.

Hands-on Training
 You will notice that a NAND gate symbol is attached with the violation message,
which indicates that violation message also has some debug information in terms of
schematic data. You can open the associated schematic data by pressing key <i> or
by clicking Incremental Schematic button on above of the Message view
window. The incremental schematic window will look as follows:

Hands-on Training
 From schematic data, you will see two drivers that are driving the reported signal
(WB_master_data_o[0]) and it can be confirmed that the port ‘m0_data_i’ is driven
simultaneously by o/p ports ‘dat_o’ (of instance ahb2wb_u0 ) and ‘m0_data_o’( of
instance conmax_u1). Hence the violation reported is structurally correct.
 If we go back and look at the HDL description, it seems like a typographical error
where user might have copy/pasted the previous line and changed the formal port but
missed changing the net connected to it.
The fix for these violation require an update to RTL. The code however uses an
“ifdef” construct to enable the fixed code. Let’s enable the definition of
“Fix_W415”.
set_option define { Fix_W415 }
Add this line in ‘Common Options Section’ of the project file (wb_subsystem.prj) to
enable the macro. Reload the project file (File -> Reload Project) and run the goal
(clicking ‘Run Goal’ in ‘Analyze Results’ tab as shown below), to verify whether
violation of W415 goes away. [Note: Automatic reload of project file happens in
GUI, if any update in project file]
You will see that the violation W415 goes away.
7.4 Waiving Violations

Go to Analyze Results tab. You will see 3 violations for rule InferLatch in the ERROR
category.
This rule flags all signals where a latch will be inferred during synthesis of the design.
So this rule helps in the detection of RTL code, which can result in the generation of
unintended latch structures.

Hands-on Training
Expand the rule folder and look at the first violation message, which is reporting that a
latch is inferred for signal "hready". Using RTL cross-probing, you can see that signal
‘hready’ is getting assigned inside an ‘if’ statement without an else part and that is a
valid reason for latch inference during synthesis.
If design requires hready signal to be latched w.r.t strobe signal ‘stb_o’, then this is not
an unintended structure. For the purposes of this lab we will assume that these latches are
intentional. So typically, user would not like to see violation messages for intended latch
structures again and again. In SpyGlass you mask the unwanted rule messages by
masking them by defining waiver constraints as we have demonstrated in first hands-on
exercise (right mouse click on violation message and selecting ‘Waive Selected
Messages...’).

Hands-on Training
 Review the violation message, rule and design unit (DU) details on which the waiver is
to be applied in the lower half of the Waiver window. This makes sure that waiver is
applied on correct or desired set of objects. If they are ok, then click on “Apply” button
to apply the same on design under analysis.
 If you want to re-use the currently generated waivers in future SpyGlass runs, then you
need to also save the waiver constraints in a waiver file (.awl). This can be done by
selecting option “Save Wavier Files” on right click menu generated on Waiver Files
folder towards the left hand side of the waiver window. Refer to snapshot below for
exact look and feel.
Repeat the same steps to waive the following violations

 Remaining InferLatch violations
 Violations of rule NoAssignX-ML

Hands-on Training
 Violations of rule W240 – An input has been declared but not used
 Violations of rule HdlLibDuCheck_01
Once the waivers are completed, click on ‘Edit File’ item in the waive editor (on right
click menu) and save the file as “wb_subsystem_files/wb_subsystem.awl” for future
reference.
Now when you save the project file, SpyGlass will add a waiver file read command in
the project file but saved in ./wb_subsystem/wb_subsystem/lint/lint_rtl/ as an input file
to the tool.
read_file -type awl
./wb_subsystem/wbsubsystem/lint/lint_rtl/wb_subsystem_waiver_file.awl
At the same time as you just have single waiver file, so, this one becomes the default
waiver file and is dumped in the project file with following option:
read_file -type awl
./wb_subsystem/wb_subsystem/lint/lint_rtl/wb_subsystem_waiver_file.awl
This will result in a clean block which is ready for hand-off. With that we have
completed fourth hands-on exercise of the training.
8 Generating Dashboard/Datasheet
Generation of SpyGlass DashBoard and SpyGlass DataSheet reports for the block
(wb_subsystem) as part of handoff too. These reports are a part of default repots
generation if user has set the required license in the setup.
Go to the SpyGlass Tcl Shell prompt:
$ spyglass -project wb_subsystem.prj -shell
Type the following commands to generate datasheet and dashboard
sg_shell> write_aggregate_report datasheet
sg_shell> write_aggregate_report dashboard
Review the DataSheet and the DashBoard reports. These provide summary of the
results that you see in the design which is being handed off. These reports can be
extended for advanced products/goals which we have not run as part of this lab but the
idea here is to let you introduced to the reports and how to generate the report. The
report can also be generated using GUI.
You can also use the DashBoard report to watch the progress of the block during RTL
development. You would be required to ensure that Design objectives are passed. They

Hands-on Training
relates to specific products like CDC, Constraints, DFT and Power and we have not
covered them as part of this training/lab and hence ignoring that part of the report
during handoff.
You can view the reports in browser as follows:
firefox wb_subsystem/html_reports/dashboard.html
firefox wb_subsystem/html_reports/datasheet.html
The Spyglass DashBoard is compatible with the following Web browsers:

 Firefox 2.0.0.20 (UNIX or Window) or higher
 IE 8.0 (Window) or higher
 Google Chrome
Once the dashboard/datasheet is ready, ship it to the SoC integrator as part of package
when sharing the IP status.

Hands-on Training
9 Sharing your status (Lab #5)

In this hands-on exercise we will prepare the block we analyzed for hand-off to the
SoC team for integration.
9.1 Block Hand-off

To enable the block hand-off, the following SpyGlass data should be packaged
 RTL
 Project File(s)
 SGDC constraints
 SpyGlass waiver
 SpyGlass DashBoard report
 SpyGlass DataSheet report
1. The following script will capture all the required data and save it in a new
directory “wb_subsystem_package”
2. Go to ‘tools’ directory to invoke the script

% cd ../tools
%source package_block.csh
This will create ‘wb_subsystem_package’ directory.
% cd ../spyglass/
% tar cvzf wb_subsystem_block.tar.gz wb_subsystem_package
10 Tools
The tools directory contains a few sample scripts which are used in the training labs.
These scripts are purposely kept simple to illustrate how a user may use those. You are
welcome to use and modify these scripts to use them in your design flows. The scripts
include:
 package_block.csh : Used to assemble the files needed to package an IP for
shipment
End of Document

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Getting Started with SpyGlass®

2 SPYGLASS ENVIRONMENT SETUP....................................................3

3 LAB DESIGN OVERVIEW...............................................................5

4 SPYGLASS OVERVIEW (LAB #1)....................................................7

5 DESIGN READ IN SPYGLASS (LAB #2)...........................................14

6 GOALS SETUP, RUN AND REVIEW RESULTS (LAB#3)..........................18

© Copyright Synopsys Inc., 2017 Page 2

2 SpyGlass Environment Setup

© Copyright Synopsys Inc., 2017 Page 3

3 Lab Design Overview

USB Controller IMA ADPCM

Block Name Source Unit Name Language

© Copyright Synopsys Inc., 2017 Page 5

3.1 Organization of Lab Structure

rtl RTL Files associated with the design

All SpyGlass runs will be performed in

Other scripts that will be used in the

© Copyright Synopsys Inc., 2017 Page 6

4 SpyGlass Overview (Lab #1)

4.1 Reading the Design into SpyGlass

3. You will now see the following main environment window:

© Copyright Synopsys Inc., 2017 Page 7

© Copyright Synopsys Inc., 2017 Page 8

4.2 Running Analysis with SpyGlass

© Copyright Synopsys Inc., 2017 Page 9

© Copyright Synopsys Inc., 2017 Page 10

© Copyright Synopsys Inc., 2017 Page 11

© Copyright Synopsys Inc., 2017 Page 12

With that we have completed first hands-on exercise of the training.

© Copyright Synopsys Inc., 2017 Page 13

5 Design Read in SpyGlass (Lab #2)

5.1 Specifying Files to Read From Source File List

% spyglass -project wb_subsystem.prj -designread -batch

Check for moresimple report generated at

© Copyright Synopsys Inc., 2017 Page 14

set_option designread_enable_synthesis yes

4. Repeat the step #1 to re-run the design read

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set_option enableSV yes

9. Configure types of reports using “report” option:

set_option report {summary count moresimple sign_off }

10. Pass list of Black-Boxes with “stop” option:

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Find more details in the moresimple report as shown below:

5.2 Pre-compiled Library

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read_file -type sourcelist ../rtl/ima_adpcm/file.list

6 Goals Setup, Run and Review Results

1. To get the list of available goals, use the following command

% spyglass –project wb_subsystem.prj -showgoals

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% spyglass -project wb_subsystem.prj -goals lint/lint_rtl -batch

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With that we have completed third hands-on exercise of the training.

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7 SpyGlass Violation Debugging (Lab #4)

7.1 Launch SpyGlass GUI mode for debugging

% spyglass –project wb_subsystem.prj &

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7.3 W415 Errors: Multiple drivers

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set_option define { Fix_W415 }