Course Content Overview

 MOSFET physics (W1)

 Short channel effect (W2)
 Advanced Devices module:(W2-W5)
 Multi-Gate device structure
 FinFet and Gate all-around
 High-k materials + metal gate
 Strained technology
 Silicide process and RSD
 High mobility Channel
 Process integration (W6)
 Future device candidates (W6)
Gate

Si

Planar FinFET Gate-all-around 1

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 Salicide Process
 Salicide: self-aligned silicidation
 Selective formation of metallic silicide in the
gate/source/drain regions.
 Used to reduce parasitic resistance.
 Widely adopted in advanced logic chip
manufacturing.

silicide

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 Contribution of Salicide
metal

metal

metal
S G D S G D

3 S G D S G D
 Silicide Formation Techniques
-Metal Deposition and Anneal
 Silicide can be formed by metal deposition on Si followed
by thermal heating, laser irradiation or ion beam mixing.
 Sensitive to interface cleanliness and heavy doping.
 Selective silicidation on Si possible.
 Widely used for silicides of Ni, Pt, Pd, Co, Ti.

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 Titanium Salicide
Titanium
Polysilicon

STI n+ n+ USG p+ p+
Ti Deposition

Titanium Silicide

STI n+ n+ USG
USG p+ p+
Annealing
Sidewall Spacer Titanium Silicide

STI n+ n+ USG
USG p+ p+
Ti Strip
First RTP Anneal, ~700 °C, to form TiSi2 (C49)
Strip un-reacted titanium and TiN using H2O2:H2SO4
5 Second RTP Anneal, ~800 °C, to form TiSi2 (C54)
 Dopant Redistribution in Silicide/Si (1)
 Silicides are polycrystalline by nature with large density
of grain boundaries. There are a large number of defects
in grain boundaries.
 As a result the diffusivity in silicides is very high. Dopant
from Si can readily redistribute into a silicide.

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 Dopant Redistribution in Silicide/Si (2)
 Besides the dopant redistribution at the S/D, this
phenomenon also occurs on the poly gate.

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 Properties of Silicide Materials
Resistivity Moving Reaction Temperature Barrier
Silicide
(µΩ-cm) Species (°C, undoped Si) Height (eV)
NiSi ~20 Ni 350-750 0.67
NiSi2 ~50 Ni 750-850 0.66
TiSi₂(C49) 60-80 Si 600-700
TiSi₂(C54) 13-16 Si >700 0.6
CoSi 100-150 Si 400-450 0.65
CoSi2 18-20 Co >550 0.65
PtSi 28-35 Pt 600-800 0.87
TaSi2 50-55 Si >600 0.59
WSi2 30-70 Si >600 0.65
MoSi2 80-250 Si >600 0.55
Pd2Si 30-35 Pd >400 0.75
 TiSi2 has high thermal budget as the low resistance phase requires T > 800°C
 TiSi2 and CoSi2 have high Si consumption  problem in scaling junctions
 NiSi has lower Si consumption
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 Problem with Salicide Technology
- Si Consumption
 For 0.25 um devices (Xj ~ 200 nm), the commonly used
TiSi2 and CoSi2 work quite well, though there is some
junction leakage.
 However, as junctions are scaled further, Ti and Co
salicides become impractical due to high Si consumption.
 Metals for salicide formation are almost always sputtered.

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 Problem with Salicide Technology
- TiSi2 Scalability (1)
 TiSi2 was the dominant salicide technology for many years.
As devices were scaled, a new limitation of the use of TiSi2
emerged.
 Low resistance TiSi2 is formed through a phase
transformation from C49 to C54. This transformation
becomes extremely difficult for thin lines, and hence, this Ti
lines have higher resistances than desirable.

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 Problem with Salicide Technology
- TiSi2 Scalability (2)
 This line-width dependence problem is essentially unique to
TiSi2; line-width effects in other silicides are much less
dramatic.
 This was the driving force for the transition from Ti to Co,
despite the fact that Co has a higher Si consumption ratio.

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 Key Issues in SALICIDE Technology (1)
 Thermal stability concern
– Agglomeration (one contributor to narrow-line-width
effect)
– Degradation of gate oxide integrity (GOI)
– Junction leakage

 Narrow-line-width effect (mainly for Ti salicide)

– Sheet resistance ↑  line width↓
(the kinetics of C-49 to C-54 phase
transition and agglomeration)
– Process window shrinks significantly
as TiSi2 thickness and channel length
is scaled down.
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 Narrow-Line-Width Effect
Implanted As for pre-amorphization and
sequential two step sintering prevents the TiSi2
overgrowth on p+ poly and diffusion layers

IRPS, p.363 (1998)

Symp. VLSI Technol. p.66 (1992)

TiSi2 sheet resistance on As doped n+ poly-Si
as a function of line width
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 Key Issues in SALICIDE Technology (2)
 Si consumption
– Ultra-thin metal film deposition are required
– Trade-off between metal thickness and sheet
resistance,
– contact resistance, junction leakage, etch selectivity
(during contact hole formation), and process window
 Bridging effect
– Short between gate and source/drain due to
undesired silicide formed on the sidewall spacer
 Junction leakage (mainly for Co salicide)
– Possibly caused by CoSi spiking in Co SALICIDE
– 2nd RTA needed to reduce leakage
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 Comparison of volumetric changes in Ti,
Co, and Ni silicidation processes

J. Electrochem. Soc. Vol.144, p.2437 (1997)

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 Major Issues in Salicide Process
Narrow-line-width effect
Agglomeration

Bridging

Degradation of GOI Junction leakage

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 Moving Species during Salicide

Bridging
Ti salicide

Si
Metal
CoSi2 and NiSi salicide

Junction leakage

T. Ohguro et al., IEEE ED, Vol.41, p.2305 (1994)

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 CoSix Spikes in Si

– CoSix Spikes generate at

low annealing
temperature (400 ~ 425
C), when the
transformations of Co 
CoSix spiking
Co2Si and Co2Si  CoSi
are both taking place.

– During annealing at
higher temperature
(>500 C), CoSix Spikes
become spherical and
JJAP. V-36, p.6244 (1998) their density decreases.

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 Solution of Co Spike

2nd annealing at 800~850°C is needed

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 Formation of T-shaped Gate and Raised S/D
Using Selective Epitaxial Growth (SEG)

Si or SiGe epi

silicide

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 Raised S/D MOSFET
Gate Isolation
Gate
Isolation Gate
Halo
Raised Raised
Epi-SiGe Epi-SiGe
S/D S/D

Channel Implant BOX

TEOS Space S/D Extension
Deep Well Implant

Reduction of Source/Drain Series Resistance.

Out-diffusion from a doped for ultra-shallow
junction formation.
Shallow junctions obtained by p+ SiGe or n+SiC
epi for S/D.

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 Dual Epitaxial Raised S/D
Blanket Epitaxial Si Selective Undercut In-Situ doped p+
Raised S/D Growth Etch PMOS regions SiGe Epitaxy
HM HM HM
Poly Poly Poly

Si Si SiGe SiGe
FIN FIN FIN

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 S/D Series Resistance Issue

Top SEM view DG FinFET before and after

selective Si epitaxy. Tsi = 20nm, Lpoly = 30nm J.Kedzierski et al., IEDM 2001

S/D series resistance will degrade the performance of

thin body device, like finfet.
Can be improved by the selective Si epitaxy raised S/D.

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 Integration of high Ge content SiGe for
pMOS transistors
Raised S/D SiGe regrowth SiGe diamond
Si fin
(111) facets shaped S/D

Embedded S/D
Si fin SiGe diamond
Si recess SiGe regrowth shaped S/D
(111) facets

 Faceted growth in a free space allows to slightly elastically relax

the strained structure.
 Increase of Ge content is needed in order to maintain the same
24 level of strain.
 Raised S/D-for 10nm ang 7nm nodes
UTBB
FinFET/Trigate Nanowire
Ultra Thin Body & BOX

N or P groundplane

‹‹ Vertical ›› double Gate-All-Around

Undoped channel gate
Back-gate control Undoped channel
Undoped or doped Multi-wires
using thin BOX channel
capacitive coupling Raised S/D
Multi-Fin
Raised S/D Raised S/D
*2014: SiGe-FinFET at 14nm
IEDM-2013 short course *2016: Ge-FinFET at 10nm
25 *2018: Nano-wire at 5nm (Si, SiGe and Ge)
 SBMOS (Schottky-barrier MOSFET)
-Metal S/D
SBMOS MOSFET
Gate Gate
Gate Oxide Gate Oxide

Schottky Schottky n+ n+
Source Drain Source Drain

Silicon Substrate Silicon Substrate

Thermal Vg=0V Vg=0V

Emission e- e-
φBn

SB TunnelingVg=1V Vg=1V

Vd=1V Vd=1V

 In SBMOS, carriers can thermonicly emit over or laterally tunnel through

Schottky barrier to contribute drain current.
 Unique Impact Ionization is observed in SBMOS.
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 Characteristic of Schottky S/D MOSFET
Advantages:
Low S/D sheet resistance
Low parasitic source and drain resistance
Low process temperature (lower than 600 °C)
Easy processing, elimination of S/D implant
Ultra-shallow and abrupt junction, better immunity from
short channel effects
Modulation of the source barrier by the gate
 High Vg  barrier thin  tunneling current   ION 
 Low Vg  barrier thick tunneling current   IOFF 
Disadvantage:
ION reduction due to the Schottky barrier.
The generation of trap states of Schottky diode interface
(Si in channel reacts with metals), causing microscopic
inhomogeneity of Schottky barrier height.
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 Review and Summary
 Silicide Process design consideration
 Resistivity, Reaction Temperature, Barrier
Height
 Si consumption ratio
 Narrow-line-width effect
 Ni, Ti, Co silicide mechanism
 RSD improvement
 Raised S/D
 Schottky-barrier MOSFET (Metal S/D)

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