Final Desi gn Specificstion For theMCS65E4 Microprocessor

W r i t t e n by: Y a n 3 / G o o d m a n /' M a t h y s
R e v i s i o n I 1*1
Date Released: 1 0-MAY-82

T h i s d o c u m e n t is s u b m i t t e d w i t h the u n d e r s t a n d i n g t h a t
it contains information which is confidential in
n a t u r e and is n ot to be r e v e a l e d to anyone without
w r i t t e n p e r m i s s i o n f r o m M OS T e c h n o l o g y f Inc.

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C ♦**** ***** P a2 e -

 Revision History

Re v t Date Description of Revision

0 ♦0 2-Gct-31 Original release

1,0 1-MAY-32 G e n e r a l c l e a n - u p arid reor ganiz a t i o n * .

R e w r i t e of s o f t w a r e a r c h i t e c t u r e d e s c r i p t i o n

*********CQNFIDENTIALf MGS T E C H N O L O G Y > INC . M X * * * * * * Fade-

 Final Des ign Specification for the M C S 6 5 E 4 M i c r o p r o c e s s o r

Table of Contents

1*0 Introduction* * * * * * * * * ♦ * * * * * ♦ * * ** * 12

1*1 Review of Project Goals* ♦♦ * * * * ♦ * * * ♦ ♦ * * 12

1*2 Summary of MC3 65E 4 Capabilities* * * * * * ♦ *

1*3 Terminology* * * * * * * * * * * * * * * * * * *♦ * 14

1*3*1 Introduction ** * * * * * * * * * * * ♦ * * * ♦ 14

1*3*2 Process* * * •> * * * * * * * ♦ ♦ * * * * * ** * 14

1*3*3 Op Code* * * * * * * * * * * * * * * * * * * * * 15

1*3*4 Operand* * * * * * * * * * * * * * * * * * ** * 15

1*3*5 Instruction* ** * * * * * * * * * * * * * * * * 15

1*3*6 Descriptor* * * * * * * ............................ * * * * *

1*3*7 Ordinal ** * * * * * * * * * * * * * * * ** * 16

1*3*8 S t atic Data? Dynamic Data* * ** * * * * * * * * 16

1*3*9 Ph y s ic a l Address * * ** * * * * * * * * * * * * 16

1*3*10 Log i c a l Address ♦ ♦ * ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 16

1*3*11 Pa^e Address* * * * * * * * * * * * * * * * * * 17

1*3*12 Offset Address? Relative Address* * * * * * * * 17

1*4 E x a m p l e of Addressing in the M C S 65 E 4 System* * * * * 20

2*0 Description of the MCS65E4 Pin Functions * ............. 22

2*1 Introduction* * ** * * * * * * * * * * * * * * * * 22

2*2 Address Bus Middle / Address Bus L ow * * * * * * * * 22

2*3 Address Bus / D a t a Bus / B us Status** * * * * * * * 22

2*3*1 Interrupt Acknowledge* * * * * * * * * * * * * * 23

2*3*2 Hold Acknowledge * * * * * * * * * * * * * * * * 23

2*3*3 Last Instruction Cycle * * * ** * * * * * * * * 23

2*3*4 I/O R e s e t ............... * * * * * * * * * * * * * 23

2*3*5 Processor Instruction Fetch* ** * * * * * * * * 23

2*3*6 Processor Data Fetch ** * * * * * * * * * * * * 23

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 Final D e sign Specification for the MC 365 E 4 Microprocessor

2.3.7 Refresh Cacle. .. . . .. . . . . . . . * * . . 24

2.3.8 External Microcode Fetch . . . . . . . . . . . . 24

2.4 Ro w Address Strobe 24

2.5 Column Address Strobe. 24

2.6 Chip Power. . .. .. . . . . . . ♦ . . . • * . * • 24

2.7 Oscillator ............... 24

2.8 Bus C l o c k ............... . . 24

2.9 Valid Memory Address . . . . . . . . . . . . . . . . 24

2.10 Memory Ready. . . . ............... ... . . . . . * * . 25

2.10.1 Read C y c l e .......... .. ............ .. .................. 25

2.10.2 Write Cycle . . . . . . . . . . . . . . . . . . 25

2.11 Interrupt Input . . . . . . . . . . . . . . . . . . 25

2.12 Reset ............. .. ............ .. . 25

2.13 Write Enables . . . . ... ......... ... . ............ * 26

2.14 Bus Error. . .. .. . . * . ♦ * * » . » » * » * * 26

2.15 Hold. . . . . . . . . . . ............... . . . . . . 26

2.16 Instruction Intercept . .. . . . . . . . . . . . * 26

3.0 Internal Architecture. .......... . . . . . ♦ . . . * .

3.1 Introduction . .. .. . . . . * . . . . • . * * * *

3.2 Execution Unit . . . . . . . . . . . . . . . . . . . 27

3.2.1 ABL/ABM Registers. . . . . . . . ............... ♦ 27

3.2.2 Register Array . . . . . . . . . . . . . . . . .

3.2.3 Arithmetic Logic U n it. . . . * . . . . . . » « » 28

3.2.4 Input Queue. . .. . . * . . . . . . » » * * * » 28

3.2.5 ABH/DB Registers ..................... .. ............. 28

3.3 Execution Control Logic. .. . . . . . . * ♦ » * ♦ « 28

3.3.1 Control Registers. . .. . . . . * * ♦ * . » ♦ * 28

3.3.2 Microcode Array 28

* * * * * * * * * C Q N F I D E N T I A L t MOS TECHNOLOGY j I N C. * * # * * * * * * Page-

 Final D esign Sp ecif icst-ion for t.h e M C S 6 5 E 4 M i c r o p r o c e s s o r

4 *0 S o f t w a r e 30

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4*2*6 Top 31

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4*2*7* 1 32

4 * 2 *7 *2 32

4 *2 * 7 * 3 32

4 * 2 *7 *4 32

4 *2 * 7 * 5 32

4 *2 * 7 * 6 “
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4 * 2 * 7 *3 32

4*2*7*? 33

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4 *3 P r o c e s s 35

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4*3*5* 1 36

4 * 3 * 5 *2 36

*********CONFIDENTIAL> MOS TECHNOLOGY?INC.**#****** PsSe-

 Final Design Specification for the MC S6 5E 4 Microprocessor

4»3*5*3 Process Stack* *♦♦ ♦ ♦ ♦ * * ♦ ♦ * * ♦ ♦ * * 36

4*3»6 Process Software * ♦♦ * ♦ ♦ ♦ ♦ * ♦ * * » * , ♦ 36

4*3*7 Process Vectors* ♦ ♦♦ * * * * ♦ ♦ * ♦ ♦ ♦ ♦ ♦ ♦ 36

4*3*8 Kernel Reset Vector* * ♦ ** * * * * ♦ ♦ ♦ ♦ * * 36

4*4 Execution of Processes in the MCS65E 4 * ** ♦ ♦ ♦ ♦ ♦ 37

4*4*1 Introduction * * * * * * ** * * * * * ♦ ♦ ♦ ♦ ♦ 37

4*4*2 Basic Inter-process Controls * * ♦ *♦ ♦ ♦ ♦ ♦ ♦ 37

4*4*2*1 Introduction * * ♦ ♦ * * ♦ ♦ ♦ ♦ ♦ ♦ ♦ * ♦ * 37

4*4*2*2 Kernel Reset Vector* ** * * * * * * ♦ ♦ ♦ * 37

4♦4 * 2 * 3 P r o c e s s Parameter List * * ♦ * ♦ ♦ * * * ♦ ♦ 37

4*4*2*4 Pointer to current Caller* * * *♦ ♦ ♦ * * ♦ 38

4 * 4 * 2 *5 P r o c e s s Link * ** * * ** ♦ ♦ * ♦ ♦ ♦ ♦ ♦ ♦ 38

4*4*2*6 Process Stack* ** * * * * * * ♦ * * * * * ♦ 39

4*4*3 Inter-Process Operations ♦ * ♦ ♦ ♦ ♦ ♦ ♦ * ♦ * ♦ 3?

4*4*3*1 Introduction .................. * ♦ ♦ ♦ ♦ ♦ ♦ ♦ 39

4*4*3*2 System reset ** * * * ** * * * * * * * * * 39

4 ♦ 4 ♦ 3 *3 Invoking Additional Processes* ** * * * * * 40

4*4*3*4 Exception Processing *♦ * * * * * * * * * * 42

4 ♦ 4 *3 ♦4 ♦ 1 I n t r o d u c t i o n * * * ** * ♦ ♦ * * * * * ♦ 42

4 * 4 * 3 * 4 * 2 S e r v i c i n g e x c e p t i o n s w i t h i n the
current process * ♦ ♦ ♦ * ♦ ♦ ♦ * ♦ ♦ * ♦ ♦ ♦ ♦ 42

4*4*3*4*3 Servicing e x c e p t i o n s w i t h i n the

calling process * * * * * ** * * * * * * * * * 45

4*4*3*5 Returning to a Suspended Process * * * * * * 46

4 * 4 * 4 E x c e p t i o n V e c t o r s w i t h i n the
M C S 6 5 E 4 P r o c e s s ** .................... * ............ * * 47

4 ♦ 4 ♦4 ♦ 1 I n t r o d u c t i o n ** * * * ** * * * * * * * * * 47

4*4*4*2 Undefined Op Code Trap * * * * * * * * * * * 48

4*4*4*3 Undefined Data Type Trap * * * * * * * * * * 48

4 * 4♦4 ♦ 4 S u b s c r i p t out-of-limits Trap * ** * * * * ♦ 48

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 Final De sign Specification for the MCSo5E 4 Microprocessor

4 * 4 * 4 ♦5 O p e r a t o r and Operand Not Compatible* ♦ * ♦ ♦ 48

4 * 4 ♦4 ♦ 6 0 ve r f l'o w ♦ * * * .......... * * ♦ * * ♦ ♦ ♦♦ 48

4 * 4 * 4 *7 O t h e r Arithmetic Error ♦* ♦ ♦ ♦ * ♦ * ♦ ♦♦ 48

4*4*4*8 Non-conformable Data Types * * * * * * * * * 48

4 * 4 * 4 *9 I n s t r u c t i o n Access Trap* * * * ♦ * ♦ ♦ ♦ ♦♦ 49

4»4»4*10 Data Access Trap* * * ** * * * * * * * ** 49

4*4*4*11 Process Stack Page Boundary Trap* * * * * * 49

4*4*4*12 Debug Tra p * ♦ ♦ ♦ * ♦ ♦ * ............... * * 49

4*4*4*13 Interrupt Input * * * ** * * * * * * * ** 49.

4»4*4*14 System C all * * * * * * * * * * * * * * ** 49

4*4*4*15 System Cal l with Message* * ♦ * * * ♦ ♦ ♦ * 49

4*4*4*16 B us Error * * * * * * * * * * * * * * * ** 49

4*4*4*17 Access out-of-limit * ** * * * * * * * ** 49

4*5 Addressing within the MCS65E4* ♦ * ♦ ♦ * ♦ ♦ ♦ ♦ ♦ ♦ 50

4*5*1 Introduction * * * * * * * * ♦ * * ♦ * * ♦ * ♦* 50

4*5*2 Primary Addressing Group * ** * ♦ ♦ * * * * ** 53

4 *5 ♦ 2 * 1 I n t r o d u c t i o n * * * * * * * * * * * * * * ** 53

4*5*2*2 Base Register Select Field ♦ ♦ ♦ ♦ ♦ ♦ * ♦ * 53

4 * 5♦2 *3 D a t a Access Format * * *♦ * * * * * * * ** 53

4*5*2*4 Number of Extension Bytes* * * * * * ♦ ♦ ♦ * 54

4*5*3 Secondary Addressing Group ** * * * * * * * ** 54

4 *5 *3 * 1 I n t r o d u c t i o n .......... * * * * * * * * * * * 55

4*5*3*2 Limit Page Addressing* * ♦ * ♦ * ♦ .......... 55

4 *5 * 3 * 3 P r o c e s s Stack PUSH / POP * * * ................ 55

4*5*3*4 Immediate Addressing? Long F orm * * * * * * * 60

4*5*4 Internal Register Addressing * **** .......... 60

4*5*5 Immediate Addressing? Short Form * * * * * * * * 60

4*5*6 Process Base Addressing? Short F orm* * * * * * * 61

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 Final Design Specification for the M C3 65 E4 Microprocessor

4*5*7 Primary Base Addressing? Short F orm * * * * * * * 61

4*6 Data Structure Within the MCS65E4 System * * * * * * 63

4*6*1 Introduction * * * * ** * ♦ * ♦ * ♦ ♦ ♦ ♦ + ♦ f 63

4*6*2 The Basic Data Elements* * ♦ * * * * * * ♦ ♦ ♦ * 66

4 *6 ♦ 2 ♦ 1 U n s i g n e d Binary Data Fields* ** * * * * * * 66

4*6*2*2 Signed Binary Data Fields* * ♦ * ♦ * ♦ ♦ ♦ * 66

4*6*2*3 BC D Data F i e l d s .......... .. 66

4*6*2*4 Floating Point Data Fields * ** ♦ * * * * * 66

4*6*2*5 String Data Fields * * * * * * * * * * * * * 66

4*6*3 Organization of the V a r i a b l e Descriptor* * * * * 63

4 *6 *3♦1 Introduction * * ** * * * * * * * * * * * * 63

4*6*3*2 O r g a n i z a t i o n of the Descriptor

Header ♦ ♦ * ♦ ♦ ♦ * .......................... ♦ 68

4 * 6 * 3 *2 * 1 I n t r o d u c t i o n ** * * * * * * * * * * * * 68

4 * 6 *3 *2 *2 T r a p Bit * * * * ............................ 68

4*6*3*2*3 Access M ode* ♦ ♦ * ♦ * * * ♦ * ♦ * ♦ * * 68

4 * 6 ♦ 3 ♦ 2 *3 * 1 A t t a c h e d * * * * * ............. * * * 69

4*6*3*2*3*2 Attached Relocatable ** * * * * * * 69

4*6*3*2*3*3 Short Relative * * * * * * * * * * * 69

4*6*3*2*3*4 Short Relocatable* * * * * * * * * * 69

4*6*3*2*3*5 Long Relative* * * * * * * * * * * * 69

4*6*3*2*3*6 Long Relocatable * * * * * * * * * * 70

4*6*3*2*3*7 Logical Addressing * * * * * * * * * 70

4*6*3*2*4 Data Type Field and Flag ** * * * * * * 70

4*6*4 T he Data Structures* * * * * * * * * * * * * * * 74

4 ♦6 ♦ 4♦1 Introduction * ** * * * * * * * * * * * * * 74

4 ♦ 6 * 4 *2 Single Dimension Arrays* * * * * * * * * * * 74

4*6*4*3 Array Structure* * * * * * * * * * * * * * * 77

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 Final Desig n Specification for the M CS 65E4 Microprocessor

4*6»4*4 Record ♦ ♦ * ♦ ♦ * ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ * ♦ ♦ ♦ 32

4*6*5 Deferred Descriptor* * * * ** * * * *• * * * * * 36

4*6*6 A p p l i c a t i o n of the M C S 6 5 E 4 D a t a
Accessing Mechanisms * * * * ♦ * ♦ ♦ ♦ * ♦ ♦ ♦ ♦ S3

4 *6 *6♦1 Introduction * * * * ♦ ♦ * * ♦ ♦ * ♦ * * ♦ ♦ 33

4*6*6*2 A c c e s s i n g D a t a in M u l t i - D i m e n s i o n a l
Arrays * * * * * * * * * * * * * * * * * * * 38

4 * 6 * 6 * 3 E x a m p l e of A c c e s s i n g a mu 1 1 i - d i m e n s i o n a 1
array * * * * * * * * * * * * * * * * * * * * * * 94

4 * 6 * 6 * 4 E x a m p l e of A c c e s s i n g D a t a in a C o m p l e x
Record Structure* ♦ * * * « * * > . * » * * « * * * 99

4*6*6*5 Exception Vectors* * * * * * * * * * * * * * 104

4 * 6 * 6 *5 * 1 I n t r o d u c t i o n * * * * * * * * * * * * * * 104

4*6*6*5*2 Descriptor Format* * * * * * * * * * * * 104

4 * 6 * 6 *5 *3 E x a m p l e of Attached Address
Descriptor Format * ♦ * ♦ * ♦ * ♦ * * * * * * ♦ 105

4*6*6*5*4 Example of Remote Exception Vector * * * 105

4*7*The MCS65E4 Instruction Set* * * * * * * * * * * * * 107

4*7*1 Introduction * * . * * * * * * * * * * * * * * * * 107

4*7*2 Format of the MCS65E4 Op C o d e s ............... * * 107

4*7*3 Basic Arithmetic arid L o g i c Operations* ** * * * 109

4 *7 * 3 * 1 I n t r o d u c t i o n * * * * * * * * * * * * * * * * 109

4*7*3*2 ADD* * * * * * * * * * * * * * * * * * * * * 111

4 * 7 *3 * 3 S U B T R A C T * * * * * * * * * * * ............... 112

4 * 7 *3 * 4 MUL* * * * * * * * * * * * * * * * * * * * * 113

4 *7*3 *5 D I V I D E * * * * * * * * * * * * ............... 114

4 * 7 *3 *6 AND* * * * * * * * * * * * * * * .......... * 115

4 * 7 *3 * 7 OR * * * * * * * * ........... * ............ * * 117

4 * 7 *3 * 8 E 0 R * * * * * * * * * * * * ........... * * * * 119

4 *7 * 3 * 9 MOD* * * * * * * * * * * * * * * * * * * * * 121

4*7*3*10 A BS * * * * * * * * * * * * * * .......... * 122

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 Final Design Specification for the MC S65E 4 Microprocessor

4.7.4.11 NEG . . . . . . . . . . . ...................... .. . 123

4.7.3.12 INC.. ............................................... 124

4.7.3.13 D E C .......... .. .................................... 125

4.7.3.14 S ORT. .......................................... .. . 126

4.7.3.15 MOM . . . . . .................................... 127

4.7.3.16 L E A D Z ......................................... .. . 123

4.7.3.17 LEAD1 . . . . . . . . . . . .......... . . . 129

4.7.3.13 CLR . . . . . . . . . . . . . . ............. 130

4 . 7 . 3 . 1 9 S E T ......................................... .... .,131

4.7.4 Program Control Instructions . . . . . . . . . . 132

4.7.4.1 Introduction . . . . . . ► . . . . . . . . . 132

4.7.4.2 B E Q . ............... .. .................... .. 133

4.7.4.3 B N E .................. .. .................... .. 134

4.7.4.4 B G T . .................................. ............... 135

4.7.4.5 B G E ............................................ .. 136

4.7.4.6 B E Q Z ................................................. 137

4.7.4.7 BNEZ . . . . . . . . . . . ............. . . . 133

4.7.4.3 BROS . . . . . . .......... . . . . . . . . . 139

4.7.4.9 BMI .................................................... 140

4.7.4.10 BR. ....................... . . . . . . . . . . 141

4.7.4.11 JMP . . . . . . . . . . . . . . . . . . . . 142

4.7.4.12 BSR ............................. .. .................. 144

4.7.4.13 JSR . . . . . . . . . . . . . . . . . . . . 145

4.7.4.14 B D E C . ....................... ............. .. 147

4.7.4.15 BCOND . . . . . . . . . . . . . . .......... 143

4.7.4.16 SC. . . . . . . . . ............... . . . . . 149

4.7.4.17 SCM .......... . . . . . . . . . . . . . . . 150

4.7.4.18 RTS ..................... . . . . . . . . . . . 151

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 Final Design Specification for the MCS65 E 4 Microprocessor

4.7.4.19 RTE . . . . . . . . . . . . . . . . . . . . 152

4.7.4.20 I O S ............... .. ............................ .. 153

4.7.4.21 T ASK. . . . . . .................................. . . . . 154

4.7.5 Advanced Operations. . . . , . .. , . , .. , . 155

4.7.5.1 Introduction ... . . , . .. . . . . . . . 155

4.7.5.2 RESET. . . . . . ............. . . . . . . . . 156

4.7.5.3 CEQ. . . . . . . . . . . . . . . .......... 157

4.7.5.4 ONE . ......................................... ...... ...... ...... .158

4.7.5.5 CGT . . . . . . . . . . . . . . . . . . . . 159

4.7.5.6 C6E ** . . .. ...... . .*.. . ..160

4.7.5.7 F I N D ..................... . . . . . . . . . . . 161

4.7.5.8 D E T C . ....................................... .. 163

4.7.5.9 N D E T ............ .................................... 164

4.7.5.10 D E T R ............... .. ............................ .. 167

4.7.5.11 SHM . ..................... .................._ . . . 169

4.7.5.12 F ' T R ................................... .. 171

4.7.5.13 DTYF'E ................................... .. 173

4.7.5.14 CNYRT .............................................. 175

4.7.5.15 EVAl. .............. .. ............................ 176

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 F i n 3 1 Design Specification for the MC S65E 4 Microprocessor

1*0 Introduction

This s p e c i f i c a t i o n c o n t a i n s a d e t a i l e d d e s c r i p t i o n of all a s p e c t s
of the MCS65E4 microprocessor d e v e l o p merit p r o j e c t ? b e g i n n i n g in
Section 1 w i t h a r e v i e w of the p r o j e c t g o a l s arid a d i s c u s s i o n of
the m a r k e t toward which this c h i p is d i r e c t e d * It is h o p e d t h a t
these discussions will lead to g r e a t e r u n d e r s t a n d i n g of the g o a l s
of the p r o j e c t on the p a r t of e v e r y o n e i n v o l v e d *

S e c t i o n 2' c o n t a i n s a d e s c r i p t i o n of the M C S 6 5 E 4 i n t e r f a c e * T h i s is
f o l l o w e d by s d e s c r i p t i o n of the i n t e r n a l a r c h i t e c t u r e of the
MC S 6 5 E 4 (Section 3 )? i n c l u d i n g the r e g i s t e r organization? the
internal buses a n d the o r g a n i z a t i o n of the c o n t r o l s t o r e * S e c t i o n
4 contains a detailed description of the MCS65E4 software
a r c h i t e c t u r e ( a d d r e s s i n g m o d e s ? i n s t r u c t i o n set? e t c * ) *

1*1 Review of MCS65E4 Project Goals

Before entering into a detailed d i s c u s s i o n of the M C S 6 5 E 4 ? it

w o u l d be u s e f u l to b r i e f l y review the major factors which have
i n f l u e n c e d the design of this p rocessor system* Understanding
these factors wi l l be p a r t i c u l a r l y i m p o r t a n t for a n y o n e i n v o l v e d
in the d e s i g n v e r i f i c a t i o n s t a g e of t h i s p r o j e c t *

A l t h o u g h t he M C S 6 5 E 4 is e q u i p p e d w i t h a " c o m p a t i b l e ' m o d e in w h i c h
it is c a p a b l e of executing software w h i c h was w r i t t e n for the
MCS6502? the M C S 6 5 E 4 is not d e s i g n e d to be u p w a r d c o m p a t i b l e w i t h
the 6502 f a m i l y of 3 - b i t m i c r o p r o c e s s o r s * T h e p r i m a r y r e a s o n for
t h i s is that the b a s i c design considerations behind the 6502
processor differ greatly from those described below for the
M C S 6 5 E 4 p r o c e s s o r * T h i s is t r u e in s p i t e of the f a c t t h a t the 6 5 0 2
h as r e a c h e d a d o m i n a n t p o s i t i o n in the m i c r o c o m p u t e r m a r k e t ? one
of the t a r g e t m a r k e t s fo r the M C S 6 5 E 4 *

To put the 6 5 0 2 a r c h i t e c t u r e i nto p e r s p e c t i v e ? it s h o u l d be n o t e d

that when this de s i g n effort began? m i c r o p r o c e s s o r s were viewed
p r i m a r i l y as replacements for random l o g i c in the design of
controllers* The 6 5 0 2 w a s optim ized toward this a p p l i c a t i o n * To
t h i s end? significant emphasis was placed on minimum system
c o n f i g u r a t i o n s and on m i n i m i z i n g d e v i c e and s y s t e m co s t * T h i s was
accomplished through the use of such things as page zero
addressing? 8-bit index registers? multiple-function support
d e v i c e s ? and g e n e r a l l y s i m p l i f i e d s y s t e m i n t e r f a c i n g *

M a n y of the c h a r a c t e r i s t i c s of the 6 5 0 2 which were d e s i g n e d to

m a x i m i z e its p e r f o r m a n c e as a r a n d o m l o g i c r e p l a c e m e n t w o u l d s e e m
to l i m i t its p e r f o r m a n c e in h i g h - e n d m i c r o c o m p u t e r systems* In
s p i t e of t h i s f act? low c o s t and e a s e of use has a l l o w e d the 6 5 0 2
to b e c o m e a d o m i n a n t f a c t o r in t h i s m a r k e t * T h e s e are the f e a t u r e s
w h i c h wil l be r e t a i n e d in the M C S 6 5 E 4 * At t he s a m e time? the
a r c h i t e c t u r e of t h i s ' next g e n e r a t i o n * p r o c e s s o r will be d e s i g n e d
to a s s u r e maximum p e r f o r m a n c e in microcomputer s y s t e m s at the
l o w e s t p o s s i b l e cost*

Modern high-end microcomputer s y s t e m s e x h ib it several feat ures

w h i c h c an g r e a t l y i n f l u e n c e the d e s i g n of a processor optimized

* * * * * * * * * C 0 N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C *** **** *** Page- 12

 Final D es ign Specification for the MC365 E 4 Microprocessor

for this application* In particular? all s u c h systems are

c o n t r o l l e d by a s o p h i st i c a t e d operating system * In m a n y c a s e s ?
c o m p o n e n t s of this o pe r at in g system are s w a p p e d into and out of
m e m o r y as required* host such systems support several user's
p r o g r a m s in a * m u l t i - t a s k " e n v i r o n m e n t ? r e a l l o c a t i n g the a v a i l a b l e
memory from system to user or f r o m one user to another as
reoui r e d *

T h e r e are several important problems i n h e r e n t in this type of

system* The f i r s t is m e m o r y p r o t e c t i o n * It is i m p o r t a n t t h a t the
operating system be p r o t e c t e d f r o m th e u s e r ' s p r o g r a m s arid t h a t
the u s e r ' s p r o g r a m s be p r o t e c t e d f r o m e a c h o t h e r * In a d d i t i o n ? the
software should be “r e l o c a t a b l e " s i n c e th e p h y s i c a l a d d r e s s s p a c e
in w h i c h the p r o g r a m wi ll be l o c a t e d is g e n e r a l l y d e t e r m i n e d at
e x e c u t i o n time*

In a d d i t i o n to the a b o v e ? it is a s s u m e d t h a t m o s t m i c r o c o m p u t e r
programming will involve the use of a high-level language*
Therefore? the s o f t w a r e a r c h i t e c t u r e of the p r oce ssor must be
d e s i g n e d to m i n i m i z e the tim e r e q u i r e d for b o t h c o m p i l a t i o n arid
e x e c u t i o n of s u c h l a n g u a g e s *

Finally? it s h o u l d be n o t e d t h a t e v e n t he most powerful processor

is w a s t e d if it is a b s o r b e d in I/O h a n d l i n g a l a r g e p o r t i o n of the
time* For t h i s r e a s o n ? the s y s t e m le vel p r o b l e m s of i n t e r r u p t ?
DMA? etc* m u s t be h a n d l e d in a m a n n e r w h i c h m a x i m i z e s the a m o u n t
of t i m e w h i c h the p r o c e s s o r has a v a i l a b l e for " c o m p u t i n g " *

All of t h e s e f a c t o r s h a v e had a s t r o n g i n f l u e n c e on the d e s i g n of

the M C S 6 5 E 4 * H o w e v e r ? the d e s i g n d e s c r i b e d b e l o w a d d r e s s e s e a c h of
these factors in a mariner w h i c h provides maximum performance
within well-defined chip size constraints* The architecture
d e s c r i b e d in t h i s d o c u m e n t can be b u i l t into a d e v i c e w h i c h will
be well within "state of the art"? providing a combination of
device cost and p e r f o r m a n c e w h i c h s h o u l d a l l o w it to a s s u m e the
dominant position in th e m i c r o - c o m p u t e r m a r k e t now h e l d by the
6502 *

1*2 Summary of MCS65E4 capabilities

The f o l l o w i n g is a b r i e f l i s t i n g of the principal features of the

MCS65E4 family of microprocessors*

1* S? 16 or 32-bit Data Bus*

2* 24-bit Address Bus*

3* ALU p r o c e s s e s 32 bits of data f or each processor cycle*

4* No i n t e r n a l d a t a r e g i s t e r s v i s i b l e to the programmer* All

o p e r a t i o n s are ' m e m o r y - t o - m e m o r y " *

5* I n t e r n a l o p e r a rid r e g i s t e r s allow processing of multi-byte

operands*

6* "Generic" Op Codes? i* e*? the Op Codes do not s p e ci fy

*********CQNFIDENTIAL? MOS T EC H N O L O GY ?I N C ♦* ***** *** Page- 13

 Final D esi gn Specification for the MCS65 E4 Mic t o p rocessor

the format of the data fields*

7 * "Self-defining* data structures? i * e *? most d a t a is

accessed through tag s arid descriptors* H o w e v e r ; the
a b i l i t y to directly access and m a n i p u l a t e byte? d o u b l e
b y t e and t r i p l e b y t e f i e l d s is p r o v i d e d to f a c i l i t a t e the
g e n e r a t i o n of d e s c r i p t o r and p o i n t e r a d d r e s s e s ? etc*

8* O n - c h i p h a r d w a r e and microcode support for many oper< -i rig

system functions*

9* Hardware support fort

^-3 ♦ E r r o r D e t e c t i o n arid c o r r e c t i o n *
b* Virtual memory*
c* P r i o r i t i z e d and v e c t o r e d i n t e r r u p t s *
d♦ F l o a t i n g point data types*
e* D e c i m a l (BCD) d a t a t y p e s *

1*3 Terminology

1*3*1 Introduction

The architecture of t he MCS65E4 contains a number of very

important concepts which ar e uniaue to the world of
microprocessors* To a s s u r e the a c c u r a t e t r a n s f e r of i n f o r m a t i o n ?
therefore? this se ction introduces what is h o p e f u l l y a cl e a r ?
consistent terminology which will be e m p l o y e d throughout this
document*

1*3*2 F'rocess

The "process" is one of the key concepts in the MCS65E4

architecture* In g e n e r a l ? a process can be described as a
self-contained combination of software and data* The a d d r e s s
limits within which a process must execute are defined by
information stored in an i n t e r n a l P r o c e s s B a s e F^egister for the
lower limit and in a P r o c e s s L i m i t R e g i s t e r for the u p p e r l i mit*
S p e c i a l h a r d w a r e w i t h i n t he M C S 6 5 E 4 assuresthat a proc e s s does
not a c c e s s any memory locations outside of the address space
d e f i n e d by t h e s e two r e g i s t e r s *

T h e r e are several important process c h aracteristics which affect

the e x e c u t i o n of s o f t w a r e w i t h i n the M C S 6 5 E 4 * The m o s t i m p o r t a n t
is t h a t all p r o c e s s e s a re t o t a l l y r e l o c a t a b l e ? i* e * ? an M C S 6 5 E 4
p r o g r a m w i l l e x e c u t e in e x a c t l y the s a m e m a n n e r no m a t t e r w h e r e it
is l o c a t e d in the 16 m e g a - b y t e address space In a d d i t i o n ? an
active process can be s u s p e n d e d ? a n d can be moved within the
address space of its caller without affecting subseq uen t
execution*

There a re three types of processes within the MCS65E4

architecture* T h e s e are the K e r n e l ? the O p e r a t i n g S y s t e m and the
User process* Each ex h ib i t s characteristics which reflect its
p o s i t i o n in a well-defined hierarchy* The t e r m " K e r n e l process'*
r e f e r s to the l o w e s t l eve l in the set of p r o c e s s e s w h i c h f o r m s a

*********CONFIDENTIAL> MOS T E C HN O LO G Y ?I N C * * * * * ** * * * Page- 14

 Final Desig n Specification for the M C S 6 5 E 4 M i c r o p r o c e s s o r

complete MCS65E 4 system* The p r o c e s s o r e n t e r s t h i s mode through

the ch i p r e s e t f u n c t i o n or t h r o u g h s y s t e m c 311 s and t r a p s w h i c h
o c c u r in the higher level processes* W i t h i n the Kernel? the
p r o c e s s o r C3n call e i t h e r 3 h i g h e r l e vel o p e r a t i n g s y s t e m p r o c e s s
or 3 User process* T h e s e h i g h e r l e v e l s of o p e r a t i n g s y s t e m csn
c o n t i n u e to call additional processes until a User pro c e s s is
encountered* T h i s h i e r a r c h y of p r o c e s s e s is d e s c r i b e d in detail,
below *

W i t h i n t h i s s p e c i f i c a t i o n ? the t e r m s “K e r n e l p r o c e s s 1 will be u s e d
to r e f e r to p r o c e s s leve l 1 in w h i c h b o t h the K e r n e l fl a g a nd the
U s e r / S u p e r v i s o r flag 3re set* The t e r m “O p e r a t i n g S y s t e m P r o c e s s
will refer to those higher level processes in which the
Us e r / S u p e r v i s o r flag is set b ut the K e r n e l f l s g is c l e a r e d * T h i s
can be s u m m a r i z e d as f o l l o w s *

Kernel User/Supervisor
Process Flag Flag

Kernel 1 1

Operating System 0 1

User 0 0

1*3*3 Op Code

The ter in bQ p Code* r e f e r s to the f i r s t b y t e of e a c h i n s t r u c t i o n *

This byte s p e c i f i e s the o p e r a t i o n to be p e r f o r m e d (Add? S u b t r a c t ?
e t c* ) arid the f o r m a t of the instruction* However? it d o e s not
s p e c i f y the ty p e of the d a t a (Real? BCD? etc*) w h i c h is to be
m a n i p u l a t e d by the i n s t r u c t i o n *

1*3*4 Operand

The t e r m * o p e r a n d " r e f e r s to t h a t p o r t i o n of the i n s t r u c t i o n w h i c h

c o n t a i n s the i n f o r m a t i o n n e c e s s a r y to a c c e s s a s i n g l e d a t a f i e l d *
The f i r s t b y t e of the o p e r a n d s p e c i f i e s the m a n n e r in w h i c h the
desired data f i e l d is to be a c c e s s e d * S p e c i f i c a l l y ? the d a t a can
be l o c a t e d in an i n t e r n a l r e g i s t e r ? it can be in the i n s t r u c t i o n
( i mmediate data)? or it can be a c c e s s e d t h r o u g h the n o r m a l d a t a
r e f e r e n c i n g m e c h a n i s m d e s c r i b e d below*

1*3*5 Instruction

The t e r m 'instruction' r e f e r s to the c o m b i n a t i o n of O p C o d e and

Operands which are a c c e s s e d u n d e r d i r e c t c o n t r o l of the P r o c e s s
Program Counter to c a u s e a complete execution seouence to t a k e
p l a c e w i t h i n the p r o c e s s o r *

1*3*6 Descriptor

W i t h i n the M C S 6 5 E 4 a r c h i t e c t u r e ? the “d a t a d e s c r i p t o r * a c t s as the

primary means by w h i c h the p r o c e s s o r d e t e r m i n e s the f o r m a t and
l o c a t i o n of a d a t a f i e l d * The t e r m d e s c r i p t o r r e f e r s to all of the
information reauired to a c c e s s a d a t a f i e l d * The c o m p o n e n t s w h i c h

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C ******** ** Page- 15

 Final Design Specification for the M C365 E4 Microprocessor

make up 3 descriptor are*

1♦ D e s c r i p t o r H e a d e r *
2 * Address Reference Information*
3♦ A u x i l i a r y I n f o r m a t i o n *

The operation of the descriptor is described in detail in S e c t i o n 4

1*3*7 Ordinal

The t e r m ■ordinal* will be u s e d to re f e r to the three-byte

unsigned binary fields which are u s e d to s t o r e l o g i c a l addresses?
o f f s e t a d d r e s s e s ? etc* w i t h i n the M C S 6 5 E 4 a r c h i t e c t u r e *

1*3*3 Static Data? Dynamic Data

D u r i n g the discussions of process organization and execution

w i t h i n the M C S 6 5 E 4 ? the t e r m s s t a t i c d a t a and d y n a m i c d a t a wi l l be
u s e d to differentiate between process variables w h i c h r e t a i n the
same format for the life of the p r o c e s s arid those which are
c r e a t e d 3nd abolished while the p r o c e s s is b e i n g e x e c u t e d * The
most important c h a r a c t e r i s t i c of t h e s e two t y p e s of d a t a is that
the a m o u n t of m e m o r y r e q u i r e d by the s t a t i c d a t a will not c h a n g e
during execution of the p r o c e s s * D y n a m i c d at a? h o w e v e r ? c o n s i s t s
of v a r i a b l e s which c a n n o t be assigned fixed a m o u n t s of memory
during compilation of the p r o c e s s software b e c a u s e the memory
r e q u i r e m e n t s for t h e s e v a r i a b l e s wil l o n l y be k n o w n at run time*

1*3*9 Physical Address

The term “p h y s i c a l a d d r e s s * will be u s e d to s p e c i f y a p o s i t i o n in

the 16-megabyte a d d r e s s s p a c e w h i c h the M C S 6 5 E 4 can a c c e s s * T h e s e
are the a d d r e s s e s w h i c h a p p e a r on the p i n s of the p r o c e s s o r *

T h r o u g h o u t this document? the p h y s i c a l a d d r e s s is a s s u m e d to be

the ■ d e f a u l t * " Therefore? if an a d d r e s s t y p e ( p h y s i c a l ? l o g i c a l ?
et c * ) is n ot specified? it c a n be assumed to be a physical
address *

1*3*10 Logical Address

One of th e m o s t i m p o r t a n t a s p e c t s of the s t a n d - a l o n e n a t u r e of a
p r o c e s s is that all a d d r e s s i n g w i t h i n the process software is
s e l f - c o n t a i n e d and is completely independent of the physical
memory locations in which the p r o c e s s resides* All a d d r e s s e s
generated during e x e c u t i o n of the p r o c e s s s o f t w a r e are a s s u m e d to
be offsets from the address contained in the Process Base
register* For e x a m p l e ? if 3 p r o c e s s w h o s e b a s e a d d r e s s is 0 4 4 B 0 0
(HEX) w e r e to s p e c i f y an a d d r e s s of 0177 (HEX)? the p h y s i c a l
address which w o u l d be a c c e s s e d is 0 4 4 C 7 7 w h i c h is o b t a i n e d by
a d d i n g 0 1 7 7 to 0 4 4 B 0 0 *

T h i s c h a r a c t e r i s t i c of a d d r e s s i n g w i t h i n the M C S 6 5 E 4 b r i n g s u p the
c o n c e p t of the l o g i c a l a d d r e s s * In t h i s d o c u m e n t ? the ter m l o g i c a l
a d d r e s s will be u s e d to r e f e r to the p o s i t i o n of a m e m o r y l o c a t i o n
w i t h i n the address s p a c e of a process* In the a b o v e example?

*********CGNFIDENTIAL? MOS T E C H N O L O GY ?INC ** * * * * * ** * oP a g e - 16

 Final Des ign Specification for the M C S6 5E 4 Microprocessor

therefore? the l o g i c a l a d d r e s s w o u l d he 0 1 77* It s h o u l d be n o t e d

t h a t all s o f t w a r e e x e c u t i o n w i t h i n the M C 3 6 5 E 4 is p e r f o r m e d w i t h i n
the c o n t e x t of a p r o c e s s * For t h i s r e a s o n j all m e m o r y l o c a t i o n s
have both a p h y s i c a l and a l o g i c a l a d d r e s s * The P h y s i c a l a d d r e s s
r e m a i n s f i x e d by the s y s t e m l o ^ ic* H o w e v e r ? the l o g i c a l a d d r e s s of
e a c h m e m o r y l o c a t i o n is e n t i r e l y a f u n c t i o n of its p o s i t i o n w i t h i n
a process* T h i s will be i l l u s t r a t e d in the example below (See
F i d u r e 1*1)*

To a s s u r e a c c u r a c y ? t h i s d o c u m e n t wi ll u t i l i z e the p h r a s e “w i t h i n
process (process name)* w h e n e v e r a l o g i c a l a d d r e s s is s p e c i f i e d *
Als o ? a memory location which is o u t s i d e of the l i m i t s of a
p r o c e s s is a s s u m e d to h a v e no l o g i c a l a d d r e s s w i t h i n t h a t p r o c e s s ?
i* e*? t he l o g i c a l a d d r e s s is a s s u m e d not to e x i s t *

1*3*11 Page Address

There are m a n y a s p e c t s of the M C S 6 5 E 4 a r c h i t e c t u r e which assume ari

eight bit o r g a n i z a t i o n * F or e x a m p l e !

1* O p c o d e s are e i g h t b i t s wi d e *
2* The m i n i m u m a d d r e s s a b l e d a t a f i e l d is e i g h t b i t s wide*
3* O f f s e t a d d r e s s e s can be zero? e i g h t ? s i x t e e n or 24 b its*
4* B o t h the b a s e and l i m i t for a p r o c e s s are s p e c i f i e d
in 2 5 6 - b y t e i n c r e m e n t s *

As a r e s u l t ? it w i l l be u s e f u l to u t i l i z e the t e r m 'p a g e a d d r e s s '

to i d e n t i f y the l o c a t i o n of a 2 5 6 - b y t e p age * T h r o u g h o u t this
document? the P a g e A d d r e s s will be s p e c i f i e d by the u p p e r 16
address bits w i t h the low o r d e r e i d h t b i t s i d e n t i f i e d by XX* For
example? Page A d d r e s s 01E4XX i d e n t i f i e s the page whose upper
s i x t e e n a d d r e s s b i t s are 01E 4 * T h i s p a g e i n c l u d e s a d d r e s s e s 0 1 E 4 0 0
through 01E4FF*

In a d d i t i o n to the P a g e A d d r e s s ? the p h r a s e ' a d d r e s s on p a g e (page

n u m b e r or name)1 will be u s e d to s p e c i f y an e i g h t bit addr e s s
within a page* For example? a d d r e s s 0 1 E 4 3 A ca n be i d e n t i f i e d as
a d d r e s s 3A on p a g e 0 1 E 4 X X *

The t e r m 'Base P a g e ' w i l l be u s e d to r e f e r to the lowest order

page within a p r o c e s s * T h i s is the 2 5 6 - b y t e b l o c k of m e m o r y w h o s e
p a g e a d d r e s s is c o n t a i n e d in the P r o c e s s B a s e r e g i s t e r * S i m i l a r l y ?
the t e r m ' L i m i t P a g e 8 wi l l be u s e d to r e f e r to the 2 5 6 - b y t e b l o c k
of m e m o r y whose page a d d r e s s is c o n t a i n e d in the Process Limit
register* The r a n g e of a d d r e s s e s w h i c h are a v a i l a b l e to a p r o c e s s
e x t e n d s f r o m a d d r e s s 00 on the B a s e P a g e t h r o u g h a d d r e s s FF on the
L i m i t P age *

1*3*12 Offset Address? Relative Address

All d a t a a d d r e s s i n g w i t h i n the M C S 6 5 E 4 is a c c o m p l i s h e d by a d d i n g a
d i s p l a c e m e n t to a memory address* T h i s can be d i v i d e d into two
specific forms of addressing* T h e s e are Offset Addressing 3 nd
Relative Addressing* T h e s e t wo d i f f e r p r i m a r i l y in the m a n n e r in
w h i c h the m e m o r y a d d r e s s arid t he d i s p l a c e m e n t are s p e c i f i e d *

*********C0NFIDENTIAL? MOS T E C H N OL O G Y ?INC ** * * ** ** ** Page- 17

 Final D e sign Specification for the MCS 6 5E 4 Microprocessor

W i t h i n the M C S 6 5 E 4 a r c h i t e c t u r e ? the t e r m “O f f s e t A d d r e s s i n g 8 will

he u s e d to i d e n t i f y an a d d r e s s i n g o p e r a t i o n in w h i c h the o f f s e t is
s p e c i f i e d in th e i n s t r u c t i o n arid the m e m o r y ■a d d r e s s is c o n t a i n e d
in a base register* Only positive o f f s e t s are permitted whon
accessing through Offset Addressing* The b a s e r e g i s t e r can be
e i t h e r on e of the o n - c h i p p r o c e s s r e g i s t e r s (TOS? BAS? PRM? LMT)
or an y t h r e e - b y t e set of a d d r e s s e s in the B a s e Page*

To a s s u r e a c c u r a c y ? t h i s d o c u m e n t will u t i l i z e the p h r a s e “o f f s e t
from register (register name)' w h e n e v e r an O f f s e t Address is
specified* In a d d i t i o n ? w h e n e v e r an e x t e r n a l base register is
e s t a b l i s h e d in the p r o c e s s B a s e Pa se? t h i s b a s e r e g i s t e r wi l l be
i d e n t i f i e d as “EXT (n ) “ ? w h e r e n is the p a g e a d d r e s s of the s t a r t
of the base register* For e x a m p l e ? if a d d r e s s e s 1 5 - 1 7 on the
process Base P a g e are to be t r e a t e d as an e x t e r n a l b a s e r e g i s t e r ?
t h i s b a s e will be i d e n t i f i e d as E X T 15 ♦ F i n a l l y ? it wi l l be a s s u m e d
th a t a memory location w h i c h c a n n o t be accessed through a base
register has no o f f s e t address relative to t h a t register* This
wi l l be t r ue? of c o u r s e ? for any m e m o r y l o c a t i o n o u t s i d e of the
process* E v e n m o r e i m p o r t a n t ? it will a l s o be t r u e f o r all m e m o r y
l o c a t i o n s w i t h a l o w e r p h y s i c a l a d d r e s s t h a n t h a t c o n t a i n e d in the
register since n e g a t i v e o f f s e t s are not p e r m i t t e d w h i l e a c c e s s i n g
d a t a via b a s e r e g i s t e r s *

In a d d i t i o n to O f f s e t A d d r e s s i n g ? t he M C S 6 5 E 4 u t i l i z e s a s i m i l a r
addre s s i n g mode in w h i c h the m e m o r y a d d r e s s is not c o n t a i n e d in 3
base register and in which both negative and positive
d i s p l a c e m e n t s are p e r m i t t e d * T h i s is t e r m e d “R e l a t i v e A d d r e s s i n g ' *
Within Relative Addressing operations the m e m o r y a d d r e s s can be
either, the c o n t e n t s of the p r o g r a m c o u n t e r or the a d d r e s s of a
data descriptor* T h i s is d e s c r i b e d in d e t a i l in S e c t i o n 4 of t h i s
specification*

*********CQNFIDENTIAL> MOS T E C H N O LO G Y ?I N C ♦** **** *** Page- 18

 Final Desi gn Specification for the MCS65E4 Microprocessor

Operating
System Us e r
Physical Kernel Process Process Registers
Address Address Address Address
Space Space Space Space Contents Name

FFFFFF FFFFFF

0E00FF

i
1 1 0 3 0 1 FF 0 3 0 1 XX LMT
I 1 1
i 1 1
1 1 1
1 1 1
1 1 1
1 1 I
1 1 1
028000
1 1 1 1 1 1 1 I
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 I
1 I I 1 1 1 1 E
1 i 1 1 1 1 D 1
I ! 1 1 1 1 ! 1
1 1 1 1 1 C 1 1
1 1 1 1 1 1 I --------- 0 2 4 7 0 0 EXT*
i! i1 l1 oD l 1 l 1 i1
1 1 1 1 1 ! ------------------- 0235A0 T03
1
1 |I II Il lI }!
i i i i i -------------------------------0 2 3 5 9 0 F'RM
1 A i i i
1 1 i i i
i 1 i i i 001 2 0 0 EXT*
i! I1 1
1 I1 1
1
1 1 1 ----- 0 2 3 5 0 0 0235XX BAS
1 1
I| >I
l I
t i 1 * B a s e F ‘ag e A d d r e s s e s 1 0 - 1 2 a r e
l l 1 a s s u m e d to c o n t a i n 0 0 1 2 0 0 . T h i s
-“ -010000 set of m e m o r y l o c a t i o n s will be
\ t r e a t e d as an e x t e r n a l b a s e
i r e g i s t e r p o i n t i n g to p h y s i c a l
I a d d r e s s 0 2 4 7 0 0 (BAS + 0 0 1 2 0 0 ) *
000000 000000

FIGURE ♦1- Initial Configuration for Addressing Example

*********C0NFIDENTIALf MOS T E C HN O L O G Y >I N C ♦*** ****** Page - 19

 Final D esig n Specification for the MCS65E 4 Microprocessor

1♦4 Example of Addressing within the M C S 65 E 4 System

The addressing concepts outlined above can be clarified by

example* T h i s wil l be a c c o m p l i s h e d by d e s c r i b i n g the addresses
a s s ociated with a memory location w h i c h is c o n t a i n e d w i t h i n the
address space of a U s e r p r o c e s s * T h i s U s e r p r o c e s s is a s s u m e d to
have been c a l l e d by an O p e r a t i n g S y s t e m p r o c e s s and is t h e r e f o r e
at level t h r e e in the hierarchy* Any m e m o r y l o c a t i o n l o c a t e d in
this User process can be a c c e s s e d by e a c h of the l o w e r l evel
processes* Therefore? the m e m o r y l o c a t i o n b e i n g discussed below
will h a v e a single physical address? hut will have a logical
address within the K e r n e l process? w i t h i n the O p e r a t i n g System
p r o c e s s arid w i t h i n the U s e r process* In a d d i t i o n to t h e s e t h r e e
logical addresses? the m e m o r y l o c a t i o n will have a number of
Offset Addresses d u r i n g any p e r i o d t h a t the M C S 6 5 E 4 is e x e c u t i n g
one of t h e s e t h r e e p r o c e s s e s *

The d i a g r a m above i l l u s t r a t e s the memory map of am u l t i - t a s k

s y s t e m in w h i c h the t h r e e p r o c e s s e s r e s i d e * The K e r n e l is a s s u m e d
to c o v e r the entire 16-megabyte space* The Operating System
pro ce ss (which was i n v o k e d by the K e r n e l ) is l i m i t e d to the r a n g e
of a d d r e s s e s from 010000 to 0 E 0 0 F F * At the s a m e time? the U s e r
p r o c e s s is a s s u m e d to r e s i d e i n i t i a l l y w i t h i n a d d r e s s e s 0 2 3 5 0 0 to
0301FF* The m e m o r y l o c a t i o n w h i c h wi l l be e x a m i n e d i n i t i a l l y will
be 0 2 8 0 0 0 ? w h i c h is w i t h i n the r a n g e of a d d r e s s e s a l l o c a t e d to the
U s e r p r o c e s s * F i g u r e 1*1 i l l u s t r a t e s t h i s c o n f i g u r a t i o n *

As described previously? each memory location has a single

physical address* For the memory location being examined
initially? this p h y s i c a l a d d r e s s is 0 2 8 0 0 0 * In fact? s i n c e the
base of the Kernel is always at address 0 0 0 0 0 0? a memory
location's logical a d d r e s s w i t h i n the K e r n e l is the sa m e as its
physical address* W i t h i n the O p e r a t i n g S y s t e m p r o c e s s (level two
in the hierarchy) the l o g i c a l a d d r e s s of t h i s m e m o r y l o c a t i o n is
018000? w h i c h is the d i s p l a c e m e n t b e t w e e n t h e p h y s i c a l a d d r e s s of
the b a s e of the O p e r a t i n g S y s t e m p r o c e s s and the p h y s i c a l a d d r e s s
of the memory l ocation itself* At the s a m e time? this memory
l o c a t i o n h as a logical address w i t h i n the U s e r p r o c e s s * T h i s is
obtained by subtracting the physical address of t he memory
location (028000) f r o m t he p h y s i c a l a d d r e s s of the process base
( 0 2 3 5 0 0 ) * Th e r e s u l t i n g l o g i c a l a d d r e s s is 0 0 4 B 0 0 *

To a l l o w the offset addresses for t h i s memory l o c a t i o n to be

specified? it is n e c e s s a r y to f i r s t s p e c i f y the c o n t e n t s of the
registers which can be u s e d as a b a s e for a d d r e s s i n g the m e m o r y
location* T h i s w il l be i l l u s t r a t e d by a s s u m i n g the e x i s t e n c e of
two a d d r e s s i n g r e g i s t e r s ? t e r m e d the P r i m a r y B a s e R e g i s t e r arid the
T o p of Stack Register* At the s a m e time? it will be u s e f u l to
assume that a d d r e s s e s 1 0 - 1 2 w i t h i n the Base Page c o n t a i n s 001200
and will be t r e a t e d as an E x t e r n a l B a s e Register* This p r o v id e s
t h r e e i n t e r n a l r e g i s t e r s , ( i n c l u d i n g the F'rocess B a s e r e g i s t e r ) and
o ne e x t e r n a l b a s e r e g i s t e r w h i c h can be u s e d to a c c e s s data*

To i l l u s t r a t e the offset address? a s s u m e t h a t the MCS65E4 is

e x e c u t i n g t he User process? the P r i m a r y Base register (PRM)
contains 023590 and that the E x t e r n a l Base Register (logical

* * * * * * * * * C O N F I D EN TI AL ? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 20
 Final D e si gn Specification for the MC365 E 4 Microprocessor

a d d re ss e s 10-12 w i t h i n the u s e r p r o c e s s ) c o n t a i n s 0 0 1 2 0 0 * The T o p

of S t a c k Register (T0S) is i n i t i a l l y at 0235A0 ♦ Under these
conditions* the O f f s e t A d d r e s s of m e m o r y l o c a t i o n 0 2 3 0 0 0 r e l a t i v e
to P RM is 0 0 4 A 70♦ Likewise* the O f f s e t A d d r e s s to' T0S is 0 0 4 A 6 0
and the O f f s e t A d d r e s s to the E x t e r n a l 'Base is 0 0 3 9 0 0 *

Du rin d the e x e c u t i o n of the U s e r p r o c e s s s o f t w a r e * it is p o s s i b l e

to m o d i f y the c o n t e n t s of the addressing registers introduced
above* D o i n g so* of c o u r s e * m o d i f i e s the O f f s e t A d d r e s s of e a c h
memory location in the p r o c e s s r e l a t i v e to t h a t r e g i s t e r * It may
in f a c t e l i m i n a t e the O f f s e t A d d r e s s since only positive offsets
are v a l i d * T h i s can be i l l u s t r a t e d by a s s u m i n g t h a t P R M .is set at
logical address 0 0 0 0 4 0 w i t h i n the U s e r p r o c e s s * D o i n g so s e t s the
r e g i s t e r co n t e n t s to 0 2 3 5 4 0 * At t h i s p o i n t * the O f f s e t A d d r e s s of
memory location 0 2 8 0 0 0 b e c o m e s 0 0 4 A C 0 * H o w e v e r * if the PRM is set
so t h a t it p o i n t s to address 029000 (logical address 0005B00
w i t h i n the User process)* t h i s r e g i s t e r c 3 n no l o n g e r be u s e d to
access address 028000 arid therefore* this memory location no
l o n g e r has an o f f s e t to t he PRM r e g i s t e r *

It s h o u l d be n o t e d t h a t all m e m o r y l o c a t i o n s o u t s i d e the l i m i t s of
a p r o c e s s h a v e no l o g i c a l a d d r e s s e s w i t h i n t h a t p r o c e s s * L i k e w i s e ?
m e m o r y l o c a t i o n s o u t s i d e of a p r o c e s s w h i c h is b e i n g e x e c u t e d h a v e
no O f f s e t Address relative to the i n t e r n a l or external base
registers since these locations cannot be accessed by these
registers*

* * * * * * * * * C O N F I B E N T I A L * MOS T E C H N O L O G Y >INC ** * * * ** * * * Page- 21

 Fins! Design Specification for the MC S65 E 4 Microprocessor

2 ♦0 D e s c r i p t i o n of the M C S65 E4 Pin Functions

2♦1 Introduction

The initial versions of the M C S 6 5 E 4 will be available in a

s t a n d a r d 40-pin d u a l - i n - l i n e package* This is made p o s s i b l e by
m u l t i p l e x i n g the address? data and bus status i n f o r m a t i o n onto a
set of 24 Pins* The pin c o n f i g u r a t i o n is as follows*

Function t of pins

1* A d d r e s s B u s M i d d l e / A d d r e s s Bus Low
(A 9 / A 1 - A 1 6 / A 8 ) 3
2. A d d r e s s Bus H i 3 h / D a t e Bus Lo
(A 1 6 / D B 0 - A 2 3 / D B 7 ) 8
3. Bus S t a t u s / D a t a B u s H i 2 h
(I A C K / D B 8 - M I C / D B 1 5 ) 3
4. R o w A d d r e s s S t r o b e (RAS) 1
5. C o l u m n A d d r e s s S t r o b e (CAS) 1
6. C h i p p o w e r (V D D rV S S ) 9
7. O s c i 1 lat o r o
8. Bus C l o c k (B C L K ) 1
10. M e m o r y R e a d y (RDY) 1
11 ♦ I n t e r r u p t I n p u t (INT) 1
12. R e s e t (RES) 1
13 . W r i t e E n a b l e s (WEL> W E H ) 9
14. Bus E r r o r (BERR) 1
15. H o l d (HLD) 1
16. I n s t r u c t i o n I n t e r c e p t (II) 1

TOTAL 40

of these sets of pins is described in detail be l o w *

2 *2 Address Bus M i d d 1e/Address Bu s L ow (A 9 / A 1 - A 1 6 / AS )

The low o r d e r s i x t e e n a d d r e s s b i t s ( a b o v e AO) are m u l t i p l e x e d o n t o

eight pins in a m a n n e r w h i c h is c o m p a t i b l e w i t h i n d u s t r y s t a n d a r d
64-Kbit dynamic RAMS* T h e s e l i n e s e n t e r the h i g h i m p e d a n c e s t a t e
f or e x t e r n a l D MA o p e r a t i o n s (see H O L D ) *

2*3 Address Bus/Data Bus/Bus Status (A 16 / D B 0 - A 2 3 / D B 7 t

IACK/DB8-MIC/DB15)

T he h i g h order eight address bits and the b us s t a t u s b i t s are

m u l t i p l e x e d w i t h the b i - d i r e c t i o n a l d a t a bit s * D u r i n g m e m o r y w r i t e
operations* the t i m i n g fo r t h e s e s i g n a l s is the s a m e as for the
low o r d e r s i x t e e n a d d r e s s line s * For a m e m o r y read o p e r a t i o n ? the
MCS65E4 output drivers e n t e r the high impedance s t a t e and the
m e m o r y d e v i c e s p l a c e d a t a o n t o t h e s e l i n es*

The h i g h order address bits are n o r m a l l y stored in external

l a t c h e s to be u s e d as c h i p s e l e c t s for the m e m o r y and I/O d e v i c e s *
These signals are s t r o b e d by R AS as are the b u s s t a t u s bits* The
b us s t a t u s b i t s are u s e d to c o n t r o l specific functions s u c h as
i n t e r r u p t and DMA*

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C ♦* ******** Page-

 Final Design Specification for the MC 36 5 E 4 Microprocessor

B it Status Function

51 Interrupt Acknowledge ( IA C K )
52 Hold A c k n o w l e d g e ( H 0 L D A )
53 Last I n s t r u c t i o n Cycle C L I O
54 I/O Reset (IORES)
55 Pr o c e s s o r I n s t r u c t i o n Fetch (INST)
56 F'rocessor Data Fetch (DAT)
57 Ref r e s h Cycle (REF)
SS E x ternal M i c r o c o d e Fetch (MIC)

2*3*1 Interrupt Acknowledge (I A C K )

T he IACK bi t g o e s h i g h to s i g n a l the I n t e r r u p t C o n t r o l l e r t h a t it
can place the active interrupt reauest information on the low
order eight b i t s of the d a t a bus* T h i s o p e r a t i o n is d e s c r i b e d in
d e t a i l in S e c t i o n 4 * 4 * 4 * 1 3 *

2*3*2 Hold Acknowledge (HOLDA)

The H o l d A c k n o w l e d g e bit g o e s h i g h to i n d i c a t e t h a t the p r o c e s s o r

will enter the H O L D s t a t e at the end of the p r e s e n t c y c l e * D u r i n g
the H O L D state* the RAS and C AS s i g n a l s c o n t i n u e to run 3nd the
bu s s t a t u s signals are g e n e r a t e d by the processor during RAS*
However^ no d ata* a d d r e s s or w r i t e e n a b l e ( U E L * WEH) i n f o r m a t i o n
is g e n e r a t e d and the c o r r e s p o n d i n g drivers remain in the high
i m p e d a n c e s t a t e at th e a p p r o p r i a t e time*

2*3*3 Last Instruction Cycle (LIC)

The LIC bi t g o e s h i g h to i n d i c a t e t h a t the c u r r e n t c y c l e is the

last cycle of an instruction execution seauence * T h i s is u s e d in
c o n j u n c t i o n with bus a r b i t r a t i o n l o g i c in m u l t i - p r o c e s s o r s y s t e m s
to c o n t r o l a c c e s s to s h a r e d r e s o u r c e s *

2*3*4 I/O Reset ( IO RES)

T h i s bit g o e s low to cause the sy s t e m I/O d e v i c e s to be reset*

This occurs when a System Reset i n s t r u c t i o n is e x e c u t e d * C a u s i n g
t h e RES i n p u t s i g n a l to go low d o e s n ot c a u se t h i s bus s t a t u s bit
to go low* T h i s a l l o w s r e s e t t i n g the p r o c e s s o r w i t h o u t e f f e c t i n g
t he p e r i p h e r a l d e v i c e s *

2*3*5 Processor Instruction Fetch

T h i s bit g o e s h i g h to i n d i c a t e t h a t the a d d r e s s on the a d d r e s s bus

comes from the P r o c e s s o r P r o g r a m C o u n t e r arid t h a t the d a t a b e i n g
f e t c h e d f r o m m e m o r y will be p l a c e d into the i n p u t Q u e u e *

2*3*6 Processor Data Fetch

T h i s bit g o e s h i g h to i n d i c a t e t h a t th e a d d r e s s on the a d d r e s s bus

w as g e n e r a t e d as the r e s u l t of an i n s t r u c t i o n e x e c u t i o n *

2*3*7 Refresh Cycle

*********CONFIDENTIAL> MOS T E C H N O L O G Y * I N C *** ******* Page- 23

 Final Design Specification for the M CS 65E4 Microprocessor

T h i s bit does high to indicate that the current cycle is a memory

refresh cycle*

2*3*8 External Microcode Fetch

T h i s bit does h i g h to indicate that the current cycle is art

external microcode fetch cycle*

2*4 Row Address Strobe (RAS)

The Row Address Strobe is a c l o c k signal usedp r i marily to l a t c h

the m i d d l e e i d h t b i t s of the a d d r e s s into e xternallatches* These
can be d i s c r e t e TTL l a t c h e s for i n t e r f a c i n g to p e r i p h e r a l d e v i c e s
or to conventional static memories* In m o s t c a s e s ? h o w e v e r ? t h e y
will be l o c a t e d in the d y n a m i c m e m o r y d e v i c e s * In a d d i t i o n to the
m i d d l e b y t e of the a d d r e s s bus? t h i s s i g n a l i n d i c a t e s the p r e s e n c e
of v a l i d d a t a on the h i g h order address l i n e s arid on the Bus
S t a t u s l i nes* R AS wil l be held low by RBY b ut wi ll continue
running during a HOLD operation*

2*5 Column Address Strobe (CAS)

T he C o l u m n A d d r e s s S t r o b e is p r i m a r i l y used to l a t c h the c o l u m n
a d d r e s s e s (low order eight a d d r e s s b its ) into e x t e r n a l l a t c h e s *
T h i s s i g n a l is a l s o u s e d to i n d i c a t e t h a t v a l i d d a t a is p r e s e n t on
the d a t a lines during a memory write o p e r a t i o n and to e n a b l e the
memory output d r i v e r s d u r i n g a m e m o r y read o p e r a t i o n * Thi s s i g n a l
is s y n c h r o n o u s w i t h the B C L K s i g n a l * The CAS s i g n a l is h e l d low by
RDY but will c o n t i n u e r u n n i n g d u r i n g a H O L D o p e r a t i o n *

2*6 Chip Power (VDDfVSS)

T he MCS65E4 will by p o w e r e d by + 5 * 0 V o l t s DC applied between the

V DD and VS S p i n s (V DD = +5? VSS = G r o u n d ) *

2 *7 Oscillator (Osc In? Osc Out)

The 8 M hz oscillator can be c o n t r o l l e d by a auartz crystal

connected between the O s c i l l a t o r In and O s c i l l a t o r Out pin s * In
addition? the c h i p can be con t r o l l e d by an e x t e r n a l o s c i l l a t o r by
d r i v i n g the O s c i l l a t o r In pin w i t h a T T L level s a u a r e wave*

2 *8 Bus Clock (BCLK)

The Bus Clock corresponds to the n o r m a l P h a s e Two clock. in the

6502 micr o p r o c e s s o r system* S i n c e t h i s s i g n a l is a l w a y s p r e s e n t ?
it c an be u s e d to s y n c h r o n i z e t he RDY? H O L D and B E R R s i g n a l s and
to c o n t r o l data transfers between the MCS65E4 and any 6502
interface device*

2 *9 Valid Memory Address

T h i s bit goes h i g h to indicate that there is a valid memory

a d d r e s s on the a d d r e s s bus *

*********CQNFIDENTIAL? MOS T E C H N O L OG Y ?I N C ♦*** ***** * Page- 24

 Final Design Specification for the M C S6 5E 4 Microprocessor

2*10 Memory Ready (R D Y )

The M e m o r y R e a d y i n p u t can be u s e d to c o n t r o l t h e o p e r a t i o n of the

p r o c e s s o r when i nt e r f a c i n g to s l o w e r m e m o r y or p e r i p h e r a l d e v i c e s *
This signal operates in the same manner as in the 650 2
m i c r o p r o c e s s o r system with the a d d i t i o n a l c a p a b i l i t y of b e i n g a b l e
to s t o p on b o t h a rea d and a w r i t e o p e r a t i o n * T h e s e tw o o p e r a t i o n s
are described separately below* The dynamic memory refresh
operation is d i s a b l e d 3S long as R DY is held low*

2*10*1 Operation of RDY during Read Cycle

At the b e g i n n i n g of a m e m o r y read o p e r a t i o n ? the p r o c e s s o r p l a c e s

A9 -A 2 3 and the bus status information on the multiplexed
a d d r e s s / d a t a li n e s * T h i s is f o l l o w e d by RA S g o i n g low to c a u s e
this information to be latched externally* Th e a d d r e s s and bus
status information is t h e n c h a n g e d to A 1 - A 8 arid D 0 - D 15 * T h i s is
f o l l o w e d by CAS g o i n g low and B C L K g o i n g h igh*

Immediately after B C L K g o e s hig h * the RDY line can be p u l l e d low

to c a u s e the p r o c e s s o r to s t o p in its cu rr en t state* If RDY is
p u l l e d low during a m e m o r y read operation* the p r o c e s s o r s t o p s
w i t h the d a t a b us l i n e s in the h i g h i m p e d a n c e s t a t e * The RAS and
C AS s i g n a l s r e m a i n low as long as RDY r e m a i n s low* T h i s will h o l d
t he a d d r e s s in the e x t e r n a l latches allowing w h a t e v e r time is
n e c e s s a r y for th e m e m o r y o u t p u t s to b e c o m e v a l i d *

2*10*2 Operation of RDY during Write Cycle

T i m i n g f or the W r i t e c y c l e is v e r y s i m i l a r to t h a t d e s c r i b e d a b o v e
for the Read cycle* The W r i t e E n a b l e S i g n a l s (WEL* WEH) will go
low i m m e d i a t e l y a f t e r t h e b e g i n n i n g of the c y c l e ( c o i n c i d e n t w i t h
A 9 - A 16 going valid)* I m m e d i a t e l y a f t e r RAS g o e s low* the d a t a to
be w r i t t e n into m e m o r y is p l a c e d on the D B 0 - D B 1 5 lines* If R DY is
p u l l e d low d u ring this cycle* the R AS and C A S s i g n a l s r e m a i n low
arid the p r o c e s s o r o u t p u t d a t a wil l r e m a i n on the D B 0 - D B 1 5 lines*
T he W r i t e E n a b l e l i n e s w i l l go h i g h c o i n c i d e n t w i t h the t r a i l i n g
e d g e of the B C L K p u l s e d u r i n g w h i c h th e RDY l ine r e t u r n s high *

2*11 Interrupt Input (INT)

T he M C S 6 5 E 4 p r o c e s s o r can be i n t e r r u p t e d t h r o u g h the Interrupt

Input* S e t t i n g the INT Pin low c a u s e s the M C S 6 5 E 4 to e n t e r an
interrupt seouence at th e end of the c u r r e n t i n s t r u c t i o n if the
Interrupt Inhibit bit in the P r o c e s s C o n t r o l R e g i s t e r is c l e a r e d *
T he o p e r a t i o n of the i n t e r r u p t f u n c t i o n is d e s c r i b e d in d e t a i l in
S e c t i on 4 *0 *

2*12 Reset (RES)

T he p r o c e s s o r ca n be r e s e t by a p p l y i n g a low s i g n a l to t h i s input*
For p o w e r - o n reset* t h i s ca n be a c c o m p l i s h e d by c o n n e c t i n g an R - C
c i r c u i t to the R E S pin* P o s i t i v e c o n t r o l of the r e s e t f u n c t i o n in
the p e r i p h e r a l d e v i c e s can be a c c o m p l i s h e d by c o n n e c t i n g these
d e v i c e s to the I O R E S Bus S t a t u s bit* As long as the r e s e t i n p u t
s t a y s low* the p r o c e s s o r will n o t p e r f o r m any w r i t e o p e r a t i o n s *

* * * * * * * * * C O NF I DE NT IA L* MOS T E C H N O L O G Y * INC* * * * * * * * * * Page-

 Final Design Specification for the MC S 6 5E 4 Microprocessor

2*13 Write Enables (LJE L ? W E H )

The w r i t e - e n a b l e s i g n 3 1 s coritrol the d i r e c t i o n of d a t a t r a n s f e r s

betweeri the M C S 6 5 E 4 and memory*. If a w r i t e - e n a b l e lin e is h i g h
( Read)? d a t a w ill be t r 3n s f e r r e d f r o m m e m o r y to the p r o c e s s o r * If
t h i s s i g n 31 is low? d a t 3 wi l l be t r a n s f e r r e d into m e m o r y * WEL
controls writing into t he l o w e r b y t e im m e m o r y (even addresses)
while WEH controls writing into the the upper byte (odd
3dd r e s s e s )*

2*14 Bus Error

The Bus E r r o r p in can be u s e d to i n d i c a t e t h a t 3n e r r o r o c c u r r e d

d u r i n g t he previous cycle* This e r r o r C3n be the r e s u l t of a
V i r t u a l M e m o r y A d d r e s s f 3 u l t ? 3 d s t s e r r o r d e t e c t e d in an e x t e r n a l
E DC c h ip? or any o t h e r form of e r r o r * W h e n th i s o c c u r s ? the
processor immediately s u s p e n d s its c u r r e n t e x e c u t i o n s e q u e n c e and
t r a p s to the o p e r a t i n g s y s t e m * The o p e r a t i n g s y s t e m can p r o c e s s
the e r r o r and? if a p p r o p r i s t e ? can t h e n r e t u r n to the e x e c u t i o n
s e a u e n c e w h i c h was i n t e r r u p t e d *

2*15 Hold (HOLD)

The H o l d pin ca n be p u l l e d low to c 3u s e the p r o c e s s o r to 'stop and

to p l 3 c e its s d d r e s s and d a t a b u s into the h i g h i m p e d a n c e sta t e *
This is used primarily for external DMA and multiprocessor
operations* As l ong as the H O L D pin is low? the R AS and CAS
signals continue to o p e r a t e n o r m a l l y arid the p r o c e s s o r c o n t i n u e s
to p u t out the Bus Status bits* However? no a d d r e s s or d3ts
s i g n 3 1 s 3re g e n e r s t e d by the p r o c e s s o r 3nd t he c o r r e s p o n d i n g p i n s
r e m a i n in th e h i g h - i m p e d a n c e s t a t e e x c e p t as r e q u i r e d to g e n e r 3 t e
the bus status information 3nd to p e r f o r m the required refresh
operations* If the e x t e r n a l m e m o r y r e f r e s h is e n a b l e d d u r i n g the
hold state ( Hold = Low)? the H O L D A bus s t a t u s b it will r e t u r n low
p e r i o d i c s l l y to s i g n a l the external devices t h a t the processor
will p l a c e r e f r e s h a d d r e s s e s on the a d d r e s s bus

2*16 Instruction Intercept (II)

The I n s t r u c t i o n I n t e r c e p t c an be u s e d to c a n c e l th e e x e c u t i o n of
an i n s t r u c t i o n w i t h i n the M C S 6 5 E 4 * If t h i s lin e is p u l l e d low? the
current instruction execution terminates immediately* The
p r o c e s s o r then t r e a t s t he n e x t b y t e in p r o g r a m s e q u e n c e as 3n O p
C o d e snd i m m e d i 3t e 1 y e n t e r s the a p p r o p r i a t e execution sequence*
T h i s pin is u s e d p r i m a r i l y by A u x i l i a r y A r i t h m e t i c P r o c e s s o r s to
c a n c e l the e x e c u t i o n of i n t e r c e p t e d i n s t r u c t i o n s *

*********CONFIDENTIAL? MOS T E C H N O L OG Y ? I N C * * * * * * * * * * Page- 26

 Final Desig n Specification for the MC3 65 E4 Microprocessor

3*0 Internal architecture of th e MCS65E4

3 *1 I n t r o d u c t i o n

All a s p e c t s of the i n t e r n a l M C 3 6 5 E 4 a r c h i t e c t u r e are d e s i g n e d to

a c h i e v e the d e s i r e d l evel of p e r f o r m a n c e in the s m a l l e s t p o s s i b l e
c h i p size* M o s t of th e r e g i s t e r s are organized into a single
dynamic array with all data modification taking place in a
high-speed 8-bit ALU* F o u r i n t e r n a l c y c l e s are e x e c u t e d for e a c h
external (processor) cycle* T h i s r a t i o of i n t e r n a l to external
cycles combined w i t h the f a c t t h a t th e ALU is u t i l i z e d in n e a r l y
every internal c y c l e a l l o w s fu l l 2 MHz o p e r a t i o n in a p r o c e s s o r
containing a ful l 64 b y t e s of r e g i s t e r w i t h i n a c h i p s i z e u s u a l l y
a s s o c i a t e d w i t h 8 bit p r o c e s s o r s *

It s h o u l d be n o t e d t h a t the d e v i c e d e s c r i b e d b e l o w is o n l y the
first implementation of the architecture described in this
document* T h i s i m p l e m e n t a t i o n t r i e s to a c h i e v e a balance between
c h i p s i z e an d c a p a b i l i t y w i t h a s t r o n g e m p h a s i s on m i n i m i z i n g c h i p
cost* It is assumed that future implementations of this
a r c h i t e c t u t e w ill result in devices with increased capability
t h r o u g h l a r g e r c o n t r o l ROMS? t h r o u g h the i n t e g r a t i o n of a d d i t i o n a l
system functions (keyboard interface* etc*) o n t o the p r o c e s s o r *
and u l t i m a t e l y * by e x p a n d i n g the i n t e r n a l o r g a n i z a t i o n f r o m 8 to
32 bits* All of t h e s e c o n f i g u r a t i o n s will be upward compatible
w i t h the e a r l i e r d e v i c e s *

The M C S 6 5 E 4 is o r g a n i z e d into an E x e c u t i o n U n i t and an E x e c u t i o n

C o n t r o l Un i t * E a c h of the m a j o r c o m p o n e n t s which comprise these
two u n i t s is d e s c r i b e d b r i e f l y b e l o w *

3*2 Execution Unit

3*2*1 ABL/ABM Registers

Those registers which 3re associated with the m u l t i p l e x e d low

order sixteen address pins are l o c a t e d in a s i n g l e d y n a m i c a r ray*
These r e g i s t e r s are!

1* Program C o u n t e r Low and M i d d l e

2* Refresh Register
4♦ Add ress R e g i s t e r 1 Low and M i d d l e
5* Add ress Reg iste r 2 Low and M i d d l e
6* Address R e g i s t e r “7 L o w a n d M i d d 1 e

These registers sre supported by an e i g h t - b i t incrementer which

o p e r a t e s in p a r a l l e l w i t h the A LU d e s c r i b e d b e l o w *

3*2*2 Register Array

The c o m p l e t e r e g i s t e r a r r a y is c o n t a i n e d in a m a t r i x of d y n a m i c
R AM c e l l s * The t r a d i t i o n a l 3-2-2 dynamic R AM cel l has been
e x p a n d e d to a l l o w two R E A D b u s e s and o ne W R I T E bus* The r e g i s t e r
refresh operation is h a n d l e d by a combination of h a r d w a r e arid
s o f t w a r e in a m a n n e r w h i c h is t o t a l l y t r a n s p a r e n t to the user*

* * * * * * * * * C O N F ID EN TI AL * MOS T E CH N OL O GY * I N C * * ** * ** * * * Page- 27
 Final D e sign Specification for the MC S65 E 4 Microprocessor

3*2*3 Arithmetic/Logic Unit (ALU)

M o s t of the d a t a m o d i f i c a t i o n operstions t a k e p l a c e in the ALU*

This includes normal execution operations as well as m i d d l e and
h i g h o r d e r P r o g r a m C o u n t e r i n c r e m e n t i n g a nd r e g i s t e r i n c r e m e n t i n g ?
decrementing? etc* The ALU is equipped with high speed carry
l o o k - a h e a d to allow it to c o m p l e t e any operation within one
internal cycle* T h i s a l l o w s an 8 - h i t ALU to p e r f o r m m o s t of the
d a t a m a n i p u l a t i o n f u n c t i o n s r e q u i r e d by a 3 2 - b i t p r o c e s s o r *

The specific functions performed in the ALU are as follows:

1 * ‘ Da t a s h i f t i n g
2* A d d r e s s l i m i t c h e c k i n g
3* 2's c o m p l e m e n t b i n a r y a d d i t i o n and s u b t r a c t i o n
4* P a c k e d BCD a d d i t i o n ancT s u b t r a c t i o n
5* L o g i c AND
6* L o g i c OR
7* L o g i c E OR

3*2*4 Input Queue

Data which is f e t c h e d from memory under c o n t r o l of the p r o g r a m

c o u n t e r is first loaded into the input queue w h e r e it is h e l d
u n t i l it is n e e d e d by the control logic* The q u e u e is u s u a l l y
f i l l e d by 8p r e - f e t c h i n g • the n e x t i n s t r u c t i o n s e q u e n c e d u r i n g e a c h
execution*

3*2*5 ABH/DB Registers

All of the r e g i s t e r s a s s o c i a t e d w i t h the D a t a Bus arid the A d d r e s s

Bus H i g h are l o c a t e d in a s i n g l e d y namic array* This f a c i li ta te s
t he m u l t i p l e x i n g of t h e s e s i g n a l s o n t o a set of s i x t e e n p i n s as
d e s c r i b e d in S e c t i o n 2* T h e s e r e g i s t e r s are as f o l l o w s :

1* P r o g r a m C o u n t e r H i g h
2* Eiata L a t c h Low and H i g h
3* A d d r e s s R e g i s t e r 1 H i g h
4* A d d r e s s R e g i s t e r 2 H i g h
5 * Address Register 3 high

The bus status s i g n a l s are generated in the control section and

a re m u l t i p l e x e d with the a p p r o p r i a t e data bus s i g n a l s at the
b o n d i n g pad*

3*3 Execution Control Logic

3*3*1 Control Registers

All of t h e r e g i s t e r s n e e d e d to a s s u r e p r o p e r i n s t r u c t i o n e x e c u t i o n
are c o n t a i n e d in the Control Register Section* These registers
perform such operations as storing execution control flags?
selecting registers w i t h i n the r e g i s t e r a r r a y ? c o u n t i n g e x e c u t i o n
c y c l e s and a d d r e s s i n g the m i c r o c o d e a r r a y *

3*3*2 Microcode Array

* * * * * * * * * C O N F I D E N T I A L ? MOS TECHNOLOGY?INC********** Page- 2S

 Final D esign Specification for the MCS6^ E 4 Microprocessor

B o t h the microcode ROM and the N a n o c o d e ROM are l o c a t e d in a

s i n g l e a r r a y * T h i s a s s u r e s m i n i m u m c h i p s i z e s i n c e o n l y one s et of
buses* d e c o d e r / d r i v e r s * etc* is r e q u i r e d * In a d d i t i o n ? this a r r a y
is o r g a n i z e d in a m a n n e r w h i c h a l l o w s the t o t a l s i z e of the R OM to
be v a r i e d w i t h o u t a f f e c t i n g the r e m a i n d e r of the c h ip* T h i s will
a l l o w the r a p i d g e n e r a t i o n of a d d i t i o n a l v e r s i o n s of the p r o c e s s o r
which provide additional capability through expanded microcode*

*********CONFIDENTIAL> MOS T E C H N OL O G Y * INC ** * * * * * * * * F’a g e - 29

 Final Design Specification for the MCS65 E4 Microprocessor

4 ♦0 M C S 6 5 E 4 Microprocessor Software Architecture

4*1 Introduction

The p r i m a r y goal of the M C S 6 5 E 4 a r c h i t e c t u r e is to s h o r t e n the gap

between the processor hardware and the high l evel language
a r c h i t e c t u r e w h i l e at the s a m e t i m e r e t a i n i n g the g e n e r a l i t y w h i c h
wi l l a l l o w it to support a broad range of applications* In
particular? the s o f t w a r e a r c h i t e c t u r e of the M C S 6 5 E 4 e x h i b i t s the
following characterictics J

1♦ Strong m u l t i - tasking support*

2* S e p a r a t i o n b e t w e e n d a t a and p r o g r a m *
3* 1T h r e e - o p e r a n d " a d d r e s s i n g * i* e * * all d a t a o p e r a t i o n s
are m e m o r y - t o - m e m o r y *
4* D a t a s t r u c t u r e s (a r r a y * r e c o r d * etc *) d i r e c t l y
resembling high-level language practices*

4*2 MCS65E4 Internal Architecture

4*2*1 Introduction

The i n t e r n a l architecture of the MCS65E4 c o n t a i n s all of the

registers needed to support e x e c u t i o n of the instruction set
d e s c r i b e d in S e c t i o n 4*8* T h i s set of r e g i s t e r s is d i v i d e d into
those which are v i s i b l e to the p r o g r a m m e r ( h e r e a f t e r r e f e r r e d to
as the Process Registers) and 3 set of temporary data registers
w h i c h are u s e d d u r i n g i n s t r u c t i o n e x e c u t i o n * The p r o c e s s r e g i s t e r s
are as f o l l o w s !

1* P r o c e s s B a s e R e g i s t e r (BAS)
2* P r o c e s s L i m i t R e g i s t e r (LMT)
3* P r o c e s s P r o g r a m C o u n t e r (PPC)
4* P r i m a r y B a s e R e g i s t e r (PRM)
5* T o p of Stack-. R e g i s t e r (TQS)
6* P r o c e s s C o n t r o l R e g i s t e r (P C R )

It s h o u l d be n o t e d t h a t for s p e e d p u r p o s e s ? the i n t e r n a l p r o c e s s
r e g i s t e r s (PRM* TOS* LMT* and PPC) contain physical addresses
during process execution* H o w e v e r * the M C S 6 5 E 4 u s e r d o e s n o t see
these physical addresses since t h e y are converted to logical
addresses whenever the c o n t e n t s of one of t h e s e registers is
t r a n s f e r r e d into memory* T h i s is a c c o m p l i s h e d by s u b t r a c t i n g the
c o n t e n t s of the P r o c e s s B a s e R e g i s t e r (BAS) f r o m the a d d r e s s b e i n g
transferred into memory* Similarly* the logical addresses
c o n t a i n e d in m e m o r y are c o n v e r t e d to p h y s i c a l a d d r e s s e s w h e n the
i n t e r n a l p r o c e s s r e g i s t e r s are l o a d e d *

4*2*2 Process Base Register (BAS)

Th e P r o c e s s B a s e R e g i s t e r s e t s the l o w e r l i m i t of the m e m o r y s p a c e
in w h i c h the p r o c e s s m u s t e x e c u t e * T h i s m e m o r y s p a c e s t a r t s at the
first byte of the p a g e w h o s e a d d r e s s is c o n t a i n e d in BAS* i*e**
the BAS r e g i s t e r c o n t a i n s the p a g e n u m b e r of the p h y s i c a l a d d r e s s
at w h i c h the p r o c e s s starts* F or e x a m p l e * if the BAS register
c o n t a i n s 0 4 E7* the lowest address w h i c h is available to the

*********CONFIDENTIAL* MOS T E C HN O LO G Y * INC ** * * * * * * * * Page- 30

 Final Desig n Specification for the M CS65 E4 Microprocessor

process is 04E700*

4*2*3 Process Limit Register (LMT)

The P r o c e s s Limit Register s e t s the upper limit of the memory

s p a c e in which 3 p r o c e s s is to e x e c u t e * At the 33me time? it
identifies 3 page in m e m o r y w h i c h is used to s t o r e exception
v e c t o r s 3nd o t h e r i n f o r m a t i o n r e q u i r e d to c o n t r o l e x e c u t i o n of the
process* The h i g h e s t s d d r e s s 3 V 3 i l 3 b l e to a p r o c e s s is the last
b y t e of t he L i m i t P age* For e x a m p l e ? if the LMT r e g i s t e r c o n t a i n s
0D 3 4 ? the h i g h e s t a v a i l a b l e s d d r e s s in the p r o c e s s is 0 D 3 4 F F *

4*2*4 Process P r o g r 3m C o u n t e r (F’PC)

E x e c u t i o n of MCS65E4 programs proceeds under control of the

P r o c e s s P r o g r 3m Counter* The o p e r s t i o n s sssociated with this
r e g i s t e r a r e m u c h the s a m e as in any p r o g r a m m 3 b l e p r o c e s s o r *

4*2*5 Primary Base Register (PRM)

The P r i m a r y B a s e r e g i s t e r is p r o v i d e d to c o n t r o l the a c c e s s i n g of
data during instruction execution*Address offsets c o n t a i n e d in
the M C S 6 5 E 4 i n s t r u c t i o n s are a d d e d to the P RM r e g i s t e r to o b t a i n
the p h y s i c a l a d d r e s s of t h e d ats*

4*2*6 Top of Stack. Register (TOS)

T he T o p of S t a c k Register controls access to the process stack

during instruction e x e c u t i o n * The s t e c k and T o p of S t a c k R e g i s t e r
(TOS) o p e r a t e in a c o n v e n t i o n a l m a n n e r to s t o r e s u b r o u t i n e r e t u r n
addresses? s u b r o u t i n e data? interrupt return addresses? etc* In
addition? the TOS C 3 n be u s e d as 3 b 3 s e r e g i s t e r to c o n t r o l the
a c c e s s i n g of dats in m e m o r y utilizing offset, a d d r e s s i n g * This
o p e r a t e s in exactly the s a m e m a n n e r as does Offset Addressing
u s i n g th e P r i m 3 ry B 3 s e (PRM) r e g i s t e r *

4*2*7 Process Control Register (PCR)

The P r o c e s s Control Register cont3ins 3 number of flsgs 3nd

control bits which sre u s e d to control instruction execution
w i t h i n the p r o c e s s o r * The PCR r e g i s t e r b i t s aret

Bit Designstion

0 K -
K e r n e l M o d e F 1 3g
1 U - U s e r / S u p e r v i s o r Mode
9
I - I n t e r r u p t Inhibit Flag
3 E - E n e b l e Exterr»3l M e m o r y R e f r e s h
4 P - Enable Periodic Interrupt
5 S - Eneble St3ck Bound3ry Check
6 D - Debug Mode
7 T - D i s 3 b l e All T r 3p s
8-11 M - Microcode Select
12-15 R - R e f r e s h R 31e

******** C O N F I D E N T I A L ? MOS T E C H N OL O G Y ?INC* * * * * * * * * * P 3g e - 31

 Final Desi gn Specification for the M CS 65 E4 Microprocessor

4 * 2 *7 * 1 K e r n e l Mode Flag (K)

The K e r n e l state (K = 1) r e p r e s e n t s the f i r s t l evel of the

o p e r ating system* Th i s f l a g is set and c l e a r e d a u t o m a t i c a l l y as
the p r o c e s s o r m o v e s into arid o ut of the K e r n e l s t a t e *

4 ♦ 2 *7 ♦2 U s e r / S u p e r v i s o r Mode (U)

T he U s e r / S u p e r v i s o r f l a g is se t to 3 l o g i c 1 to e n a b l e e x e c u t i o n
of 3 number of privileged instructions which are normally
available only to the operating system* This flag is set
a u t o m s t i c s l l y by the R e s e t i n p u t or w h e n the p r o c e s s o r e x i t s fr o m
3 U s e r p r o c e s s * It is c l e 3 r e d w h e n a U s e r p r o c e s s is i n v o k e d *

4*2*7*3 Interrupt Inhibit Flag (I)

Th e Interrupt Inhibit Flag can be set to disable interrupts on the

INT input*

4*2*7*4 Enable External Memory Refresh (E)

The E f l a g m u s t be set to a l o g i c 1 to enable the p r o c e s s o r to

perform periodic external memory refresh o p e r a t i o n s * The i n t e r n a l
refresh logic will a s s u r e t h a t e a c h row in the d y n a m i c m e m o r i e s
w i l l be r e f r e s h e d at a r a t e d e t e r m i n e d by the p r o g r a m m a b l e R e f r e s h
Control Counter*

4*2*7*5 Enable Periodic Interrupt (P )

T he P f l a g can* be set to a* l o g i c 1* to c a u s e the p r o c e s s o r to

execute a trap each time the m e m o r y r e f r e s h logic "rolls over**
This occurs at a rate d e t e r m i n e d by the Refresh Control Counter
(typically between 2 and 4 milliseconds)* T h i s t r a p will o c c u r
whether or not the e x t e r n a l r e f r e s h o p e r a t i o n is enabled*

4*2*7*6 Enable Stack Boundary Check (S)

The S f l a g can be set to c a u s e the p r o c e s s o r to e x e c u t e a tra p

w h e n e v e r the stack crosses a P 3g e boundary during a P U S H or POP
operation* T h i s a l l o w s e i t h e r the p r o c e s s or the o p e r a t i n g s y s t e m
to v e r i f y t h a t the s t a c k will n o t o v e r - w r i t e d a t a in m e m o r y *

4*2*7*4 Debug Mode (D)

The D e b u g f l a g ca n be s et to a l l o w s i n g l e - i n s t r u c t i o n e x e c u t i o n of
3 User process* E s c h t i m e the p r o c e s s o r e n t e r s 3 U s e r p r o c e s s it
will e x e c u t e a s i n g l e i n s t r u c t i o n a nd will t h e n t r a p b a c k to the
o p erating system? a l l o w i n g the o p e r a t i n g s y s t e m to d i s p l a y the
effects of e a c h i n s t r u c t i o n e x e c u t i o n for d e b u g p u r p o s e s *

4 * 2 * 7 *8 Enable Read Before Byte Write (W)

All trsps 3re d i s a h 1 ?d if this flag is set*

4 * 2 *7 * 9 M i c r o c o d e Select (M)

*********CONFIDENTIAL? MOS T E C H N O L O G Y >INC ** * * * * * * * * Page- 32

 Final Desi gn Specification for the M C S6 5E 4 Microprocessor

These four bits directly reflect the c o n t e n t s of the internal

Microcode Select R e g i s t e r * T h i s d a t a is p l a c e d o n t o bits 1 2 - 1 5 of
t he a d d r e s s bus d u r i n g an e x t e r n a l m i c r o c o d e f e t c h *

4*2*7*10 Refresh Rate

These four bits d i r ec 1 1 y r e f l e c t the c o n t e n t s of the internal

Refresh Control R e g i s t e r * T h i s d a t a d i r e c t l y c o n t r o l s the rate at
w h i c h the M C 3 6 5 E 4 r e f r e s h e s the e x t e r n a l m e m o r i e s *

* * * * * * * * * C O N F I D E N T I A L t MOS T E C H N OL O G Y ?I N C * * ** * ** * * * Page- 33
 Final Design Specification for the MCS65E 4 Microprocessor

K e rn e 1 R e s e t V e c t o r

.i iTli t F'3g e Process Vactor'

Process Software

Process Stack

Dy n am ic
Memo ry Free Memory

Dynamic Data (Heap)

Static Data

Global Data

Base Page I
Inter-process Control*

*~ Kernel and Supervisor Process only

Figure 4*0 Suggested Process Organization in the MCS65E4 System

*********CQNFIDENTIAL> MOS T E C H N O L O G Y ?INC ** * * * * * * * * Page-

 Final Design Specification for the M CS6 5 E 4 Microprocessor

4* 3 Process Struetu re

4 .>3*1 Introduction

Those factors which in f 11 jence the o r g a n i z a t i o n of a p r o c e s s w i t h i n

t he M C S 6 5 E 4 are m u c h the s a m e as the factors which g o v e r n the
o r g a n i z a t i o n of memory w i t h i n an M C S 6502 system* T h e s e are 3 s
f o .1lows'

1* The v e c t o r s a s s o c i s t e d w i t h the p r o c e s s i n g of i n t e r r u p t s ?
s yst e m calls? etc* are l o c a t e d in the L i m i t p age? i* e*?
in high order memory* This g enerally dictates that
p r o g r a m m e m o ry be at the u p p e r l i m i t of the a d d r e s s s p a c e
a l l o c a t e d to the p r o c e s s *

2* The a v a i l a b i l i t y of s h o r t o f f s e t s f r o m the P r o c e s s B a s e
Register would s e e m to d i c t a t e t h a t R e a d / W r i t e m e m o r y be
l o c a t e d in the low order portion of the address space
a l l o c a t e d to a process* In a d d i t i o n ? the f i r s t t h r e e
b y t e s of m e m o r y w i t h i n the K e r n e l p r o c e s s arid w i t h i n any
O p e r a t i n g S y s t e m p r o c e s s m u s t be r e a d / w r i t e m e m o r y *

These factors l ead to the general process organization s h o w n in

F i g u r e 4*0* However? this process structure is by no means
mandatory* T h i s is p a r t i c u l s r l y tru e if the entire process is
l o c a t e d in read/write memory* As long as the process vectors
r e m a i n in the a d d r e s s e s outlined* it is p o s s i b l e to p l a c e the
process software a n y w h e r e in the process a dd re s s space? s u c h as
directly above the s t a t i c d a t a are3* T h i s w o u l d p l a c e the e n t i r e
d y n a m i c d a t a a r e a ( i n c l u d i n g the stack.) in h i g h o r d e r m e m o r y *

4*3.2 Inter-process Contro 1

As m e n t i o n e d above? th e f i r s t t h r e e bytes of the Kernel arid

O p e r a t i n g S y s t e m p r o c e s s e s m u s t be r e s e r v e d for use by the M C S 6 5 E 4
to c o n t r o l m o v e m e n t into arid out of the p r o c e s s * T h e s e a d d r e s s e s
m u s t be l o c a t e d in r e a d / w r i t e m e m o r y * The p r o c e s s o r wil l t r a n s f e r
d a t a into arid out of t h i s a r e s d u r i n g the s e r v i c i n g of i n t e r r u p t s ?
s y s t e m c a l l s ? etc*

The M C S 6 5 E 4 architecture does not r e q u i r e that the first three

b y t e s of the User proc es s be r e s e r v e d *

4*3*3 Global Data

The f i r s t 64 bytes of m e m o r y above the process base can be

accessed with a single byte of addressing information* In
addition? a d d r e s s e s 65 through 511 can be accessed with one
a d d i t i o n a l b y t e of o f f s e t (two b y t e s t o t a l ) * For t h i s r e a s o n ? t h i s
region should be u s e d to store those static v a r i a b l e s w h i c h are
accessed most f r e o u e n t l y *

4*3*4 Static Data

This area consists primarily of s t a t i c variables which w ill be

u t i l i z e d by the p r o c e s s software* This data should be accessed

*********C0NFIDENTIAL? MOS T E C H N O L O G Y ? I N C * * * * * **** * Page- 35

 Final Design Specification for the MC365E 4 Microprocessor

t h r o u g h the Primary Base Register or through the Process Base

R e g is te r ♦

4 v 3♦5 Dynamic M e m c ry

The d y n a m i c m e m o r y a r e a c o n s i s t s of t h r e e s e c t i o n s * T h e s e are the

dynamic data area* the f r e e m e m o r y a r e a and the p r o c e s s stack.*
E a c h of t h e s e is d i s c u s s e d s e p a r a t e l y b e l o w *

4♦3 *5♦1 D y n a mi c Data

The f i r s t s e c t i o n is the d y n a m i c d a t a a r e a in w h i c h the p r o c e s s o r

allocates memory to d y n a m i c variables during process execution*
This data can be a c c e s s e d t h r o u g h the P r i m a r y B a s e R e g i s t e r arid
t h r o u g h the external base registers* T h i s a r e a may be u s e d for a
p r o c e s s he a p ? or for the s t o r a g e of h i g h e r le v e l p r o c e s s e s c a l l e d
d u r i n g e x e c u t i o n of p r o c e s s s o f t w a r e *

4* 3 *5 *2 F r e e Memory

The fr e e m e m o r y a r e a a c t s as a b u f f e r b e t w e e n the d y n a m i c d a t a arid

the p r o c e s s stack* S i n c e the M C S 6 5 E 4 s t a c k g r o w s d o w n w a r d t o w a r d
lower-order memory? the o p t i m u m c o n f i g u r a t i o n w o u l d be t h a t in
w h i c h the d y n a m i c d a t a a r e a g r o w s u p w a r d into the fre e m e m o r y a r e a
w h i l e the stack, g r o w s d o w n w a r d * The M C S 6 5 E 4 a r c h i t e c t u r e c o n t a i n s
p r o v i s i o n for a s s u r i n g t h a t t h e s e two d a t a a r e a s do not o v e r l a p *

4 * 3 * 5 *3 P r o c e s s Stack

T r a n s f e r of d a t a into arid out of the p r o c e s s s t a c k is p e r f o r m e d

under control of the T o p of Stack Register w i t h i n the MCS65E4
processor* In the M C S 6 5 E 4 ? the T OS r e g i s t e r a l w a y s c o n t a i n s the
physical address of the last b y t e of d a t a p l a c e d o n t o the s t a c k *
Therefore? the T OS r e g i s t e r is d e c r e m e n t e d b e f o r e d a t a is p l a c e d
into the s t a c k and is i n c r e m e n t e d a f t e r e a c h t r a n s f e r of d a t a out
of the s t a c k *

4*3*6 Process Software

The p r o c e s s s o f t w a r e C3n g e n e r a l l y be v i e w e d as " s t a t i c 1 ? i*e*?

the m e m o r y r e q u i r e m e n t s w ill not c h a n g e d u r i n g the e x e c u t i o n of
the p r o c e s s * T h e r e f o r e ? t h i s s o f t w a r e s h o u l d g e n e r a l l y be l o c a t e d
o u t s i d e of the d y n a m i c m e m o r y area* As o u t l i n e d a b o v e ? M C S 6 5 E 4
architecture requires t h a t a set of p r o c e s s v e c t o r s be l o c a t e d in
f i x e d p o s i t i o n s w i t h i n the p r o c e s s a d d r e s s s p a c e * For t h i s r e a s o n ?
it will generally be more s a t i s f a c t o r y to place the process
s o f t w a r e in h i g h - o r d e r m e m o r y alorig w i t h t h e s e v e c t o r s *

4*3*7 Process Vectors

P r o c e s s i n g of interrupts? system calls? arid s y s t e m errors is

c o n t r o l l e d by a set of v e c t o r s w h i c h m u s t be l o c a t e d in the L i m i t
P a g e of the p r o c e s s *

4*3*8 Kernel Reset Vector

*********CONFIDENTIAL> MOS T E C H N O L O G Y >INC ** * * * * * * * * Page- 36

 Final Desig n Specification for the MCS65 E 4 Microprocessor

In the Kernel Process? the high order four bytes of m emory are
reserved for s t orin g the Kernel Reset Ve c t o r ♦ This is used by the
p r o c e s s o r duri ng the system reset o perati on* The Reset Ve ctor is
stored in the same format as the exception vectors*

4*4 Execution of Processes in the MCS65E 4

4 * 4 * 1 -Introduct i o n

The r e g i s t e r s d e s c r i b e d in S e c t i o n 5 * 2 * 1 are d e s i g n e d to s u p p o r t
the execution of a hierarchy of processes in a multi-task
e n v i r o n m e n t ijnder the c o n t r o 1 of a s o p h i s t i c a t e d o p e r a t i n g s y s t e m *
One of the key a s p e c t s of t h i s a r c h i t e c t u r e is s u p p o r t f r o m the
p r o c e s s o r to i n i t i a t e a n e w p r o c e s s ? to e x i t f r o m a p r o c e s s in the
e v e n t of a fault or i n t e r r u p t ? and to r e t u r n to an i n t e r r u p t e d
process* All of t h e s e i n t e r - p r o c e s s o p e r a t i o n s are d e s c r i b e d in
this s e c t i o n *

4*4*2 Basic Inter-process controls

4 * 4 *2 * 1 I n t r o d u c t i o n

The M C S 6 5 E 4 p r o v id es five primary tools for c o n t r o l l i n g movement

into and out of p r o c e s s e s * T h e y are the f o l l o w i n g ?

1* Kernel Reset Vector

2* P r ocess P a r a m e t e r List
3* Process Link
4* P o i n t e r to C u r r e n t C a l l e r
5* P r o c e s s Stack.

4♦4 *2 *2 K e r n e l Reset Vector

The h ig h order four memory locations in the Kernel process

( p h y s i c a l a d d r e s s e s F F F F F C - F F F F F F ) are r e s e r v e d for s t o r a g e of the
Reset vector*

4*4*2*3 Process Parameter List (PPL)

The Process Parameter List (PPL) contains the information

n e c e s s a r y to enter a process f o r the f i r s t tim e * The a r g u m e n t s in
this list are as f o l l o w s *

1 * List Size

This eight-bit p a r a m e t e r s p e c i f i e s th e n u m b e r of b y t e s of
data contained in the li s t (not i n c l u d i n g the L i s t S i z e
parameter)*

2* Process Base Address

T he P r o c e s s B a s e A d d r e s s p a r a m e t e r s p e c i f i e s the l o g i c a l
page address of the B a s e P a g e of the new p r o c e s s w i t h i n
the c a l l e r ' s address space*

3* Process Size

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ********** Page- 37

 Final D esign Specification for the MCS65E 4 Microprocessor

This 16 - b it p a r a m e t e r s p e c i f i e s the l o g i c a l p a g e a d d r e s s
of the L i m i t P a g e w i t h i n the new p r o c e s s ? it e *7 the p a g e
address relative to the new p r o c e s s ' s base? not to the
caller's base * T h i s d a t a is u s e d by the M C S 6 5 E 4 to load
the P r o c e s s L i m i t R e g i s t e r d u r i n g p r o c e s s i n i t i a l i z a t i o n *

4* Program En t ry Address

This 2 4 -bit parameter specifies the logical address

w i t h i n the new p r o c e s s of the e n t r y p o i n t f or the process
software* T hi s d a t a is u s e d to load the P r o c e s s P ro g ra m
Counter during process initialization*

5* PRM Initial Value

This 24-bit parameter specifies the logical address

w i t h i n the new process of the initial Primary Base
Register contents* T h i s d a t a is u s e d to load the PRM
register during process initialization*

6* TOS Initial Value

This 24-bit parameter specifies the logical address

wit hiin the new p r o c e s s of the i n i t i a l top of s t a c k * The
MCS65E4 uses t h i s d a t a to loa d the TOS register during
process initialization*

7 * Process Control Register Initial Value*

This 1 6- bit p a r a m e t e r s p e c i f i e s the i n i t i a l c o n t e n t s of

the P r o c e s s Control Register* T h i s d a t a is t r a n s f e r r e d
d i r e c t l y into the PCR d u r i n g p r o c e s s i n i t i a l i z a t i o n *

4 * 4 *2 *4 Po i rite r to Current Caller

D u r i n g the execution of any process (other than the Kernel

process) it is v e r y i m p o r t a n t t h a t th e M C S 6 5 E 4 be a b l e to e x i t
f r o m the p r o c e s s and r e t u r n to its c a l l e r * T h i s is a c c o m p l i s h e d by
utilizing physical addresses 000000 through 000002 within the
Kernel process to store the physical address of the current
caller's T o p of S t a c k * T h i s i n f o r m a t i o n will be u t i l i z e d by the
M C S 6 5 E 4 d u r i n g the p r o c e s s i n g of any e x c e p t i o n s w h i c h r e q u i r e t h a t
e x e c u t i o n of the c u r r e n t p r o c e s s be s u s p e n d e d *

A d d r e s s e s 0 0 0 0 0 0 - 0 0 0 0 0 2 w i t h i n the K e r n a l P r o c e s s are r e s e r v e d and

s h o u l d n ot be used by the K e r n e l software for general data
storage*

4 * 4 *2 *5 P r o c e s s L i nk

For O p e r a t i n g S y s t e m p r o c e s s e s it is n e c e s s a r y t h a t t he M C S 6 5 E 4 be
a b l e to e x i t to b o t h l o w e r lev el and h i g h e r level p r o c e s s e s * The
P o i n t e r to C u r r e n t C a l l e r d e s c r i b e d p r e v i o u s l y s t o r e s the p h y s i c a l
a d d r e s s of the c a l l e r ' s top of s t a c k ? a l l o w i n g a p r o c e s s to r e t u r n
to its c a l l e r at a ny t i me* H o w e v e r ? w h e n a h i g h e r level p r o c e s s is

* * * * * * * * * C G N F I D E N T I A L ? MOS T E C H N O L O GY ?INC ** * * * * * * * * Page- 38

 .rial D e sign Specification for the M CS6 5E 4 Microprocessor

invoked? it ui l l be n e c e s s a r y to s t o r e t h i s p o i n t e r in a m a n n e r
which assures t h a t it w il l be a v a i l a b l e w h e n the MCS65E4 exits
f roiTi the higher l e vel process and b e 3 in s executing the
i n t e r m e d i a t e l evel p rocess once sgain * T h i s is a c c o m p l i s h e d by
s t o r i n g 'the i n f o r m a t i o n c o n t a i n e d in the P o i n t e r to C u r r e n t Ca 11 er
into the first three bytes of the i n t e r m e d i a t e process (logical
addresses 000000 through 000002) before exiting to the higher
level p r o c e s s * T h e s e t h r e e l o g i c a l a d d r e s s e s will be r e f e r r e d to
as the P r o c e s s L i n k *

It s h o u l d be n o t e d t h a t the P r o c e s s Link, is a r e s e r v e d a r e a arid

s h o u l d n ot be u s e d by the O p e r a t i n g System Process for g e n e r a l
d a t a s t o r a g e * In a d d i t i o n * t h i s p r o c e s s link d o e s not e x i s t w i t h i n
t he U s e r process s i n c e it is i m p o s s i b l e to invoke additional
p r o c e s s e s w i t h i n the U s e r p r o c e s s *

4 ♦ 4 ♦ 2 +6 P r o c e s s Stack

Throughout the inter-process operations described below? the

process stack is u t i l i z e d for saving the internal registers when
exiting from a process*

4*4*3 Inter-process Operations

4 * 4 *3 * 1 I n t r o d u c t i o n

The m a n n e r in w h i c h e a c h of t h e s e a r c h i t e c t u r a l e l e m e n t s is u s e d
in a s y s t e m can be d e s c r i b e d m o s t effectively through a detailed
d i s c u s s i o n of the p r i m a r y i n t e r - p r o c e s s o p e r a t i o n s t h a t m u s t t a k e
place during the operation of a full scale multi-task
m i c r o c o m p u t e r * S p e c i f i c a l l y ? t h e s e o p e r a t i o n s are!

1* System Reset*
2* Invoking hig her level proce sses*
3* E x i t i n g from a p r oces s in the event of an interrupt?
system call? or bus error*
4* R e t u r n i n g to a p r o cess after an interrupt? sy stem call 7
or bus error*

4 ♦4 *3 ♦2 System Reset

When the M C S65E4 is reset? it i m m e d i a t e l y ente rs the Kernal mode

with the Base? Limit and P r ocess Control reg isters i n i t i a l i z e d as
follows!

Regis ter Initial Contents

P r o ce ss Base (BAS) Reg i s t e r 0 000XX

P r ocess Limit (LMT) Register FFFFXX

P r ocess Control Register (P C R )

Bit 0 ( K ) 1
Bit 1 ( U ) 1
Bit 2 ( I ) 0

*********C0NFIDENTIAL> MOS T E C H N O L O G Y ? I N C ** ******** Page- 39

 Final Design Specification for the MC S65E 4 Microprocessor

B it 3 ( 0
B it 4 ( P 0
B i t 5 ( S 0
B it 6 ( D 0
Bit
A.* It 7
/ \ U 0
B i t s 8 -11 ( M 0
Bits 12-15 ( R 0 (2 M S E C R e f r e s h rate)
The processor then fetches a 2 4 -bit address utilizing the
information stored in the R e s e t V e c t o r ( a d d r e s s e s F F F F F F C t h r o u g h
FFFFFFF) arid b e g i n s e x e c u t i n g the i n s t r u c t i o n s l o c a t e d at this
address* The m a n n e r in w h i c h the Reset Vector information is
u t i l i z e d to d e t e r m i n e the K e r n e l s t a r t i n g a d d r e s s is d e s c r i b e d in
P a r a g r a p h 4*7 *6*2*

4 * 4 * 3 *3 Invoking Additional Processes

H i g h e r leve l processes can be invoked either from the Kernel

p r o c e s s or f r o m an O p e r a t i n g S y s t e m p r o c e s s by e x e c u t i n g an 1 0 S or
TASK instructors The s i n g l e o p e r a n d c o n t a i n e d in the i n s t r u c t i o n
must point to the P r o c e s s P a r a m e t e r L i s t for the new p r o c e s s * The
M C S 6 5 E 4 b e g i n s e x e c u t i o n of t he IOS or T A S K i n s t r u c t i o n by p l a c i n g
t he c o n t e n t s of t he i n t e r n a l r e g i s t e r s o n t o the current process
s t a c k and t h e n e x a m i n i n g the P r o c e s s P a r a m e t e r L i s t to d e t e r m i n e
th e o p e r a t i n g p a r a m e t e r s for the new process* More specifically?
the s e q u e n c e p r o c e e d s as f o l l o w s !

1* The c o n t e n t s of the P r o c e s s r e g i s t e r s are p u s h e d o n t o the

current process s t a c k * A f t e r t h i s o p e r a t i o n ? the p r o c e s s
s t a c k c o n t a i n s the f o l l o w i n g :

M e m o ry
Location Contents

T0S+11 PCR? Bits 8-15

T 0 S + 10 PCR? Bits 0-7
TOS + 9 PRM? Bits 16-23
TOS-f-8 PRM? Bits 8-15
TO S + 7 PRM? Bits 0-7
TOS + 6 PPC? Bits 16-23
TO S + 5 PPC? Bits 8-15
T QS + 4 PPC? Bits 0-7
TOS + 3 LMT? Bits 8-15
T OS + 2 LMT? Bits 0-7
T 0S + 1 BAS? Bits 8-15
TOS BAS? Bits 0-7

2* The p r o c e s s o r t h e n f e t c h e s the c o n t e n t s of the P o i n t e r to

Current Caller (physical addresses 000000-000002) arid
places this information into th e Process L i n k of the
current process (logical addresses 0 0 0 0 0 0 - 0 0 0 0 0 2 of the
current process)*

3* The Pointer to Current Caller is then updated by

t r a n s f e r r i n g the d a t a c o n t a i n e d in the TOS r e g i s t e r into
physical addresses 000000 through 000002*

*********CQNFIDENTIAL? MOS T EC HN O L O G Y ?INC ** * * * * * * * * Page- 40

 Final Desi gn Specification for the M C S6 5E 4 Microprocessor

T h e r e are s e v e r a l i t e m s w o r t h n o t i n g in the p r e c e e d i n g o p e r a t i o n s *
T h e f i r s t is t h a t the a d d r e s s e s w h i c h are p l a c e d o n t o the c a l l e r ' s
sta ck from the i n t e r n a l p r o c e s s r e g i s t e r s are p h y s i c a l a d d r e s s e s *
No a t t e m p t is m a d e to c o n v e r t t h e s e p h y s i c a l a d d r e s s e s to l o g i c a l
addresses. In a d d i t i o n ? the p r o c e s s o r d o e s no t a 11 e m p t to f o r m a t
this data in a manner which would facilitate subsequent
manipulation through the n o r m a l p r o c e s s o r s o f t w a r e * B o t h of t h e s e
are m a d e p o s s i b l e by the b a s i c n a t u r e of p r o c e s s e x e c u t i o n wi t h i n
the M C S 6 5 E 4 architecture* In p a r t i c u l a r ? it is a s s u m e d t h a t the
limits within w h i c h the new p r o c e s s wil l e x e c u t e will not i n c l u d e
that po rtion of m e m o r y in w h i c h the c a l l e r ' s s t a c k is l o c a t e d and
t h a t it wil l not i n c l u d e the c a l l e r ' s B a s e P a g e or L i m i t P ag e*
Therefore? it wil l be i m p o s s i b l e for any h i g h e r level p r o c e s s to
access this data* S i m i l a r l y ? th e use of p h y s i c a l a d d r e s s e s on the
c a l l e r ' s s t a c k is m a d e p o s s i b l e by the f a c t t h a t the c a l l e r c a n n o t
be m o v e d w i t h i n the p h y s i c a l address space while a h i g h e r l evel
p r o c e s s is b e i n g e x e c u t e d *

A f t e r the p r e c e e d i n g o p e r a t i o n s are c o m p l e t e ? the M C S 6 5 E 4 is ready

to e n t e r the new p r o c e s s * T h i s is a c c o m p l i s h e d 3S follows*

1* T he processor first c a l c u l a t e s the p h y s i c a l a d d r e s s of

the PPL for the new p r o c e s s * T h i s is a c c o m p l i s h e d t h r o u g h
one of the n o r m a l o p e r a n d a d d r e s s i n g s e q u e n c e s d e s c r i b e d
in S e c t i o n 4*5 u t i l i z i n g the i n f o r m a t i o n c o n t a i n e d in the
instruction* This physical address is t h e n transferred
in t o o ne of the i n t e r n a l r e g i s t e r s for use during the
remainder of t h i s o p e r a t i o n *

2* The f i r s t item in the P P L s p e c i f i e s the n u m b e r of b y t e s

of d a t a w h i c h are c o n t a i n e d in the list* T h i s list l e n g t h
parameter is t r a n s f e r r e d i nto an i n t e r n a l register to
c o n t r o l t e r m i n a t i o n of the IOS or T A S K i n s t r u c t i o n *

3* The second p a r a m e t e r in th e P P L c o n t a i n s the logical

a d d r e s s of the b a s e of t he n e w p r o c e s s * T h i s is e x p r e s s e d
as a 1 6 -bit logical page a ddress w i t h i n the calling
process* The p h y s i c a l a d d r e s s of t he b a s e of the new
p r o c e s s is d e t e r m i n e d by a d d i n g t h i s d a t a to the c a l l e r ' s
physical base address* The resulting physical page
a d d r e s s is l o a d e d into the P r o c e s s B a s e r e g i s t e r *

4* The t h i r d item in the P r o c e s s P a r a m e t e r List specifies

the n u m b e r of p a g e s of m e m o r y w h i c h m u s t be a l l o c a t e d to
the p r o c e s s * T h i s i n f o r m a t i o n is a d d e d to t he Process
Base Register* T he r e s u l t i n g 1 6 - b i t p h y s i c a l p a g e a d d r e s s
is t r a n s f e r r e d into the P r o c e s s L i m i t R e g i s t e r *

5 * The f o u r t h item in the P P L s p e c i f i e s the l o g i c a l a d d r e s s

of the p r o c e s s e n t r y p o i n t ? i * e*? the 1 r e s e t v e c t o r 1 for
the p r o c e s s * This 2 4 -bit parameter is added to the
c o n t e n t s of the P r o c e s s B a s e R e g i s t e r ? i * e * to the b a s e
a d d r e s s of the new process? to d e t e r m i n e the physical
a d d r e s s of the p r o c e s s e n t r y p o i n t * T h i s p h y s i c a l a d d r e s s
is l o a d e d into the P r o c e s s P r o g r a m C o u n t e r *

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Page- 41

 F i ns 1 Design Specification for the MCS65E4 Microprocessor

Those items l i s t e d s h o v e r e p r e s e n t a m i n i m u m l e n g t h PPL* H o w e v e r ?

* t is Possible to initialize additional process registers by
e x t e n d i n g the l e n g t h of the PPL* In t his case ? the M C S 6 5 E 4 will
f e t c h a d d i t i o n a l p a r a m e t e r s in the f o l l o w i n g o r d e r t

1* The first parameter in the e x t e n d e d PPL s p e c i f i e s the

logical address of the i n i t i a l T o p of S t a c k w i t h i n the
new p r o c e s s * T h i s d a t a is added to the Process Base
Register* The r e s u l t i n g p h y s i c a l a d d r e s s is t r a n s f e r r e d
in t o the TOS r e g i s t e r *

2 * The next p a r s m e t e r in the PPL s p e c i f i e s the initial

contents of the Process C o n t ro 1 Register* This
i n f o r m a t i o n is t r a n s f e r r e d d i r e c t l y into the PCR*

3* The next parameter s p e c i f i e s the initial value of the

P r imary Base Register* T h i s is e x p r e s s e d as a 24-bit
logical address within the n ew process* Th i s d a t a is
a d d e d to the c o n t e n t s of the P r o c e s s B a s e R e g i s t e r * The
re s u i t i n g physical address is transferred into the
Pr imary Base register*

4 * 4 *3 * 4 E x c e p t i o n Processing

4 * 4 *3 *4 * 1 I n t r o d u c t i o n

Exiting from the current software occurs w h e n e v e r the MCS65E4

e n c o u n t e r s one of a n u m b e r of e x c e p t i o n s * T h e s e e x c e p t i o n s may be
the r e s u l t of 3 sign3l on one of the p r o c e s s o r ' s input pins
( i n t e r r u p t ? e t c * ) ? it may be the d i r e c t r e s u l t of p r o c e s s s o f t w a r e
( S y s t e m Ca l l instruction? D a t a A c c e s s Trap? e t c * ) ? or it may be
due to a problem in the data being processed* A ny of these
c o n d i t i o n s will c a u s e the M C S 6 5 E 4 to d i s c o n t i n u e e x e c u t i o n of the
current software and to b e g i n e x e c u t i o n of an e x c e p t i o n h a n d l e r *
Trie p r o c e d u r e s i n v o l v e d in d o i n g so are d e s c r i b e d in d e t a i l in
this section*

The M C S 6 5 E 4 e x c e p t i o n s ca n be d i v i d e d into 3 n u m b e r of c l a s s e s *
The f i r s t are t h o s e ' p r i v i l e g e d * e x c e p t i o n s w h i c h m u s t be s e r v i c e d
by the o p e r a t i n g s y s t e m (by a S u p e r v i s o r M o d e p r o c e s s ) * The s e c o n d
c o n s i s t s of t h o s e w h i c h c an be s e r v i c e d w i t h i n a U s e r p r o c e s s * In
addition? a n u m b e r of e x c e p t i o n s are r e c o g n i z e d at the en d of an
i n s t r u c t i o n e x e c u t i o n s e q u e n c e w h i l e o t h e r s m u s t be r e c o g n i z e d and
processed immediately* As s h o w n in the d i s c u s s i o n b e l o w ? e a c h of
t h e s e e x c e p t i o n g r o u p s is h a n d l e d d i f f e r e n t l y *

All e x c e p t i o n s ? r e g a r d l e s s of ty pe? 3 r e s e r v i c e d u n d e r c o n t r o l of
an e x c e p t i o n vector located in a r e s e r v e d p o r t i o n of the L i m i t
Page* W i t h i n the U s e r p r o c e s s ? h o w e v e r ? t h e r e is no p r o v i s i o n for
storing vectors for the privileged exceptions* These exceptions
are s e r v i c e d by r e t u r n i n g i m m e d i a t e l y to the c u r r e n t process's
caller* F o r t h i s r e a s o n ? the U s e r p r o c e s s v e c t o r s are a s u b s e t of
those which must be stored in the Supervisor Mode processes
(Operating System and Kernel)* All of these exceptions are
d e s c r i b e d in d e t a i l in S e c t i o n 4 * 4 * 4 * The E x c e p t i o n V e c t o r f o r m a t
a nd the m a n n e r in w h i c h the M C S 6 5 E 4 u t i l i z e s the e x c e p t i o n v e c t o r

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O GY ?INC ** * * * * * * * * Page- 42

 Final Design Specification for the MCS65E 4 Microprocessor

i n f o r m a t i o n to d e t e r m i n e the a ddress of the exception han d l e r are

d e s c r i b e d in S e c t i o n 4*7*6*

4 * 4♦3 ♦4♦2 Servicing Exceptions Within the Current Process

Many of the fault c o n d i t i o n s o c c u r i n g w ith in the MCS65E4 system

can be serviced by the currently executing process* When a
n o n - p r iv e 1 e g e d e x c e p t i o n occurs d u ring the e x e c u t i o n of a User
Pro c e s s or when any exception oc curs dur ing execution of an
O p e r a t i n g System process? the MCS 6 5 E 4 i m m e d i a t e l y checks the TRAP
bit in the a p p r o p r i a t e e x c e p t i o n vector* If this bit is a logical
zero 7 the e x c e p t i o n is serviced in the c u r r e n t process as
d e s c r i b e d in this parag raph* If the TRAP bit is a logic 1? the
p r o c e s s o r will return to the c u r r e n t c aller for s e r v i c i n g the
exce ption* (Note that all e x c e p t i o n s which occur d uring e x e c u t i o n
of the Kernel Pro c e s s must be s e r v i c e d w ithin the Kernel P r oce ss
s o ftware *) The s e q u e n c e of o p e r a t i o n s which tak.es place when an
e x c e p t i o n is serviced withi n the current process dep e n d s on
wheth er the e x c e p t i o n is reco g n i z e d at the end of each m ac h i n e
cycle or b e t ween i nstruc t i o n s * For those e x c e p t i o n s which 3re
recogriized only b e t w een i n struct ions? the s e q u e n c e p r o c e e d s as
follows!

1* The physical address c o n t a i n e d in t he P r o c e s s Program

Counter is con v e r t e d into the corresponding logical
address and is the n p u s h e d o n t o the current process
stack* The TOS R e g i s t e r is a d j u s t e d to p o i n t to t he last
b y t e of d a t a w h i c h was p u s h e d o n t o the s t a c k * A f t e r the
above sequence is c o m p l e t e ? the p r o c e s s s t a c k c o n t a i n s
the f o l l o w i n g ?

M e m o ry
Location Contents

TGS + 2 PP C 7 B i t s 16-23
TOS+1 PPC? B i t s 8-15
TOS PPC? B i t s 0-7

2* The M C S 6 5 E 4 then loads the p h y s i c a l address of the

exception servicing software into the Process Program
C o u n t e r * T h i s a d d r e s s is d e t e r m i n e d by a d d i n g the l o g i c a l
address referenced by the exception vector to the
c o n t e n t s of the P r o c e s s B a s e R e g i s t e r * The p r o c e s s o r t h e n
b e g i n s e x e c u t i n g the s o f t w a r e at t h i s a d d r e s s *

After servicing of the e x c e p t i o n is c o m p l e t e ? the p r o c e s s o r can

r e t u r n to the p r o c e s s s o f t w a r e at the p o i n t w h e r e the e x c e p t i o n
o c c u r r e d by e x e c u t i n g a R e t u r n F r o m S u b r o u t i n e (RTS) i n s t r u c t i o n *
This t r a n sf e rs data from the process stack into the Process
Program Counter? a d j u s t i n g the T OS R e g i s t e r to p o i n t to the last
v a l i d b y t e of d a t a in the s t a c k *

For t h o s e exceptions which m u s t be r e c o g n i z e d at the end of a

p r o c e s s o r c y c l e r a t h e r t h a n at the end of the c u r r e n t i n s t r u c t i o n ?
the p r o c e s s i n g sequence is much more complex than that Just

* * * * * * * * * C Q N F I D E N T I A L ? MOS T E C H N O L O G Y ?INC ** * * * * * * * * P 3g e - 43
 F i n a 1 De sign Specif i Cot i on for the MCS6 5E 4 Microprocessor

d e s c r i b e d * T h i s is c a u s e d by the f a c t t h a t it wil l be n e c e s s a r y to
r e t u r n to the m i d d l e of an i n s t r u c t i o n e x e c u t i o n sequence after
exception processing is c o m p l e t e * T h i s is a c c o m p l i s h e d by p 1a c i n g
the c o n t e n t s of all of the internal registers o n t o the stack?
i n c l u d i n g all of the P r o c e s s r e g i s t e r s ( e x c e p t the P r o c e s s Base
R e g i s t e r and the P r o c e s s Limit Register)? all of the t e m p o r a r y
data registers used d uring i ns t r u c t i o n e x e c u t i o n and all of the
various latches? registers? etc* w h i c h c o n t r o l the i n s t r u c t i o n
execution sequences* This sequence of operations proceeds as
followst

1* The M C3 65E 4 first places t he con t e n t s of the Process

Registers? the t e m p o r a r y d a t a registers? 3nd the rriisc*
execution control registers? latches? etc* o n t o the
stack.* The p r o c e s s o r d o e s n ot a t t e m p t to o r g a n i z e this
d a t a in a mariner w h i c h will f a c i l i t a t e p r o c e s s i n g of t h i s
information by the exception handler* After this
o p e r a t i o n is complete? the p r o c e s s s t a c k c o n t a i n s the
following*

Memory
Location C on ten ts

TQS+59 Temporary Operand Register

TOS+58
TOS + 57
TOS+56
TOS+55 Temporary Operand Register 7
TOS+54
TOS+53
TOS+52
TOS+51 Temporary Operand Register 6
T0S+50•
TGS+49
TQS+48
TOS + 47 Temporary Operand Register 5
TOS+46
TOS+45
TOS+44
TOS+43 Temporary Operand Register 4
TOS+42
TOS+41
T0S+40
TOS+39 Temporary O p e r a rid R e g i s t e r 3
TOS+38
TQS+37
TOS+36
TOS+35 Temporary Operand Register 2
TOS+34
TOS + 33
TOS+32
TOS+31 Temporary Operand Register 1
T0S+30
TOS + 29
TOS+28
TQS+27 Temporary Address Registers

* * * * * * * * * C O NF ID EN TI AL ? MOS T E C H N O L O GY ?INC ** * * * * * * * * Page- 44

 Final Desig n Specification for the M C S 65 E4 Microprocessor

TOS+26
TOS + 25
TOS+24
TGS+23
TOS+22
TOS+21
T0S+20
TOS+1?
TOS+18 P RM y B i t s 1 6 - 2 3
TOS+17 * ? Bits 8-15
TOS+16 Bi t s 0-7
TOS+15 PPC; B i t s 1 6 - 2 3
TOS+14 1 t Bits 8-15
TQS+13 1 ? B i t s 0-7
TOS+12 Literal Register
TOS+11
T0S+10 Internal Control Registers
TOS + 9
TOS + 8
TOS + 7
TOS + 6
TOS + 5
TOS + 4
TOS + 3 Data Input Latch? Bits 8-15
TOS + 2 > B i t s 0-7
TOS + 1 Data O u t p u t Latch? Bits 8-15
TOS ? Bits 0-7

2♦ T he MCS65E4 t h e n l o a d s the physical address of the

e x c e p t i o n s e r v i c i n g sof t w a r e i nto the P r o c e s s F‘rograiTi
C o u n t e r * T h i s a d d r e s s is d e t e r m i n e d by a d d i n g the l o g i c a l
address r e f e r e n c e d by the exception vector to the
c o n t e n t s of the P r o c e s s B a s e R e g i s t e r * The p r o c e s s o r t h e n
b e g i n s e x e c u t i n g the s o f t w a r e at t h i s a d d r e s s *

After servicing of the e x c e p t i o n is c o m p l e t e ? the p r o c e s s o r can

r e t u r n to the p r o c e s s s o f t w a r e at the p o i n t w h e r e the e x c e p t i o n
o c c u r r e d by executing a Return From E x c e p t i o n (RTE) i n s t r u c t i o n *
This transfers all of t he d a t a p r e v i o u s l y p l a c e d o n t o t he p r o c e s s
stack back into the appropriate processor registers* The TOS
R e g i s t e r is t h e n a d j u s t e d to p o i n t to the last v a l i d b y t e of d a t a
in the s t a c k * The M C S 6 5 E 4 t h e n b e g i n s e x e c u t i o n of the i n s t r u c t i o n
s e q u e n c e s w h i c h had b e e n i n t e r r u p t e d by the e x c e p t i o n *

4*4*3.4*3 Servicing Exceptions Within the Current Caller

If the TRAP bit is set w i t h i n the e xception vector? or if a

privileged exception occurs within a User Process? the M C S 6 5 E 4
must exit from the c u r r e n t p r o c e s s and return to the current
process's caller to service the exception* This seq ue nc e of
o p e r a t i o n s is much more c o m p l e x than that d e s c r i b e d above b e c a u s e
of the n e e d to p u s h the c o n t e n t s of all of the p r o c e s s r e g i s t e r s
o n t o the stack, to a l l o w a r e t u r n to the p r o c e s s at a l a t e r time*
Th e s e q u e n c e of o p e r a t i o n s w h i c h tak es p l a c e d e p e n d s p r i m a r i l y on
w h e t h e r the e x c e p t i o n was r e c o g n i z e d at the end of an i n s t r u c t i o n

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 Final Eie s i g n S p e c i f i c a t i o n for the MCS65 E 4 Microprocessor

e x e c u t i o n or during an instruction* In t he l a t t e r case? the

p r o c e s s o r will b e g i n the e x c e p t i o n p r o c e s s i n g by f i r s t p l a c i n g the
c o n t e n t s of all of the i n t e r n a l r e g i s t e r s in e x a c t l y the same
s e q u e n c e as described above (Paragraph 4*4*3*4*2)* After this
o p © r a t i o n is c o m p l e t e ? the r e m a i n d e r of the P r o c e s s R e g i s t e r s are
placed onto the s t a c k in a m a n n e r w h i c h is c o m p a t i b l e w i t h the
P r o c e s s P a r a m e t e r L i s t d e s c r i b e d a b o v e * T h i s a l l o w s the M C S 6 5 E 4 to
r e t u r n to the p r o c e s s at a l a t e r t i m e u t i l i z i n g the s a m e IOS or
T A S K i n s t r u c t i o n w h i c h was u s e d to e n t e r the p r o c e s s i n i t i a l l y *

After this s e q u e n c e of o p e r a t i o n s is c o m p l e t e ? the p r o c e s s o r is

r e a d y to exit f r o m the process and to return to the current
c a l l e r * T h i s is a c c o m p l i s h e d as f o l l o w s !

1* The p r o c e s s o r f i r s t f e t c h e s the a d d r e s s of the c u r r e n t

caller's top of stack from absolute addresses
0 0 0 0 0 0 - 0 0 0 0 0 2 * This is p l a c e d int o the TOS R e g i s t e r *

2* If the p r o c e s s o r is r e t u r n i n g to an O p e r a t i n g S y s t e m
process? the d a t a in the P r o c e s s L i n k is t h e n m o v e d into
the P o i n t e r to C u r r e n t C a l l e r *

3* The P r o c e s s o r n e x t t r a n s f e r s the d a t a f r o m the c a l l e r ' s

s t a c k into the i n t e r n a l process registers* This allows
the p r o c e s s o r to b e g i n e x e c u t i n g the c a l l e r ' s e x c e p t i o n
servicing software*

4* B e f o r e e x e c u t i n g the e x c e p t i o n h a n d l e r w i t h i n the c a l l e r ?
the p r o c e s s o r first p u s h e s the information which will
allow returning to th e p r o c e s s w h i c h was i n t e r r u p t e d by
the e x c e p t i o n * T h i s is a c c o m p l i s h e d by f i r s t c a l c u l a t i n g
the l o g i c a l a d d r e s s w i t h i n the c a l l e r of the T o p of S t a c k
for the i n t e r r u p t e d p r o c e s s by s u b t r a c t i n g the p h y s i c a l
a d d r e s s of the C a l l e r ' s b a s e f r o m the p h y s i c a l a d d r e s s of
the T o p of S t a c k for the h i g h e r level process* This
i n f o r m a t i o n is t h e n p u s h e d o n t o the c a l l e r ' s s t a c k *

5* If t h e r e are any except ion quali f i e r s a s s ocia ted with the

exception? this information is then pushed onto the
c a l l er ' s stack*

6 * The p r o c e s s o r t h e n f e t c h e s the a p p r o p r i a t e e x c e p t i o n
v ector from the L i m i t P a g e of the c a l l e r * The l o g i c a l
a d d r e s s r e f e r e n c e d by t h i s v e c t o r is t r a n s f e r r e d int o the
Process Program Counter* The MCS65E4 then begins
e x e c u t i n g the s o f t w a r e l o c a t e d at t h i s a d d r e s s *

4*4 *3 * 5 R e t u r n i n g to a process after an interrupt? system call?

or bus e r r o r *

The p r o c e d u r e s w h i c h a l l o w r e t u r n i n g to a p r o c e s s w h i c h h ad b e e n
s u s p e n d e d by the o c c u r r a n c e of an e x c e p t i o n a r e e x a c t l y the sam e
as t h o s e w h i c h are u t i l i z e d for e n t e r i n g the p r o c e s s for the f i r s t
t i me * T h i s is m a d e p o s s i b l e by the f a c t t h a t the p r o c e s s o r c r e a t e d
a Process P a rameter List on t he s t a c k of the suspended process
before exiting* W h e n r e t u r n i n g to the p r o c e s s ? the s i n g l e o p e r a n d

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 Final Design Specification for the MCS 65 E4 Microprocessor

in the IOS or T A S K i n s t r u c t i o n must r e f e r e n c e this PPL* T h i s is

f a c i l i t a t e d by the f a c t tha t the l o g i c a l address of thi s PPL
w i t h i n the c a l l e r had b e e n p l a c e d o n t o the c a l l e r ' s stack* This
logical address can be a c c e s s e d by r e f e r e n c i n g the T o p of S t a c k
w i t h i n the T A S K or IOS i n s t r u c t i o n * N o t e t h a t the a m o u n t of d a t a
w h i c h m u s t be t r a n s f e r r e d into the i n t e r n a l p r o c e s s o r r e g i s t e r s is
c o n t r o l l e d by the L i s t L e n g t h p a r a m e t e r w h i c h was p l a c e d on the
s t a c k last* T h i s a l l o w s the s a m e p r o c e d u r e s for r e t u r n i n g to the
process whether the e x c e p t i o n was r e c o g n i z e d a f t e r an i n s t r u c t i o n
e x e c u t i o n s e q u e n c e or in the m i d d l e of an i n s t r u c t i o n *

4*4*4 Exception Vectors within the M C S 6 5 E 4 Process*

4 *4 *4 *1 I n t r o d u c t i o n

The Exceptions Vectors a nd their location within the limit page

are as f o 11o w s I

Non-privileged Exceptions Add ress

1 Un d e f i n e d O p Code
* F8-FB
Ur;defined d a t a ty p e F4-F7
Subscript out-of-limits F0-F3
4 * O p e r a t o r arid O p e r a n d no t compatible EC-EF
r
r
U * Overflow E8-EB
6* Other arithmetic error (divide by zero; etc* E4-E7
7* N o n - c o n f o r m a b l e data types E0-E3
8* In st r u c t i o n Acce ss Trap DC-DF
? * Data A c c e s s Trap D8-DB
10 * Stack P3ge B o u nd a ry Trap D4-D7

Privileged Exceptions Address

I n t e r r u p t R e q u e s t ( IRQ) D0-D3
S y s t e m Call CC-CF
S y s t e m Call w i t h m e s s a g e C3-CB
4 * C h a n n e l Trap; C h a n n e l A C4-C7
5* C h a n n e l Trap; C h a n n e l B C0-C3
6* B us E r r o r BC-BF
7* A c c e s s o u t - o f - l i m i t B8-BB
3* D e b u g T r a p B4-B7

E a c h of t h e s e is d e s c r i b e d in d e t a i l b e l o w * N o t e t h a t w i t h i n the
U s e r p r o c e s s ; a d d r e s s e s D4 t h r o u g h FB are r e s e r v e d for the s t o r a g e
of e x c e p t i o n vectors* A d d r e s s e s B4 t h r o u g h It3 are a v a i l a b l e for
general data s t o r a g e * In the S u p e r v i s o r M o d e p r o c e s s e s ; a d d r e s s e s
A8 t h r o u g h FB a re r e s e r v e d arid s h o u l d not be u s e d for g e n e r a l d a t a
storage* A d d r e s s e s FC through FF are u s e d within the Kernel
p r o c e s s to s t o r e t he K e r n e l R e s e t Vector* Addresses FC-FF cannot
be u s e d for g e n e r a l d a t a s t o r a g e in e i t h e r the S u p e r v i s o r or U s e r
Modes ♦

The e x c e p t i o n v e c t o r s a re 2 4 - b i t p o i n t e r s s t o r e d in m e m o r y in a
format which is c o m p a t i b l e w i t h the d a t a d e s c r i p t o r d e s c r i b e d in
S e c t i o n 4*7* W i t h i n the e x c e p t i o n v e c t o r d e s c r i p t o r h e a d e r ; the
T R A P bit is u s e d to i n d i c a t e w h e n the e x c e p t i o n is to be s e r v i c e d

* * * * * * * * * C 0 N F I D E N T I A L ; MOS T E C H N OL O G Y ?I N C * * * ** * ** * * P ag e- 47
 Final Desi gn Specification for the MCS65E 4 Microprocessor

in the c u r r e n t p r o c e s s * If t h i s bit is a l o g i c zero? the v e c t o r is

a s s u m e d to r e f e r e n c e a l o g i c a l a d d r e s s w i t h i n the c u r r e n t p r o c e s s *
The f o r m s t of the E x c e p t i o n V e c t o r s and the m a n n e r in w h i c h the
the M C S 6 5 E 4 u t i l i z e s the i n f o r m a t i o n in the E x c e p t i o n V e c t o r to
d e t e r m i n e the a d d r e s s of the e x c e p t i o n h a n d l e r are d e s c r i b e d in
S ec t i on 4 * 7 * 6 *

4 * 4 ♦ 4 *2 U n d e f i n e d Op Code Trap

The M C S 6 5 E 4 will trap thro u g h this ve c t o r w h e n e v e r it e n c o u n t e r s

an O p C o d e w h i c h is not s u p p o r t e d in the s t a n d a r d i n s t r u c t i o n set*
This allows the p r o c e s s to e i t h e r a b o r t or to i n t e r p r e t the O p
C o d e t h r o u g h the e x c e p t i o n p r o c e s s i n g s o f t w a r e *

4*4*4*3 Undefined Data Type Trap

The M C S 6 5 E 4 will trap through this v ector w h e n it encounters a

data type w h i c h is n ot s u p p o r t e d in the s t a n d a r d i n s t r u c t i o n sat*
This allows the p r o c e s s to a b o r t or to i n t e r p r e t the data type
i n f o r m a t i o n in the e x c e p t i o n p r o c e s s i n g s o f t w a r e *

4 * 4 *4 *4 S u b s c r i p t out-of-limits Trap

The M C S 6 5 E 4 will trap through this vector when the software

a t t e m p t s to a c c e s s a s t r u c t u r e or a r r a y w i t h a s u b s c r i p t w h i c h is
out of the limits specified in the d a t a d e s c r i p t o r (see S e c t i o n
4 * 7 * 4 *3 ) *

4*4*4*5 Operator and Operand not Compatible

T he M C S 6 5 E 4 will trap through this vector when the software

a t t e m p t s to p e r f o r m an o p e r a t i o n on a data field which is not
compa t i b l e with the o p e r a t i o n * T h i s a l l o w s the p r o c e s s to e i t h e r
a b o r t or to i n t e r p r e t the o p e r a t i o n in the exception servicing
software*

4*4*4*6 Overflow

The M C S 6 5 E 4 will trap th rough this vector when an arithmetic

overflow is encountered during execution of an arithmetic
instruction*

4♦4 *4 *7 O t h e r arithmetic error (divide by zer o? etc*)

The M C S 6 5 E 4 wil l t r a p t h r o u g h t h i s v e c t o r w h e n it e n c o u n t e r s any

arithmetic error other than overflow* Specifica lly? these errors
ar e the f o l l o w i n g *

1* Divide-by-zero*
2* S a u a r e ro ot of n e g a t i v e number*

4*4>4*3 Non-conformable data types

The M C S 6 5 E 4 will t ra p t h r o u g h this ve c t o r when the software

a t t e m p t s to p e r f o r m an o p e r a t i o n on two i n c o m p a t i b l e d a t a f i e l d s *
This allows the p r o c e s s to a b o r t or to p e r f o r m an automatic

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O LO G Y >INC ** * * * * * * * * Page- 43

 Final D esign Specification for the MC365E 4 Microprocessor

co n v e r s i o n of one of the operands*

4 ♦ 4 * 4 *9 In s t r u c t i o n Access Trap

The M C S 6 5 E 4 will t r a p t h r o u g h t h i s v e c t o r w h e n it begins execution

of an i n s t r u c t i o n in w h i c h the TRAF' b it is set*

4*4*4*10 D ata Access Trap

The M C S 6 5 E 4 will t r a p through this v e ct or when it encounters a

d e s c r i p t o r w i t h the T R A P bit set to a I o d i c 1♦

4*4*4*11 Process Stack. Fade Boundary Trap

The M C S 6 5 E 4 wi ll t r a p t h r o u d h this vector when the T o p - o f - S t a c k

Redister crosses a pade boundary durind a P u s h or P op o p e r a t i o n *
T h i s a l l o w s the p r o c e s s or the o p e r a t i n d s y s t e m to v e r i f y t h a t the
process stack has n ot o v e r - w r i t t e n o t h e r d a t a in the d y n a m i c d a t a
area *

4*4*4*12 Debud Trap

The h C S 6 5 E 4 traps throudh this v e c t o r w h e n e v e r it e n t e r s a Use r

p r o c e s s w i t h the Debud f l a d set* This except ion can only be
s e r v i c e d in a S u p e r v i s o r M o d e p r o c e s s *

4*4*4*13 Interrupt Input (INT)

The M C S 6 5 E 4 will t r a p t h r o u d h t h i s vector when t he Interrupt Input

d o e s low d u r i n d p r o c e s s e x e c u t i o n *

4*4*4*14 System Call

The M C S 6 5 E 4 will t r a p t h r o u d h t h i s v e c t o r w h e n it encounters an SC

i n s t r u c t i o n d u r i n d the e x e c u t i o n af a p r o c e s s *

4*4*4*15 System C al l with Hessade

Th e MCS65E4 will t r a p t h r o u d h this v e c t o r when it encounters an

SC M i n s t r u c t i o n d u r i n d the e x e c u t i o n af a p r o c e s s *

4*4*4*16 Bus Error

The M C S 6 5 E 4 will t r a p t h r o u d h t h i s v e c t o r w h e n the Bu s E r r o r i n p u t

s ignal does low d u r i n d instruction execution* T h i s o p e r a t i o n is
d e s c r i b e d in d e t a i l in F'aradraph 4 * 4 * 3 * 4 * 2 *

4*4*4*17 Access out-of-limit

The M C S 6 5 E 4 w il l trap throudh this vector when the processor

s o f t w a r e a t t e m p t s to a c c e s s a P h y s i c a l a d d r e s s w h i c h is o u t s i d e of
the l i m i t s s p e c i f i e d by the P r o c e s s B a s e R e d i s t e r and the P r o c e s s
L i m i t R e d i s t e r ; i * e * > a b o v e a d d r e s s FF in the L i m i t p a d e or b e l o w
a d d r e s s 00 on the B a s e Pade*

4*5 A d d r e s s i n g within the MC365E4

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 Final Design Specification for the M CS65E4 M i cr o p r o c e s s o r

4*5*1 Introduction

T h e r e are three primary l o c a t i o n s in which data can be stored

w i t h i n the MCS65E4 architecture* These are t

1* In the i n t e r n a l p r o c e s s o r r e g i s t e r s *
2* In the i n s t r u c t i o n s w h i c h f o r m the p r o c e s s s o f t w a r e *
3* In the d a t a s t o r a g e a r e a of the p r o c e s s a d d r e s s s p ace*

The M C S 6 5 E 4 o p e r a n d s t r u c t u r e c o n t a i n s p r o v i s i o n s for r e f e r e n c i n g
d a t a in e a c h of t h e s e l o c a t i o n s * R e f e r e n c i n g d a t a in the i n t e r n a l
r e g i s t e r s is a c c o m p l i s h e d by s p e c i f y i n g the r e g i s t e r in the f i r s t
b y t e of the o p e r a n d * I m m e d i a t e d a t a cart be s p e c i f i e d e i t h e r in the
first byte of the o p e r a n d ( s h o r t f o r m i m m e d i a t e a d d r e s s i n g ) or in
t he o p e r a n d e x t e n s i o n b y t e s (lo n g f o r m i m m e d i a t e a d d r e s s i n g ) * All
other data r e f e r e n c e s are a c c o m p l i s h e d by a d d i n g the v a l u e of an
offset contained in the i n s t r u c t i o n to the c o n t e n t s of a base
register* This base register c 3 n be e i t h e r o n e of the i n t e r n a l
r e g i s t e r s or any three-byte location in th e Base P 3 g e of the
process*

The most important advantages 3ssoci3ted with the use of b 3 se

r e gister s to control the 3 c c e s s i n g of dsta is that it ss sures
compl ete r e l o c a t i b i l i t y for both the p r o c e s s and for the d a t 3
w i thin a p r o c e s s andr in a ddition* it f a c i l i t a t e s the c r e a t i o n and
m a n i p u l a t i o n of dy n a m i c dat3* This r e c o g n i z e s that most s o f t w a r e
routines m a n i p u l a t e a re l a t i v e l y small a mount of d a t 3 * Very seldom
does 3 progrsiTi find it n e c e s s e r y to access the entire 24 -bit
sddress s P 3 c e while m a n i p u l a t i n g d a 1 3 * For this resson? it should
be po s s i b l e to eccess most of the data with one or two bytes of
offset instead of the three, bytes which would be n e c e s s a r y if
co n v e n t i o n a l absolute addressing were the only . 3 V3il3 ble
a d d r e s s i n g mode* U t i l i z i n g the base r e g is ters w ithi n the M C S 6 5 E 4
in an e f f e c t i v e manner c 3 n result in 3 s i g n i f i c s n t reduc tion in
the t o 1 3 1 p ro g r s m s t o r 3 g e r e q u i r e m e n t s by red ucing the smount of
a d d r e s s i n g i n f o r m a t i o n which must be prov ided*

The first byte of each operand specifies the following!

1* T he internal register which contains the data (register

addressing*)

2* The v a l u e of the immediate dat3 (Short Form Immediate

Addressing) *

3* The n u m b e r of e x t e n s i o n b y t e s of immediste d31a which

fo l l o w (Long Form I m m e d i s t e A d d r e s s i n g ) *

4* The base register to be used (inter r»3l or exter nel)*

5* The offset between the b a s e 3 nd the desired data (S h o r t

Form Offset Addressing)*

6* The n u m b e r of b y t e s of offset which follow ( Long Form

Offset Addressing)*

*********CONFIDENTIAL> MOS T E C H N O L O G Y 7 INC ** * * * * * * * * P3g e- 50

 Final Design Specification for the MC S65E 4 Microprocessor

7* The Variable Access Mode (Byte? Two-byte Integer?

Ordinal; or data field defined by a d e s c r i p t o r ) *

The d a t a c o n t a i n e d in the f i r s t b y t e of the O p e r a rid ( h e r e a f t e r

r e f e r r e d to as the ’O p e r a rid Co nt rol B y t e " ) c an be o r g a n i z e d into a
n u m b e r of f i e l d s arid s ub - f i e l d s * T h i s o r g a n i z a t i o n is s u m m a r i z e d
in F i g u r e '4*1 b e l o w * E a c h of the d i v i s i o n s in t h i s f i g u r e are
d e s c r i b e d in d e t a i l in s u b s e q u e n t p a r a g r a p h s of S e c t i o n 4*

*********CQNFIDENTIAL> MOS T E C H N O LO G Y >I N C ♦ *** **** ** F'a g e - 51

 Final Design Specification for the MCS 65 E4 Microprocessor

BIT

1 7 6 5 4 3 2 1 0 1 R e m a rk s

1 1 N u m b e r of I Base f Data P r i itia r y

1 0 0 1 E x t e n s ion i Register i Access Addressing
1 ! Bytes 1 Select 1 Format Group

I 1 1 Addressingl Auxiliary Secoridary

1 0 1 I 0 0 1 Mode I Data Addressing
I 1 1 Select 1 Field Group

1 1 1 Internal
I 0 1 1 0 1 1 Register Register
I 1 Addressing

i 1 i I iti m e d i a t e
1 0 1 1 1 1 Immediate Data Data
1 I 1 Short Form

1 1 BAS O f f s e t
1 1 0 1 Offset from BAS Addressing
1 1 Short Form

1 1 PR M O f f s e t
1 1 1 1 0ffset from P RM Addressing
1 I Short Form

Figure 4 ♦1 ♦ O r g a n i z a t i o n of Operand Control Byte

*********CGNFIDENTIAL> MOS T E C H N OL O G Y tINC *** **** *** P ag e -

 Final Design Specification for the MCS65E4 Microprocessor

4*5*2 Primary Addressing Group

4 * 5 * 2♦1 Introduction

The Process B a s e R e g i s t e r (BAS)? P r i m a r y B a s e R e g i s t e r (PRM); arid

Top of Stack. R e g i s t e r (TOS) are the p r i n c i p a l a d d r e s s i n g r e g i s t e r s
w i t h i n the MCS65E4* In a d d i t i o n ? any t h r e e c o n s e c u t i v e b y t e s of
memory within the p r o c e s s B a s e P a g e can s e r v e as a b a s e r e g i s t e r
during data accessing operations* For this reason? the O p e r a n d
Control Byte is o r g a n i z e d in a m a n n e r w h i c h a s s u r e s t h a t e a c h of
t h e s e r eg i s t e rs c an be u s e d with maximum effectiveness during
process execution* T h i s is accomplished through the primary
addressing group arid by p r o v i d i n g short form a d d r e s s i n g for the
B AS arid P RM r e g i s t e r s * T h i s s h o r t f o r m a d d r e s s i n g is d e s c r i b e d in
•s u b s e q u e n t p a r a g r a p h s of S e c t i o n 5*6* L o n g f o r m a d d r e s s i n g for
these internal and e x t e r n a l b a s e r e g i s t e r s is d e s c r i b e d in t h i s
paragraph *

The a d d r e s s i n g i n f o r m a t i o n p r o v i d e d in t h i s g r o u p c an be d i v i d e d
int o three fields* The f i r s t group specifies which of the
r e g i s t e r s is to be u t i l i z e d as the base register* The s e c o n d
s p e c i f i e s the number of b y t e s of addressing information which
f o l l o w s the A d d r e s s i n g C o n t r o l Byte? arid the t h i r d s p e c i f i e s the
f o r m a t of the d a t a acauisttion* E a c h of t h e s e is d e s c r i b e d in
detail below*

4*5*2*2 Base Register Select Field

The B a s e R e g i s t e r Select Field specifies one of the base registers

as f o l l o w s ^

Bit 3 B it 2 Selected Register

0 0 Process Base R e g i s t e r (BAS)

0 1 Primary Base R e g i s t e r (PRM)
1 0 T o p of Stack (TOS)
1 1 External Base ( E XTXX)

As d e s c r i b e d p r e v i o u s l y ? the p h y s i c a l a d d r e s s of the d a t a w h i c h is
to a c c e s s e d is d e t e r m i n e d by a d d i n g t he o f f s e t c o n t a i n e d in the
i n s t r u c t i o n to the r e g i s t e r s e l e c t e d by t h i s f i e l d * If E x t e r n a l
Base Addressing is s e l e c t e d ? the a d d r e s s of t h i s base register
( w i t h i n the P r o c e s s B a s e Pa ge) is s p e c i f i e d by the b y t e f o l l o w i n g
the O p e r a n d C o n t r o l Byte*

4*5*2*3 Data Access Format

The two b i t s of the Data Access Format f i e l d are u s e d to c o n t r o l

the m a n n e r in w h i c h data is to be a c c e s s e d * T h i s is a c c o m p l i s h e d
as f o l l o w s :

Bit 1 Bit 0 Format

0 0 Descriptor Access

Data is to be accessed through a descriptor*

*********CONFIDENTIAL> M OS T E C H N O L O G Y ? INC * * * * * * * * * * Page- 53

 Final Design Specification for the MC S65 E 4 Microprocessor

The a d d r e s s in the i n s t r u c t i o n is a s s u m e d to
be that of a d e s c r i p t o r w h i c h c o n t a i n s all
of the i n fo r m a t i o n required to properly
m a n i p u l a t e the d e s i r e d d a t a f i e l d *

Single Byte Access

Th e a d d r e s s c o n t a i n e d in the i n s t r u c t i o n is
assumed to be that of a single byte of
u n s i g n e d i n t e g e r data*

Two byte Integer Access

The a d d r e s s c o n t a i n e d in the i n s t r u c t i o n is
a s s u m e d to be t h a t of a s i x t e e n - b i t w o r d of
2' s c o m p l e m e n t i n t e g e r d a t a * Lo w o r d e r d a t a
is a s s u m e d to be l o c a t e d in the low o r d e r
add r e s s *

Three byte ordinal Access

The a d d r e s s c o n t a i n e d in the i n s t r u c t i o n is
a s s u m e d to be t h a t of a 24 bit o r d i n a l data
field* Low o r d e r d a t a is a s s u m e d to be in
the low o r d e r a d d r e s s *

4 * 5 * 2 *4 N u m b e r of Extension Bytes

The N u m b e r of E x t e n s i o n B y t e s f i e l d s p e c i f i e s the n u m b e r of b y t e s
of o f f s e t i n f o r m a t i o n w h i c h f o l l o w s the O p e r a n d C o n t r o l Byte* T h i s
is s p e c i f i e d as f o l l o w s !

N u m b e r of
B it 3 Bit 2 Addressing Bytes

0 0 None- The o f f s e t address is assumed to be

zero*

0 1 One- The h i g h o r d e r b i t s of the o f f s e t are

a s s u m e d to be zeros*
(offset value t 0 <= o f f s e t <= 255)

1 0 One- Bit 3 of the o f f s e t is a s s u m e d to be a

l o g i c 1* The remaining high order
bits of the o f f s e t are a s s u m e d to be
zer o s *
( o f f s e t v a l u e ** 256 <= o f f s e t <= 511)

1 1 Two- The low order 3 addressbits of the

offset follow the O p e r a rid Control
Byte* T h i s is f o l l o w e d by b i t s 3- 1 5 *
The h i g h o r d e r e i g h t a d d r e s s b i t s are
a s s u m e d to be z e r o s *
( o f f s e t v a l u e I 0 <= o f f s e t < = 6 5 5 3 6 5 )

4*5*3 Secondary Addressing Group

*********CONFIDENTIAL> MOS T E C H N O L O G Y ? I N C * * ** ** * ** * Page- 54

 Final Design Specification for the M C S6 5 L 4 Microprocessor

4 *5 ♦3 * 1 In t rc d u c t io n

In a d d i t i o n to t h e s e p r i m a r y a d d r e s s i n g m o d e s ? t h e r e 3 re s e v e r a l
a d d r e s s i n g m o d e s w i t h i n the M C 3 6 5 E 4 s o f t w a r e a r c h i t e c t u r e w h i c h do
n ot r e a u i r e the f l e x i b i l i t y w h i c h is i n h e r e n t in the a d d r e s s i n g
d e s c r i b e d in the p r e v i o u s p a r a d r a p h * T h i s is tru e for L i m i t P a 3 e
addressing (utilizing the LMT Resister as b ase) s i n c e th i s
operation never requires more than 3 single byte of offset*
Similarly? the P U S H arid POP operations do not require any
addressing information s i n c e the d a t a is p l a c e d d i r e c t l y o n t o the
process s t a c k without offset* F i n a l l y ? the I m m e d i a t e A d d r e s s i n g
requires only t h a t the s i z e of the i m m e d i a t e o p e r a n d be s p e c i f i e d
s i n c e the data f o l l o w s d i r e c t l y a f t e r the O p e r a n d C o n t r o l Byte*
T h e s e address!rig m o d e s are s e l e c t e d by the A d d r e s s i n g M o d e S e l e c t
f i e l d as F o l l o w s :

Bit 3 Bit 2 Addressing Mode

0 0 Limit Page Addressing

0 1 Process Stack PUSH / POP

1 0 Immediate Addressing (L o n g Form)

1 1 Process Base Addressing (L o n g form)

Each of these modes is described in detail below*

4 *5 * 3 *2 L i m i t P a ge Addressing

As d e s c r i b e d previously? the L i m i t P a g e w i t h i n a p r o c e s s is u s e d
to store the vectors which are used in the servicing of
interrupts? system calls? etc* during process execution* These
v e c t o r s can be manipulated directly by the process whenever
a p p r o p r i a t e * L i m i t P a g e a d d r e s s i n g p r o v i d e s an e f f i c i e n t m e t h o d of
a ccessing these vectors* W h e n L i m i t P a g e a d d r e s s i n g is s e l e c t e d ?
the A u x i l i a r y D a t a F i e l d (bits 0 and 1) s p e c i f i e s the D a t a A c c e s s
F o r m a t in e x a c t l y the s a m e m a n n e r as that d e s c r i b e d a b o v e (See
P a r a g r a p h 5 ♦ 6 ♦ 2 *3) ♦

4 * 5 *3 *3 P r o c e s s Stack PUSH / POP

The top of the p r o c e s s s t a c k can be s p e c i f i e d as the s o u r c e ( P O P )

or destination (PUSH) for d a t a within most of the MCS65E4
instructions* T h i s is a c c o m p l i s h e d by specifying PUSH/POP
a d d r e s s i n g in the a p p r o p r i a t e o p e r a rid f i e l d * If t h i s a d d r e s s i n g is
specified within a source operand? the p r o c e s s o r will e x e c u t e a
POP o p e r a t i o n in w h i c h the c o n t e n t s of the d a t a f i e l d l o c a t e d on
the top of the p r o c e s s stack, will be t r a n s f e r r e d into an i n t e r n a l
d a t a r e g i s t e r * The TOS r e g i s t e r will then be i n c r e m e n t e d by an
amount determined by the length of the data field* The TOS
Registe r then p o i n t s to the next data f i e l d on the s t a c k * If
P U S H / POP a d d r e s s i n g is s p e c i f i e d in a d e s t i n a t i o n o p e r a rid? the
r e s u l t s of the i n s t r u c t i o n e x e c u t i o n w i l l be t r a n s f e r r e d o n t o the
process stack * As w i t h all process stack, o p e r a t i o n s ? the TOS

*********CONFIDENTIAL? MOS T E C H N OL O GY ?INC ** * * * * * * * * Page-

 Final D es i gn Specification for the M C S65E 4 Microprocessor

r e g i s t e r is a d j u s t e d to p o i n t to the last b y t e of d a t a w h i c h was

placed onto the s t a c k * W h e n P U S H / P O P a d d r e s s i n g is s e l e c t e d ? the
A u x i l i a r y D a t a F i e l d s p e c i f i e s th e D a t a A c c e s s M o d e in e x a c t l y the
same manner as t h a t described above for th e primary addressing
modes*

The a u x i l i a r y data f i e l d ( bits 1 through 0 ) of the o p e r a n d

c o n t r o l b y t e are d e f i n e d as f o l l o w s for P U S H / P O P o p e r a t i o n s ?

hit 1 bitO Operation

0 0 PUSH/POP a variable defined by

d e s c r i p t o r (P P D )*

0 1 PUS H/POP byte (1 b yte ) (PPEO*

1 0 PUSH/PO P half word (2 b y t e s )

(PPHW)*

1 1 PUSH/POP triple byte (3 b y t e s )

(PPTB)*

The P U S H / P 0 P operations are illustrated in Figure 2*1 with the

f o l l o w i n g instru ction!

Add P P D ? P P B ?P P H W (POP d e s c r i p t o r v a r i a b l e arid b y t e

* ( v a r i a b l e f r o m s t a c k ? add them
♦ ( t o g e t h e r a n d P U S H the r e s u l t s o n t o
* (the s t a c k in a two b y t e
♦ ?integer field*

Figure 2*la s h o w s the p r o c e s s s t a c k b e f o r e the add i n s t r u c t i o n *

N o t e the top t wo e l e m e n t s of the s t a c k a re a data field with
d e s c r i p t o r (Data F i e l d * 1) and a s i n g l e b y t e of d a t a (D a t a F i e l d
$ 2)* T he TOS r e g i s t e r i n i t i a l l y p o i n t s to the d e s c r i p t o r of the
D a t a F i e l d * 1*

Figure 2*lb s h o w s the p r o c e s s s t a c k a f t e r the PPD P OP o p e r a t i o n *

A f t e r the o p e r a t i o n is c o m p l e t e ? the c o n t e n t s of t h i s d a t a h a v e
been t r a n s f e r r e d into an internal data register arid the TOS
r e g ister has b e e n a d J u c t e d to p o i n t to D a t a F i e l d *2 * N o t e t h a t
the POP operation d o e s not c h a n g e the c o n t e n t s of the memory
l o c a t i o n s in w h i c h D a t a F i e l d *1 is s t o r e d *

A f t e r the P P B (POP) o p e r a t i o n ? i l l u s t r a t e d in f i g u r e 2 * 1C? the TOS

has b e e n i n c r e m e n t e d by 1 and n o w p o i n t s to e a r l i e r d a t a s t o r e d on
t h e stack.*

The result of the add operation w ill be pushed onto the stack as a

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O LO G Y ? INC ** * * * * * * * * Page- 56

 l-inal Des ig n Specification for the MCS 65 E4 Microprocessor

t wo byte integer* Note the TOS r e gister has been ad j u s t e d to point

to the last byte of data acce s s e d on the stack* F i g »jre 2 ♦ 1 d
d e p i c t s the P P H U (PUSH) o p e r a t i o n *

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y jINC ** * * * * * * * * Fade-

 1"i n 3 1 De sign Specification for the MC365E 4 Microprocessor

Figure 2♦1A - Memory and TOS register contents before PO P

Continuation of High Order Memory

Process Stack

Da t a
Field Byte
*2

Address or
Data Da ta
Field
*1

Descriptor < --- C o n t e n t s of TOS

Register

Free Memory Lo w Order memory

Figure 2 ♦2 B - M e m o r y a nd TOS register contents after PPD (POP)

Continuation of High Order Memory

Process Stack

D ata
Field
*2
< --- C o n t e n t s of TOS
Register

Free Memory

Low Order memory

* * * * * * * * * C O N F I D E N T I A L > MOS T E C H N O L O GY ,I N C ♦***** **** Page-

 Final Design Specification for the M C S6 5 E4 Microprocessor

Figure 2* 1C - Memory and TOS register contents before PPB (POP)

High Order Memory

Continuation of
Process Stack < --- C o n t e n t s of TOS
Register

Free Memory

Low Order Memory

Figure 2*1D - Memory and TOS register contents after PPHW (PUSH)

High Order Memory

Continuation of
Process Stack

Data I
Field I
£3 I < --- C o n t e n t s of TOS
Register

Free Memory

Low Order memory

*********CONFIDENTIAL> MOS T E C H N OL O GY tI N C ♦**** **** * Page- 59

 Final Design Specification for the M C S6 5E 4 Microprocessor

4 * s ♦3♦4 Immediate Addressing? Lons Form

The long form of i m m ed iate a d d r e s s i n g allows «jp to three bytes of

osto or addressing information to be specified within the
instru ction* This d a 1 3 f ol lows d i r e c t l y be hi n d the Addressing
Control Byte* When this form of a d d r e s s i n g is selected? the
A u x i l i a r y Data Field (bits 0 arid 1) s p e c i f i e s the n umbe r of bytes
arid the format of the i m m edi ate data as follows!

Bit 1 Bit 0 Fo rma t of Data

0 0 U n s i g n e d B yte* Assumed to be
positive *

0 1 Signed 2 byte integer*

1 0 Three byte ordinal* Assumed to

be p o s i t i v e *

Not Used

4*5*4 Internal Register Addressing

This a d d r e s s i n g m o d e a l l o w s the i n t e r n a l p r o c e s s o r r e g i s t e r s can

be s p e c i f i e d as the s o u r c e or d e s t i n a t i o n of the d a t a to be
m a n i p u l a t e d by the i n s t r u c t i o n * The f o u r - b i t R e g i s t e r S e l e c t d a t a
f i e l d s e l e c t s t h e i n t e r n a l r e g i s t e r s as f o l l o w s !

Bit 3 Bit 2 Bit 1 Bit 0 Register Selected

0 0 0 0 Process Limit Register

0 0 0 1 Process Program Counter

0 0 1 0 Top Of Stack Register

0 0 1 1 Primary Base Register

0 1 0 0 Process Control register

0 1 0 1 Microcode Select Register

0 1 1 0 Refresh Control Register

The LMT register is " r e a d - o n l y ' ? i* e *? the p r o c e s s s o f t w a r e

c a n n o t m o d i f y the c o n t e n t s of t h i s r e g i s t e r s u n d e r a ny c o n d i t i o n s *
The P r o c e s s Control Register? Microcode Select Register? arid
Refresh Control Register are " r e a d - o n l y " in the U s e r M o d e and
“R e a d / W r i t e * in t he S u p e r v i s o r Mo de*

4*5*5 Immediate Addressing? Short Form

The f i r s t of the short form a d d r e s s i n g m o d e s a l l o w s f i v e b i t s of

immediate d a t a to be i n c l u d e d in the O p e r a n d C o n t r o l B y t e (in b i t s

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 60

 Final De s i g n Specification for the MC3 65 E 4 Microprocessor

0 " 4) * T h i s a l l o w s i m m e d i a t e v a l u e s b e t w e e n - 1 6 arid + 15 t o be
s p ec i f i ed w i t h i n t h e O p e r a n d c o n t r o 1 B y t e *

4 * 5 * 6 P r o c e s s B ase A d d r e s s i n g ? S h o r t Form

The s h o r t fo r m o f BAS o f f s e t a d d r e s s i n g a l l o w s u p to 6 b i t s o f
o f f s e t i n f o r m a t i o n to be i n c l u d e d in t h e O p e r a n d C o n t r o l B y t e ( i n
b i t s 0 - 5 ) * T h i s a l l o w s t h e O p e r a n d C o n t r o l B y te to d i r e c t l y
s p e c i f y d a t a f i e l d s w h ic h a r e a c c e s s e d t h r o u g h d e s c r i p t o r s l o c a t e d
in t h e f i r s t 64 b y t e s o f t h e B ase P a g e *

4 * 5 * 6 P r i m a r y B ase A d d r e s s i n g S h o r t Form

The s h o r t fo r m o f PRM o f f s e t a d d r e s s i n g a l l o w s u p to 6 b i t s o f
a d d r e s s i n g i n f o r m a t i o n to be i n c l u d e d in t h e A d d r e s s i n g C o n t r o l
B y t e ( i n b i t s 0 - 5 ) * T h i s a l l o w s t h e O p e r a n d C o n t r o l B y t e to
d i r e c t l y c o n t r o l a c c e s s t o d a t a f i e l d s w h ic h a r e a c c e s s e d t h r o u g h
d e s c r i p t o r s l o c a t e d in t h e f i r s t 6 4 b y t e s a b o v e t h a t memory
l o c a t i o n w hose a d d r e s s i s c o n t a i n e d in t h e P r i m a r y B ase R e g i s t e r *

F i g u r e 4 * 6 A arid 4 * 6 B b e lo w s u m m a r i z e s t h e a d d r e s s i n g modes f o r th e
M C S 6 5 E 4 *

* * * * * * * * * C O N F I D E N T I A L > MOS T E C H N O L O G Y * INC ** * * * * * * * * Page- 61

 S pe c i f y the v a l i d d a t a types
"*x
•: Terminal symbols which soecifv the form of

Reference mors liagram d v that

Program I
>
V

instruction i

SYNTAX DIAGRAM

1
ructio ._ N/j v: ODerand Operand
Operand
OP-Code
V 1
"7»

Oioerand Ooerand Ooerand

OP-Code B Oicerand

OP-Code ! B aw

.Ficrare 5.6a
 - (BASE) t of fs e t

value tbV -7* 0< value < 15,777,215 <ORD>

y
t./ ooerand offset=0
rir nrontrol 3 f--r- — ■ ,internaL iorrse^ push/poo — oyte
-nd J variai descriDtor short variable
rtarav'onr'a / , -1
externajj I
base )< <255 ig\
J _^3norr
2 56< <511 integer
a)- variable
,<BYT>
immediate or<2I> 0<: <65,535
lescriDtor <:
/"
variable
^ value <15M <2
HW\__
m. > <3YT>-^ °-
or <21> < ll r
v _____
* only for BAS
value

Figure 5.6b
 Final De s i gn Specification for the MC S65 E 4 Microprocessor

4 ♦6 Data Structure With in the MCS6 5E4 Syst em

4♦6 * 1 I n tr o d u c t i o n

N o w h e r e is the “h i g h level* a p p r o a c h to a r c h i t e c t u r e m o r e a p p a r e n t
t h a n in the m a n n e r in w h i c h d a t a is s t o r e d and a c c e s s e d w i t h i n an
M C 3 6 5 E 4 s y s t e m * T h i s w as i n t r o d u c e d in S e c t i o n 4 * 5 w h i c h d i s c u s s e s
the o rgan i za t i on of the ope r a n d * S e c t i o n 4*6 c o n t a i n s a d e t a i l e d
d e s c r i p t i o n of the remaining a s p e c t s of these data accessing
m e c h a n i s m s a l o n g w i t h a d e s c r i p t i o n of the m a n n e r in w h i c h d a t a is
s t o r e d w i t h i n the M C S 6 5 E 4 s y s t e m *

The p r i n c i p a l f e a t u r e of the M C S 6 5 E 4 d a t a s t r u c t u r e is the use of

d e s c r i p t o r s to s p e c i f y all of t h e pertinent details concerning a
data field* T h i s c o n t r a s t s s h a r p l y w i t h the c o n v e n t i o n a l a p p r o a c h
in w h i c h the f i e l d l e n g t h is d e t e r m i n e d p r i m a r i l y by the O p C o d e
(8 bits* 16 bits; etc .) and the a c t u a l d a t a f i e l d s are c r e a t e d by
u t i l i z i n g the processor software to o r g a n i z e t h e s e simple fixed
length fields into g r o u p s to s t o r e c o m p l e x d a t a e n t i t i e s ( 1 0 - b y t e
R eal; 3 - b y t e BCD; e t c * ) *

The p r i n c i p a l a d v a nt ag e a s s o c i a t e d with this t r a d i t i o n a l appro ac h

is that it is much simpler to implement in hardware* The
i n s t r u c t i o n set c o n s i s t s of a l a r g e n u m b e r of relatively simple
operations* T h i s is compatible with art environment in which
hardware is expensive; logic design is still somewhat
u n s o p h i s t i c a t e d ; arid the s c i e n c e of s y s t e m p r o g r a m m i n g is s t i l l in
its i n f a n c y * I m p l e m e n t a t i o n of t h i s t y p e of a r c h i t e c t u r e at t h i s
tim e ; however; d o e s n ot r e c o g n i z e the s i g n i f i c a n t developments
w h i c h h a v e ' t a k e n p l a c e in p r o c e s s o r d e s i g n t e c h n i q u e s ( m u l t i - l e v e l
microprogramming; etc*)* In a d d i t i o n ; it i g n o r e s the f a c t that
software design techniques have achieved a s u b s t a n t i a l d e g r e e of
maturity* S p ec if ica11y ; the c o m p i l e r languages in use today
e x h i b i t the f o l l o w i n g c h a r a c t e r i s t i c s I

1* The a l g o r i t h m s arid d a t a s t r u c t u r e s are k e p t as s e p a r a t e ?

s e l f - c o n t a i n e d e n t i t i e s * For e x a m p l e ; the s t a t e merit A = B + C
typically contains no i n f o r m a t i o n r e g a r d i n g t he t y p e of
d a t a w h i c h is s t o r e d in A; B or C* I n s t e a d ; the d a t a t y p e
is d e f i n e d e a r l i e r in the p r o g r a m as i n t e g e r ; real; etc*

2* Data e l e m e n t s are t r e a t e d as complete entities m o s t of

the time* This means; for e x a m p l e ; t h a t the various
s e g m e n t s of a f l o a t i n g p o i n t v a r i a b l e will n ot be treated
i n d i v i d u a l l y by a u s e r ' s a p p l i c a t i o n p r o g r a m *

3* In m o s t i n s t a n c e s ; the f o r m of the data w i thin a data

f i e l d wi l l not c h a n g e d u r i n g the life of a p r o g r a m *

4* The o p e r a t i o n s w h i c h are p e r f o r m e d on a d a t a f i e l d are

generally a f u n c t i o n of the s p e c i f i c d a t a c o n t a i n e d in
the f i e l d ; for e x a m p l e ; the a r i t h m e t i c o p e r a t i o n s w h i c h
a re p e r f o r m e d on a f l o a t i n g p o i n t d a t a f i e l d wil l d i f f e r
s h a r p l y f r o m t h o s e w h i c h are p e r f o r m e d on an i n t e g e r d a t a
field*

*********CONFIDENTIAL; MOS T E C H N O L O G Y ;I N C * * * * ** * * * * Page- 63

 Final Design Specification for the MCS65E4 Microprocessor

The a r c h i t e c t u r e of the M C S 6 5E4 is d e s i g n e d in a manner which

recognizes these c h a r a c t e r i s t i c s * H o w e v e r ? it a l s o r e c o g n i z e s the
use of the p h r a s e s “m o s t of th e t i m e " ? 'in m o s t i n s t a n c e s * ? and
"generally* in the a b o v e list* S p e c i f i c a l l y ? it p r o v i d e s all of
the advantages of descriptors while still retaining the
flexibility needed by s u c h l a n g u a g e s as F o r t r a n ? a nd C in w h i c h
the d e f i n i t i o n of a d a t a f i e l d can be a l t e r e d d u r i n g the e x e c u t i o n
of a program* In a d d i t i o n ? it r e c o g n i z e s the need to allow
e f f i c i e n t m a n i p u l a t i o n of the d e s c r i p t o r arid o t h e r k e y e l e m e n t s of
the d a t a s t r u c t u r e *

All d a t a m a n i p u l a t i o n i n s t r u c t i o n s w i t h i n the M C S 6 5 E 4 c o n s i s t of
an O p C o d e and u p to three operands* The Op C o d e s s p e c i f y the
o p e r a t i o n to be p e r f o r m e d w h i l e the o p e r a n d s s p e c i f y the l o c a t i o n
of the d a t a to be m a n i p u l a t e d * T h i s d a t a can be a c c e s s e d d i r e c t l y
or it c an be l o c a t e d in one of the c o m p l e x data structures
d e s c r i b e d below* In all c a s e s ? h o w e v e r ? p r o c e s s i n g of the o p e r a n d
must result in the g e n e r a t i o n of the a d d r e s s of a basic data
element since all d a t a m a n i p u l a t i o n o p e r a t i o n s are p e r f o r m e d o n l y
on t h e s e e l e m e n t s *

Within the MCS65E4 system most data is . a c c e s s e d through

d e s c r i p t o r s * H e r e a f t e r ? t h e s e d e s c r i p t o r s c o n t a i n the ty pe? f o r m a t
and l o c a t i o n i n f o r m a t i o n w h i c h a l l o w s t he p r o c e s s o r to m a n i p u l a t e
the d a t a in a d a t a f i e l d * A f t e r a b r i e f d e s c r i p t i o n of the b a s i c
data elements? the o r g a n i z a t i o n arid o p e r a t i o n of these variable
d e s c r i p t o r s are d i s c u s s e d in d e t a i l *

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ****** * ** * Page- 64

 ur
FORM 0 i HE DATA
(B)

(HW)j

'riois
lyte (T3)

■iord (W)
31

Double
'lord (DW)
53 0

u
! »
iord (LW) 1 • u
79

n-3yte / I
3tring(n3
8n-l o
 -Data Tyoe Meaning Size

3Ym byte 3 Binary = 0 to 25 5

BCD =" 0 to 99

2 21 2 byte signed HW I -55 ,535 to 55 ,535

integer i
j
3 ORD Ordinal-3 bytss T3 0 to 15,777,215 1
unsigned intes

i+ M-I byte w -231 to 2 ^-1

s ign ed inte ge ]
i ± i o - j / to i o T - d j
5 M* byte real | W |
7 decimal digit of precision

5 4D 4- byte BCD w -7 decimal digit

1
7 31 3 byte DW -253 to 253 -1
integer signec1
i
3 3R 8 byte real DW ± I Q - 3 0 3 zo l o 3 0 3
j 15 decimal digit of precision

9 3D j 3 byte BCD DW +15 decimal digit

i q I0R 10 byte real j LW il0-t+932 t0 101+932

I 19 decimal digit of precision
|
n ,,262,136
12 STR String 0 to Binary: 0 to 2
i 32767
I 65 5^4
I bytes Decirral: 0 to 1C '
i |
| i 1

Note: 1-11 will be refered to as scalar

 Final Desig n Specification for the MC3 6 5 E 4 Microprocessor

4*6+2 The Basic Data Elements

The g r o u p of b a s i c d a t a e l e m e n t s is c o m p o s e d of 10 simple data

f i e l d s arid 1 s t r i n g d a t a f i e l d * The s i m p l e d a t a f i e l d s ( h e r e a f t e r
r e f e r r e d to as s c a l e r s ) ? c o n s i s t of s i g n e d arid unsigned binary
d ata? BCD data? or f l o a t i n g p o i n t (REAL) d a t a in v a r y i n g l e n g t h
fields* E a c h of t h e s e Basic Data E l e m e n t s is s t o r e d in o ne of
seven different f i e l d s i z e s (Byte? H a l f W or d? T r i p l e Byte? W o rd?
D o u b l e Uo rd? L o n g Wor d? n - B y t e S t r i n g ) w h i c h is d e p i c t e d in F i g u r e
5 * 7 ♦2 a

*********CGNFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Page- 66

 Final D e sign Specification for the MCS6 5E 4 Microprocessor

4*6 *2 ♦ 1 U n s i g n e d Binary Data Fields

The u n s i g n e d binary data fields are t y p e b y t e and o r d i na 1 ♦ T h e y

are a s s u m e d to be p o s i t i v e and t h u s have no s i g n i n f o r m a t i o n
a s s o c i a t e d with them* A b y t e is 8 b i t s and an o r d i n a 1 is 24 b i t s *
The r a n g e of t h e s e f i e l d s i z e s ar e i n d i c a t e d in f i g u r e 5 * 7 * 2 b *

4 *6 ♦2 *2 S i g n e d Binary Data Fields

Th e s i g n e d binary data f i e l d s ar e two? fou r ? and e i g h t b y t e

integer* T h e y are s t o r e d in t w o ' s c o m p l i m e n t b i n a r y f o r m a t * The
r a n g e of t h e s e f i e l d s are i n d i c a t e d in f i g u r e 5 * 7 * 2 B *

T he M C 3 6 5 E 4 supports four and e i g h t b y t e B CD fields stored as

packed binary i n t e g e r and s i g n e d m a g n i t u d e * Th e m o s t s i g n i f i c a n t
four bits of the f i e l d c o n t a i n s the s i g n i n f o r m a t i o n (i*e 0 0 0 0 = >■
positive number? 1111 = > n e g a t i v e number)* The r a n g e of these
f i e l d s are i n d i c a t e d in f i g u r e 5 * 7 * 2 b *

4*6*2*4 Floating Point Data Fields

The f l o a t i n g point data fields are c o m p a t i b l e w i t h the p r o p o s e d

IEEE f l o a t i n g point standard* The are s t o r e d in three parts!
mantissa? biased exponent? 3nd si gn* B o t h the m a n t i s s a and the
e x p o n e n t are s t o r e d in two's compliment binary format w i t h the
most significant bit being the sign indicator (i*e* 0 =>
positive? 1 => n e g a t i v e ) * The r a n g e of t h e s e f i e l d s are i n d i c a t e d
in f i g u r e 5 * 7 *2B *

4*6*2*5 String Data Fields

String data fields are treated as unsigned binary data*

Figure 5*7*2C depicts the format of the Basic Data Elements

* * * * * * * * * C G N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C * ** * * ** * * * Pa g e - 68
 A

Is!
li~30 23 22

A+7

8R
63 52 52

A+9

10R
Is e______ J____
79 73 5*+ 53 52

At 3

M-D
n I digit
31--- T T

A+7

3D n 15 disit
63

A+n-1
---------------- ---------------------------------------------------- _

n Byte String I „ | ,
>Y ,
n byres

s = sign
e - exponent
f - fraction
K - key
M - message
j - 1-bit integer part
n = siqn 0000
1111
 <21 >

<ORD >

<-ur>,OR> ,<>D>

< 8I > , < 8R > , < 8D ->>

< 10R>

\ STR> with length n

 Final De s i g n Specification for the MCS65E4 Microprocessor

4*6*3 0 rg a n i z a t i o n of the Variable Descriptor

4 * 6 ♦3 * 1 I n t r o d u c t i o n

The V a r i a b l e D e s c r i p t o r is the p r i m a r y m e a n s by w h i c h the M C S 6 5 E 4

d e t e r m i n e s the f o r m a t of the d a t a f i e l d * W i t h the e x c e p t i o n of the
one b y t e u n s i g n e d b i n a r y f i e l d ? the two b y t e s i g n e d i n t e g e r f i e l d ?
arid the t h r e e b y t e o r d i n a l w h i c h can be a c c e s s e d d i r e c t l y ( w i t h o u t
going through a descriptor)? all d a t a f i e l d s m u s t be accessed
through a descriptor* T h i s ass u res t h a t all i n s t r u c t i o n s wi l l be
e x e c u t e d iri a manner w h i c h is a p p r o p r i a t e to the t y p e of d a t a
w h i c h is b e i n g m a n i p u 1 a t e d *

The V a r i a b l e Descriptor is com p o s e d of one or more of the

following elements!

1* D e s c r i p t o r H e a d e r
2 * A d d r es sing Information (optional)
3* A u x i l i a r y i n f o r m a t i o n ( o p t i o n a l )

All V a r i a b l e Descriptors must begin with a Descriptor Header*

H o w e v e r ? the a d d r e s s i n g i n f o r m a t i o n m u s t be p r o v i d e d o n l y w h e n the
data field is n ot attached directly to the descriptor arid the
a ux i l i a r y data m u s t be pr o v i d e d only when r eferencing the m o r e
com pl ex data s t r u c t u r e s (strings? records? etc*)*

4*6*3*2 Organization of the Descriptor Header

4 * 6 *3 *2 * 1 I n t r o d u c t i o n

The o r g a n i z a t i o n of the Descriptor Header can be depicted as

follows!

7 6 5 4 3 2 1 0

I Trap! F l a g I Data Type I Access I

I I I i Mode i
I (T ) I (F ) I (D ) I (M ) I

E a c h of these fields is described briefly below* A detailed

d e s c r i p t i o n of the o p e r a t i o n of the d e s c r i p t o r is c o n t a i n e d in the
r e m a i n i n g p a r a g r a p h s of t h i s s e c t i o n *

4 *6 ♦ 3 ♦ 2 *2 T r a p Bit (Bit 7)

The tr a p b it in th e d e s c r i p t o r c an be set to c a u s e a D a t a A c c e s s
T r a p to occur w h e n the processor attempts to a c c e s s the data
field* W i t h i n the E x c e p t i o n V e c t o r f i e l d ? the T R A P b it is u s e d to
specify that the exception will be serviced in the current
process's c a 11e r *

4 * 6 *3 *2 *3 A c c e s s Mode (Bits 1 arid 0)

The Access Mode field specifies the manner in which the location

*********C0NFIDENTIAL? MOS T E C H N O L O G Y ?I N C ♦***** * * * * Page- 70

 Final Design Specification for the MCS65E4 Microprocessor

of the d a t a f i e l d will be d e t e r m i n e d * S p e c i f i c a l l y * the d a t a can

be a t t a c h e d to the d e s c r i p t o r ? it c an be l o c a t e d at a s p e c i f i e d
offset from the d e s c r i p t o r or it can be l o c a t e d at a specified
logical address w i t h i n t he process* The two b i t s in this field
s p e c i f y one of f o u r a c c e s s m o d e s as f o l l o w s *

F i e l d D e s c r i p t o r or
B it 1 Bi t 0 Descriptor Element Descriptor

0 0 Attached Attached Relocatable

0 1 Short Relative Short Relocatable
1 0 Long Rel a ti ve Long R e l o c a t a b l e
1 1 Logical Addressing Logical Addressing

4*6*3*2*3*1 Attached

If the A t t a c h e d A c c e s s M o d e is s p e c i f i e d ? t he v a r i a b l e d e s c r i p t o r
c o n s i s t s of a d e s c r i p t o r h e a d e r and? if a p p r o p i a t e ? an a u x i l i a r y
data field* No a d d r e s s i n g i n f o r m a t i o n is r e q u i r e d s i n c e the d a t a
f i e l d is l o c a t e d in m e m o r y i m m e d i a t e l y f o l l o w i n g the d e s c r i p t o r *

4 ♦ 6 * 3 *2 * 3 * 2 A t t a c h e d Relocatable

Within 3n element descriptor in an array structure or a field

d e s c r i p t o r in 3 record? the 3 t t 3 c h e d 3 d d r e s s i n g b e c o m e s s t t s c h e d
relocatable* T h e 3 t t 3 c h e d r e l o c a t a b l e a d d r e s s i n g m o d e o p e r a t e s in
m u c h the s a m e m a n n e r as a t t a c h e d e x c e p t o 11 a t t h s d 3 trs is a s s u m e d
t o be attached to the address which was p r e v i o u s l y calculated
d u r i n g t h e d e s c r i p t o r p r o c e s s i n g * T h i s is i l l u s t r s t e d in d e t s i l in
the e x am p 1e s below*

4 * 6 * 3 *2 *3 *3 S h o r t Rel3tive

If the s h o r t r e l a t i v e a c c e s s m o d e is s p e c i f i e d ? the d a t a f i e l d is
l o c a t e d at a s p e c i f i e d o f f s e t f r o m the a d d r e s s of the d e s c r i p t o r *
The o f f s e t is c o n t a i n e d in a s i n g l e b y t e of a d d r e s s i n g i n f o r m a t i o n
immediately following the d e s c r i p t o r header* The d a 1 3 f i e l d c 3 n
t h e r e f o r e be l o c s t e d w i t h i n the r 3 n g e of - 1 2 3 to + 1 2 7 b y t e s f r o m
the address of the descriptor* If a u x i l i a r y information is
required for s c c e s s i n g the data field? this in for m a t i o n follows
i mmediate ly after the s i n g l e b y t e of o f f s e t * ( r e f e r to d e s c r i p t o r
flowchart)

4*6*3*2*3*4 Short Relocatable

The s h o r t relocatable access m o d e is exactly the s a m e as s h o r t

relative addressing mode except that the offset information is
a d d e d to the 'previously calcul3ted address" w i t h i n an array
s t r u c t u r e or r e c o r d * See e x a m p l e b e l o w for a c c e s s i n g d a t 3 w i t h i n a
m u l t i - d i m e n s i o n a l a r r a y or r e c o r d *

4 * 6 * 3 * 2 * 3 *5 L o n g Relative

If the lon g r e l a t i v e a c c e s s m o d e is s p e c i f i e d ? two b y t e s of o f f s e t

i n f o m a t i o n are i n c l u d e d in the v a r i s b l e d e s c r i p t o r * The d e s c r i p t o r
h e a d e r is f o l l o w e d by the low o r d e r 3 nd h i g h order bytes of a

*********C0NFIDENTIAL7 MOS T E C H N O L O G Y ?INC ****** * * ** Page- 71

 Final Design Specification for the MCS65E4 Microprocessor

1 6 - bit o f f s e t field* T h i s a l l o w s the data field to be located

within 3 r a n g e of - 3 2 8 6 8 to + 3 2 7 6 7 b y t e s f r o m the a d d r e s s of the
descriptor* If the data field is one of the ■ m o r e complex
structures described below? the r e q u i r e d auxiliary data will
f o l l o w the two b y t e o f f s e t in the d e s c r i p t o r *

4 * 6 * 3 *2 * 3 * 6 Long Relocatable

The long relocatable access mode is e x a c t l y the s a m e as long

relative addressing mode except t h a t the offset information is
a d d e d to the •previously calculeted address" w i t h i n an array
s t r u c t u r e or record* S e e the e x a m p l e b e l o w for a c c e s s i n g dat3
w i t h i n a m u l t i - d i m e n s i o n a l a r r a y or r e c o r d *

4 ♦ 6 ♦ 3 ♦2 ♦ 3 ♦ 7 Logical Addressing

If L o g i c a l A d d r e s s i n g is s p e c i f i e d ? the d e s c r i p t o r h e a d e r will be
f o l l o w e d by s t h r e e - b y t e o r d i n a l w h i c h is the l o g i c a l a d d r e s s of
the d a t a field* T h i s l o g i c a l a d d r e s s is a d d e d to the c o n t e n t s of
the BAS r e g i s t e r to d e t e r m i n e the p h y s i c a l a d d r e s s of the d a t a
field* T h i s 3 l l o w s the d a t a f i e l d to be p l a c e d a n y w h e r e in the
a d d r e s s s p a c e of the p r o c e s s * As b e f o r e ? any a u x i l i a r y i n f o r m a t i o n
w h i c h is required will follow the t h r e e bytes of addressing
i n f o r m a t i o n * ( R e f e r to d e s c r i p t o r f l o w c h a r t )

* * * * * * * * * C O NF I D E N T I A L ? MOS T E C H N O L O G Y ?I N C ** * * * * * * * * Page- 72
 T ' n
1 1 / attacnec Field
Discriptar x Attached
!
__ s,. snort ;3 u> Header 3
Element !Relocatable
! V relative I J ( Discriiotor
! r
j |
o<s a r ’ •jS k
jHwy / Short
7 Relative

Long
HB '
i /

A
Logical
-^scalar Address

scalar (initiate a fetch of

array subscript operand in the instruction)
string /string tyt>e\
----- 5---MS length iHW:- 4 binary stririg or BCD string

string - string type \ v. y v(initiate a fetch of the

L i . a u ? 3. i. ? ------ 7
U w i i U i. L U ?

array length |HW^/ subscript operand in the instruction)

i^. viiiiLidcs
(initiate a reicn
fetch or
of rieia.
field select. ^J ,
byte in the instruction) [Discriptor
Tpr

retch another descriptor

arr av initiate a retcn ,

^•/unit ! tof the subscriot-i ^lerr.ent
.
I\Length____ jHWf' Discriotc-
structure operand m tne
instruction)

array maximum
lement |
structure
with limit
check

i
 Final Design Specification for the M C S 65 E 4 Microprocessor

4 *6 ♦ 3 *2 ♦ 4 D a t a Type Field ( hits 5 - 2) arid F 1 a d (hit 6)

The D a t a T y p e F i e l d and the FI a 5 o p e r a t e t o g e t h e r to s p e c i f y the

exact nature of th e d a t a f i e l d * The D f i e l d s p e c i f i e s the s i z e of
the f i e l d and the t y p e of d a t a s t o r e d in the f i e l d as f o l l o w s ;

* * * * Bit * * * *
5 4 3 9 Data Ty p e

0 0 0 0 Not Used (Reserved fo r future expansion)

0 0 o 1 B y t e (BYT) < --- f < - — ----- [

0 0 1 0 O r d i n a l (ORD) 3 1
0 0 1 1 T w o - B y t e I n t e g e r (21) C B D E
0 1 0 0 F o u r - B y t e I n t e d e r (41) A A A L
0 1 0 1 E i d h t - B y t e I n t e d e r (31) L S T E
0 1 1 0 F o u r - B y t e Real (4R) E I A M
0 1 1 1 E i d h t - B y t e Real (SR) R C E
1 0 0 0 Ten B y t e Real (10 R ) 1 T
1 0 0 1 F o u r - B y t e BCD (4D) 1 S
1 0 1 0 E i d h t - B y t e BCD (SD) < --- ! !
i
1
1 0 1 1 S t r i n d (S T R ) < ---------- ----- j

1 1 0 0 Deferred Descriptor/Record

1 1 0 1 Array Structure

1 1 1 0 N ot Used (Reserved f or future Expansion)

1 1 1 1 Not Used (Reserved for future Expansion)

For the first 11 i t e m s in this t a b l e (b yte throudh string) >

s e t t i n g the F L A G to a I o d i c 1 s p e c i f i e s t h a t the d a t a f i e l d is an
e l e m e n t in a s i n g l e d i m e n s i o n array* In t h i s case? the p r o c e s s o r
wil l f e t c h the n e x t o p e r a n d f r o m the i n s t u c t i o n and u se the v a l u e
as the i n d e x i n f o r m a t i o n to d e t e r m i n e the l o c a t i o n of the d a t a in
the a r r a y * If the F L A G is a Iodic 0/ t he d e s c r i p t o r points
d i r e c t l y to the d a t a f i e l d *

If the Data Type field s p e c i f i e s that the d a t a f i e l d is an a r r a y

structure <D=1101)> the F L A G is used to enable and disable
automatic check in d of the i n d e x c o n t a i n e d in the i n s t r u c t i o n to
assure that it is not less t h a n 0 or dreater than the m a x i m u m
v a l u e s p e c i f i e d in the d e s c r i p t o r * If the D a t a T y p e f i e l d c o n t a i n s
a binary 1100 ( D e f e r r e d D e s c r i p t o r / r e c o r d ) f t he F L A G is u s e d to
s e l e c t b e t w e e n the D e f e r r e d D e s c r i p t o r arid the R e c o r d *

The f o l l o w i n d table summarizes the u se of the FLAG bi t within the

descriptor header!

Data Type FLAG Value Definition

j------------ -----I--------------- l------- ---------------------- I
I Byte I 0 I Descriptor Access i

*********CQNFIDENTIAL> MOS T E C H N O L O G Y ,INC ** * * * * * * * * F'ade- 74

 Final Design Specification for the MC S65 E 4 Microprocessor

i through 1- 1------------------------------ 1
1 String 1 1 1 Array Access 1
i — 1— — 1— — —— 1
1 1 0 i No R a n g e C h e c k i n g i
1 Array 1-- „ 1------------------------------ |
1 Structure ! 1 1 P e r f o r m R a n g e C h e c k in g i
1 _ _ 1— . — _ —
1 —
1 _ ______ _ — __ _
—_ _
—_ __ 1
1
1 Deferred 1 0 1 R e c 0r d 1
1 Descriptor !-- 1------------------------------ |
I or r e c o r d I 1 I Deferred Descriptor 1
1----------------- 1-- „ 1------------------------------ j

T he dsts type c l a s s i f i c a t i o n s depicited above can be organized

int o t h r e e g r o u p s * The f i r s t g r o u p c o n t a i n s all of the b a s i c d a t a
elements which are the d a t a f i e l d s t h a t are o p e r a t e d u p o n by all
of the d a t a m a n i p u l a t i o n i n s t r u c t i o n s * The e l e m e n t s in t h i s g r o u p
are i d e n t i f i e d by a 0001 t h r o u g h 1011 in the D a t a T y p e f i e l d (byte
through string)* The s e c o n d g r o u p c o n t a i n s all of the s i m p l e d a t a
structures (arrays ? r e c o r d s ? e t c * ) ? w h i l e the t h i r d c o n t a i n s the
Deferred Descriptor*

The s e a u e n c e of operations which the M C S65E4 goes through to

access 3 basic data e l e m e n t is shown below ( r e f e r to the f l o w
d i a g r a m - the s e a u e n c e n u m b e r s c o r r e s p o n d s to the d i a g r a m ) *

1* Th e p r o c e s s o r a c c e s s e s the d e s c r i p t o r block.
t h r o u g h any of the M C S 6 5 E 4 a d d r e s s i n g m o d e (see s e c t i o n
_____ .)* Set Y = the address f o l l o w i n g the addressing
information*

2* A c h e c k is m a d e to d e t e r m i n e w h e t h e r t he d e s c r i p t o r
i n d i c a t e s an b a s i c d a t a type* If it is not? the p r o c e s s o r
c o n t i n u e s to d e t e r m i n e the d e s e c r i p t o r ' s type*

3* If the d e s c r i p t o r i n d i c a t e s b a s i c d a t a type? the M C S 6 5 E 4

gets the addressing information from the descriptor
block.*

4 * The a d d r e s s i n g i n f o r m a t i o n and t he a c c e s s m o d e b i t s
together determine the s t a r t i n g a d d r e s s of the raw data*
(In the f l o w d i a g r a m ? t h i s c a l c u l a t e d a d d r e s s is s a v e d in
v a r i a b l e Y - an i n t e r n a l r e g i s t e r * F o r a t t a c h e d mode? Y =
Y + 0* For r e l o c a t a b l e mo de? Y = Y + r e l a t i v e * For
l o g i c a l mode? Y = the p h y s i c a l a d d r e s s * )

10* A c h e c k is m a d e to d e t e r m i n e if the b a s i c
d a t a is of t y p e s t r i n g * If it is? the n e x t two b y t e s are
fetched from the i n s t r u c t i o n and are u s e d as the string
length*

11* If the b a s i c d a t a t y p e is not t y p e s t r i n g

the l e n g t h is d e t e r m i n e d by the d a t a type* The l e n g t h can be
e i t h e r 1? 2? 3? 4? S? or 10 b y t e s *

** * ** * * * *C0NFIDENTIAL? MOS T E C H N O L O G Y ? INC ** * * * * * * * * Page- 75

POINT TO
DESCRIPTOR BY
OPERAND CONTROL
BYTE PLUS OFFSET

(i0s)
 Final Design Specification for the M CS 6 5 E 4 Microprocessor

4*6*4 The Data Structures

4 * 6 *4*1 I n t r o d u c t i o i"j

In a d d i t i o n to the s i m p l e data fields described previously? the

MC S6 5E4 directly supports the s t o r a g e of d a t a in a number of
s i m p l e d a t a s t r u c t u r e s * T h e s e aret

1* Single-dimension arrays
2* Array Structures
3* Records

In a d d i t i o n ? t h e s e s t r u c t u r e s can be o r g a n i z e d into c o m p l e x d a t a
s t r u c t u r e s such as m u l t i - d i m e n s i o n a l arrays? a r r a y s of r e c o r d s ?
etc* The s i m p l e d a t a s t r u c t u r e s are d e s c r i b e d in t h i s s e c t i o n * The
m a n n e r in w h i c h t h e s e s i m p l e d a t a s t r u c t u r e s c a n be u s e d to b u i l d
the c o m p l e x d a t a s t r u c t u r e s is b e s t i l l u s t r a t e d by e x a m p l e *

4*6*4*2 Single-Dimension Arrays

The s i n g l e - d i m e n s i o n a r r a y is the s i m p l e s t of th e d a t a s t r u c t u r e s
w h i c h are d i r e c t l y s u p p o r t e d by the M C S 6 5 E 4 * T h i s is s e l e c t e d by
s e t t i n g the F L A G b it in the v a r i a b l e d e s c r i p t o r to a l o g i c 1* The
p r o c e s s o r then a s s u m e s t h a t the s c a l a r or s t r i n g w h i c h is to be
m a n i p u l a t e d by the i n s t r u c t i o n is an e l e m e n t of an ar r a y * To
a c c e s s this element? the p r o c e s s o r f e t c h e s an i n d e x from the
instruction*

The s e q u e n c e of operations which t he MCS65E4 goes through to

a c c e s s an element within a single dimension a r r a y is as f o l l o w s :
( r e f e r to the f l o w d i a g r a m - the s e a u e n c e n u m b e r s c o r r e s p o n d s to
the d i a g r a m ) *

1* The p r o c e s s o r a c c e s s e s the d e s c r i p t o r block.

t h r o u g h any of the M C S 6 5 E 4 a d d r e s s i n g mode* Set Y = the
a d d r e s s f o l l o w i n g the a d d r e s s i n g i n f o r m a t i o n *

2* A c h e c k is m a d e to d e t e r m i n e w h e t h e r t he d e s c r i p t o r
indicates single dimesion array* If it is not? the
p r o c e s s o r c o n t i n u e s to d e t e r m i n e the d e s e c r i p t o r ' s t ype *

3* If the d e s c r i p t o r i n d i c a t e s s i n g l e d i m e n s i o n a r r a y ( F L A G = 1 ) ?
t he M C S 6 5 E 4 gets the addressing information from the
descriptor block *

4* The a d d r e s s i n g i n f o r m a t i o n a n d the a c c e s s m o d e b i t s
together determine the s t a r t i n g a d d r e s s of the raw da t a
for the f i r s t e l e m e n t of the a r r a y (In the f l o w d i a g r a m ?
this calculated address is s a v e d in variable Y - an
internal register* Fo r a t t a c h e d m ode ? Y = Y + 0* For
r e l o c a t a b l e mo d e ? Y = Y i r e l a t i v e * For l o g i c a l mode? Y =
the p h y s i c a l a d d r e s s * )

5* To d e t e r m i n e w h i c h e l e m e n t in the a r r a y to a c c e s s ?
the p r o c e s s o r fetches the d a t a specified by the next

*********C0NFIDENTIAL? MOS T EC H N O L O G Y ? I N C * ********* Page- 77

 Final De s i g n Specification for the MC S6 5E 4 Microprocessor

o p e r a n d in the instruction* This d a t a is t r e a t e d as the

i n d e x (In the flow d i a g r a m this value is r e f e r r e d as
variable I ) *

10* A check, is m a d e to d e t e r m i n e if the b a s i c

d a t a is of t y p e s t r i n 3 ♦ If it is? the n e x t two b y t e s are
fe t ched from th e i n s t r u c t i o n and are used as the s t r i n g
length *

11* If the b a s i c d a t a t y p e is n o t t y p e s t r i n g
the l e n g t h is d e t e r m i n e d by the d a t a typ e * The length can be
e i t h e r 1? 2? 3? 4? 8? or 10 b y t e s *

8* The e l e m e n t l e n g t h (EL)? the i n d e x v a l u e (I)? and the

previous calculated a d d r e s s (Y) ar e u s e d to a d d r e s s the
sought after element w i t h i n the array structure* The
f o r m u l a for the a d d r e s s c a l c u l a t i o n is Y = Y + (I I EL)*
Note that the l o c a t i o n of t h i s e l e m e n t can be d e t e r m i n e d
without regard for t he exact nature of the data being
s t o r e d in the a r r a y *

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C **** * ** * * * Page- 78

 :POINT TO DESCRIPTOR.
|3Y OPERAND CONTROL ;
START — '■ ■■ IgYTE PLUS OFFSET

CONTINUE TO \
DETERMINE SINGLE '
DESCRIPTOR DIMENSION sC 2
rTTV D ‘P

ADDRESSING /'T
INFO FROM
DESCRIPTOR!

jPOINT TO
jBEGINNING 1
OF NEW
^ATA

SET NEXT
3YTE FRCM
ENSTRUCTI:
cn
■OR INDEX
S .

GET NEXT 2
BYTES FOR
LENGTH BUILT STRING LENGTH
INTO DATA TYPE
CAN BE EITHER:
1,2,3,4,8 or 10
BYTES

POINT TO RAW
DATA BY
Y=Y+I*EL

---------
EONE
 Final D e sign Specification for the MCS65E4 Hicroprocessor

4♦6♦4♦3 Array Structure

In addition to the simple array described in the previous

paragraph? the M C 3 6 5 E 4 s u p p o r t s the s t o r a g e of d a t a in a r r a y s in
which elements can be m o r e t h a n the b a s i c d a t a e l e m e n t s * T h i s is
t e r m e d the 'array s t ructure" arid is s e l e c t e d by s e t t i n g the D a t a
T y p e to 1101 ( b i n a r y ) *

W h e n an array structure is specified? the d e s c r i p t o r header

c o n t a i n s no i n f o r m a t i o n r e g a r d i n g the t y p e of d a t a w h i c h is s t o r e d
in the array* Instead? t h i s is c o n t a i n e d in the a u x i l i a r y data
field which f o l l o w s the addressing information* Also? w h e n F L A G
eauals 0 ( i *e * no l i m i t c h e c k i n g ) ? the m a x i m u m i n d e x f i e l d w i t h i n
the a r r a y d e s c r i p t o r block, is o m i t t e d *

The f o r m a t for the descriptor block? w i t h 3nd without limit

checking? which r e f e r e n c e s an a r r a y s t r u c t u r e is s h o w n b e l o w :

-----j
I i i I
(T)1 1 I 1 1 0 1 1 (M) I -- Descriptor Header
1 I 1 I
i
1
Addressing I
Information 1
1
----- j 1
Element* 1 I#
Length i A n*
---- - j u F
Maximu m ! x 0
In d e x 1 i r
----- j 1 m
1 i a
Element 1 a t
Discriptor 1 r i
1 y o
1 n
— ---I 1

Array Descriptor Block (with limit checking field)

----- I
i S 1 1
(T)1 0 1 1 1 0 1 1 (M) i < -- — Descriptor Header
! I I i
-----i

Addressing
Information

*********C0NFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * P ag e - 80

 Final Design bpecification for *th 0 M C S 6 5 E 4 Hie pop rocessor

1 Element i !
1 Length I 1
... 1 i
1 Auxiliary
1 Element 1 I n f 0 r m a t i 0n
I Descriptor ! 1
1 1
1 i

Array Descriptor Block (without limit checki ng fi e l d )

*********CONFIDENTIAL> MOS T E C H N O L O G Y rI N C * * * # * * # * * * P age-

 Final D e s i d n Specifi c a t i o n for the MCS 6 5 E 4 Microprocessor

The f o r m a t of the Descriptor Header in the Variable Descriptor

m u s t be as d e s c r i b e d in P a r a g r a p h 4 * 6 * 3 * 2 w i t h the D a t a T y p e f i e l d
set to 1101* The a c t u a l d a t a w i t h i n the a r r a y is a c c e s s e d t h r o u g h
the a d d r e s s i n g i n f o r m a t i o n of the d e s c r i p t o r block.* N o t e t h a t the
attached mode is not v a l i d for the array s t r u c t u r e si nee the
actual array data can not immediately follow the descriptor
header*

The f i r s t item in the a u x i l i a r y d a t a is the E l e m e n t L e n s t h * T h i s

field specifies the n u m b e r of b y t e s in e a c h e l e m e n t of the a r r a y *
This i n f o r m a t i o n m u s t be c o m p a t i b l e w i t h the i n f o r m a t i o n c o n t a i n e d
in the e l e m e n t d e s c r i p t o r to a s s u r e p r o p e r a c c e s s i n g of the d a t a
in the a r r a y * The M a x i m u m I n d e x f i e l d is u s e d to check, t h a t the
index c o n t a i n e d in the i n s t r u c t i o n d o e s not e x c e e d the b o u n d s of
the a r r a y * T h i s check, w ill o n l y be p e r f o r m e d if the F 1 a d f i e l d is
set to a I o d i c 1* The las t f i e l d in the d e s c r i p t o r is the a r r a y
element descriptor* T h i s is a n o r m a l Variable Descriptor which
s p e c i f i e s the f o r m a t of the a r r a y e l e m e n t * In d e n e r a l ? all of the
access modes? d a t a t y p e s ? etc* are p e r m i t t e d in t hi s d e s c r i p t o r *
H o w e v e r ? the o p e r a t i o n of the a d d r e s s a c c e s s i n g m o d e s is d i f f e r e n t
f r o m t h a t d e s c r i b e d a b o v e for the n o r m a l V a r i a b l e D e s c r i p t o r (i*e*
the a t t a c h e d m o d e b e c o m e s a t t a c h e d r e l o c a t a b l e and s h o r t and land
relative becomes s h o r t arid 1 ond r e l o c a t a b l e r e s p e c t i v e l y ) T h i s is
specifically designed to f a c i l i t a t e the d i r e c t s u p p o r t of c o m p l e x
data s t r u c t u r e s (multi-dimensional arrays? a r r a y s of records?
etc* ) * If the l o d i c a l addressind access m o d e is s p e c i f i e d ? the
specified lodical address replaces the previous address
calculated*

The s e a u e n c e of operations which the MCS65E4 does throudh to

access a raw d a t a item w i t h i n an a r r a y s t r u c t u r e is as f o l l o w s
( r e f e r to the f l o w d i a d r a m b e l o w t h r o u d h o u t the d i s c u s s i o n - the
s e a u e n c e n u m b e r s c o r r e s p o n d to the d i a d r a m ) t

1* The p r o c e s s o r a c c e s s e s the a r r a y d e s c r i p t o r b l o c k (A D B )
t h r o u d h any of the M C S 6 5 E 4 a d d r e s s i n d mode* Set Y = the
a d d r e s s f o l l o w i n d the a d d r e s s i n d i n f o r m a t i o n *

2* A check, is m a d e to d e t e r m i n e w h e t h e r t he d e s c r i p t o r
i n d i c a t e s an a r r a y s t r u c t u r e * If it is not? t he p r o c e s s o r
c o n t i n u e s to d e t e r m i n e the d e s e c r i p t o r ' s t y pe*

3* If the d e s c r i p t o r i n d i c a t e s a r r a y s t r u c t u r e ? the M C S 6 5 E 4
dets the addressind information from the descriptor
block.*

4* The a d d r e s s i n d i n f o r m a t i o n and t h e a c c e s s m o d e b i t s
todether determine the s t a r t i n d a d d r e s s of the raw d a t a
f or the f i r s t e l e m e n t of the a r r a y (In the f l o w d i a d r a m ?
this c a l c u l a t e d address is s a v e d in variable Y - an
internal redister* F o r a t t a c h e d mode? Y = Y + 0* For
r e l o c a t a b l e m ode? Y = Y + r e l a t i v e * F o r l o d i c a l mode ? Y =
the p h y s i c a l a d d r e s s * ) )♦ N o t e t h a t the a t t a c h e d m o d e is
n ot v a l i d for an array structure s i n c e the a c t u a l raw
d a t a d o e s not f o l l o w the d e s c r i p t o r h e a d e r *

*«******C0NFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Pade- 82

 Final Desi g n Specification for the M C S 6 5 E 4 M i c r o p r o c e s s o r

5 * To d e t e r m i n e w h i c h e l e m e n t in the a r r a y to a c c e s s ?
the p r o c e s s o r fetches the d a t a specified by the next
o p e r a n d in the i n s t r u c t i o n * T h i s d a t a is t r e a t e d as the
i n d e x (In the flow diag ra m this value is r e f e r r e d as
variable I ) *

6 * H o w e v e r ? b e f o r e the e l e m e n t is a c c e s s e d ? the M C S 6 5 E 4
d e t e r m i n e s if the i n d e x v a l u e is g r e a t e r t h a n or e a u a l to
z e r o and less t h a n or e a u a l to the maximum index value
c o n t a i n e d in the a r r a y d e s c r i p t o r * The check, w ill n ot be
p e r f o r m e d if F L A G e a u a l s z e r o (see s e c t i o n 4 * 6 * 3 * 2 * 3 * 4 ) *
If F L A G e a u a l s one in the d e s c r i p t o r h e a d e r 3nd the i n d e x
v a l u e is invalid? the p r o c e s s o r t e r m i n a t e s e x e c u t i o n of
t h e c u r r e n t i n s t r u c t i o n and wi l l e x e c u t e a t r a p s e a u e n c e *

7 * The p r o c e s s o r t h e n g e t s the e l e m e n t l e n g t h f r o m the

descriptor block* The element length (in the flow
diagram? t h i s v a l u e is r e f e r e d to as v a r i a b l e EL) w i t h i n
the a r r a y descriptor is the number of b y t e s of each
e l e m e n t in the a r r a y *

S* Th e e l e m e n t l e n g t h (EL)? the i n d e x v a l u e (I)? arid the

previous calculated a d d r e s s (Y) are u s e d to a d d r e s s the
sought after element w i t h i n the array structure* The
f o r m u l a for the a d d r e s s c a l c u l a t i o n is Y = Y + (I * EL)*
Note that the l o c a t i o n of t h i s e l e m e n t can be d e t e r m i n e d
without regard for the exact nature of t h e data being
s t o r e d in the a r r a y *

9* If th*e e l e m e n t d e s c r i p t o r s p e c i f i e s a b a s i c d a t a t y p e
(byte t h r o u g h string)? the p r o c e s s o r can process its
address information to get the a d d r e s s of the raw data*
O n c e the processor has the a d d r e s s of the raw data
element? it can p r o c e e d to m o v e the d a t a i n t o the chip*
If h o w e v e r ? the e l e m e n t d i s c r i p t o r is an a r r a y s t r u c t u r e ?
the a b o v e seauenee (3 t h r o u g h 9) w ill r e p e a t * When a
basic data e l e m e n t is e n c o u n t e r e d ? o n l y 3 and 4 wi l l be
p e r f o r m e d to f e t c h the d a t a f i e l d * In b o t h c a s e s ? 4 h a s a
d i f f e r e n t m e a n i n g s i n c e Y n o w c o n t a i n s the a d d r e s s to the
b a s e of t he a r r a y * T h e r f o r e ? a t t a c h e d m o d e (in t h i s c a s e
c a l l e d the a t t a c h e d r e l o c a t a b l e m ode) is u s e d to a c c e s s
t he f i r s t e l e m e n t of the array* R e l a t i v e m o d e (in t h i s
case called s h o r t or long r e l o c a t a b l e m ode) now c o n t a i n s
the the o f f s e t f r o m p r e v i o u s l y c a l c u l a t e d a d d r e s s i n s t e a d
of t h a t of the d e s c r i p t o r *

* * * * * * * * * C O N F I D E N T I A L ? MOS TECHNOLOGY?INC* ********* Page- 83

 j POINT TO ARRAY ADI \
"7
START j DESCRIPTOR SLOCK
j (AD3) 3Y OPERAND ! A^ ^ a c c ir>T
!: '
■j-
I CONTROL BYTE PLUS ^ |inrormation
! OFFSET
cr-rh
;Ele. Uw,i3

fM ax COptional]
;T1 .O .
Descrio j
t
J

Addr’ Info.
!
Ele Length

Max (Optional
i
j Desr •
i
!

Array
Descriptor
Block

©Attached Mode
not allowed here
 Final De s ig n Specification for the M C S 6 5 E 4 Microprocessor

4 *6 * 4 * 4 R e c o r d

A record consists of a n u m b e r of related b ut d i s s i m i l a r data

fields which are o r g a n i z e d into a s i n g l e d a t a s t r u c t u r e * W h e n the
MCS65E4 encounters a record descriptor during an instruction
executioni it f e t c h e s the n e x t b y t e of d a t a f r o m the i n s t r u c t i o n *
T h i s is a s s u m e d to be an o f f s e t f r o m the f i r s t f i e l d d e s c r i p t o r to
a field descriptor* The f i e l d descriptor then provides the
information reauired to a c c e s s the raw d ata* The f o r m a t of the
R e c o r d D e s c r i p t o r is as f o l l o w s t

Descriptor
Header

Addressing
Information

Field Descriptor
F i e l d *1

Field Descriptor
F i e l d *2

Field D e scriptor
F i e l d *3

As w i t h all V a r i a b l e Descriptors? th e r e c o r d d e s c r i p t o r begins

with a Header* The D a t a T y p e f i e l d m u s t be 1100 ( b i n a r y ) and the
f l a g m u s t be a l o g i c 1* The A c c e s s M o d e f i e l d c an be e i t h e r of the
r e l a t i v e m o d e s or the l o g i c a l a d d r e s s i n g m ode* The a t t a c h e d A c c e s s
M o d e is n o t s u p p o r t e d f or the s a m e r e a s o n m e n t i o n e d a b o v e for the
array structure* Therefore? the a d d r e s s i n g i n f o r m a t i o n is not
o p t i o n a l in the R e c o r d D e s c r i p t o r *

The f o r m a t of the F i e l d D e s c r i p t o r is e x a c t l y like t h a t of the

normal Variable Descriptor* H o w e v e r ? t he o p e r a t i o n of the o f f s e t
and logical addressing access modes is different from tha t
described above for th e n o r m a l V a r i a b l e D e s c r i p t o r arid s i m i l a r to
that described for the V a r i a b l e D e s c r i p t o r * T h i s is s p e c i f i c a l l y
designed to facilitate the direct support of complex data

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Page- 85

 Final Design Specification for the MC S65 E 4 Microprocessor

s t r u c t u r e s ( mu 1 1 i - d i m e n s i o n a 1 a r r a y s ? a r r a y s of r e c o r d s * etc ♦ ) ♦ If
the s h o r t or long r e l o c a t a b l e o f f s e t is s p e c i f i e d in the f i e l d
descriptor? the o f f s e t will be added to the p r e v i o u s address
calculated* If the attached relocatable addressing mode is
specified? t h e n z e r o is a d d e d to the p r e v i o u s a d d r e s s c a l c u l a t e d *
I t the l o g i c a l a d d r e s s i n g a c c e s s m o d e is s p e c i f i e d ? the s p e c i f i e d
logical address r e p l a c e s the p r e v i o u s a d d r e s s c a l c u l a t e d * T h i s is
i l l u s t r a t e d in d e t a i l in the e x a m p l e s b e l o w *

The s e a u e n c e of operations which the M C S 6 5 E 4 goes through to

access a raw d a t a item w i t h i n a r e c o r d s t r u c t u r e is as f o l l o w s
( r e f e r to the f l o w d i a g r a m b e l o w t h r o u g h o u t the d i s c u s s i o n - the
s e a u e n c e n u m b e r s c o r r e s p o n d to the d i a g r a m ) !

1* The p r o c e s s o r a c c e s s e s the record descriptor

b l o c k (RDB) t h r o u g h a n y of the M C S 6 5 E 4 a d d r e s s i n g modes*

2* A c h e c k is m a d e to d e t e r m i n e w h e t h e r the d e s c r i p t o r
i n d i c a t e s a r e c o r d s t r u c t u r e * If it is not? t he p r o c e s s o r
c o n t i n u e s to d e t e r m i n e the d e s e c r i p t o r ' s t ype*

3* If the d e s c r i p t o r i n d i c a t e s a r r a y s t r u c t u r e ? the M C S 6 5 E 4
gets the addressing information from the descriptor
block*

4* The a d d r e s s i n g i n f o r m a t i o n arid the 3 c c e s s m o d e b i t s

together determine the s t a r t i n g a d d r e s s of the raw d a t a
f or the first field* In the flow diagrsm? this
calculated address is s a v e d in v a r i a b l e Y - an i n t e r n a l
register* For a t t a c h e d mo d e ? Y = Y + 0* F or r e l o c a t a b l e
m od e ? Y = Y + relative* For l o g i c a l mode ? Y = the
physical address*

5* To d e t e r m i n e w h i c h f i e l d w i t h i n the r e c o r d to a c c e s s ?
the p r o c e s s o r fetches the d a t a specified by the next
o p e r a n d in the i n s t r u c t i o n * T h i s d a t a is t r e a t e d as the
o f f s e t into the r e c o r d d e s c r i p t o r to o b t a i n the field
descriptor *

« * * * * * * * C 0 N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C * ** * ****** Page- 86

POINT TO RECORD
PH RECORD
DESCRIPTOR BLOCK
(RDB) 3Y OPERAND STRUCTURE -
. ..... .... fmmm'j
CONTROL BYTE PLUS ADDRESSING I
o n ,CTTrP
INFORMATION 1
....
rIELD
DESCRIPTOR 1 :
FIELD
^r'DTP'TPR ? *
RECORD
DESCRIPTOR I
J

• 1
Y

GET ADDRESSING
INFORMATION FROM
RECORD DESCRIPTOR

A
POINT TO b e g i n n i n g ;
OF RECORD's ROW
DATA. THIS IS j
OBTAINED BY ACCESSj
MODE BITS, AND 1
ADDRESS INFORMATION
hvj ETELD___________ !

GET FIELD
 Final Design Specification for the MCS65E4 Micros

Thi s p-3^e intentionally left blank

*********CONFIDENTIAL> MOS TECHNOLOGY? INC.***#*****

 Final De s i g n Specification for the MC 36 5E 4 Microprocessor

4*6*5 Deferred Descriptor

The d e f e r r e d d e s c r i p t o r c o n t a i n s no i n f o r m a t i o n r e d a r d i n d t h e t y p e
of d a t a w h i c h is s t o r e d in the d a t a f i e l d w h i c h is to be a c c e s s e d
by the i n s t r u c t i o n * For t h i s r e a s o n * the d e f e r r e d d e s c r i p t o r d o e s
not d i r e c t l y re f e r to the raw d a ta* I n s t e a d ? it p o i n t s to a n o t h e r
d escriptor which can c o n t a i n d a t a t y p e i n f o r m a t i o n * It s h o u l d be
rioted t h a t this second descriptor is e x a c t l y the s a m e as any
variable descriptor ( i * e * ? t he s e c o n d d e s c r i p t o r c o u l d v e r y well
be a n o t h e r deferred descriptor)* In all c a s e s ? it is n e c e s s a r y
that the p r o c e s s o r e n c o u n t e r d a t a t y p e i n f o r m a t i o n b e f o r e raw d a t a
can be fetched from memory* The o p e r a t i o n of the deferred
d e s c r i p t o r is i l l u s t r a t e d in F'arsraph 4 * 6 * 6 * 4*

A summary of all th e data types is depicted belowt

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * P a3 e - 89
 Final D e sign Specification for the MC S6 5E 4 Microprocessor

4+6*6 Application of the MCS65E4 Data Accessing Mechanisms

4 *6 *6 * 1 I n t r o d u c t i o n

The dat a a c c e s s i n g m e c h a n i s m s d e s c r i b e d a b o v e are u s e d t h r o u g h o u t

the M C S 6 5 E 4 architecture for s t o r i n g raw data ^ array indexes ?
exception vector a d d r e s s e s ? etc* For t h i s r e a s o n ? t h e y are a v e r y
i m p o r t a n t k ey to u n d e r s t a n d i n g the o p e r a t i o n of this p r o cessor*
Therefore? a n u m b e r of e x a m p l e s of d a t a s t r u c t u r e s are d e s c r i b e d
in d e t a i l below* It is h o p e d t h a t t h e s e w ill c o n t r i b u t e to the
readers understanding of the m a n n e r in w h i c h d a t a is s t o r e d arid
a c c e s s e d w i t h i n the M C 3 6 5 E 4 s y s t e m *

4*6*6*2 Accessing Data in Multi-Dimensional Array Structures

T he m a n n e r in w h i c h th e data st orage and a c c e s s i n g techniaues

described above c a n be e x t e n d e d to c o n t r o l the a c c e s s i n g of d a t a
in c o m p l e x a r r a y s t r u c t u r e s can be d e s c r i b e d m o s t e f f e c t i v e l y by
r e v i e w i n g the s e a u e n c e of o p e r a t i o n s w h i c h tak.es p l a c e w h e n the
MCS65E4 encounters the A r r a y D e s c r i p t o r * As d e s c r i b e d p r e v i o u s l y ?
the a d d r e s s i n g i n f o r m a t i o n c o n t a i n e d in the d e s c r i p t o r s p e c i f i e s
the a d d r e s s of the f i r s t e l e m e n t in the a r r a y b e i n g a c c e s s e d * The
element length information contained in the d e s c r i p t o r is th e n
c o m b i n e d w i t h the n e x t o p e r a n d in the i n s t r u c t i o n to d e t e r m i n e the
l o c a t i o n of the a r r a y e l e m e n t b e i n g a c c e s s e d *

After the physical address of the array element has been

determined? the p r o c e s s o r t h e n r e f e r e n c e s the e l e m e n t d e s c r i p t o r
to d e t e r m i n e the m a n n e r in w h i c h the e l e m e n t is to be p r o c e s s e d *
As noted above? the format for the element descriptor is
e s s e n t i a l l y the same as for any of the normal descriptors*
Specifically? t h i s m e a n s t h a t the e l e m e n t d e s c r i p t o r can s p e c i f y
any of the n o r m a l d a t a t y p e s s u c h as the s c a l e r (byte? o r d i n a l ?
real? etc*)* E v e n m o r e i m p o r t a n t is the fact t h a t the element
d e s c r i p t o r can s p e c i f y th a t the e l e m e n t is a s i m p l e array? an
a r r a y s t r u c t u r e ? or a r e c o r d * T h i s is t he key to a c c e s s i n g c o m p l e x
d a t a s t r u c t u r e s in the M C S 6 5 E 4 s y s t e m *

The o p e r a t i o n of the e l e m e n t d e s c r i p t o r can be i l l u s t r a t e d by

e x a m i n i n g the m a n n e r in w h i c h the M C S 6 5 E 4 w o u l d a c c e s s d a t a in a
simple 3 X 4 t w o - d i m e n s i o n a l a r r a y ( t e r m e d D A T A ( X ? Y ) b e l o w ) * The
t w e l v e e l e m e n t s in t h i s a r r a y w o u l d be s t o r e d in c o n t i g u o u s m e m o r y
l o c a t i o n s as f o l l o w s *

* * * * * * * * * C G N F I D E N T I A L , MOS T EC H N O L O G Y ? I N C * ********* Page- 91

 Final De s ig n Specification for the MC3 65 E 4 Microprocessor

H i5 h - order Memory

(3*4)

( 3 *2 )

(3*1)

(2/4)

(2^3)

(2 *2 )

(2*1)

(1*4)

(1*3)

(1*2)

( 1* 1) Address of array

Low-Order Memory

To c r e a t e the d e s c r i p t o r fo r t h i s a r r a y * the s t r u c t u r e m u s t be
v i e w e d 3s a s i n g l e - d i m e n s i o n a r r a y in w h i c h each elem e nt conta in s
four data f i e l d s * T h i s can be i l l u s t r a t e d as follows}

Full Array* Sirid 1 e - D i m e n s i o n Depiction*

! I I 1
IHidh-order Memory! 1H i d h - o r d e r m e m o r y !
1 1 1 I
j----------- ---- ------j 1 _ ___ !
1 (3*4) I 1 1
i — i
i (3*3) I ! Element !
j„ ------------------------ ------------------------------------------------------j
1- 3 -!
1 (3*2) I ! 1
i
i —
— — i
i
1 (3,1) 1 1 !
1
1
— — !
! i
i — — i
i
1 (2*4) 1 1 1
j ----------------------------------------------------------------------------------- j j- - j

* * * * * * * * * C G N F I D E N T I A L f MQS T E C H N O L O G Y * INC * ********* Fade- 92

 Final D e sign Specification for the M C3 6 5 E 4 Microprocessor

1 (2 ? 3 ) i 1 Element 1
j--------------------- |
1 (2 ? 2 ) I 1 " j
i--------------------- j
1 (2? 1 ) 1 i i
i — — i i— — i
1 (1,4) i ! I
1— — ———— —1
1 <1,3) 1 1 Element 1
1--------------------- | 1- 1 -J
1 (1,2) 1 1 1
1 — — —— 1
1 (1,1) 1 I 1
I — — —— I \— — — — _ i
i \ i i
ILow-Order Memory 1 IL o u - o r d e r Memory 1
1 1 1 1

The d e s c r i p t o r w h i c h s p e c i f i e s the f o r m of t h i s s i n g l e - d i m e n s i o n
array must contain an e l e m e n t length which is four times the
a c t u a l e l e m e n t s i z e * F or e x a m p l e ? if the raw d a t a is t e n b y t e real
t h e n the e l e m e n t l e n g t h in the a r r a y d e s c r i p t o r w o u l d be f o r t y * I f
the i n d e x is to be c h e c k e d for m a x i m u m si ze? the d e s c r i p t o r m u s t
s p e c i f y 3 as the m a x i m u m for the f i r s t i n d e x into the a r r a y * U s i n d
the p r o c e d u r e s d e s c r i b e d a b o v e ? the M C S 6 5 E 4 will f i r s t u t i l i z e the
addressing; e l e m e n t s i z e arid i n d e x i n f o r m a t i o n to d e t e r m i n e the
location of an element in this single-dimension ar ra y * For
instance? if the instruction references element (2?3) in the
a r r a y ? the p r o c e s s o r will f i r s t d e t e r m i n e the a d d r e s s of e l e m e n t 2
in the s i n g l e - d i m e n s i o n a r r a y by e v a l u a t i n g the f o l l o w i n g f o r m u l a *

Physical Address = ( C o n t e n t s of S p e c i f i e d B a s e Register)

+ (Array Address) i (Element Size * Index)

Motet * = multiplication

After this o p e r a t i o n is complete? the M C S 6 5 E 4 b e d i n s p r o c e s s i n g

the e l e m e n t descriptor* T h i s o p e r a t i o n is v e r y s i m i l a r to n o r m a l
descriptor processing except that the Relative arid Attached
addressing becomes short and lond relocatable as r e a u i r e d for
a cc es si n g data in the array structures* R a t h e r t h a n a d d i n s the
d i s p l a c e m e n t to the address of the descriptor? the p r o c e s s o r
instead adds it to the a d d r e s s w h i c h was d e t e r m i n e d d u r i n g the
previous phase of the a d d r e s s i n g s e a u e n c e in progress* In the
example above ( a c c e s s i n g e l e m e n t (2?3) in the a r r a y ) ? the a d d r e s s
d e t e r m i n e d d u r i n g the f i r s t p h a s e of the a d d r e s s i n g s e a u e n c e w o u l d
be that of e l e m e n t (2?1) in the 3 r r a y * T h i s c o r r e s p o n d s to e l e m e n t
2 in the s i n g l e - d i m e n s i o n d e p i c t i o n i l l u s t r a t e d a b o v e *

For the 3 X 4 two-dimensional array described previously? there

are two m e t h o d s w h i c h c o u l d be u t i l i z e d for s p e c i f y i n g the e l e m e n t
descriptor* If e a c h e l e m e n t in the t o t a l a r r a y is a s c a l a r and if
no i n d e x c h e c k i n g is r e a u i r e d ? the e l e m e n t d e s c r i p t o r C 3 n s p e c i f y
t h a t e a c h e l e m e n t in the s i n g l e - d i m e n s i o n a r r a y is a s i m p l e s c a l e r
array* If i n d e x c h e c k i n S is d e s i r e d ? t h e n the e l e m e n t d e s c r i p t o r
m u s t s p e c i f y t h a t e a c h e l e m e n t of the s i n g l e - d i m e n s i o n a r r a y is an

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Fade- 93

 Final Design Specification for the M C 3 6 5 E 4 M i c r o p r o c e s s o r

array structure* This element descriptorwould then contain a

second element descriptor which would s p e c i f y the ex act data type
f or the array element*

The a b o v e discussion becomes somewhat confusing b e c a u s e of the

" l e v e l s " w h i c h the p r o c e s s o r m u s t go t h r o u g h d u r i n g the a d d r e s s i n g
sequence* T h i s can be i l l u s t r a t e d m o r e c l e a r l y by c o n t i n u i n g the
exa mp le from above* M o s t i m p o r t a n t l y ? the r e a d e r m u s t u n d e r s t a n d
the f a c t t h a t d u r i n g the i n i t i a l p r o c e s s i n g of the d e s c r i p t o r ? the
MCS65E4 views this two-dimensional array as a single-dimension
array structure* This 'first-level' of a d d r e s s i n g allows the
p r o c e s s o r to a c c e s s a r r a y e l e m e n t s in s e t s of fo u r (for e x a m p l e ?
(2 j 1 ) ? ( 2 > 2 ) ? (2? 3) arid ( 2 * 4))* The e l e m e n t d e s c r i p t o r w i t h i n t h i s
array descriptor must t h e r e f o r e c o n t a i n the i n f o r m a t i o n r e a u i r e d
for a c c e s s i n g t he " s e c o n d l e v e l * ? i * e * ? for d e t e r m i n i n g the e x a c t
l o c a t i o n of the desired element w i t h i n the groups which are
accessed during the f i r s t le vel* The t o t a l d e s c r i p t o r for the
example above ( a s s u m i n g i n d e x c h e c k i n g is r e a u i r e d and t h a t e a c h
e l e m e n t of the a r r a y c o n t a i n s a byte data typ e) w o u l d t h e r e f o r e
be :

* * * * * * * * * C O N F I D E N T I A L , MOS T E C H N O L O G Y >I N C ♦* * * * * * * * * Page- 94

 Final De s i g n Specification for the M C365 E 4 Microprocessor

Low-Order Memory

Descriptor Header

Addressing
Information

Element Size 1

Max i murn In d e x V a 1 1
j e

Total I---- >

Array I Element
Descriptor I Descriptor
I I
I Descriptor Addressing
I for ' f i r s t Information
I 1 e ve 1 *
I element Element Size 2

Maximum Index Value

Element Descriptor
Header

Addressing
Information

High-order Memory

T h e r e are several important points which can be n o t e d from

this i l l u s t r a t i o n * The element descriptor's addressing
i n f o r m a t i o n in the p r e v i o u s e x a m p l e c an be e l i m i n a t e d s i n c e
attached addressing mode (in this case called attached
r e l o c a t a b l e mod e ) is u t i l i z e d * The p h y s i c a l a d d r e s s of ( 2 >3 )
0 GU3 1S ♦

( c o n t e n t s of s p e c i f i e d b a s e r e g i s t e r ) +
(base of a r r a y l o g i c a l a d d r e s s ) +
( e l e m e n t s i z e 1 * i n d e x 1) +
(element 2 addressing information) +
( e l e m e n t s i z e 2 * in d e x ) +
Data A d d r e s s i n g Infor m at io n

If this is a 3 X 4 array of 10 byte Reals? the address is

calculated 3S follows!

Data Address = Physical A d d r e s s of the base of array +

(40 * 1) + 0 + (10*2) 4-0

*********C0NFIDENTIAL> MOS T E C H N O L O G Y >I N C ♦*** ** * ** * P ag e - 95

 Final Desi g n Specification for the M C S6 5E 4 Microprocessor

™ Physical address of the base of array + 60

N o t e t ha t index 1 = 2 - 1 = i ? index 2 = 3 - 1 = 2♦ The e l e m e n t

addressing information e a u a l s 0 for a t t a c h e d m o d e and o f f s e t for
s h o r t or lend r e l o c a t a b l e * T h e r e is no way for the p r o c e s s o r to
d e t e r m i n e the t o t a l l e n g t h of the a r r a y d e s c r i p t o r * Thi s is the
reason that attached addressing is not valid in the first
D escriptor Header* Als o ? it s h o u l d be n o t e d t h a t the n e s t i n g of
the s e c o n d l evel d e s c r i p t o r in t o the f i r s t lev e l d e s c r i p t o r can be
e x t e n d e d to any level of complexity* T h i s m e a n s t h a t the s e c o n d
element descriptor s h o w n in t h i s d i a g r a m can? in fact? be a n o t h e r
array descriptor or even a record descriptor* In all ca s e s ?
however? c a r e m u s t be t a k e n to a s s u r e tha t the e l e m e n t l e n g t h be
specified properly arid t h a t all addressing be s p e c i f i e d in a
manner which allows the p r o c e s s o r to process each level of
addressing*

Low-Qrder Memory

Descriptor Header

Addressing
Information

Element Size

Maximum Index Value

Element Descriptor
Header

Addressing
EDI Information

Element Size
TAD
Maximum Index Value

Element Descriptor
Header

Ad d re s s i ng
Information
ED2
I Element Size
I
Maximum Index Value

Element Descriptor
ED3 for a r r a y e l e m e n t
* thi rd le v e l 1

High-order Memory

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * P ag e - 96

 Final Design Specification for the M C S65 E 4 Microprocessor

TAD t Total Array Descrip tor

EDI t E l e m e n t D e s c r i p t o r For First Level Element
ED 2 t E l e m e n t D e s c r i p t o r For Second Level Element
ED 3 t E l e m e n t D e s c r i p t o r For Third Level Element

4 * 6 *6 *3 E x a m p l e of Accessing Multi-Dimensional Array

For our n e x t e x a m p l e we a s s u m e we h a v e a F O R T R A N data area where

data within the a r e a can be a c c e s s e d e i t h e r as s i n g l e e i g h t - b y t e
integers or single four-byte reals through an eauvalence
statement* The d a t a in m e m o r y h as ' holes " in it (i * e ♦ the real or
i n t e g e r s are not c o n t i g u o u s ) * H o w e v e r ? the M C S 6 5 E 4 d e s c r i p t o r can
be s e t u p to be a b l e to a c c e s s the data properly (i*e* to b y - p a s s
the " h o l e s * )♦ A s s u m e we have a three d i m e n s i o n a l array? A? with
m a x i m u m d i m e n s i o n C 15 ? 10 ? 51 * The d a t a is s t o r e d s e a u e n t i s l l y as I
A(Q7Q?Q)? A(0?0?1)? ♦♦♦? A (0 ? 0 ? 4)
A (0 ?1? 0) ? A (0 ? 2 ? 0) ? ***? A (0 ? ? 7 4 )
A (1? 0 ? 0)? A (2 ? 0 ? 0)? ***? A (9 ? 0 ?0)

A(14?9?4) (without showing 'holes*)

Geometrically? the a r r a y c o n s i s t s of f i f t e e n planes where each

p l a n e c o n s i s t s of one 10 x 5 m a t r i x p l u s s o m e i m b e d d e d ' h o l e s ' * The
p l a n e is depicted below* Remember there are f i f t e e n of these
p l a n e s to f o r m a s o l i d g e o m e t r i c s t r u c t u r e *

j — ---------------J

I 5 byte 1
1 hole 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 1

1 hole real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 1

1 hole real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte i

I hole real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte i

I ho l e real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 1

1 hole real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 1

I hole real real real real real 1

1 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 1

1 hole real real real real real 1

1 4 byte ! 4 byte 1 4 byte 1 4 byte i 4 byte 1 4 byte 1

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ?INC * * ** * * ** * * Page- 97

 Final Desi g n Specification for the MC365E4 Microprocessor

hole I real I real I real I real I real

4 byte i 4 byte !
i 4 byte i 4 byte ! 4 byte t 4 byte
hole 1
i real i
1 real ! real i
1 real 1 real

4 byte 1 4 byte 1 4 byte ! 4 byte 1 4 byte 1 4 byte

hole 1 real 1 real 1
I real 1 real 1
! real

The descriptor for t h i s a r r a y is shown below with a description of

ho w each field is d e r i v e d *

Logical
Address

i — —-
1* 011FF0 1 T 1 I 0 1 1101 i 11 Define Array Structure
ii —
2* 1 56
ii I
1 34 Logical of raw data
ii — _____
— ——— — I
1 12
ii
3* I- F5 - Element Length
1
i ____
4♦ 1 T i 1 I 1101 1 01 lElement Descriptor (array)
i
i
5* 1 5 Short Relocatable Addressing
it ___
—
6♦ I- 9 - Maxi m urn I n d e x Value
ii___ _
7* |- 18 - Element Length
ii ___i
3* I T ! 1 I 0110 1 01 Element Descriptor (REAL4 )
i
i _
—
9* 1 4 Short Relocatable Addressing
i ____

Descriptor for Multi-Dimensional Array

Field Description

1* Specifies first dimension as array structure with

logical addressing*

2♦ S p e c i f i e s the logical address of the array (123456)

3* S p e c i f i e s the e l e m e n t l e n g t h for f i r s t d i m e n s i o n *
E l e m e n t l e n g t h = HI + M A X 2 * (H2 + ( M A X 3 * L ) )

(where HI = hole 1
MAX2 = second d i mension size
H2 = hole 2
MAX3 = third d i m e n s i o n size
L = l e n g t h of e l e m e n t )

*********CQNFIDENTIAL> MQS T E C H N O L O G Y >I N C ♦*** * * * * * * Page- 98

 Final Design Specification for the MC365E4 Microprocessor

Element length = 5 + 10 * (4 + (5*4) )

= F 5 (hex) u s i n g a b o v e f o r m u l a *

4* S p e c i f i e s s e c o n d d i m e n s i o n as a r r a y structure with
short relocatable mode a ddressing

5* S p e c i f i e s the f i v e b y t e o f f s e t (i*e* skip 5 byte

hole at b e g i n n i n g of e a c h p l a n e ) *

6* Specifies maximum index v a l u e for seco nd dimension

7* S p e c i f i e s e l e m e n t l e n g t h for s e c o n d d i m e n s i o n *
E l e m e n t l e n g t h = 4 + 5*4
= 18 (hex) u s i n g f o r m u l a *

Element length = HI 4* M A X 3 * L

(where HI = 4 hole
M A X 3 = third dimension size)

3* S p e c i f i e s the t h i r d d i m e n s i o n as an a r r a y of
f o u r - b y t e r e a l s (th i s as a c c o m p l i s h e d by s e t t i n g
F L A G = 1) w i t h s h o r t r e l o c a t a b l e o f f s e t m o d e
addressing♦

9* Specifies th e four byte offset ( s kip over the hole)*

The processor wi l l 3c c e s s A C 10 ?8 ? 3 ] * T h i s assembles into*

I PRM + 1 I 10 1 *0A I *08 I +03 I

I Ext B y t e I i I I I
I-------------|---------- |---------- ,---------- j-----------|

The c o n t e n t s of the P RM r e g i s t e r is 0 1 1 F E 0 * To get to the a d d r e s s

of the a r r a y d e s c r i p t o r the p r o c e s s o r w i l l ad d the c o n t e n t s of the
primary register (011FE0) w i t h t he n e x t b y t e in the i n s t u c t i o n
(10) g i v i n g 0 1 1 F F 0 * The n e x t b y t e (* 0 A ) is an o p e r a n d c o n t r o l b y t e
and will be u s e d by t he p r o c e s s o r to c a l c u l a t e the f i r s t i n d e x of
the s o u g h t a f t e r e l e m e n t and #08 for the s e c o n d i n d e x and *02 for
the t h i r d * U s i n g the a r r a y d e s c r i p t o r ? the p r o c e s s o r c a l c u l a t e s
the a d d r e s s of A C 10 ? 3 ? 2 3 w i t h the f o l l o w i n g f o r m u l a *

Q = AID + (ELI * I I ) +
E2A +
(EL2 * 12) +
E3 A +
(L * 13)

where A ID = A d d r e s s I n f o r m a t i o n of D e s c r i p t o r
ELI = Element 1 Length
II = Index 1
E2A = Element 2 Addressing Information (relocatable)

********C O N F I D E N T I A L ? MQS T E C H N O L O G Y ?I N C * * * * * * * * * * Page- 99

 Final De s i g n Specification for the M C S65 E 4 Microprocessor

EL 2 = Element 2 Length
12 = Index 2
E3A = Element 3 Addressing Information (relocatable)
L = Data Le n g t h
13 = Index 3

Substituting the example data in t o the above formula we g e 11

Q = 123456 + (F 5 * OA) +
5 +
(18 * 08) 4*
4 i
'(4 * 3)
Q = 123EBD

At logical address 123EBD is the data for element A [ 1 0 j 8 f 33

If we access element A C I ? J ?K 3 w h e r e 1 = 1? j J= 5 ? and K= -3? the

p r o c e s s o r will not t r a p out fo r 1e l e m e n t - o u t - o f - r s n g e ' s i n c e b o t h
I arid K do not h a v e r a n g e c h e c k ins s p e c i f i e d in the d e s r c i p t o r ♦
H o w e v e r w h e n 1=0? J = 10 ? and K = 1 the p r o c e s s o r will t r a p out w h e n J
is p r o c e s s e d s i n c e J is g r e a t e r t h e n 9 ( i *e ♦ 9 is the max i n d e x
as s p e c i f i e d in d e s c r i p t o r ) *

This FORTRAN d a t a are a c an a l s o be a c c e s s e d as a two d i m e n s i o n a l

a r r a y £ f e i g h t - b y t e i n t e g e r s t h r o u g h an e q u i v a l e n c e s t a t e merit* The
array? By h as m a x i m u m d i m e n s i o n 10X3* E a c h row of d a t a is now
t r e a t e d as three eight-byte integers instead of f i v e four-byte
real s * N o t e t h a t the f o u r b y t e h o l e at the b e g i n n i n g of e a c h row
w i l l now be utilized* The d e s c r i p t o r for a r r a y B will be as
follows*

1 T 1 0 1 1101 1011

1 03 1

1- 13 -1

1 T 11 1 1 0101 1 00 1

Field Definition

1* Specifies array structure with short relocatable

a d d r e s s i n g mo d e *

2* S p e c i f i e s the short relocatable offset

3* S p e c i f i e s the e l e m e n t l e n g t h of the first dimension*

Element length = MA X 2 * L
= 3 * 8
= 18 (hex)

* * * * * * * * * C O N F I D EN T I A L ? MOS T E C H N O L O G Y >I N C ** * * * * * * * * Page- 100

 Final De s i g n Specification for the MCS65E4 Microprocessor

4> S p e c i f i e s an a r r a y of 8- b y t e integers with

a t t a c h e d a d d r e s s i n g mode*

N o t e t h a t the d e s c r i p t o r for a r r a y B is f i v e b y t e s long w h i c h will

f it into the f i v e b y t e “h ole" in the b e g i n n i n g of e a c h p l a n e * If
we ijse external base a d dressing we can m o d i f y the b a s e p a g e and
a d d r e s s a ny p l a n e w i t h i n the a r r a ^ :or e x a m p l e t.o acce*: B C 3 r2 ] :

I
IE x t e r n a l
1B a s e w i t h
In g o f f s e t

T he Q r i d i n a l 20 into the BAS p a g e is 1 2 3 D E 3 w h i c h is the a d d r e s s

of v a r i a b l e B * N o t e t h a t t h i s b y - p a s s e s t he f i r s t d i m e n s i o n of the
previous example ( A C 10 ?8 *31 )♦ U s i n g the a b o v e f o r m u l a we can
a d d r e s s A C 10 ?8 y31 by s p e c i f y i n g B C 8 ?2 3 *

Q = 123DEA+ {see note below>

3+
18*08+
02*3 +
= 123EBD

note ♦ Th e r e l a t i v e c a l c u l a t i o n w i l l s t a r t from the byte

f o l l o w i n g the a d d r e s s i n f o r m a t i o n *

Note that e l e m e n t AC10?8y3Il is r e f e r r i n g to e l e m e n t B C 8 > 2 3 (i*e*

b o t h g e n e r a t e d a d d r e s s e s are e o u a l ) ♦T h i s iss h o w n below*

j-------- j------------ j-- ----- |---------|-------- j----- ------ 1 T h i r d E l e m e n t

I hole 1 0 1 1 1 2 1 3 1 4 Iof A r r a y A
,---------------------------------------------------------------j

( both have same address) =

----------- I-------------------- 1--------- ----------- - I Second Element

0 I 1 I 2 I of Array B
--------------------- ------------ ------------ ---- - |

*********C0NFIDENTIAL> MOS TECHNOLOGY j INC * ** * ****** Page- 101

 Finsi D e sign Specification for the MC S 65E 4 Microprocessor

4 ♦6 *6 *4 E x a m p l e of Accessing Data in a Complex Record Structure

Th e c o m p l e x r e c o r d s t r u c t u r e c a n b e s t be d e s c r i b e d by r e f e r r i n g to
a diagram arid f o l l o w i n g the o p e r a t i o n s t he p r o c e s s o r m u s t p e r f o r m
to a c c e s s the da t a * A s s u m e we h a v e a P A S C A L - l i k e record shown
belowt

A = Record
B : A R R A Y C l ♦ ♦ 1 5 3 of I N T E G E R *2? -Cdefine 2 b y t e i n t e g e r a r r a y >
C : BC D4 ? { d e f i n e 4 b y t e BCD f i e 1d >
D : REAL40 ? • -Cdefine p o i n t e r to 4 b y t e R E A L )
E = Record { d e f i n e new r e c o r d )
BB : BYTE? ■Cdefine a b y t e f i e l d >
CC : O R D I N A L -Cdefine an o r d i n a l fie 1 d >
End 7 {end record)
F : A R R A Y C l ♦*260] of C H A R; -Cdefine a 260 b y t e s t r i n g )
G : INTEGER*4 -Cdefine a 4 b y t e i n t e g e r f i e l d )
End 7 -Cend r e c o r d )

As p r e v i o u s l y described a record is 3 group of related but

d i s s i m i l a r data fields w h i c h are o r g a n i z e d into a single data
structure* The d e s c r i p t o r for an M C S 6 5 E 4 r e c o r d c o n s i s t s of a
record header? addressing information? a nd f i e l d descriptors*
Basically? the h e a d e r defines the da13 type as record? the
addressing information g e t s the p r o c e s s o r to the s t a r t of the raw
d a t a and the f i e l d d e s c r i p t o r s d e f i n e the s p e c i f i c f i e l d s w i t h i n
the r e c o r d * T h e r e is a o n e - t o - o n e c o r r e s p o n d e n c e between a field
d e s c r i p t o r and the d a t 3 f i e l d in the r e c o r d * W i t h i n th e field
d e s c r i p t o r is 3 d d r e s s i n g i n f o r m a t i o n w h i c h is the o f f s e t f r o m the
b a s e of the r e c o r d * The b a s e a d d r e s s of th e r3w d a 1 3 ( c o n t s i n e d in
the r e c o r d descriptor) 3 nd the o f f s e t ( c o n t a i n e d in the field
descriptor) p r o v i d e the p r o c e s s o r w i t h s u f f i c i e n t i n f o r m a t i o n to
address an y field within the record* The f o l l o w i n g example
illustrates accessing a complex r e c o r d by depicting a record's
d e s c r i p t o r and raw d at a t

*********C0NFIDENTIAL? MOS TECHNOLOGY?INC* ********* P ag e- 1 0 2

 Final D e sign Specification for the MC365E4 Microprocessor

Logical Relative
A d d re s s Address

123456 1st 2 byte integer

2nd 2 byte integer

Field B
I

15th 2 byte integer

123474 4 byte BCD field Field C

123473 T I 0 I 0110 11
Field D
125656

12347C 6 Byte Field E.BB

12347D 7 Ordinal Field E.CC

::--- I
12347E 3 1st byte of string

I
Field F

260th byte of str*

1235AA 2C 4 byte Integer Field G

Raw Data For Complex Record

125656 11

33

44

Rea l D at 3 Field

I
01F234 T I 0 I 11 0 0 i 11

56 Define Record
with
34 Logical

*********CONFIDENTIAL, MOS T E C H N O L O G Y yI N C . # * * * * * * * # Page- 103

 Final D e s ig n Specification for the MC S6 5E 4 Microprocessor

Base Addressing
12

01F238 0 1*1 001 1 I 00 Define Field A ♦B

01F239 1 0 I 1001 I 01
Define Field A .C
IE

01F23B 1101 I 01
Define Field A.DS
(deferred descriptor)

01F23D T I 0 I 0010 I 01
Define Field A ♦D
6 23

01F23F 7 T I 0 I 11 0 0 I 01 Define Record with

short relocatable
8 26 addressing

01F241 9 T I 0 I 000 1 I 00 Define Field A.E.BB

01F242 A T I 0 I 0010 I 01
Define Field A.E.CC
B 01

01F244 C 0 i 1011 01

28
Define Field A .F
04 I

01

01F248 10 0 I 0100 I 10
I
2C Define Field A.G

01 I

* - No t e : Single Dimension Array

Descriptor For Complex Record

*********C0NFIDENTIAL> MOS T E C H N O L O G Y ,I M C .********* Page- 104

 Final De s i g n Specification for the MCS65E4 Microprocessor

The field A ♦F is to be accessed* The instruction assembles into*

BAS + 3 e xt F2 01 OC
bytes
I

operano ----- +-3 e x t e n s i o n b y t e s ---------• field

c o n t ro 1 selection
byte byte

The o p e r a n d control byte followed by t h r e e e x t e n s i o n b y t e s will

p o i n t to the d e s c r i p t o r at logical address O I F 234 ( a s s u m e BAS
register eauals 0 )* After d e t e r m i n i n g that the descriptor is
logical addressing m o d e the p r o c e s s o r u s e s the n e x t three bytes
( s t a r t i n g at 0 1 F 2 3 5 ) to p o i n t to the s t a r t of the raw d a t a for the
record* S i n c e the d e s c r i p t o r s p e c i f i e s that it is record data
type? the M C S 6 5 E 4 t h e n f e t c h e s the n e x t b y t e f r o m the i n s t r u c t i o n
(OC in our example) a nd u s e s t h i s as a d i s p l a c e m e n t into the
record d e s c ript or to o b t a i n the a p p r o p i a t e f i e l d d e s c r i p t o r * In
our e x a m p l e th i s is l o c a t e d at 0 1 F 2 4 4 (01F238 + OC)* The f i e l d
descriptor header indicates string data type with short
relocatable offset* The o f f s e t in our e x a m p l e is 23 w h i c h is
located after t he d e s c r i p t o r h e a d e r < 0 1 F 2 4 5 ) * T h i s o f f s e t is t h e n
a d d e d to the s t a r t of the raw d a t a ( 1 2 3 4 5 6 + 23 = 1 2 3 4 7 E ) w h i c h is
the a d d r e s s of the f i r s t b y t e of the s t r i n g * The n e x t t wo b y t e s of
the f i e l d d e s c r i p t o r is ’th e s t r i n g l e n g t h *

As a n o t h e r example? th e f i e l d A ♦D 0 is to be accessed* The

instruction assembles into:

I---------------- j----- ----------,---------- ---- |------------- |------------,

I BAS + 3 ext I 34 I F2 I 01 I 03 I
I bytes I I I I I

operand < --------- 3 e x t e n s i o n b y t e s ---------> field

control selection
byte byte

The o p e r a n d control byte followed by t h r e e e x t e n s i o n b y t e s will

p o i n t to t he d e s c r i p t o r at logical address 01F234 (assume BAS
register eauals 0)* After d e t e r m i n i n g that the descriptor is
logical a d dressing m o d e the p r o c e s s o r u s e s the n e x t three bytes
( s t a r t i n g at 0 1 F 2 3 5 ) to p o i n t to the s t a r t of the raw d a t a for the
record* S i n c e the d e s c r i p t o r s p e c i f i e s t h a t it is a record data
type? the M C S 6 5 E 4 t h e n f e t c h e s the n e x t f i e l d s e l e c t i o n b y t e f r o m
the instruction (03 in our example) an d uses this as a
d i s p l a c e m e n t into the r e c o r d d e s c r i p t o r to o b t a i n the a p p r o p i a t e
f i e l d d e s c r i p t o r * In our e x a m p l e t h i s is l o c a t e d at 0 1 F 2 3 B ( 0 1 F 2 3 3
+ 03)* The f i e l d ’d e s c r i p t o r h e a d e r i n d i c a t e s d e f e r r e d type with
short relocatable o f f s e t * The o f f s e t ? 22 in our e x a m p l e ? is a d d e d
to 1 2 3 4 5 6 giving 123478* Since this a deferred d e s c r i p t o r ? the
data c o n t ai ne d at 1 2 3 4 7 8 is n ot raw d a t a but a n o t h e r d e s c r i p t o r *
Th e d e s c r i p t o r ? l o c a t e d at 1 2 3 4 7 3 ? is t h e n p r o c e s s e d the s a m e as

*********C0NFIDENTIAL? MGS T E C H N 0 L 0 G Y ?I N C ** * * * * * * * * Page- 105

 Final Design Specification for the MC 365 E 4 Microprocessor

any o t h e r descriptor♦ In our e x a m p l e ? the d e s c r i p t o r i n d i c a t e s

f o u r - b y t e real t y p e w i t h l o g i c a l b a s e a d d r e s s i n g (i*e* the d a t a is
l o c a t e d at 125656)* Therefore? the a c t u a l raw d a t a is 1 1 2 2 3 3 4 4
(see d i a g r a m a b o v e ) *

Similarly? the field A *D can be accessed* The instruction

a s s e m b l e s into;

I BAS 4- 3 ext F2 01
1 bytes

operand --------- 3 e x t e n s i o n b y t e s ---------; field

control selection
byte byte

The A ♦D d i f f e r s f r o m A ♦D 0 in t h a t the f o r m e r r e f e r s to the l o g i c a l

address that p o i n t s to the f o u r - b y t e real* T h e r e f o r e the f i e l d
descriptor indicates Ordinal data type with short relocatable
offset* Th e o f f s e t is 23 (one m o r e b y t e t h a n A * D 8)? so it p o i n t s
to the l o g i c a l a d d r e s s iristead of the f o u r - b y t e real d e s c r i p t o r *
Using this t e c h n i a u e we can i m p l e m e n t any p o i n t e r d ata? s u c h t h a t
P is a p o i n t e r to p o i n t e r to p o i n t e r to the f o u r - b y t e real ? i*e*?
P ?P 0 ? P00 ? P0 00 * All h a v e m e a n i n g arid can all be i m p l e m e n t e d by
the M C S 6 5 E 4 d a t a s t r u c t u r e *

For the last example? field A*E*BB 1s to be accessed* The

i n s t r u c t i o n a s s e m b l e s intot

iB A S + 3 ext! 34 F2 01 07 00
I bytes I
j------------- ,

operand extension b y t e s --- ‘ field field

c o n t ro 1 select select
byte byte byte

The o p e r a n d control byte followed by t h r e e e x t e n s i o n b y t e s will

p o i n t to the d e s c r i p t o r at logical address 01F234 (assume BAS
register eauals 0)* After d e t e r m i n i n g that the descriptor is
logical a d d ressing m o d e the p r o c e s s o r u s e s the n e x t three bytes
( s t a r t i n g at 0 1 F 2 3 5 ) to p o i n t to the s t a r t of t he raw d a t a for the
record* S i n c e t he d e s c r i p t o r s p e c i f i e s t h a t it is a record data
typ e ? the M C S 6 5 E 4 t h e n f e t c h e s the n e x t f i e l d s e l e c t b y t e f r o m the
i n s t r u c t i o n (07 in our e x a m p l e ) and u s e s t h i s as a d i s p l a c e m e n t
int o the record descriptor to obtain the appropriate field
descriptor* In our e x a m p l e t h i s is l o c a t e d at 0 1 F 2 3 F (01F238 +
07)* The f i e l d d e s c r i p t o r h e a d e r i n d i c a t e s r e c o r d t y p e w i t h s h o r t
relocatable offset* The o f f s e t ? 26 in o ur e x a m p l e ? is a d d e d to
123456 giving 1 2 3 4 7 C * S i n c e t h i s is a n o t h e r r e c o r d ? the p r o c e s s o r
m u s t get a n o t h e r b y t e f r o m the i n s t r u c t i o n to d e t e r m i n e the o f f s e t
fr o m the b a s e of the r e c o r d d e s c r i p t o r * In ou r e x a m p l e ? t h i s b y t e
is 0 w h i c h is a d d e d to 0 1 F 2 4 1 g i v i n g 0 1 F 2 4 1 w h i c h is the f i e l d

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 I"i n s 1 De s i g n Specification for the HCS65E4 Microprocessor

d e s c r i p t o r fo r A *E * B B ♦ This field d e s c r i p t o r i n d i c a t e s byte data

type with attached (relocathle) addressing m o d e ( i ♦e ♦ A d d 0 to
12347C giving 1 2 3 4 7 C )♦ Therefore? the raw d a t a for A *E ♦B B is
l o c a t e d at 1 2 3 4 7 C * The p r o c e s s o r c a l c u l a t e s t he a d d r e s s of a f i e l d
in the r e c o r d by u s i n g t h e f o l l o w i n g f o r m u 1 a 1

(record address + (field d e s c r i p t o r 1 + (field descriptor 2

information) relocatable offset) relocatable offset)

4 *6 *6 *5 E x c e p t i o n Vectors

4♦6♦6♦5♦1 Introduction

E a c h of the e x c e p t i o n v e c t o r s l i s t e d in S e c t i o n 4 * 4 * 4 is s t o r e d in
a four - b y t e f i e l d in a manner w h i c h is compa t i b l e with the
MC365E4 data structure* The f i r s t b y t e of t h e vector contains a
descriptor which p r i m a r i l y s p e c i f i e s t h a t the l o g i c a l a d d r e s s of
the e x c e p t i o n processing s o f t w a r e is either "attached" to the
d e s c r i p t o r or is l o c a t e d in a " r e m o t e " data structure* If the
a d d r e s s is a t t a c h e d ? the t h r e e b y t e s f o l l o w i n g the d e s c r i p t o r are
a s s u m e d to be t he l o g i c a l a d d r e s s of the software which will
s e r v i c e the exception (exeception h a n d l e r ) * T h i s a d d r e s s wil l be
a d d e d to the c o n t e n t s of the P r o c e s s B a s e R e g i s t e r to d e t e r m i n e
the corresponding physical address* This address is then
t r s n s f e r e d into the P r o c e s s P r o g r a m C o u n t e r * The p r o c e s s o r the n
begins execution of the exception software* In a d d i t i o n to the
simple "attached" f o r m of the exception vector? the l o g i c a l
a d d r e s s car! be l o c a t e d in a d a t a s t r u c t u r e w h i c h is s e p a r a t e f r o m
the f o u r byte ex c e p t i o n vector* In t h i s ca s e ? the t h r e e b y t e s
f o l l o w i n g the d e s c r i p t o r c o n t a i n s the l o g i c a l a d d r e s s of the d a t a
s t r u c t u r e in which the address of the execution software is
stored* In all cases this vector format must c o n f o r m to the
M C S 6 5 E 4 d a t a s t r u c t u r e d e s c r i b e d a b o v e arid the d a t a f i e l d w h i c h is
r e f e r e n c e d by the vector m u s t be a three byte ordinal* This
o r d i n a l is a s s u m e d to be the logical address of the exception
handler*

The use of c o m p l e x d a t a s t r u c t u r e s w i t h i n the e x e p t i o n v e c t o r is

p a r t i c u l a r l y u s e f u l for i n t e r r u p t s ? s y s t e m s c a l l s ? etc* in w h i c h a
b y t e of i n f o r m a t i o n is G e n e r a t e d by t he e x e p t i o n to be u s e d as an
index value in to the a r r a y * A d o o d e x a m p l e of t h i s is the S y s t e m
Call in w h i c h a b y t e of d a t a is p a s s e d to the o p e r a t i n g s y s t e m *
In a d d i t i o n to p l a c i n g t h i s " e x e c e p t i o n Q u a l i f i e r " o n t o the s t a c k ?
the d a t a is r e t a i n e d in an i n t e r n a l working r e g i s t e r f or use
d u r i n g the e x c e p t i o n v e c t o r p r o c e s s i n g * T h i s a l l o w s the use of an
a r r a y of ordinals to i m p l e m e n t a direct vectored system call?
direct vectored interrupts? etc* E a c h of t h e s e o p t i o n s w i l l be
i l l u s t r a t e d in the e x a m p l e s b e l o w * These "exception Qualifiers"
a re d e s c r i b e d in detail in th e discussion of the exception
vectors*

4 * 6 *6 *5 *2 D e s c r i p t o r Format

The d e s c r i p t o r arid a s s o c i a t e d data within the e x c e p t i o n vector

m u s t c o n f o r m e x a c t l y to the f o r m a t d e s c r i b e d a b o v e for the M C S 6 5 E 4
data structure* The T R A P bit is u s e d to indicate whether the

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 Final Design Specification for the MCS65E4 Microprocessor

e x c e p t i o n can be s e r v i c e d w i t h i n the c u r r e n t p r o c e s s (T = 0)* If

the T bi t is a l o g i c a l 1 ? the p r o c e s s o r will r e t u r n to the l o w e r
level p r o c e s s to s e r v i c e the e x c e p t i o n * O n l y one b a s i c d a t a t y p e
( o r d i n a l ) is v a l i d * If the d a t a t y p e is a s i n g l e d i m e n s i o n o r d i n a l
ar r a y ? o n l y a s i n g l e b y t e of a d d i t i o n a l i n f o r m a t i o n is a v a i l a b l e
for use in d e t e r m i n i n g the index value of the o r d i n a l array*
Therefore? the e x c e p t i o n v e c t o r represents limited s u b - s e t of
the d a t a t y p e s w h i c h the M C S 6 5 E 4 s u p p o r t s *

4*6*6*5*3 Example of Attached Address Exception Vector Format

The s i m p l e s t f o r m of e x c e p t i o n v e c t o r is one in w h i c h the l o g i c a l

address of the software which will service the exception
(exception handler) directly follows the descriptor* T h i s is
i l l u s t r a t e d b e l o w for an O v e r f l o w T r a p w h o s e h a n d l e r is l o c a t e d at
logical ad dress 0034A0* N o t e t h a t the T R A P bit in the d e s c r i p t o r
is se t to l o g i c 0 arid t h a t t h e M O D E f i e l d c o n t a i n s 00? s p e c i f y i n g
a t t a c h e d dat a* The c o n t e n t s of the e x c e p t i o n v e c t o r will be as
follows^

Address Contents Remarks

E8* T ?0 ?0 0 1 0 ? 00 Descriptor

E?> A0 (HEX) Low o r d e r b y t e of exception handler

add r es s *

EA* 34 (HEX) Middle order byte of exception handler

address *

E B* 00 (HEX) High order byte of exception handler

address *

0 0 3 4 A0 Actual exception handler code for overflow condition

* - Page address within LM T page

4+6*6*5*4 Example of Remote Exception Vector

In m a n y processes? p a r t i c u l a r l y w i t h i n the Kernel and O p e r a t i n g

System processes? it is v e r y l i k e l y t h a t the exception vectors
will be l o c a t e d in Read-Only Memory* In t h i s case? use of the
attached form of the e x c e p t i o n v e c t o r w o u l d n ot a l l o w the v e c t o r
a d d r e s s to be m o d i f i e d d u r i n g p r o c e s s e x e c u t i o n * H o w e v e r ? u se of
the r e m o t e e x c e p t i o n v e c t o r a l l o w s the v e c t o r a d d r e s s to be p l a c e d
in R E A D / W R I T E memory* T h i s will be i l l u s t r a t e d by describing a
Data Access Trap V e c t o r in w h i c h the a d d r e s s of the h a n d l e r is
l o c a t e d in logical addresses 000003 through 000005 within the
process* The e x c e p t i o n h a n d l e r b e g i n s at l o g i c a l address 01C450
w i t h i n th e p r o c e s s * In t h i s c ase? a d d r e s s DS w i t h i n the L i m i t P a g e
c o n t a i n s a d e s c r i p t o r whi c h s p e c i f i e s a remote ordinal data field*
The r e m a i n i n g b y t e s of the v e c t o r c o n t a i n l o g i c a l a d d r e s s 0 0 0 0 0 3 *
This causes the p r o c e s s o r to f e t c h the a d d r e s s of the e x c e p t i o n
han d l e r from logical a d d r e s s 0 0 0 0 0 3 t h r o u g h 00005*

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 Final D e sign Specification for the MCS65 E 4 Microprocessor

A d d ra s < Contents Remarks

D3* T ? 0 , 0 0 1 0 : 11 Descriptor \

D9* 03 (HEX) Low o r d e r b y t e of t he pointer to the

exception handler*

DA* 00 (HEX) Middle o r d e r b y t e of the p o i n t e r to

the exception handler*

D B* 00 (HEX) H i g h o r d e r b y t e of the p o i n t e r to
the e x c e p t i o n h a n d l e r *

000003** 50 (HEX) Low order byte of exception handler

address *

000004** C4 (HEX) M i d d l e o r d e r b y t e of exception

handler address*

000005** 01 (HEX) High order b y t e of exception

handler address

01 C 4 5 0 Actual exception handler code for data access tr a p

* - P a g e a d d r e s s w i t h i n the L M T P 3 g e
** - L o g i c a l a d d r e s s w i t h i n t he p r o c e s s

*********C0NFIDENTIAL> MOS T E C H N O L O G Y >INC* * * * * * * * * * Page- 109

 Final De sign Specification for the HCS65E4 Microprocessor

4 ♦7 The MCS6u£4 Instruction Set

4*7*1 Introduction

The use of descriptors to control accessing data within the

M C S 6 5 E 4 h as a s i g n i f i c a n t i m p a c t on the n a t u r e of the i n s t r u c t i o n
set w h i c h ise x e c u t e d by this p r o c e s s o r * Host i m p o r t a n t l y ? it
a l l o w s the use of " g e n e r i c * instructions; i* e*? i n s t r u c t i o n s
w h i c h do n ot s p e c i f y t h o s e a s p e c t s of the o p e r a t i o n w h i c h are d a t a
dependent* For example* lik e most processors? the M C S 6 5 E 4
i n s t r u c t i o n set c o n t a i n s art a r i t h m e t i c ADD i n s t r u c t i o n * H o w e v e r ?
this i n st ru c ti on only specifies t h a t an add o p e r a t i o n is to be
performed between two d a t a fields* The e x a c t n a t u r e of the add
o p e r a t i o n is d e t e r m i n e d by the d a t a c o n t a i n e d in the d a t a f i e l d s
(BCD add for B CD data? etc)* T h i s t e c h n i o u e f o r co n t r o l l i n g the
d e t a i l s of an i n s t r u c t i o n e x e c u t i o n introduces several important
c h a r a c t e r i s t i c s of the i n s t r u c t i o n set d e s c r i b e d b e l o w * The f i r s t
is t h a t t h e r e are m a n y c o m b i n a t i o n s of d a t a t y p e arid i n s t r u c t i o n
w h i c h are not v a l i d * In a d d i t i o n ? for t h o s e i n s t r u c t i o n s w h i c h
r e a u i r e two o p e r a n d s ? the d a t a t y p e for the two d a t a f i e l d s w h i c h
are to be m a n i p u l a t e d by the i n s t r u c t i o n m u s t be s i m i l a r * F i n a l l y ?
t h e use of d e s c r i p t o r s r e s u l t s in a s i g n i f i c a n t r e d u c t i o n in the
total n u mber of i n s t r u c t i o n s in the i n s t r u c t i o n set? w h i l e at the
same time the o p e r a t i o n s w h i c h c an o c c u r d u r i n g the e x e c u t i o n of
each instruction can be Q u i t e c o m p l e x b e c a u s e of the b r o a d r a n g e
of d a t a types which are s u p p o r t e d by the p r o c e s s o r * T h i s is
r e f l e c t e d in th e i n s t r u c t i o n d e s c r i p t i o n s below* E a c h of t h e s e
paragraphs contains a general d e s c r i p t i o n of the instruction? a
l i s t i n g of the applicable data types? a description of the
execution seauence for each d a t a t ype? and a l i s t i n g of the
a p p l i c a b l e h e x i d e c i m a l Op Codes*

4*7*2 Format of the MCS65E4 Op Codes

All M C S 6 5 E 4 i n s t r u c t i o n s are c o n t a i n e d w i t h i n o ne byte* Bit 7 of

each O p Code is r e s e r v e d for use as a TRAP b it to c a u s e an
Instruction Access Trap* The r e m a i n i n g b i t s are u s e d to s p e c i f y
o ne of sixteen instruction modes ( bits 0-3) and one of the
i n s t r u c t i o n s w i t h i n the s e l e c t e d m o de* T h i s f o r m a t c an be d e p i c t e d
as f o l l o w s ^

b i t : 7

T he i n s t r u c t i o n s e t C 3 n be o r g a n i z e d in t o t h r e e m a j o r g r o u p s * The
first group contains the basic data manipulation instructions
(Add? s u b t r a c t ? e t c * ) * T h e s e c o n d c o n t a i n s all i n s t r u c t i o n s w h i c h
c o n t r o l p r o g r a m f l o w ( b r a n c h e s ? J u m p to s u b r o u t i n e ? e t c * ) * G r o u p 3
c o n t a i n s the advanced arithmetic and l o g i c operations* E a c h of
t h e s e g r o u p s is d i s c u s s e d s e p a r a t e l y b e l o w *

Figure 5*3 below summarizes the instruction set format for the

*********CGNFIDENTIAL? M0S T E C H N O L O G Y ?INC ** * * * * * * * * Page- 110

 Final Design Specification for the M C S 6 5 E 4 Microprocessor

Format Mnemonic

i I ? I ?R 1 ADD f S U B > HUL» D I V 1

1 1 A N D f OR > E Q R , M O D 1

1 1 1 IR 1 ADD? S U B , MULf DIV 1

1 1 A N D f ORf E O R , MOD 1

1 1 ,R i ABSf NEGf I N C , DEC 1

1 1 S O R T f MOV f L E A D Z f L E A D 1 1

1 IR 1 ABS , N E G , INC? DEC 1

1 1 S O R T f CLRf S E T 1
1— — — —
1 _ _
—_—_
— ___ _—
— --- __I__
— j— -
1 If If* 1 BEGf B N E , B G T , BG E 1
1 1,1,** i
i —— — _ (_
1 I»* i B E Q Z » B N EZf B P OSt BMI 1
1 If** 1

i I ? I ?R 1 C E Q , C N E , C G T , CGE 1

1 I » IR » S 1 FIND j DETCf N DETf DETR !

I_ _ ______ __J___
1 ( I t I , R ) » (I fIR) 1 SHM
1— — — — —
I------ _ __ «.11_ _
---
1 I 1 C A L L f JMP I
1 1 T A S K f IOSf RTE I
1
j _____________
-------- --- j-1- _
1 ( IR ) ? ( I ? I ) ? * 1
I-------------------- j BRf J S R , B DECf BCOND 1
1 < I R )? ( I ? I ) ? ** i

1 No O p e r a rid i RTS > R E S E T , SCf SCM 1

i
i _ _ __ji
1 I tR 1 F'TRf D TYPf CNVT 1
I____
1 ——— ____
— __ __ _ I
|
1 Special 1 EVAL
1-------------------- |

Rt R e s u l t ? It Input? RIt Input and Result? St String

( ) t Optional

*********CONFIDENTIAL? MOS T E C H N O L O G Y ?I N C ♦ * * ** * * ** * Page- 111

 Final Desi g n Specification for the MCS65E4 Hicroprocessor

4*7*3 Basic Arithmetic *n d L o g i c Operations

4*7,3*1 Introduction

The a r i t h m e t i c arid l o g i c i n s t r u c t i o n s c a n be o r g a n i z e d into a set

of o p e r a t i o n s w h i c h m u s t be p e r f o r m e d on two s e p a r a t e d 3ta f i e l d s
arid a set of o p e r a t i o n s which involve only a single data field*
The f i r s t set of i n s t r u c t i o n s will c o n t a i n e i t h e r two or t h r e e
operands while one or two o p e r a n d s m u s t be p r o v i d e d in the s e c o n d
se t *

T he following is a s u m m a r y of the mnemonics? Op Codes and format

for the b a s i c a r i t h m e t i c and l o g i c instructions*

Group 1 Instructions (utilizing two data fields)

Two O p e r a rid Three Operand

Instruction Mnemonic O p Code Op code

Add ADD
Subtract SUB
Multiply MUL
D iv id e div
Modulus MOD
L o g i c And AND
L o g i c Or OR
Exclusive Or EOR

Format

Three o p e r a rid *
♦ Qp-Code 0P1?0P2?0P3

0 p e ran d 1 (0P1 ) - Specifies the

0 p e ran d 2 (0 P 2 ) - Specifies the
Operand 3 (0 P 3 ) - Specifies the

Two operand! Qp-Code 0 P 1 *0 P 2

Operand 1 (0P1 ) - Specifies the

O pe r and 2 (0 P 2 ) - Specifies both
f i e l d and the

Instructions (utilizing one data fi e l d )

Single
Ope rand Two O p e r a n d
Instruction Mnemonic O p Code O p code

Absolute Value ABS

Negate NEG
Increment INC
Decrement DEC
S q u are Root SORT
Move MOV
Convert CNV T
Clear CLR

*********CONFIDENTIAL? MQS TECHNOLOGY?INC* ********* Page- 112

 Final Design Specification for the MCS6 5E4 Microprocessor

F o rm a t

Two operand: Qp-Code 0P1?0P2

Operand 1 (0P1)~ Specifies the only source field

Operand 2 <0 P 2 ) - Specifies the result field*

One operand: Qp-Code 0P1

Operand 1 (0P1)- S p e c i f i e s b o t h the s o u r c e field

and the r e s u l t s f i e l d *

*********CONFIDENTIAL> MOS TECHNOLOGY?INC********** Page- 11

 Final Design Specification for the MC S 65 E 4 Microprocessor

*********
* AD D *
*********

4 * 7 *3 *2 A dd

Formati A DD 0P1?0P2?QP3
A DD 0Pli0P2

Description:

A d d s the c o n t e n t s of th e d a t a f i e l d s p e c i f i e d by o p e r a rid 2
to the c o n t e n t s of the d a t 3 f i e l d s p e c i f i e d by o p e r a n d 1 and
p l a c e s the r e s u l t s in the data field specified by e i t h e r
operand 2 (two operand addressing) or o p e r a rid 3 (three
operand addressing)*

Valid Da t a Types:

Binary (Byte? Integer arid S t r i n g )

Performs a b i n a r y add operation treating the byte and

string data as a p o s i t i v e i n t e g e r *

Re a l
Q*
Performs a floating point add o p e r a t i o n * I n p u t d a t a is
a s s u m e d to be normalized* A f t e r the add o p e r a t i o n is
complete? the r e s u l t s are n o r m a l i z e d b e f o r e b e i n g s t o r e d
in the r e s u I t s f i e l d * Real o p e r a n d s c a n n o t be m i x e d w i t h
B i n a r y or BCD d a t a f i e l d s *

BCD

P e r f o r m s a s i g n e d ? p a c k e d BCD add o p e r a t i o n * All operands

m u s t be th e s a m e t y p e and l e n g t h *

Immediate Operands

Immediate operands c a n be s p e c i f i e d in c o m b i n a t i o n w i t h
any of the o t h e r data types* The i m m e d i a t e operand
a s s u m e s the d a t a t y p e of the s e c o n d i n p u t o p e r a n d * If
both input o p e r a n d s are I m m e d i a t e d a t a ? the d a t a t y p e is
a s s u m e d to be i n t e g e r *

Op Codes:

Two o p e r a n d a d d r e s s i n g - ____
T h r e e o p e r a n d a d d r e s s i n g - _______

** ** * ** ** CONFIDENTIAL? MOS TECHNOLOGY?INC* ********* Page- 114

 Final Design Specification for the MCS65E4 Microprocessor

*********
* SUB *
**^******

4 * 7 *3 *3 S u b t r a c t

Format: S UB QF’l * 0 P 2 y Q P3
SU B 0 P 1 ?0 P 2

Description:

CASE1 : S u b t r a c t s the c o n t e n t s of the d a t a f i e l d s p e c i f i e d

by o p e r a n d 1 f r o m the c o n t e n t s of the d a t a f i e l d s p e c i f i e d
by o p e r a n d 2 and p l a c e s the results in the data field
s p e c i f i e d by o p e r a n d 3 ( t h r e e o p e r a n d a d d r e s s i n g ) * E x a m p l e t
SU B aib j c => c = b - a

CASE2 : S u b t r a c t s the c o n t e n t s of the d a t a f i e l d s p e c i f i e d

by o p e r a n d 1 f r o m the c o n t e n t s of the d a t a f i e l d s p e c i f i e d
by o p e r a n d 2 and p l a c e s the results in the data field
s p e c i f i e d by o p e r a n d 2 (two o p e r a n d addressing)* Example ♦
SUB a ib => b =b - a

Valid Data Types: S a m e as Add Instruction*

Op Codes:

Two o p e r a n d a d d r e s s i n g - _______
T h r e e o p e r a n d a d d r e s s i n g - _____ __

* * * * * * * * * C O N F I D E N T I A L r MOS T E C H N O L O G Y j INC********** Page- 115

 Final Design Specification for the MCS65E4 Microprocessor

* M UL *
*********

4*7*3*4 Multiply

Format; M UL Q P i >Q P 2 >0 P3

MUL 0Plf0P2

Description:

CASE1 : M u l t i p l i e s the c o n t e n t s of the d a t a f i e l d s p e c i f i e d

by o p e r a rid 1 t i m e s the c o n t e n t s of the d a t a f i e l d s p e c i f i e d
by o p e r a n d 2 and p l a c e s the results in the data field
s p e c i f i e d by o p e r a n d 3 ( t h r e e o p e r a n d a d d r e s s i n g ) *

CASE2 : M u l t i p l i e s the c o n t e n t s of the data field specified

by o p e r a n d 1 t i m e s the c o n t e n t s of the data field specified
by o p e r a n d 2 arid p l a c e s the results in the data field
s p e c i f i e d by o p e r a n d 1 (two o p e r a n d a d d r e s s i n g ) *

Valid Data Types:

yes no

Integer I x I i

Bed I x I I

Real ‘ I x I I

String I x I I

Notes:

If t he d a t a f i e l d s p e c i f i e d by 0P1 and 0 P2 are s t r i n g type?

o n l y the f i r s t e i g t h b y t e s wil l be u s e d for m u l t i p l i c a t i o n *
If the r e s u l t f i e l d is s t r i n g d a t a type; the m u l t i p l i c a t i o n
of the i n p u t s ( e i t h e r s t r i n g or i n t e g e r ) will be s t o r e d into
the f i r s t sixteen bytes of the r e s u l t a n t string (assuming
the r e s u l t f i e l d is g r e a t e r than or e a u a l to 16 b y t e s ) *

Restrictions:

The length and type of operands 1 and 2 must be eaual*

Op Codes:

T wo o p e r a n d a d d r e s s i n g - _____
T h r e e o p e r a n d a d d r e s s i n g - _______ _

*********CONFIDENTIAL? MOS T E C H N O L O G Y ,INC ** * * * * * * * * Page- 116

 Final D e sign Specification for the MC S65 E 4 Microprocessor

* DIV *
*********

4*7*3*5 Divide

Format: DIV QP1>0P2>0P2

DIV 0P1 >GP2

Descriptiont

CASE1 I D i v i d e the c o n t e n t s of the d a t a f i e l d s p e c i f i e d by

operand 2 by the c o n t e n t s of the data field s p e c i f i e d by
operand 1 and p l a c e s t he results in t o the data field
s p e c i f i e d by o p e r a n d 3 ( t h r e e o p e r a n d a d d r e s s i n g ) *

CASE2 I D i v i d e s the c o n t e n t s of the d a t a f i e l d s p e c i f i e d by

o p e r a rid 2 into the c o n t e n t s of the d a t a f i e l d s p e c i f i e d by
operand 1 arid p l a c e s the results into the data field
s p e c i f i e d by o p e r a rid 2 (two o p e r a rid a d d r e s s i n g ) *

Valid Data Types*

yes no

Integer I xI I

Bed I xi I

Real I xI I

String I xI I

Restrictions^

The length and type of operands 1 and 2 must be eaual*

Op Codes:

Tw o o p e r a n d a d d r e s s i n g - .________
T h r e e o p e r a rid a d d r e s s i n g - _______

*********CONFIDENTIAL> MOS TECHNOLOGY?INC********** Page- 117

 Final Design Specification for the MC 36 5 E 4 Microprocessor

^ 4 ^ «*|N '4'/jv /yv /fv

* AND *
*********

4 ♦ 7 ♦3 ♦6 A n d

Format: A ND 0P1?0P2?0P3
AND 0P1?0P2

De s c r i p t i o n :

CASE1 : P e r f o r m s a l o g i c ANIi o p e r a t i o n b e t w e e n e a c h b it of
the d a t a f i e l d s p e c i f i e d by o p e r a n d 1 and the c o r r e s p o n d i n g
b i t of the d a t a f i e l d s p e c i f i e d by o p e r a n d 2 arid p l a c e s the
r e s u l t s in the data field s p e c i f i e d by operand 3 (three
o p e r a rid a d d r e s s i n g ) * The f o l l o w i n g d i a g r a m d e p i c t s t h e AND
operation:

0P2
0 1

0 0 0
op: = > 0P1
1 0 1

CASE2 : P e r f o r m s a logic AND o p e r a t i o n b e t w e e n e a c h b i t of

the d a t a f i e l d s p e c i f i e d by o p e r a n d 1 and the c o r r e s p o n d i n g
bi t of t he d a t a f i e l d s p e c i f i e d by o p e r a n d 2 and p l a c e s the
r e s u l t s in the data field s p e c i f i e d by o p e r a rid 2 (two
o p e r a n d a d d r e s s i n g )* T h e f o l l o w i n g d i a g r a m d e p i c t s the AN D
operation:

0P1 = = > OP 1

Valid Data Types:

y es no

I n teg e r

Bed

R e a 14

R e a 18

R e a 110

* * * * * * * * * C O N F I DE N T I A L ? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 113

 Final D esign Specification for the MC S6 5E 4 Microprocessor

String I y% ( i
I |---- ,

Restrictions^

The length and type of operands 1 and 2 must be eoual*

Op Codes:

T wo o p e r a n d a d d r e s s i n g - _______
T h r e e o p e r a n d a d d r e s s i n g - _______

*********CONFIDENTIAL> MOS TECHNOLOGY j I N C * * * * * * * * ** Page-

 h i n 3 1 Des ig n Specification for the MC S6 5 E 4 Microprocessor

********
* OR *
■•
'n^P>o''
V' 'P
V^
'V-r* o
‘
-'
V

4 ♦ 7 ♦3 ♦7 Or

Format: OR Q P 1 >0 P 2 *Q P 3
OR OP 1 f0 P 2

Description;

CASE! : P er forms a logic OR o p e r a t i o n b e t w e e n e a c h bit of

t he d a t a f i e l d s p e c i f i e d by o p e r a n d 1 arid th e c o r r e s p o n d i n g
b i t of th e d a t a f i e l d s p e c i f i e d by o p e r a n d 2 and p l a c e s the
r e s u l t s in the data field s p e c i f i e d by operand 3 (three
operand addressing)* The f o l l o w i n g d i a g r a m d e p i c t s th e AND
operation:

0P2
0 1

0 0
0P3 = = > 0P1
1 1

CASE2 : P e r f o r m s a logic OR o p e r a t i o n b e t w e e n e a c h bi t of
the data f i e l d s p e c i f i e d by o p e r a n d 1 a nd the cor r e s p o n d i n g
b i t of t h e d a t a f i e l d s p e c i f i e d by o p e r a rid 2 a nd p l a c e s the
r e s u l t s in the data field s p e c i f i e d by operand 2 (two
operand addressing)* The f o l l o w i n g d i a g r a m d e p i c t s the OR
operation:

0P2
O

1^
I
1O 1
1
1
1

0 l
!

= > 0P1
1 l l

Valid Data Types:

y es no

I ntege r

Bed

Re a 14

RealS

ReallO

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C ♦* ** ** * ** * Page- 120

 Final De si gn Specification for the M C S 65£4 Microprocessor

j--- j----
String I x I

Restrictions^

The length arid t y p e of o p e r a rids 1 3nd 2 must be eaual ♦

Op Codes:

Two o p e r a n d a d d r e s s i n g -
Three operand a d d r e ssing-

** * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y rI N C * * * ** * ** * * Page-
 Final Desig n Specification for the M CS 6 5E 4 Microprocessor

^ ^
EOR *

4 . 7 .3 .8 E x c l u s i v e Or

F o r m a t J EOR 0P1»0P2»0P3
EOR 0P1»0P2

DescriptionJ

CASE1 J P e r f o r m s a logic EOR o p e r a t i o n b e t w e e n e a c h b i t of

t he d a t a f i e l d s p e c i f i e d by o p e r a n d 1 and the c o r r e s p o n d i n g
b i t of t h e d a t a f i e l d s p e c i f i e d by o p e r a n d 2 3nd p l a c e s t he
r e s u l t s in t he d3ta field s p e c i f i e d by operand 3 (three
operand addressing). Th e f o l l o w i n g d i a g r a m d e p i c t s the EOR
operation!

OP 2
0 1

0 0 1
OP = > 0P1
1 1 0

CASE2 I P e r f o r m s a l o g i c EO R o p e r a t i o n b e t w e e n e a c h b i t of
the data f i e l d s p e c i f i e d by o p e r a n d 1 an d the c o r r e s p o n d i n g
b it of th e d a t a f i e l d s p e c i f i e d by o p e r a rid 2 and p l a c e s the
r e s u l t s in th e data field s p e c i f i e d by operand 2 (two
operand addressing). T he f o l l o w i n g d i a g r a m d e p i c t s th e EOR
operationJ

OF'2
0 1

0 0 1
0P3 = = > 0P1
1 1 0

Valid D 3 1 3 Types;

yes no

Integer I x I I

Bed I x I I

R e s 14 I x I I

R e a 18 I x I I

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C . *** ** ** ** Page- 122

 Finsi Design Specification for the M C S 6 5E 4 Microprocessor

R e a 110 I I y, I
I--- i----- i
String i x I I
j--- j----- j

Restrictions^

The length arid type of opera rids 1 arid 2 must be eau a 1 ♦

Op Codes:

Two o p e r a nd a d d r e s s i n g - ______
Three o p e r a nd a d d r e s s i n g - _____

*********CONFIDENTIAL> MOS T E C H N O L O G Y ?I N C ♦*** ** ** ** Page-

 Final Design Specification for the MC S6 5E 4 Microprocessor

*********
* MOD *
*********

4*7*3*9 Modulus (Remainder Function)

Format: MO D 0P1>QP2>0P3
MOD OF*1f OP2

Description:

CASE1 : D i v i d e th e c o n t e n t s of the d a t a f i e l d s p e c i f i e d by
operand 2 by the c o n t e n t s of the data field s p e c i f i e d by
operand 1 a nd p l a c e s the remainder i n t o the data field
s p e c i f i e d by o p e r a n d 3 ( t h r e e o p e r a n d a d d r e s s i n g ) *

CASE2 : D i v i d e s the c on t e n t s of the d a t a f i e l d s p e c i f i e d by

o p e r a rid 2 by the c o n t e n t s of the d a t a f i e l d s p e c i f i e d by
operand 1 arid p l a c e s the remainder i nt o the data field
s p e c i f i e d by o p e r a n d 2 (two o p e r a n d a d d r e s s i n g ) *

Valid Data Types:

yes no

Integer ! x I I

Bed I x i I

Real Ii x !

String I x l I

Restrictions:

T he length and type of operands 1 and 2 must be eoual*

Valid Data Types:

Op C o de s :

Two o p e r a n d a d d r e s s i n g - _______
T h r e e o p e r a n d a d d r e s s i n g - _______

********C O N F I D E N T I A L ? MOS T E C H N O L O G Y >I N C * * * * * * ** ** Page- 124

 Final D esign Specification for the MC S65 E 4 Microprocessor

*********
* ABS *
*********

4 * 7 * 3 * 1 0 A b s o l u t e V a l u e

Format: ABS 0P1?0P2

ABS 0P1

Description:

C A S E 1 : C h a n g e s t he d a 1 3 f i e l d s p e c i f i e d by o p e r a n d 1 i nt o a
positive number storing the r e s u l t s int o t he d a t a field
s p e c i f i e d by o p e r a n d 2 (two o p e r a n d a d d r e s s i n g ) *

CASE2 : C h a n g e s th e the dats field s p ecified by operand 1

into a positive number s t o r i n g th e results into the s a m e
d a 1 3 field (single operand sddtessing)*

Valid Dots Types:

yes no

In t e g e r I x I I

Bed I x I I

Resl I x l I

3 1 r in g I I x l

Notes: For integer d3t3 type? c h s n g i n g 3 n e g 3 t i v e n u m b e r in t o 3

positive number will involve more than c h a n g i n g the s i g n bit
s i n c e i n t e g e r d a t 3 is s t o r e d in 2 7 s c o m p l e m e n t f orm*

Op Codes:

One operand addressing- _______

T wo operand addressing- ______

** ** ** * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C ***** ** ** * Psge- 125

 Final D esi gn Specification for the MCS65E4 Microprocessor

*********
* NEG *
& /{&\ /|S
"k& ^'in'x^ it£

4♦7♦3♦11 Negate Value

Format; NEG 0P1?0P2

NEG 0P1

Description i

CASE! I I n v e r t s the s i g n of the d a t a field specified by

operand 1 s t o r i n g the r e s u l t s i n to the data field specified
by o p e r a n d 2 (two o p e r a n d a d d r e s s i n g ) *

CASE2 t I n v e r t s the s i g n of the d a t a field specified by

operand 1 storing the r e s u l t s in t o the same data field
(single operand addtessing)*

Valid Data Types!

yes no

Integer I x I I

Bed 1 x I !

Real I x I i

String II x I

Notes t

For i n t e g e r t ype? th e n e g a t i o n w i l l be m o r e than Just change

the s i g n (i*e* t w o s c o m p l i m e n t arithmetic)*

Op Codesi

One operand addressing- _______

Two operand addressing- ______

********CO N FI D E N T I A L ? MOS T E C H N O L O G Y ? I N C ** * * * * ** * * Page- 126

 Final Desig n Specification for the M C S6 5E 4 Microprocessor

*********
* INC *
O'O''T*<T*O*O'-T*-h‘
V-

4.7.3.12 Increment

Format: INC 0P1»OP2

INC OP 1

Description*

CASE1 ! Adds one to the d a t e s p e c i f i e d by o p e r a n d 1? s t o r i n g

the results b a c k into the d a t a f i e l d s p e c i f i e d by o p e r a n d 2
( two o p e r a n d addressing).

CASE2 t Adds o ne to th e data s p e c i f i e d by the operand

s t o r i n g th e r e s u l t s b a c k into the s a m e d a t a field (single
operand addressing).

Valid D 3 13 Types!

yes no

Integer I xI I

B ed I ;< I I

R e 31 I I I

String I I x l

Op Codes!

One oper3nd addressing-

Two operand addressing-

***####**CONFIDENTIAL> HOS TECHNOLOGY*INC.*****#*#* Page- 127

 Final Design Specification for the M C S6 5E 4 Microprocessor

*********
* DEC *
*********

4 ♦ 7 ♦ 3 ♦ i3 D e c r e m e n t

Format: DEC 0P1>0P2

DEC 0P1

Description:

CASE1 : S u b t r a c t s orie f r o m the d a t a s p e c i f i e d by o p e r a n d 1?

s t o r i n g the r e s u l t s int o th e d a t a f i e l d s p e c i f i e d by o p e r a rid
2 (two o p e r a n d a d d r e s s i n g ) ♦

CASE2 : Subtracts one from the data specified by the

operand? s t o r i n g the r e s u l t s back into the s a m e d 3 t a f i e l d
( s i n g l e o p e r a rid a d d r e s s i n g ) ♦

Valid Data Types:

yes no

Integer 1 x I

Be d i x S

R ea l I I x

String I ! x

Op Codes:

One operand addressing-

T wo operand addressing-

********C O N F I D E NT I AL ? MOS T E C H N O L O G Y >I N C ♦ *** ** ** * * Page- 128

 Final Design Specification for the H C S6 5E 4 Microprocessor

* SORT * *
**********

4*7*3*14 S q u ar e Root

Format: SQRT QP1*0P2

SQRT 0P1

Description:

CASE1 : D e t e r m i n e s the s q u a r e roo t of the d a t a s p e c i f i e d by

o p e r a n d 1 r s t o r i n g the r e s u l t s i n t o the d a t a f i e l d s p e c i f i e d
by o p e r a n d 2 (two o p e r a n d a d d r e s s i n g ) *

CASE2 : D e t e r m i n e s the s q u are root of the d a t a s p e c i f i e d by

the o p e r a n d ? s t o r i n g t h e r e s u l t s in t o the s a m e data field
(single operand addressing)*

Valid Data Types;

yes no

Integer I x l I

B ed I x I I

Real I x l I

String I I x l

Op Codes:

One operand addressing-

Two operand addressing-

********CONFIDENTIAL* MOS T E C H N O LO G Y >I N C ♦*** **** ** Page- 129

 Final Design Specification for the MCS6 5E 4 Microprocessor

^ v if ^ v y \Lr ^ \Lr
^ ^ 4v ^ ^ ^

*^ MO V *

4 ♦7 ♦ 3 ♦ 1 5 Move

Format: MOV 0 P 1 f 0P 2

Description:

Transfers the c o n t e n t s of the data field specified by

operand 1 into the data fields p e c i f i e d by o p e r a rid 2 »

Valid Data Types:

yes no

Integer I x i i

Bed I x I 1

Real I x l 1

String 1 x 1 1

Restrictions:

The length and type of operands 1 oa n d 2 m u s t be eq u a 1 ♦

Op Code- _______

*********CONFIDENTIAL> MOS T E C H N O L O G Y ?I N C ♦ ** ** ** ** * Page- 130

 Final D esign Specification for the M CS 6 5E 4 Microprocessor

***********
* LEADZ *
* * * * * * * * *<|v*

4 ♦ 7 ♦ 3 ♦ 16 Leadz

Format: LEADZ GP1?GP2

Descript i o n ;

S e a r c h e s th e data f i e l d referericed by o p e r a rid 1 for the

first occuranee of a z e r o bit* The r e s u l t s ar e r e t u r n e d in
the d a t a f i e l d s p e c i f i e d by o p e r a n d 2*

Valid Data Types for QPi:

ye s no

Integer4

Integers

B ed

Real

String i x l

Restrictions:

Th e data field referenced by 0P2 must be an integer*

F or ten byte real only the mantissa will be searched*

Example:

If the f i r s t z e r o is in the f i f t h p o s i t i o n of t he f o u r t h
b y t e t h e n a v a l u e of 30 < ( 4 - l ) * 8 + 4) ) w i l l be r e t u r n e d *
If th e f i r s t z e r o b i t is t h e f i r s t p o s i t i o n t h e n a v a l u e of
0 w i l l be r e t u r n e d *

Op Code-

********C O NFIDENTIAL? MOS TECHNOLOGY?INC********** Page- 131

 Final Design Specification for the MCS65 E 4 Microprocessor

***********
* LEAD1 *
***********

4*7*3*17 Leadl

Format! LEAD1 0P1>QP2

Description:

S e a r c h e s th e data field referenced by o p e r a rid 1 for the

first occuranee of a one bit* The r e s u l t s are r e t u r n e d in
th e d at a f i e l d s p e c i f i e d by o p e r a n d 2*

Valid Data Types for 0P 1 :

y es no

In t e g e r4 { x 1 I

Integers 1 x I I

Bed I x 1 i

Real I x l 1

String I x l 1

Restrictions:

T he data field referenced by Operand 2 must be an integer*

For ten byte real only the mantissa w i ll be searched*

Example:

If the f i r s t o n e is in t h e s e c o n d p o s i t i o n of th e t h i r d byte then

a v a l u e of 17 < ( 3 - l ) * 8 + 1) ) w il l be r e t u r n e d *

N ot e : If the f i r s t one bit is the first position then a value of 0

w i l l be r e t u r n e d *

Op Code- _______

*********CQNFIDENTIAL> MOS T E CH N O L O G Y >I N C ♦**** *** ** Page- 132

 Final Design Specification for the M C S6 5 E4 Microprocessor

* * * * * * * **
* C LR *
*********

4 ♦7 * 3 ♦ 1 8 Clear

Format: CLR QF‘l

Description:

L o a d s an a r i t h m e t i c z e r o into the data field specified by

the s i n g l e o p e r a n d c o n t a i n e d in the instruction*

Valid Data Types:

yes no

Integer i x l I

Bed I x l I

Real I x l 1

String I x l I

Op Code- _______

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C **** ** ** ** Page- 133

 Final De sign Specification for the M C S6 5E 4 Microprocessor

*********
* SE T *
*r 'Af v i/ %L* *Xr ^
✓fw • / f . ^ ^ ^ ^

4*7*3*19 Set

Format* SET OF* 1

I
Description:

S et on all b i t s (i*e m a k e s bits logic 1) in t h e data field

specified by the single o p e r a rid contained in the
instruction *

Valid Data Types:

yes no

Integer I x I

Be d I x I

Real i x l

String I x I

Op Code-

*********CONFIDENTIAL> MOS T E C H N O L O G Y >INC* * * * * * * * * * Page- 134

 Final Design Specification for the MCS6 5E4 Microprocessor

7*5 Pr o g r a m Control Instructions

7*5+1 Introduction

The set of progra m control i n s t r u c t i o n s d e s c r i b e d in this

section consists of those o p e r a t i o n s which d i r e c t l y affect
p r ogram flow d u r ing p r oces s e x ecut ion* This inclu des
co n d i t i o n a l branching? unconditional bran c h and Jump
instr u c t i o n s ? s u b r o u t i n e call and return? sy stem call and
return? and m i s c e l l a n e o u s pro c e s s control intru ctions * These
in s t r u c t i o n s will be o r g a n i z e d into four groups 3S follows!

1* Compar e and branch o perat i o n s *

2* Test and branch o perat ions*
3* Single o p erand control functions*
4* M i s c e l l a n e o u s (no operand) control funct ions*

*******CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 135

 i“ i n a 1 Des ig n SpeeifiC3tion for "the M C S 6 5 E 4 M i c r o p r o c e s s o r

OL/ •±r vLr - i/ \L* sir *Jj 'hr

/ v* ' t ' ^ 'p

* BE Q *
%y ^
•*'n•-!*
'ft* *JL* '±r ‘±r ^
T*■'ft'ft'ft'ft^'ft

4 * 7 *5 *2 C s m p are 3 nd B r 3 nch If Eq u3 1

Forinst: BEQ GP1?GP2>*

B EQ 0 P 1 fGP2>**

Description:

CouiP3re the d 3 to f i e l d referericed by OP 1 w i t h the d 3 t 3 field

r e f e r e n c e d by OF’2 and b r 3 n c h conditionslly ( $ : one byte
offset? two b y t e o f f s e t ) if t h e y a re e a u 31 ♦

Notes:

Loc3tiori f is d e t e r m i n e d by subtrsctirig the progrsiTi c o u n t e r

f r o m the b r s n c h d e s t in 3 1 i o n ♦ T h i s o f f s e t m u s t be grester
t h 3 n or e a u 31 to - 1 2 3 3rid l ess t h 3 n or e a u s l to -1*127 b y t e s
f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Loc3tiori is d e t e r m i n e d by s u b t r s c t i n g the p r o g r 3m c o u n t e r
f r o m the brsnch destinstion* T h i s o f f s e t m u s t be grester
t h a n or e a u a 1 to - 6 5 5 3 6 3nd l e s s t h 3 n or e a u 3 1 to + 6 5 5 3 5
b y t e s f r o m the s t s r t of the n e x t i n s t r u c t i o n s o p c o d e *

Restrictions:

Th e d 3 1 3 fields referenced by OF'l 3nd 0P2 must be the s em e

t y p e 3 nd length*

Op Codes:

*********CONFIDENTIAL> MOS T E C H N O L O G Y rI N C * * ** * * * * * * P 3 g e - 136

 Final Des ig n Specification for the M C S 6 5 E4 Microprocessor

*********
* BN E *
*********

4 * 7 * 5 *3 C o m a p r e a nd Branch If No t Eaua 1

Format: BNE 0P1>0P2**

BNE 0P1>QP2***

Description♦

C o m p a r e the d a t a f i e l d r e f e r e n c e d by 0P1 w i t h the d a t a f i e l d

r e f e r e n c e d by 0P2 and b r a n c h conditionally ($ o ne b y t e
offset? two b y t e o f f s e t ) if t h e y are no t e o u a l *

Notes:

Location # is d e t e r m i n e d by s u b t r a c t i n g th e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 8 and l ess t h a n or e a u a l to +1 2 7 b y t e s
f r o m the s t a r t of th e n e x t i n s t r u c t i o n s o p c o d e *

Location is d e t e r m i n e d by s u b t r a c t i n g t h e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 and l es s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Restrictions:

The data fields referenced by 0P1 and QP 2 must be the same

t y p e arid l e n g t h *

Op Codes!

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C * * * * ** * ** * Page- 137

 Final Des ig n Specification for the MC S6 5E 4 Microprocessor

* ********
* BGT *
*********

4*7*5*4 Compare an d Branch If Greater Than

Format: BGT 0F‘1 ? 0 P 2 ? *

BGT 0P1?GP2?*#

Description♦

Branch c o n d i t io n a11y (t on e b y t e o f f s e t ? l o c a t i o n two

byte offset) if the d a t a f i e l d r e f e r e n c e d by OF' 1 is greater
t h a n the d a t a f i e l d r e f e r e n c e d by Q P 2 ♦

Notes:

Location # is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 8 arid less t h a n or e a u a l to + 1 2 7 b y t e s
f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n ♦♦ is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 3n d l es s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Restrictions;

Th e d a t a fields referenced by 0P1 and QP2 must be the same

t y p e and length*

Op Codes:

********CONFIDENTIAL? MOS TECHNOLOGY?INC********** Page- 138

 Final Design Specification for the M C3 6 5E 4 Microprocessor

*********
* BGE *

4 * 7 *5 *5 C o m p a r e and Branch If Greater Than

Format; BGE 0 P 1 ? 0 F ‘2 ? *
BGE 0P1'?QP2?«

Description:

Branch conditionally (# one b y t e o f f s e t ? l o c a t i o n # * two

byte offset) if the data field r e f e r e n c e d by OF11 isg r e a t e r
t h a n or e o u a l to the data field r e f e r e n c e d by 0 P 2♦

Notes:

Location t is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 3 arid less than or e o u a l to + 1 2 7 bytes
f r o m the s t a r t of t he n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n #4 is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 and less t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Restrictions:

T he d a t a fields referenced by OF'l and 0F*2 m u s t be the same

t y p e and 1e n g t h *

Op Codes:

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 139

 Final Desig n Specification for the MC S6 5 E 4 Microprocessor

**********
* BEQZ *
**********

4♦7 *5♦6 Branch if Eaual

Format: BEQZ DPI?#

BEQZ QPlf**

Description:

Branch conditional! (# one byte offset; location ** two

byte offset) if data field referenced by QP1 is eaual to
zero*

Notes:

Location f is determined by subtracting the program counter

from the branch destination* This offset must be greater
than or eaual to -128? and less than or eaual to +127 bytes
from the start of the next instructions opcode*

Location £ # is determined by subtracting the program counter

from the branch destination* This offset must be greater
than or eaual to -65536 and less than or eaual to +65535
bytes from the start of the next instructions opcode*

0 p Codes:

* * * * * * * * * C O N F I D E N T I A L * MOS TECHNOLOGY?INC* ********* Page- 140

 Final De sign Specification for the MC S65 E4 Microprocessor

* BNEZ *
**********

4♦7♦5♦7 Branch If Not Eaual

Format: BNEZ QF’l;*

BNEZ 0P1,**

Description;

Branch conditionally (t one b y t e o f f s e t ? l o c a t i o n -t# two

b y t e o f f s e t ) if d a t a field r e f e r e n c e d by OF' 1 is n o t e a u a l to
zero *
*

Notes:

Location ♦ is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be Greater
t h a n or e a u a l to - 1 2 8 a nd less t h a n or e a u a l to + 1 2 7 b y t e s
f r o m the s t a r t of t he n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n * * is d e t e r m i n e d by s u b t r a c t i n g th e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be Greater
t h a n or e a u a l to - 6 5 5 3 6 a nd l es s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Op Codes;

*********CONFIDENTIAL> MOS T E C H N O L O G Y jINC ** * * * * * * * * F‘a3e- 141

 Final Desi gn Specification for the MC S65E 4 Microprocessor

* BROS *
**********

4* 7 *5♦3 B ranch If Positive

Format: BPOS 0P 1 j*
BPOS Q P 1 >**

Description:

Compare the data field referenced by 0P1 arid branch

c o n d i t i o n a l l y <$ one b y t e o f f s e t ? two b y t e o f f s e t ) if
the m o s t s i g n i f i c a n t bit is set to l o g i c 0*

Notes ;

Location # is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 3 a n d less t h a n or e a u a l to + 12 7 b y t e s
f r o m the s t a r t of th e n e x t i n s t r u c t i o n s o p c o d e *

Location is d e t e r m i n e d by s u b t r a c t i n g t h e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 arid l es s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of t h e n e x t i n s t r u c t i o n s o p c o d e *

Fo r bed? i n t e g e r and real? the s i g n b i t w h i c h is a l w a y s in

th e m o s t s i g n i f i c a n t bit? wi l l be t e s t e d for l o g i c 0* If the
v a l u e is p o s i t i v e a b r a n c h wil l o c c u r * The BMI i n s t r u c t i o n
(see S e c t i o n 4*7*5*?) ca n be u s e d for b r a n c h on n e g a t i v e
numbers *

Op Codes:

*********C0NFIDENTIAL? MOS T E C H N O L O G Y ?INC ** * * * * * * * * Page- 142

 Final Desi gn Specification for the M C S6 5 E4 Microprocessor

*********
* BM I *
*********
4*7*5*9 Branch If Minus

Format; BMI 0 P 1 ? #
BM I OP if**

Description;

Co m p a r e the data field referenced by OF' 1 arid branch

c o n d i t i o n a l l y (* one b y t e o f f s e t ? l o c a t i o n ** tw o b y t e
o f f s e t ) if t he m o s t s i g n i f i c a n t b i t is set to 1 o 2 i c 1 *

Notes :

Location * is d e t e r m i n e d by s u b t r a c t i n g th e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be Greater
than or e a u a l to - 1 2 8 and l ess t h a n or e a u a l to 4*127 b y t e s
f r o m the s t a r t of th e n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n ** is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be Greater
t h a n or e a u a l to - 6 5 5 3 6 and l ess t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

F o r bed? i n t e g e r arid real? the s i 2 ri b i t w h i c h is a l w a y s in

the m o s t s i g n i f i c a n t bit? w i l l be t e s t e d f o r 1 o 2 i c 1* If the
v a l u e is n e g a t i v e a b r a n c h w i ll o c c u r *

Op Codes J

* * * * * * * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ?INC ** * * * * * * * * P a 3 e - 143

 Final De sign Specification for the M CS 6 5E 4 Microprocessor

********
* BR *
********

4 ♦7 ♦5 ♦ 1,0 B r a n c h Relative Unconditionally

F o rm a 1 1 B R £
BR **

Description*

B r a n c h (t orie b y t e offset? location *t tw o byte offset)

unconditionally*

Notes t

Location # is d e t e r m i n e d by s u b t r a c t i n g the prodraui c o u n t e r

f r o m the branch destination* T h i s o f f s e t m u s t be greater
than or e a u a l to - 1 2 3 an d less t h a n or e a u a l to +127 bytes
from the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n t £ is d e t e r m i n e d by s u b t r a c t i n g t h e p r o g r a m c o u n t e r
from the br a rich destination* T h i s o f f s e t m u s t be greater
than or e a u a l to - 6 5 5 3 6 an d l es s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n s $ and ** c a n n o t s p e c i f y a v a r i a b l e w h i c h c o u l d be
u s e d for i n d i r e c t a d d r e s s i n g * I n s t e a d ? the g e n e r a t e d a d d r e s s
is a p o s i t i v e or n e g a t i v e o f f s e t f r o m th e o p c o d e of th e n e x t
instruction* I n d i r e c t a d d r e s s i n g c an be a c c o m p l i s h e d with
t he JMP i n s t r u c t i o n (see S e c t i o n 4 * 7 * 5 * 1 1 ) *

* * * * * * * * * C 0 N F I D E N T I A L ? MOS T E C H N O L O G Y ? I N C * ** * * * * * * * Page- 144

 Final Design Specification for the M C S6 5 E4 Microprocessor

*********
* JMP *

4*7*5*11 Jump Logical Address Unconditionally

Formatt JMP OF' 1

Description;

Jump u n c o n d i t i o n a l l y to th e address contained in the data

f i e l d r e f e r e n c e d by OP 1 ♦

Notes :

If the d e s t i n a t i o n l o c a t i o n is f i x e d (i»e» no t c a l c u l a t e d at
run t i m e bu t r a t h e r a s s e m b l e time) the d a t a f i e l d r e f e r e n c e d
by 0P1 should be an immediate value* However? if the
destination address is n o t k n o w n at a s s e m b l e t i m e t h e n 0P1
s h o u l d be a variable* In fact? O P 1 can d e f i n e an array
structure which could be u s e d to e s t a b l i s h an array of
addresses* Thu s ? a 'case' t y p e of i n s t r u c t i o n c a n be f o r m e d
(see e x a m p l e b e l o w ) *

Example

JMP TABLE C I3 0P1 = References an array structure*

LABLA

LABLB

LABLC

TABLE =
Descriptor Header

LABLA

LABLB

LABLC

The processor does the following to obtain th e JM P address:

Ge t TABLE'S operand control byte which indicates primary

*********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 145

 Final Design Specification for the M CS 6 5E 4 Microprocessor

based descriptor accessing and a two byte offset* The

c o n t e n t s of the p r i m a r y r e g i s t e r p l u s th e t wo byte offset
p o i n t to the d e s c r i p t o r h e a d e r *

Determ ine that T A B L E is 3 s i m p l e a r r a y of a t t a c h e d ordinals

(TABLE'S d e s c r i p t o r header indicat es this)*

Fetch subsript operand (variable I) fo r the index i nt o the

array*

D e t e r m i n e the address of T A B L E C I 1 (the a d d r e s s of t h e raw

d a t a is TABLE + 3*1 (see S E C T I O N _______ ) for t r a v e r s i n g
th r o u g h an a r r a y ) *

T he d a t a field (three byte ordinal) referenced by TABLECIU

is t h e l o g i c a l a d d r e s s fo r the p r o g r a m c o u n t e r *

T he program continues with the appropiate program counter*

In th e above example if I e a u a l s 0 t h e n the p r o g r a m will

J u m p to LABLA* If I e a u a l s 1 t h e n the p r o g r a m w i l l J u m p to
L A B L B and if I e a u a l s 2 t h e n the p r o g r a m w ill J u m p to L A B L C *

*********CONFIDENTIAL> MOS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 146

 Final De sign Specification for the M C S 6 5 E4 Microprocessor

*********
* BSR *
*********

4♦7♦5♦12 Branch to Subroutine

Format: BSR *
BSR **

Dascription!

B r a n c h to subroutine at l o c a t i o n $ (one b y t e offset) or

l o c a t i o n * * (two b y t e offset) u nconditionally*

Notes:

Location # is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 8 an d less t h a n or e a u a l to + 1 2 7 b y t e s
f r o m the s t a r t of th e n e x t i n s t r u c t i o n s o p c o d e *

Location is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 and le s s t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n s t and ** ca n n o t s p e c i f y a v a r i a b l e w h i c h c o u l d be
u s e d for i n d i r e c t a d d r e s s i n g * I n s t e a d ? the g e n e r a t e d a d d r e s s
is a p o s i t i v e or n e g a t i v e o f f s e t f r o m the o p c o d e of t h e n e x t
instruction* I n d i r e c t a d d r e s s i n g c an be a c c o m p l i s h e d with
t h e JSR i n s t r u c t i o n (see S e c t i o n 4 * 7 * 5 * 1 3 ) *

Th e r e t u r n a d d r e s s from the s u b r o u t i n e is s a v e d o n t o the

s t a c k as described in S e c t i o n ___________ * E x i t i n g f r o m the
s u b r o u t i n e is accomplished by e x e c u t i n g the return from
s u b r o u t i n e (RTS) i n s t r u c t i o n (see S e c t i o n 4 * 7 * 5 * 1 8 ) *

*********CQNFIDENTIAL> MQS T E C H N O L O G Y ?I N C * * * * * * * * * * Page- 147

 Final D esign Specification for the M C S6 5 E4 Microprocessor

^ ^ ^

* JSR *
*********

4,7.5.13 Jump To Subroutine

Format; JS R DPI

Description t

B r a n c h to s u b r o u t i n e at the address contained in th e data

f i e l d r e f e r e n c e d by 0P1.

Notes J

If the d e s t i n a t i o n l o c a t i o n is f i x e d (i.e. n ot c a l c u l a t e d st
run t i m e bu t r a t h e r a s s e m b l e time) the d a t a f i e l d r e f e r e n c e d
by 0P1 should be an immediate value. However) if the
destination address is no t k n o w n at a s s e m b l e t i m e t h e n OF'l
s h o u l d be a variable. In fact* QP1 c a n d e f i n e an array
structure which could be u s e d to e s t a b l i s h an array of
a d d r e s s e s (see e x a m p l e b e l o w ) .

The return a d d r e s s from the s u b r o u t i n e is s a v e d o n t o the

s t a c k as described in S e c t i o n ___________ . E x i t i n g f r o m the
s u b r o u t i n e is accomplished by e x e c u t i n g the return from
s u b r o u t i n e (RTS) i n s t r u c t i o n (see S e c t i o n 4 . 7 . 5 . 1 8 ) .

E x a m p 1e

JS R TABLECIIl 0P1 = References an array structure,

LABLA

LABLB

LABLC

TABLE =
Descriptor Header

LABLA

LABLB

i LABLC I

*********CONFIBENTIAL> MOS T E C H N O L O G Y > I N C . ** ** ** *** P 3 g e - 148

 Final D es ig n Specification for the M C S 65 E 4 Microprocessor

T he processor does the following to ohtairi t he s u b r o u t i n e a d d r e s s :

Get T A B L E ' S operand control byte which indicates primary

based descriptor accessing and a two byte offset* The
c o n t e n t s of the p r i m a r y r e g i s t e r p l u s the two byte of f s e t
p o i n t to the d e s c r i p t o r h e a d e r *

Determine that TABLE is an array of a t t a c h e d ordinals

(TABLE'S descriptor header indicates this)*

Fetch subsript operand (variable I) for the index into the

array*

D e t e r m i n e the address of T A B L E C I U (the a d d r e s s of t h e raw

d a t a is TABLE + 3*1 (see S E C T I O N _______ ) for t r a v e r s i n g
t h r o u g h an a r r a y ) *

The da t a field (three byte ordinal) referenced by TABLECI3

is the l o g i c a l a d d r e s s for the p r o g r a m c o u n t e r *

The program continues with the appropiate program counter*

In the above example if I e a u a l s 0 t h e n the p r o g r a m will

J u m p to LABLA* If I e a u a l s 1 t h e n the p r o g r a m wi l l J u m p to
L A B L B a nd if I e a u a l s 2 t h e n the p r o g r a m w i l l J u m p to L A B L C *

*********CONFIDENTIAL> MOS T E C H N O L O G Y ; I N C *** * * * * * * * Page- 14?

 Final Design Specification for the M CS 65 E4 Microprocessor

* BDEC *
**********

4 ♦ 7 ♦5 * 14 Decrement arid B r a n c h

Format I BDEC 0 P 1 ? -t !
BDEC OPlf*#

Description t

D e c r e m e n t the data field referenced by GPl and branch

conditionally (t one b y t e o f f s e t ? location £# two b y t e
o f f s e t ) if it is n o t e a u a l to 0*

Notes*

Location # is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 1 2 8 a n d less t h a n or e a u a l to +1 2 7 b y t e s
f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

Location is d e t e r m i n e d by s u b t r a c t i n g th e p r o g r a m c o u n t e r
f r o m the branch destination* T h i s o f f s e t m u s t be greater
t h a n or e a u a l to - 6 5 5 3 6 and l e ss t h a n or e a u a l to + 6 5 5 3 5
b y t e s f r o m the s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

This i n s t r u c t i o n is v e r y useful in a l oo p s i t u a t i o n * GPl

first contains a positive integer w h i c h s e r v e s as a c o u n t e r *
The M C S 6 5 E 4 will e x e c u t e t h e lo o p until this c o u n t e r reaches
z e r o and wi l l t h e n p r o c e e d to t h e next instruction*
Op C o d es J

********CONFIDENTIAL? MOS T E C H N O L O G Y >I N C ♦ ** ** ** ** * Page- 150

 Final Desig n Specification for the M C3 6 5E 4 Microprocessor

***********
* BCQND *
******* ****

4*7*5*15 Brarich On Coriditiori

Format: BCOND aPl?0P2?GP3

Description:

A d d t he data field referenced by 0P1 to the d a t a field

r e f e r e n c e d by 0P2 s t o r i n g the r e s u l t s b a c k into the f i e l d
r e f e r e n c e d by OF‘2* The r e s u l t is c o m p a r e d to the field
r e f e r e n c e d by O P 3♦ Th e p r o c e s s o r w il l then c o n d i t i o n a l l y
b r a n c h to location * (one b y t e o f f s e t ) or l o c a t i o n ** (two
byte o f f s e t ) *

Notes:

T h e B C O N D i n s t r u c t i o n is s i m i l a r to the F O R T R A N do loop* The

field referenced by 0P1 is the ' s t e p p i n g v a l u e * ? the f i e l d
referenced by OF*3 is t he limit value? arid the field
r e f e r e n c e d by OF’2 is the c u r r e n t v a l u e w i t h i n th e loop*

T h e “s t e p p i n g v a l u e - c an e i t h e r be p o s i t i v e or n e g a t i v e * If
it is p o s i t i v e the c u r r e n t v a l u e is i n c r e m e n t e d u n t i l it is
greater than or e a u a l to the l i m i t v a l u e * If th e “s t e p p i n g
v a l u e * is n e g a t i v e the c u r r e n t v a l u e is d e c r e m e n t e d u n t i l it
is l e ss t h a n or e a u a l to t he l i m i t v a l u e *

Relative Value t is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m

counter f r o m the b r a n c h destination* This offset must be
g r e a t e r t h a n or e a u a l to - 1 2 3 3n d less t h a n or e a u a l to + 1 27
b y t e s f r o m t h e s t a r t of t he n e x t i n s t r u c t i o n s o p c o d e *

Relative Value $* is d e t e r m i n e d by s u b t r a c t i n g the p r o g r a m

counter f r o m the b r a n c h destination* This offset must be
greater t h a n or e a u a l to - 6 5 5 3 6 and le s s t h a n or eaual to
+65535 bytes f r o m th e s t a r t of the n e x t i n s t r u c t i o n s o p c o d e *

L o c a t i o n s * and ** can n o t s p e c i f y a v a r i a b l e w h i c h c o u l d be
u s e d for i n d i r e c t a d d r e s s i n g * I n s t e a d ? the g e n e r a t e d a d d r e s s
is a p o s i t i v e or n e g a t i v e o f f s e t f r o m th e o p c o d e of the n e x t
instruction*

*********CONFIDENTIAL? MGS TECHNOLOGY?INC* ********* P a g e - 151

 Final Des ig n Specification for the MC S6 5E 4 Microprocessor

* SC *
********

4♦7♦5♦16 System Call

Format: SC

Description:

C a u s e s the p r o c e s s o r to e x e c u t e a t r 3P t h r o u g h the e x c e p t i o n
v e c t o r l o c a t e d at the a d d r e s s _____________ _ on the l i m i t p a g e *
This operation is described in more detail in Section

Restrictions X

Must be serviced within operating system process (U = 0)*

********CONFIDENTIAL? MOS T E C H N O L O G Y ? I N C ♦*** ** ** ** P a g e - 152

 Final Design Specification for the MCS65 E 4 Microprocessor

*********
* 3CM *
*********

4*7*5*17 System C all Message

Format! SC M *

Description t

C a u s e s the p r o c e s s o r to e x e c u t e a t r a p t h r o u g h the e x c e p t i o n
vector located at a d d r e s s ------- w i t h i n the l i m i t p a g e * At
the s a m e ti me? the 8 b i t m e s s a g e ($> w h i c h f o l l o w s the
o p e r a n d is p a s s e d to the o p e r a t i n g s y s t e m * T h i s o p e r a t i o n is
d e s c r i b e d in m o r e d e t a i l in S e c t i o n ___________ ♦

Restrictions;

Must be serviced within operating system process*

*********CONFIDENTIAL? MOS T E C H N O L O G Y >I N C * * * * * * * * * * Page- 153

 Final D e si gn Specification for the M C S6 5 E4 Microprocessor

* ****^ ** *
* RTS *
*********

4 ♦ 7 ♦5 ♦ 18 Return From Subroutine

Format: RTS

Description:

Return from subroutine*

Notes:

The J SR or BSR was used to C3ll the s u b r o u t i n e arid

subsequently the r e t u r n a d d r e s s was s a v e d on t he p r o c e s s
stack* The RTS instruction is u s e d to get b a c k to the
caller*

* * * * * * * * * C 0 N FID E N T IA L ? HQS T E C H N O L O G Y ? I N C * ** * * * * * * * Page- 154

 Final De sign Specification for the M C S 65 E4 Microprocessor

sj^ ^

* RTE *
*********

4*7*5*19 Retrurn From Exception

Format: RTE DPI

Description:

R e t u r n to th e m i d d l e of instruction execution* The d a t a

field referenced by 0P1 c o n t a i n s all the necessary return
information*

Notes:

This instruction s h o u l d o n l y be executed w h e n r e t u r n i n g to

an i n s t r u c t i o n within the s a m e process* The T A S K or IOS
instruction should be u s e d w h e n returning to 3n i n s t r u c t i o n
within another process*

********CONFIDENTIAL? tfOS T E C H N O L O G Y >I N C ♦ ** *** ** ** Page- 155

 Final Desi gn Specification for the M C S 6 5 E 4 Microprocessor

\Lf s ir \Lr *i^ * lf

^ sf%

* I OS *
*********

4*7*5*20 Initiate Operating System

Format: IOS 0P1

Description:

Initiates a higher - le ve l o p e r a t i n g s y s t e m p r o c e s s * The

u s e r / s u p e r v i s o r f l a g r e m a i n s l o g i c 0* The k e r n a l f l a g is set
to a logic 0* The o p e r a t i o n is d e s c r i b e d in detail in
S e c t i o n _________ ♦

Notes:

The data field referenced by OP 1 specifies th e logical

a d d r e s s of the n e w p r o c e s s *

Restrictions:

M u s t be serviced within an Operating System or Kernel

p ro c e s s *

*********C0NFIDENTIAL> MOS T E C H N O L O G Y ? INC* * * * * * * * * * Page- 156

 Final D es i gn Specification for the M CS 6 5E 4 Microprocessor

**********
* TASK *
•■
;
Pkns
± /yv
± /'fJ\z £ £ 'k&
/p %
*X«

4 ♦ 7 ♦5 ♦ 21 TASK

Format: TASK 0P1

Description;

Initiates a u s e r p r o c e s s * B o t h th e u s e r / s u p e r v i s o r f l a g and
t he k e r n s l f l a g 3re set to 0♦ T h i s o p e r a t i o n is d e s c r i b e d in
d e t a i l in S e c t i o n _________ ♦

Notes ;

T he datafield referenced by 0 P 1s p e c i f i e s the l o g i c a l

a d d r e s s of the processparameter l ist (PPL) for the new
process*

Restrictions;

Must be serviced within 3n operating system process*

********C ONFIDENTIAL? MOS T E C H N O L O G Y >I N C ♦* *** ** ** * Page- 157

 Final Design Specification for the M C S6 5E 4 Microprocessor

4*7*6 Advanced Operations

4 ♦ 7 ♦6♦1 Introduction

T hi s g r o u p of i n s t r u c t i o n s c o n t a i n s a n u m b e r of p o w e r f u l i n s t r u c t i o n s
w h i c h g r e a t l y f a c i l i t a t e th e c o n t r o l of p r o g r a m s e q u e n c i n g w i t h i n
the M C S 6 5 E 4 s o f t w a r e * T h e s e i n s t r u c t i o n s a l l o w t h e p r o c e s s o r to c o m p a r e tw
d a t a f i e l d s and to set a B o o l e a n v a r i a b l e as a f u n c t i o n of the d a t a in the
two f i e l d s * In a d d i t i o n ? a fu l l set of s t r i n g i n s t r u c t i o n s ? d a t a s h i f t i n g
i n s t r u c t i o n s and d a t a c o n v e r s i o n i n s t r u c t i o n s is p r o v i d e d a l o n g w i t h a num
of i n s t r u c t i o n s w h i c h are s p e c i f i c a l l y d e s i g n e d to f a c i l i t a t e th e c o n t r o l
of the d a t a w i t h i n the M C 3 6 5 E 4 p r o c e s s * E a c h of t h e s e i n s t r u c t i o n s is
d e s c r i b e d below*

*********CONFIDENTIAL? MOS T E C H N O L O G Y ?I N C ** * * * * * * * * Page- 158

 Final D esi gn Specification for the MCS6 5 E 4 Microprocessor

***********
* RESET *
***********

4 ♦ 7 ♦ 6 ♦2 R e s e t

Format: RESET

Description;

C a u s e s the IORES bit in the bus status word to go low for 16

cycles ♦

Notes!

The instruction has no operands*

* * * * * * * * * C O N F I D E N T I A L > HQS T E C H N O L O G Y ? I N C ** * * * * * * * * Page- 15?

 Final D esign Specification for the M CS 6 5E 4 Microprocessor

*********
* CEQ *

4 ♦ 7 ♦ 6 ♦3 C o m p a r e Tw o O p e r a rids For Eauality

Format: CEQ 0P1*QP2>QP3

Description:

C o m p a r e for e a u a l l t y the d a t a f i e l d r e f e r e n c e d by 0P1 w i t h

the d a t a f i e l d r e f e r e n c e d by 0 P2 and place the boolean
result into the low order bit p o s i t i o n of the field
r e f e r e n c e d by 0P3*

Notes :

If the field referenced by 0P1 is eaual to the field

r e f e r e n c e d by OF'2 t h e n the v a l u e 0 0 0 0 00 0 1 wil l be p u t into
t he d a t a field referenced by OF'3* If th e f i e l d s are not
e a u a l the value 0000 0000 wi l l be pu t into the field
r e f e r e n c e d by OP 3 ♦

The d a t a f i e l d r e f e r e n c e d by OF'3 s h o u l d be b y t e d a t a type*

If it is not? o n l y the l e a s t s i g n i f i c a n t byte w il l be
a f f e c t e d by the instruction*

Restrictions:

T he fields referenced by 0P1 and 0 P2 must be the same type

and length*

Example:

B e f o r e CEQ i n s t r u c t i o n :
OF* 1 = R e f e r e n c e s a d a t a field whose value is 16
OF’2 = R e f e r e n c e s a d a t a field whose value is 16
0P3 = R e f e r e n c e s a data field whose value is 0111 0001

A f t e r CE Q i n s t r u c t i o n :
QF‘1 = R e f e r e n c e s a d a t a field whose value is 16
0P2 = R e f e r e n c e s a data field whose value is 16
OF*3 = R e f e r e n c e s a d a t a field whose value is 0 0 0 0 000 1

*********C0NFIDENTIALi H0S TECHNOLOGY*INC********** Page- 160

 Pinal D esi gn Specification for the MC S65 E 4 Microprocessor

*********
* CNE *
*********

4 ♦7 ♦6 ♦4 Co hip a r e Tw o Operands F or Ineauality

Format! CN E 0P1>0P2>0P3

Description ;

C o m p a r e for ineauality? t he d a t a f i e l d r e f e r e n c e d by OF' 1

w i t h the data field reference d by OF'2 an d p u t the b o o l e a n
result i n to the low order bit position of th e field
r e f e r e n c e d by 0 P 3 *

Notes;

If the field referenced by 0F‘1 is n o t e a u a l to the f i e l d

r e f e r e n c e d by 0 P 2 t h e n the v a l u e 0 0 0 0 0 0 0 1 w il l be p u t int o
t he d a t a f i e l d r e f e r e n c e d by OP3 ♦ If t h e f i e l d s are e a u a l
t he v a l u e 0 0 0 0 0 0 0 0 w i l l be pu t i n t o the f i e l d r e f e r e n c e d by
0P3 ♦

T he d a t a field referenced by OF'3 s h o u l d be b y t e d a t a type*

If it is not? o n l y th e least s i g n i ficant byte will be
affected♦

Restrictions;

The fields referenced by OP 1 and OF'2 must be the same type

a nd length*

Example;

B e f o r e CNE i n s t r u c t i o n ;
0P1 = R e f e r e n c e s a d a t a field whose value i s 13
0P2 = R e f e r e n c e s a d a t a field whose v a 11 je is 1 6
0P3 R e f e r e n c e s 3 data field whose v a 1 *j e is 011 1 0001

After C NE i n s t r u c t i o n ;
0P1 = R e f e r e n c e s a data field whose v a l u e i s 13
0P2 = R e f e r e n c e s 3 data field whose v a 11 je is 16
OF‘3 = R e f e r e n c e s 3 data field whose v a l u e is 0000 0001

*********C0NFIDENTIAL? M0S T E C H N O L O G Y ?I N C * * * * * * * * * * Page- 161

 Final Design Specification for the M CS 6 5E 4 Microprocessor

L- -J/ •<, X , -J.- -V -.U -4/

.j-. f - • r 'f r 'r - ' I ' /»*•

* CGT *
r-
* -V• ! ' *'r*k * •T'><»'
'V's'-

4 * 7 * 6 *5 C o hip 3 r e T w o Operands For Greater Than

Format: CGT 0 P 1 ?0 P 2 ? 0 P 3

Description:

C o m p a r e the d a t a f i e l d r e f e r e n c e d by 0 P 1 w i t h the d at a f i e l d
r e f e r e n c e d by QP2* If t he d a t a f i e l d r e f e r e n c e d by 0P1 is
greater than the d a t a f i e l d r e f e r e n c e d b y O P 2 t h e n p u t the
boolean result into the low order bit position into the
f i e l d r e f e r e n c e d by OF’3*

Notes :

If the f ie 1d r e f e r e nc e d by 0 P 1 is greater than the f i e l d

r e f e r e n c e d by 0P2 t h e n t h e v a l u e 0 0 0 0 0 00 1 w i l l be p u t i n t o
the data field r e f e r e n c e d by 0P3 else the value 0000 0000
will be used*

Th e dats field referenced by OF’3 should be byte data type*

If it is not? only the least significant byte will be
affected*

Restrictions:

Th e fields referenced by 0 P 1 arid OF’2 must be the same type

a nd length*

Example:

B e f o r e CGT i n s t r u c t i o n :
OF* 1 = R e f e r e n c e s a d a t a field whose v a l u e is 47
OF’2 = R e f e r e n c e s a d a t 3 field whose v a l u e is 16
OF’3 = R e f e r e n c e s a d a t a field whose v a l u e is 0111 0001

A f t e r CGT i n s t r u c t i o n
0 P 1 = Refer e n c e s a data field whose v a l u e is 47
0F‘2 = R e f e r e n c e s a d a t a field whose v a l u e is 16
OF'3 = R e f e r e n c e s a d a t a field whose v a l u e is 1 1 10 0011

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ? I N C *** * * * * * * * P a g e - 162

 F i n s 1 D esi gn Specification for the MC365E 4 Microprocessor

*********
■ V ■( / • !/ -,Lr •»/ \( / •,<.*
• i-. • ) ' ■?• f‘- • ! ' -t>

4 * 7 *6 *6 C o hip a r e Two Operands For G re a t e r T h a n Or Eaual

Format: CGE 0Pl*QP2i0P3

Description:

C o m p a r e the d a t a f i e l d r e f e r e n c e d by 0 P 1 w i t h the d a t a f i e l d
r e f e r e n c e d by 0 P 2♦ If the d a t a f i e l d r e f e r e n c e d by 0 P 1 is
g r e ater than or e a u a l to the d a t a f i e l d r e f e r e n c e d by 0 P 2
t h e n pu t the b o o l e a n r e s u l t into the low o r d e r b i t p o s i t ion
i n t o the f i e l d r e f e r e n c e d by 0 P3 *

Notes:

If the f i e l d r e f e r e n c e d by 0 P 1 is g r e a t e r t h a n or e a u a l to
th e f i e l d r e f e r e n c e d by 0 P 2 t h e n the v a l u e 0 0 0 0 0001 w ill be
p u t into the d a t a f i e l d r e f e r e n c e d by 0 P 3 else the v a l u e
0 0 0 0 0 0 0 0 wi l l be u sed*

T he d a t a field referenced by 0 P 3 s h o u l d be b y t e d a t a type*

If it is not? o n l y the least si g n i f i c a n t byte wi l l be
affected*

Restrictions t

The fields referenced by OF’1 arid OF’2 must be the same type,
arid l e n g t h *

Example:

Before C GE i n s t r u c t i o n :
0P 1 = R e f e r e n c e s a data field whose value is 47
OF‘2 = R eferences a data field whose value is 16
0P3 = R e f e r e n c e s a data field whose value is 0111 0 001

After CGE i n s t r u c t i o n :
OF* 1 = R e f e r e n c e s a data field whose value is 47
OF‘2 = R e f e r e n c e s a data field whose value is 16
OF*3 = R e f e r e n c e s a data field whose value is 0 0 0 0 0001

* * * * * * * * * C 0 N F I D E N T I A L j MQS T E C H N O L O G Y ?INC ** * * * * * * * * Page-

 Final D esign Specification for the MCS65E 4 Microprocessor

•I.* *.V -X- \J / \^r * ir \ y \ ir '« /

/,■. •■f* *r* *t > -r> •r« •{•

* FIND *
• v-vv •>-V *V--k'k
/ f . . f . . f. .fv .-fs -r* •P' -r-

4 *7 *6 * 7 F i n d S t ri ng

Format : FIND 0P1?0P2?0P3

Description

F i n d the first occurance of 3 specified data i t em within a

gi ve n s t r i n g *

opi:

The dat3 field referenced by OF’1 contains the search

a r g u m e n t and must be of t yp e b yt e ? integer* o r d i n a l or
string*

0P2J

T h e d a t a f i e l d r e f e r e n c e d by OF’2 c o n t a i n s the starting point

of the s t r i n g d 3 t a f i e l d r e f e r e n c e d by 0P3*

GP3:

T h e d a t s f i e l d r e f e r e n c e d by O P 3 r e p r e s e n t s the s t r i n g f i e l d
to be searched* The s t a r t i n g point w i t h i n the dats field
r e f e r e n c e d by OF‘3 is c o n t a i n e d in the d a t a f i e l d r e f e r e n c e d
by OF‘2 *

Notes!

T h e d a t a r e f e r e n c e d by O p e r a rid 3 m u s t be of t y p e s t r i n g * The
l e n g t h of t h i s s t r i n g is d e f i n e d by its d e s c r i p t o r *

If the d a t a r e f e r e n c e d by O p e r a rid 1 is of t y p e s t r i n g ? t h e n
o n l y the f i r s t 8 b y t e s are u s e d for the search argument*

It is the u s e r s r e s p o n s i b i l i t y to i n i t i a l i z e the d a t a f i e l d
r e f e r e n c e d by O P 2 w i t h the i n i t i a l s t a r t i n g p o i n t w i t h i n the
string* T he s e a r c h will b e g i n f r o m the first byte of the
s t r i n g if the d a t a f i e l d r e f e r e n c e d by 0 P 2 c o n t a i n s -1* If a
m a t c h is detected? the d a t s f i e l d r e f e r e n c e d by OF*2 will
contain a positive number w h i c h w ill indicate the byte
p o s i t i o n w i t h i n the s t r i n g * W h e n t h e s e 3 r c h is c o m p l e t e ? the
d a t a f i e l d r e f e r e n c e d by GP 2 will c o n t a i n -2*

Example:

Before FIND instruction:

OF11 = R e f e r e n c e s a dats field whose value is: N O W BR

OF12 = R e f e r e n c e s a data field whose value is: -1
OP3 = References a dats field whose value is: H O W M O W BROWN COW*

********CONFIDENTIAL? MOS T E C H N OL OG Y ?INC ** * * * * * * * * P a g e - 164

 Final D es i gn Specification for the M CS 65 E4 Microprocessor

After FIND instruction?

OF'l =References a data field whose value is* NOW BR

0P2 = R e f e r e nc es a da t a field whose value is? +9
OP3 =R e f e r e n c e s a data field whose value is? H O W N 0 U B R O U N COW

*********CONFIDENTIAL» MOS T E C H N O L O G Y »I N C . ** ** ** * ** Page- 165

 Final D esi gn Specification for the MCS65 E 4 Microprocessor

##***:***#*
* 'f|:r— p
***#*#*###

4 * 7 ♦6 *8 D e t e c t Character in String

Format: DETC 0P1?QP2?QP3

Description:

F i n d the first byte in a string which matches a byte from a

g i v e n set of b y t e s *

opi :

The data f i e l d r e f e r e n c e d by OPI contains the s e t of bytes

w h i c h will be m a t c h e d a g a i n s t the search string*

0 P2 :

T h e d a t a f i e l d r e f e r e n c e d by 0P2 c o n t a i n s the starting point

of the s t r i n g d a t a f i e l d r e f e r e n c e d by OF’l*

op 3:

T he d a t a f i e l d r e f e r e n c e d by O P 3 r e p r e s e n t s the s t r i n g f i e l d
to be searched* The s t a r t i n g p o i n t w i t h i n the data field
r e f e r e n c e d by OF‘3 is c o n t a i n e d in the d a t a f i e l d r e f e r e n c e d
by 0 P2*

Notes :

T h e d a t a r e f e r e n c e d by O p e r a n d 3 m u s t be of t y p e s t r i n g * The
l e n g t h of t h i s s t r i n g is d e f i n e d by, its d e s c r i p t o r *

If the d a t a r e f e r e n c e d by O p e r a n d 1 is of t y p e s t r i n g ? t h e n
o n l y the f i r s t 8 b y t e s are u s e d for the search argument*

It is the u s e r s r e s p o n s i b i l i t y to i n i t i a l i z e the d a t a f i e l d
r e f e r e n c e d by OF'2 w i t h the i n i t i a l s t a r t i n g p o i n t w i t h i n the
string* The s e a r c h will begin from the first byte of the
s t r i n g if t h e d a t a f i e l d r e f e r e n c e d by OF'2 c o n t a i n s -1 *

T he s e a r c h s t o p s if any b y t e f r o m the set of b y t e s m a t c h e s a

byte within the s e a r c h s t r i n g * In t h a t c a s e? the d a t a f i e l d
r e f e r e n c e d by OF’2 wi l l c o n t a i n a p o s i t i v e n u m b e r w h i c h will
i n d i c a t e the byte position w i t h i n the string* W h e n the
s e a r c h is complete? the d a t a f i e l d r e f e r e n c e d by OF’2 will
cor«tain -2*

Example J

Before DETC instruction:

OPI = R e f e r e n c e s a data field whose value is: XYZW

0P2 = References a data field whose value is: -1

** *** * * * C O N F I D E N T I A L ? MOS T E C H N O L O G Y ?I N C ** * * * * * * * * Page- 166

 F i n 3 1 D es ig n Specif'ic3 t i o n ■for the MC365E 4 Microprocessor

0P3 = References s data field whose v a l u e is: HOW NO W B R O U N COU.

After DETC instruction:

0P1 = References a da ta field whose v a l u e is: X YZ U

0F‘2 = References a data field whose v a l u e is: +2
OF'3 = References s data field whose v a l u e is: H O W N O W B R O U N COW.

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C ♦ * ** *** *** p 3o 0 — 167

 Final Design Specification for the MC S6 5E 4 Microprocessor

###*#***##
% NDET t
#**###***#

4 * 7 *6 ♦? D e t e c t Character no t in String

Format: NDET 0P1?0P2?0P3

Description:

Find the first byte in a string which does not matches a

byte from a given set of bytes*

opi :

The data f i e l d r e f e r e n c e d by 0P1 contains the s e t of bytes

w h i c h w i ll be m a t c h e d a g a i n s t the search string*

QP2:

T he d a t a f i e l d r e f e r e n c e d by QP2 c o n t a i n s the starting point

of th e s t r i n g d a t a f i e l d r e f e r e n c e d by GP3*

QF'3 :

T h e d a t a f i e l d r e f e r e n c e d by OF'3 r e p r e s e n t s the s t r i n g f i e l d
to be searched* Th e s t a r t i n g p o i n t w i t h i n the data field
r e f e r e n c e d by OF’3 is c o n t a i n e d in the d a t a f i e l d r e f e r e n c e d
by 0 P 2 *

Notes:

T h e d a t a r e f e r e n c e d by O p e r a n d 3 m u s t be of t y p e s t r i n g * The
l e n g t h of t h i s s t r i n g is d e f i n e d by its d e s c r i p t o r *

If the d a t a r e f e r e n c e d by O p e r a n d 1 is of t y p e s t r i n g ? t h e n
o n l y the f i r s t 8 b y t e s are u s e d for the search argument*

It is the u s e r s r e s p o n s i b i l i t y to i n i t i a l i z e the d a t a f i e l d
r e f e r e n c e d by OF'2 w i t h th e i n i t i a l s t a r t i n g p o i n t w i t h i n the
string* The s e a r c h will b e g i n f r o m the frrst byte of the
s t r i n g if the d a t a f i e l d r e f e r e n c e d by OF’2 c o n t a i n s -1*

Th e s e a r c h s t o p s ifany b y t e f r o m the se t of b y t e s d o e s not

match a b y t e w i t h i n the s e a r c h s t r i n g * In t h a t case* the
data field r e f e r e n c e d by 0P2 wil l c o n t a i n a p o s i t i v e n u m b e r
w h i c h w il l i n d i c a t e the byte p o s i t i o n w i t h i n the string*
W h e n the s e a r c h is c o m p l e t e ? t h e d a t a f i e l d r e f e r e n c e d by
0 P 2 will c o n t a i n -2*

Example:

Before NDET instruction:

0F‘2 = References a data f i e l d w h o s e v a l u e is: ABCMCS

OF* 1 = References a data field whose value is: -1

******#**CONFIDENTIAL> MOS T E C H N O L O G Y >INC ** * * * * * * * * Page- 168

 F i n 31 D es ig n Specification for the M C S6 5 E4 Microprocessor

0P3 = References a data field whose value is I H C S 6 5 E 4

After ND E T instruction!

0P1 = References 3 data field whose value is: ABCMCS

0P2 = References 3 data field whose value is { +3
0P 3 = References a data field whose value ist M C S 6 5 E 4

*********CONFIDENTIAL> MOS T E C H N O L O G Y >I N C , ** ** ** ** * P a 2 e - 16?

 Final Design Specification for the M C365 E 4 Microprocessor

!/£ ;•'/;£ 'V-4/;£•£

;:
v f!F T R >K
**********

4,7,6*10 DETR

Format: DETR GF‘1 ? 0 P 2 ? 0 P 3

Description:

Search strind for a sirisle byte which is within a defined

ranSe *

0P1 :

T h e d a t a f i e l d r e f e r e n c e d by 0P1 c o n t a i n s the tw o b y t e r a n d e
field which d e f i n e s the l o w e r and upper bound* The l e a s t
signif i c a n t byte of t h i s f i e l d d e f i n e s the u p p e r b o u n d and
n e x t c o n s e c u t i v e b y t e d e f i n e s the l o w e r b o u n d *

0P2:

The d a t a f i e l d r e f e r e n c e d by OF'2 c o n t a i n s the starting point

of the s t r i n g d a t a f i e l d r e f e r e n c e d by 0 P 3 *

QP3:

T h e d a t a f i e l d r e f e r e n c e d by QF‘3 r e p r e s e n t s the s t r i n g f i e l d
to be searched* Th e s t a r t i n g p o i n t w i t h i n the data field
r e f e r e n c e d by .OF'3 is c o n t a i n e d in the d a t a f i e l d r e f e r e n c e d
by 0 P 2 *

Notes:

As s t a t e d above? the l e a s t s i g n i f i c a n t b y t e of the f i e l d

r e f e r e n c e d by OP 1 d e f i n e s the lower b o u n d and the next
cons e c u t i v e byte defines the upper bound of the ran 2 e *
D u r i n g the search operation? a n y b y t e f r o m the data field
w h i c h is r e f e r e n c e d by OF'3 w h i c h is g r e a t e r t h a n or e a u a l to
th e l o w e r b o u n d and l e s s t h a n or e a u a l to the u p p e r b o u n d
will halt the s e a r c h o p e r a t i o n *

It is the u s e r s r e s p o n s i b i 1 ity to i n i t i a l i z e the d a t a f i e l d

r e f e r e n c e d by 0P2 w i t h th e i n i t i a l s t a r t i n g p o i n t w i t h i n the
string* The s e a r c h will b e d i n f r o m the first byte of the
s t r i n g if th e d a t a f i e l d r e f e r e n c e d by OF'2 c o n t a i n s -1* W h e n
a byte is w i t h i n the d e f i n e d ra n ^e ? a p o s i t i v e n u m b e r will
be r e t u r n e d which indicates the b y t e position within the
string* When the search is complete? the d a t a field
r e f e r e n c e d by OF*2 wi l l c o n t a i n -2*

E x a m p le :

Before DETR instruction:

OF’1 = R e f e r e n c e s a data field whose value .is: AB12 B 4D7

*********C0NFIDENTIAL? MOS T E C H N O L O G Y ?INC* * * * * * * * * * P a 2 e - 170

 Finsi Design Specification for the MCS65 E 4 Microprocessor

OF* 2 = R e f e r e n c e s a Q3 ta field w h o S Q v slue is* -i

OF‘3 = R e f e r e n c e s a data field w h o s e v a 11
je is: 2 •*b F 4 5 6 7 ooi p
<_< / J. i

After D E T F: in s t r jj c t ion I

OPI = R e f e r e n c e s a data field w h o s e v a 1 1j e i s { A B 1 2 B 4 D 7

OP 2 = R e f e r e n c e s a data field w h o s e v a I u e is * + 1
OF‘3 = R e f e r e n c e s a data field w h o s e v a l u e i s t 2 2 B F 4 5 6 7 8? IF

In t h i s e x a m p l e the l o w e r b o u n d = D 7 an d the u p p e r b o u n d = B
S i n c e BF is g r e a t e r t h a n or e a u a 1 to D 7 and l es s t h a n or ecu
to B 4 f the d a t a f i e l d r e f e r e n c e d by 0 F’3 wil l c o n t a i n r 1 ♦

#***#*#**CONFIDENTIAL> MOS T EC H NO LO GY ? I N C ♦** *** **** F'age- 171

 Final Des ig n Specification for the M C S 6 5 E4 Microprocessor

*********
* 3HM *
**$%** *$ %

4 , 7 ♦6 , 11 Shift Multiple

Format: SHM GP1?GP2?0P3 >

S HM OPlf0P2

Description:

C A S E 1 : S h i f t the d a t a f i e l d r e f e r e n c e d by DPI by the n u m b e r

of b it p o s i t i o n s s p e c i f i e d by the data field r e f e r e n c e d by
OF’2 s t o r i n g the r e s u l t s i n t o th e d a t a f i e l d r e f e r e n c e d by
0F*3 ( t h r e e o p e r a n d a d d r e s s i n g ) .

C A S E 2 : S h i f t the d a t a f i e l d r e f e r e n c e d by OF'l by the n u m b e r

of b i t p o s i t i o n s s p e c i f i e d by the d a t a f i e l d r e f e r e n c e d by
OF'2 s t o r i n g the r e s u l t s b a c k i nt o the field r e f e r e n c e d by
OF'2 (two o p e r a n d a d d r e s s i n g ) .

Notes:

If the f i e l d r e f e r e n c e d by OF’2 is p o s i t i v e a l e ft s h i f t w : 11
occur, A n e g a t i v e n u m b e r wi l l c a u s e a r i g h t shift*.

Th e l e n t h of the d a t a f i e l d to be s h i f t e d is s p e c i f i e d in
th e d e s c r i p t o r of the field referenced by OF’l or in the
o p e r a rid c o n t r o l byte in the case of by t e* i n t e g e r or
ordinal ,

L o g i c 0 wi l l f ill the bit p o s i t i o n s e re a ted by s h i f t le f t or

shift right u n l e s s the d a t a f i e l d r e f e r e n c e d by OF'l is an
integer. In t h i s case? a right shift o p e r a t i o n will s i g n
e x t e n d (i ,e , the m o s t s i g n i f i c a n t b i t w ill fill the bi t
positions ) ,

For ten byte real? only the mantissa will be shifted.

Example :

♦
♦

SHM 0P1 ?0 P 2 ? 0 F*3

B e f o r e SHM i n s t r u c t i o n :
OF’1 = R e f e r e n c e s a one b y t e f i e l d whose- v a l u e is 1011 000 1
OF*2 = R e f e r e n c e s a d a t a f i e l d w h o s e v a l u e is -2
OF’3 = R e f e r e n c e s a d a t a f i e l d w h o s e v a l u e is 1111 1111

A f t e r SHM i n s t r u c t i o n :
OF11 = R e f e r e n c e s a one byte field whose value is 1011 00 01

*********CQNFIDENTIAL? MGS T E C H N O L O G Y ?I N C ,**** *** ** Page- 172

 Final D es ig n Specification for the M C 3 6 5 E 4 M i c r o p r o c e sso r

w ro = References a data field whose va 1 u e is -2

= References a data field whose v a l u e is 1110 1100

*********CQNFIDENTIAL? MOS T E C H N O L O G Y ? I N C ******** * * Page- 173

 Final D es ig n Specification for the M C S6 5 E4 Microprocessor

^
U y --V
-f--t-t- -r*
4 / ir -J/ - 4 - 1 / -4 .*
-r-
* PTR *
\V 4 / ■ • i ' v U 'V ■ • i ' * 4 -' • j ' 'i - *
. r. . f. /i% .r \ .r . 4 ’.. r-

4*7*6*14 Point to Da t a Field

Format; PTR OPI ?0 F*2

Description*

Returns th e Logical Address of a Data Field*

OPI : •

The PTR instruction will determine the logical address

w i t h i n the process of the field referenced by OPI* This
field c 3n be any d a t 3 t y p e but it can no t be an i m m e d i a t e
v a l u e or an i n t e r n a l r e g i s t e r *

QP2:

Th e 24 bit r e s u l t w ill be p l a c e d in th e field referenced by

0 P 2 w h i c h m u s t be of t y p e o r i d i n a l *

Notes:

The res u l t s of this operation will return th e logical

a d d r e s s of q i t ** >r s t r i n d cr scalar < e ?g » b yt e ? i n t e g e r ?
real? e t c*) type d a t a * If the d a t a f i e l d r e f e r e n c e d by OPI
is n ot s t r i n g or scalar type d a t 3 ( i *e ♦ r e c o r d or a r r a y
typ e ) the p r o c e s s o r w ill s e a r c h t h r o u g h the d a t a s t r u c t u r e
u n t i l it e n c o u n t e r s a b a s i c d a t a e l e m e n t f r o m the s t r u c t u r e *

T h i s i n s t r u c t i o n is v e r y u s e f u l to s p e e d up the o p e r a t i o n in
t he loop i n s t e a d of h a v i n g to c a l c u l a t e the a d d r e s s of the
o p e r a n d e v e r y t i m e * All t h a t is n e e d e d is f i r s t c a l c u l a t e the
a d d r e s s of the d a 1 3 item t h e n u p d a t e the pointer address*

Example4
* P TR T A B L E C I 3 ?B

TABLE = 12345678 <0th element - logical address = 001 C O O

23456789 <8th element - logical adreess = 0 0 1 C 20>

B e f o r e PTR i n s t r u c t i o n :
OF* 1 = R e f e r e n c e s t h e d 3 t 3 f i e l d whose vslue is 23456789 with
1o g i c 3 1 3 d d r ess 001C20*
B = R e f e r e n c e s th e d s t a f i e l d whose value is 00 0 0 0 0

*********CGNFIDENTIAL? MOS T EC H N O L O G Y * INC ** * * * * * * * * P a g e - 174

 Final Eie s i 3 n S p e c i f i c a t i o n for the M C S6 5 E4 Microprocessor

Af t e r PTR i n s t r u c t i o n *
0P1 = R e f e r e n c e s th e d s t s f i e l d whose value is 2 34 5 6 7 8 <i w i t h
logical address 001C20*
B = R e f e r e n c e s th e d a t a f i e l d whose value is 001C20

* * * * * * * * * C O N F I I iE N T I A L j MOS T E C H N O L O G Y >I N C . ** ** ** ** * P a 2 e - 175

 Final D es ig n Specification for the M CS 65 E 4 Microprocessor

' VM''V-4/y
/ f . /’js rff. /|% 4*.
V / f . -V'V*4^
.f.

* D TYPE *
***********

4*7,6*15 Ge t Date type

Format: DTYPE OF’l ?0F‘2

Description:

Determines th e Data Type of a Data Field*

OPI :

The DTYPE i n s t r u c t i o n will d e t e r m i n e the d a t a t y p e of the

f i e l d r e f e r e n c e d by OPI* T h i s f i e l d ca n be any d a t a t y p e bu t
it can not be an i m m e d i a t e v a l u e or an i n t e r n a l r e g i s t e r *

OP2 :

The results wil l be p l a c e d in the f i r s t b y t e of the f i e l d

r e f e r e n c e d by 0P2 a c c o r d i n g to the t a b l e listed below (
R e s u l t T a b l e ) , If the r e s u l t a n t d a t a t y p e is s t r i n g the n e x t
tw o c o n s e c u t i v e b y t e s of the f i e l d r e f e r e n c e d by 0P 2 will
c o n t a i n th e s t r i n g l e n g t h *

Notes :

T h e r e s u l t s of t h i s o p e r a t i o n m u s t r e t u r n e i t h e r s t r i n g d a t a
t y p e or s c a l a r <e*g* by t e * i n t e g e r ? real? etc *) d a t a type*
If the d a t a f i e l d r e f e r e n c e d by OF’1 is n o t s t r i n g or s c a l a r
data type (i*e* re.cord or a r r a y t y pe) the p r o c e s s o r will
search through the data s t r u c t u r e until it e n c o u n t e r s a
b a s i c d a t a e l e m e n t f r o m the s t r u c t u r e *

The d a t a f i e l d r e f e r e n c e d by OF’2 ( r e s u l t f i e l d ) wi l l contain

a value which will reflect the descriptor header field*
T h e s e v a l u e s a re s h o w n b e l o w in the R e s u l t T a b l e :

Field Referenced By Field Referenced By

OPI 0 P2

Byte 04
Ordinal 08
Two B y t e I n t e g e r OC
Four Byte Integer 10
Eight Byte Integer 14
F o u r B y t e R eal 18
E i g h t B y t e Real 1C
Ten B y t e Re a l 20
F o u r B y t e BCD 24
E i g h t B y t e BCD 28
Ten B y t e BC D 2C
String 30

Examp 1e :

* * * * * * * * * C O N F I D E N T I A L ? MGS T E C H N O L O G Y ?INC ** * * * * * * * * Page- 176

 Final De sign Specification for the M C S 65 E4 Microprocessor

Eefore DTYF'E instruction

0 F‘1 = R e f e r e n c e s the 4 t h e l e m e n t of an a r r a y of two bate integer,

0P2 = R e f e r e n c e s the d a t a f i e l d w h o s e v a l u e is 00,

After DTYPE instruction

QF’l = R e f e r e n c e s t he 4th e l e m e n t of 3n a r r a y of tw o byte integer,

QF'2 = R e f e r e n c e s the d a t a f i e l d w h o s e v a l u e is 0C,

*********CONFIDENTIALf MOS T E C H N O L O G Y >I N C . ** ** ** ** * Page- 177

 Final De sig n Specification for the MCS 65E 4 Microprocessor

V /*V^ 'A' -i--if•Jr-'V'V- •

'r * *?• •T ' *<> -T‘ • - r- • r '
t
V
- * t t

* CNVRT *
\ l r \ l t '4 / \ \ f \1/ \ty - it ' i t -.J? '.It
• i ' -f* • '!' 'P- *T* *'»' -T* *T* -r> M-

4*7.6.16 CNVRT

Description^

T r a n s f e r s the contents of th e data field specified by

operand 1 into th e data field specified by operand 2?
c o n v e r t i n g th e f o r m a t of th e d a t a to t h a t of th e s e c o n d d a t a
f i e l d in the p r o c e s s ,

Valid Dat3 Types;

Op Code- _______

*********CONFIDENTIAL, MOS T E C H N O L O G Y >I N C .* ** ** ** ** Page- 173

 Final De sign Specification for the M CS 6 5E 4 Microprocessor

% EVAL *
#**#**#**#

4,7,6.17 EMAL

Th e E V A L i n s t r u c t i o n a l l o w s t he M C S 6 5 E 4 to d i r e c t l y e v a l u a t e an
arithmetic expression. T h i s is a c c o m p l i s h e d by organizing the
e x p r e s s i o n in t o Reverse Polish notation and a t t a c h i n g it to the
EVAL O p Code,

The p r o c e d u r e s for incorporating an expression into an EVAL

i n s t r u c t i o n are as f o l l o w s !

1♦ All of the d a t a accessing procedures operate in the

normal manner e x c e p t t h a t the d a t a f i e l d s m u s t be c o n t a i n e d
in m e m o r y ? i, e , ; d a t a c o n t a i n e d in t h e i n t e r n a l r e g i s t e r s
c a n n o t be r e f e r e n c e d w i t h i n the a r i t h m e t i c e x p r e s s i o n ,

2♦ T h o s e o p e r a rid c o n t r o l byte codes which would normally

r e f e r e n c e the internal registers (see S e c t i o n ____ ) are
r e p l a c e d by the a r i t h m e t i c and l o g i c i n s t r u c t i o n s d e s c r i b e d
above. This specifies the o p e r a t i o n s to be P e r f o r m e d as
follows!

3, The f i n a l operation which must be performed in the

e x p r e s s i o n is a MOVE operation. This m u s t p l a c e the results
int o the d e s i r e d r e s u l t s f i e l d .

Code Operation

50 AD D
51 SUBTRACT
52 MULTIPLY
53 DIVIDE
54 AND
55 OR
56 EOR
57 MOD
58 ABS
59 NEG
5A INC
5B DEC
CEO
CNE
COT
CGE
5D MOV
5E LEADZ
5F LEAD1

The o p e r a t i o n of this instruction is illustrated in the

example below,
Example!

The e x p r e s s i on t

* * * * * * * * * C O N F I D E N T I A L , MOS T E C H N O L O G Y ;I N C ,* * * * * * * * * P a g e - 17?
 Final Desig n Specification for the MCS 65 E 4 Microprocessor

Y = ( ( ( (A + (B + l) * C) / (D - E) AN D (NEG F + (G OF: H>>>

can be converted to Reverse Polish notation as follows:

A B INC + C * D E - / F NEG G H OR + AND MOV

This expression c an be converted to a single EVAL instruction as follow

Field * Contents Comments

1 EVAL O p Code .
2 OF'A Variable A Operand
3 OPB VariableBOperand
4 5A INC O p C o d e
5 OPC Variable C Operand
6 52 MU L O p C o d e
7 OPD Variable D Operand
S OPE Variable E Operand
9 51 SUB O p C o d e
10 53 DIV O p C o d e
11 OPF Variable F Operand
12 59 N EG O p C o d e
13 OF'G Variable G Operand
14 OF'H Variable H Operand
15 55 L o g i c OR O p C o d e
16 50 AD D O p C o d e
17 54 Logic AND O p Code
18 5D MO V O p C o d e
19 OPY Results Data Field (Y)

*********CONFIDENTIAL> MOS T E C H N O L O G Y j I N C . ** ** ** *** Page- ISO