ECE 3010

Microprocessor
Architecture and Memory
Interfacing

ECE 3010 Microprocessor & Interfacing

FCST-MIIT Dr. Nu War
Professor
Faculty of Computer Systems and Technologies
Myanmar Institute of Information Technology
ECE 3010
FCST-MIIT
Contents

Operation of 8085 Microprocessor

Memory Interfacing
ECE 3010
FCST-MIIT Microprocessor Architecture and Its
Operations

Microprocessor-initiated operations

Internal operations

Peripheral (or externally initiated ) operations

ECE 3010
FCST-MIIT
Microprocessor Architecture

The microprocessor is a programmable digital device,

designed with registers, flip-flops, and timing elements.
The microprocessor has a set of instructions, designed
internally, to manipulate data and communicate with
peripherals.
This process of data manipulation and communication is
determined by the logic design of the microprocessor,
called the architecture.
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Microprocessor-Initiated Operation
FCST-MIIT
System Bus
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FCST-MIIT
Major Operations

 MPU performs primarily four operations:

1. Memory Read: Reads data (or instructions) from memory

2. Memory Write: Writes data (or instructions) into memory

3. I/O Read: Accepts data from input devices

4. I/O Write: Sends data to output devices

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FCST-MIIT Communicate with A Peripheral/Memory

The MPU needs to perform the following steps:

1. Identify the peripheral or the memory location (with its

address)

2. Transfer binary information (data and instructions)

3. Provide timing or synchronization signals

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The 8085 Bus Structure/ System Bus

The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the
other units using :
 a 16-bit address bus,
 an 8-bit data bus and
 a control bus.

FCST-MIIT
8
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The 8085 System Bus
Address Bus

 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode:
 The address bits are always sent from the MPU to peripheral devices, not
reverse.
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9
 16 address lines are capable of addressing a total of 216 = 65,536 (64k)
memory locations.
 Address locations: 0000 (hex) – FFFF (hex)
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The 8085 System Bus
Data Bus
 Consists of 8 data lines: D0 – D7

 Operates in bidirectional mode:

 The data bits are sent from the MPU to peripheral devices, as
well as from the peripheral devices to the MPU.
 Data range: 00 (hex) – FF (hex)

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10
Control Bus
 Consists of various lines carrying the control signals such as read /
write enable, flag bits.
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FCST-MIIT
8085 Address Bus

 A15 – A8s Address Bus;

Unidirectional and used for the most significant bits, called the
high-order address of a 16-bit address

 AD0 - AD7 (Input/Output 3state) Multiplexed Address/Data

Bus;
Lower 8 bits of the memory address (or I/0 address) appear
on the bus during the first clock cycle of a machine state.
It then becomes the data bus during the second and third
clock cycles.
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FCST-MIIT
8085 Control and Status Signals
 ALE (Output) Address Latch Enable
 It occurs during the first clock cycle of a machine state and enables the address to get latched
into the on chip latch of peripherals.
 The falling edge of ALE is set to guarantee setup and hold times for the address information.
 ALE can also be used to strobe the status information. ALE is never 3stated.
 S0, S1 (Output)
 Data Bus Status. Encoded status of the bus cycle:
S1 S0
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
 S1 can be used as an advanced R/W status.
ECE 3010
FCST-MIIT Machine Cycle Status and Control Signals

Machine Cycle Status Control Signals

IO/𝑀 S1 S0
Opcode Fetch 0 1 1 𝑅𝐷=0
Memory Read 0 1 0 𝑅𝐷=0
Memory Write 0 0 1 𝑊𝑅=0
I/O Read 1 1 0 𝑅𝐷=0
I/O Write 1 0 1 𝑊𝑅=0
Interrupt Acknowledge 1 1 1 𝐼𝑁𝑇𝐴=0
Halt Z 0 0 𝑅𝐷=Z, 𝑊𝑅=Z and
Hold Z X X 𝐼𝑁𝑇𝐴=1

Reset Z X X
ECE 3010
FCST-MIIT
8085 Control and Status Signals
 (Output 3state)
 READ indicates the selected memory or 1/0 device is to be read and that the
Data Bus is available for the data transfer.

 (Output 3state)
 WRITE indicates the data on the Data Bus is to be written into the selected
memory or 1/0 location.
 Data is set up at the trailing edge of WR. 3 stated during Hold and Halt modes.

 IO/ (Output)
 IO/𝑀 indicates whether the Read/Write is to memory or l/O Tristated during
Hold and Halt modes.
ECE 3010
Example: Memory Read Operation

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15
ECE 3010

Internal Data Operations and

FCST-MIIT the 8085 Registers

The internal architecture of the 8085 microprocessor determines how and

what operations can be performed with the data.
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The 8085: CPU Internal Structure
The internal architecture of the 8085 CPU is capable of performing
the following operations:

 Store 8-bit data (Registers, Accumulator)

 Perform arithmetic and logic operations (ALU)

 Test for conditions (IF / THEN)

FCST-MIIT
17  Sequence the execution of instructions
 Store temporary data in RAM during execution
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The 8085: CPU Internal Structure

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18

Simplified block diagram

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FCST-MIIT
Internal Operations

Address Mnemonic Memory

Code
2000 MVI B, 76H 06

2001 78
2002 MVI A,F2H 3E

2003 F2
2004 ADD B 80
2005 HLT 76
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FCST-MIIT Internal Data Operation
1. The PC is a 16-bit register that perform the fourth operation in the list sequencing the execution of the instructions.
• Places the address 2000H on the address bus, and increments the address in the PC to 2001 for the next operation
• Brings the code 06H, interprets the code, places the address 2001H on the address bus and then gets byte 78H and
increments the address in PC to 2002H.

2. When the processor executes the first two instructions, it uses register B to store 78H and A to store F2 H in binary
(Operation 1)

3. When the processor executes the instruction ADD B in the ALU(Operation 2), it adds 78 H to F2H, resulting in the
sum 16AH. It replace F2H by 6AH in A and sets the Carry flag as described next.

4. The addition operation generates a carry because the sum is larger than the size of the accumulator (8 bits). To
indicate the carry, the processor sets the flip-flop called CY flag to 1

5. The fifth operation deals with the concept of the stack.

ECE 3010

Peripheral or Externally Initiated

Operations
Reset
FCST-MIIT
Interrupt
Ready
Hold
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FCST-MIIT Peripheral or Externally Initiated Operations
 Reset:
 When the reset pin is activated by an external key (also called a reset
key), all internal operations are suspended and the program counter is
cleared (if holds 0000H).
 Now the program execution can again begin at the zero memory
address.

 Interrupt:
 The microprocessor can be interrupted form the normal execution of
instructions and asked to execute some other instructions called a
service routine (for example, emergency procedure).
 The microprocessor resumes its operation after completing the service
routine.
ECE 3010
FCST-MIIT Peripheral or Externally Initiated Operations
 Ready:
 The 8085 has a pin called READY.
 If the signal at this READY pin is low, the microprocessor enters into a
Wait state.
 This signal is used primarily to synchronize slower peripherals with the
microprocessor.

 Hold:
 When the HOLD pin is activated by an external signal, the microprocessor
relinquishes control of buses and allows the external peripheral to use
them.
 For example, the HOLD signal is used in Direct Memory Access (DMA)
data transfer.
ECE 3010
Example: Instruction Fetch Operation

 All instructions (program steps) are stored in memory.

 To run a program, the individual instructions must be read from the
memory in sequence, and executed.

 Program counter puts the 16-bit memory address of the instruction on the address
bus
 Control unit sends the Memory Read Enable signal to access the memory
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 The 8-bit instruction stored in memory is placed on the data bus and transferred to
the instruction decoder
 Instruction is decoded and executed
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Memory Chip
FCST-MIIT
Flip-Flop or Latch as a Storage Element
Memory Map and Address
Memory Address Range of a chip
Memory Address Lines
Memory Word Size
Memory Classification
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FCST-MIIT
Memory

To communicate with memory, the MPU should be able to

Select the chip

Identify the register

Read from or write into the register

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FCST-MIIT Flip-Flop or Latch
A circuit that can store bits- high or low, generally voltage
levels or capacitive charges representing 1 and 0.
Basic element of memory
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FCST-MIIT
Four Latches as a 4-bit Register
 The size of this register is specified either as 4-bit or 1x4-bit

I3 I2 I1 I0
𝑊𝑅
𝑊𝑅 Input Buffer EN 4-bit Register
𝑅𝐷

Register
EN

Output
𝑅𝐷 Buffer

O3 O2 O1 O0
ECE 3010
4-to-8 Bit Register
FCST-MIIT
 No. of register=2n , n= no. of line

I7 I6 I5 I4 I3 I2 I1 I0

𝑊𝑅 Input Buffer Input Buffer

A0
4x4 4x4
A1

Output Output
𝑅𝐷 Buffer Buffer

O7 O6 O5 O4 O3 O2 O 1 O0
ECE 3010
FCST-MIIT
Two Memory Chips with Four Registers Each
and Chip Select
A2

A0 A0
𝑫𝒆𝒄𝒐𝒅𝒆𝒓 𝑪𝑺 𝑹𝑫 𝑾𝑹 𝑫𝒆𝒄𝒐𝒅𝒆𝒓 𝑪𝑺 𝑹𝑫 𝑾𝑹
A1 M1 A1 M1
1 11 R3 0 11 R3
1 10 R2 0 10 R2
1 01 R1 0 01 R1
1 00 R0 0 00 R0
ECE 3010
FCST-MIIT
Memory Map and Addresses

 The microprocessor with its 16 address line is capable of identifying or addressing 65,536
(64K) such memory register or locations and the microprocessor with its 20 address line is
capable of addressing 1,048,576 (1Mbyte) memory location.

 The size of this chip can be specified either as 8 byte, 8x8 bit or 64 bit.

 A memory chip with 256 register (or location) with 4 I/O lines is specified as 256x4 bit or 1024
bit, for an 8-bit mp, two such memory chips (256 x 4) would be necessary to form the 8 bit
memory word size, resulting 256 bytes of memory.

 The chip select 𝐶 ̅̅ line, also known as chip enable (𝐶 ̅),

̅ is necessary to select one particular
memory chip from among several memory chips in a system.
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FCST-MIIT
Memory Map

The assignment of addresses to memory register in

various memory chips in system.

The assignment of memory addresses is done through the

chip select logic.
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FCST-MIIT
Change Memory Map

Illustration the memory map of the chip with 256 Showing how the memory map can be changed by
bytes of memory modifying the hardware of the chip select (C̅S̅) line
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FCST-MIIT
Change Memory Map
 It has eight address lines, one chip select (C̅S̅) line (active low) and read/write
( ÚW̅ ) line.
 The 8 address lines (A7-A0) of the microprocessors are required to identify
256 (28 ) memory registers.
 Eight other addresses lines (A15-A8) are connected to the chip select (C̅S̅)
line through inverters and NAND gate.

 The entire range of the memory addresses from 0000 to 00FF is known as the
memory map of the chip
 The memory map of the chip (fig: changed) range from 8000H to 80FF H.
ECE 3010
FCST-MIIT Memory Classification

 RAM is volatile, meaning that when the

power is turn off, all the contents are
destroyed.

 ROM is nonvolatile, meaning that it

retains the stored information even if
the power is turn off.
ECE 3010
FCST-MIIT
Memory Address Lines
 The relationship between the number of registers in memory chip and the
number of address line for a chip

combinations
 x: Address lines

Calculate the address lines required for an 8K-byte (1024 x 8=8192 registers)
memory chip.
 Number of address line x= log 8192/log 2=13 address lines
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FCST-MIIT
Memory Word Size
 Various word sizes (1, 4, and 8)
 The size of memory chip is generally specified in terms of the total
number of bits it can store.

Calculate the number of memory chips needed to design 8K-byte

memory if the memory chip size is 1024 x 1.
 8192 x 8 1024 x 1 = 64
ECE 3010
FCST-MIIT Example
Suppose the ROM memory has 15 address lines and eight data
line. How many bytes of information can be stored in the ROM?
What is its total storage capacity?

With 8 data lines, the number of bytes is equal to the number of

locations, which is 215 = 32,768 bytes
This gives a total storage of 32,768 * 8 = 262,144 bits
ECE 3010
FCST-MIIT
Memory Expansion
 In many applications, the microcomputer system requirement for memory is
greater than what is available in a single device.

 There are two basic reasons for expanding memory capacity:

 The byte-wide length is not large enough

 The total storage capacity is not enough bytes

 Both of these expansion needs can be satisfied by interconnecting a number of

ICs.
ECE 3010
FCST-MIIT
Practice
Show how to implement 32K× 16 EPROM using two 32K×8
EPROM
ECE 3010
FCST-MIIT
Practice
Show how to implement 64K× 16 EPROM using two 32K×8
EPROM
ECE 3010
Practice
FCST-MIIT

 Design an interfacing memory circuit with a microprocessor have 16 addresses

lines to meet the following specifications:
 74LS138: 3-to-8 decoder
 2732 (4K X 8): EPROM—address range should begin at 0000H and additional 4K
memory space should be available for future expansion.
 6116 (2K X 8): CMOS R/W memory
ECE 3010
Practice
FCST-MIIT

 Design an interfacing memory circuit with a microprocessor have 16 addresses

lines to meet the following specifications:
 74LS138: 3-to-8 decoder
 2732 (4K X 8): EPROM—address range should begin at 0000H and additional 4K
memory space should be available for future expansion.
 6116 (2K X 8): CMOS R/W memory
ECE 3010
FCST-MIIT
System Memory and Memory Map
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FCST-MIIT Absolute vs Partial Address Decoding
 Partial Decoding
The decoding in which all available address line (16 lines in
memory mapping and 8 lines in peripheral mapping) are not used
for decoding resulting in multiple address for same port is called
partial decoding.

 Absolute Decoding
The decoding in which all available address line (16 lines in
memory mapped and 8 lines in peripheral mapping) are used for
decoding to generate a unquie address is called absolute
decoding.
ECE 3010
FCST-MIIT
Absolute vs Partial Address
Absolute Decoding Partial Decoding

Pros • Complete address utilization • Simple

• Ease in future expansion • Cheap
• No bus contention, as all • Fast
addresses are unique.

Cons • Increased hardware and cost • Unutilized space & fold back (multiple
• Speed is less due to increased mapping)
delay • Bus contention
• Different future expansion
ECE 3010
FCST-MIIT
Address Decoding
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FCST-MIIT Address Decoding
ECE 3010
FCST-MIIT
ECE 3010
FCST-MIIT
ECE 3010

Microprocessor Communication
FCST-MIIT
and Bus Timing

Instruction Cycle
Machine Cycle
T states
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FCST-MIIT
Instruction Fetch
The primary function of memory is to store instructions and
data and to provide that information to the MPU whenever the
MPU requests it.

Example:
The instruction code 0100 1111 (4FH) is stored in memory
location 2005H. Illustrate the data flow and list the sequence of
events when the instruction code is fetched by the MPU
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Example: Instruction Fetch Operation

FCST-MIIT
53
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FCST-MIIT
Instruction Fetch Operation
1. The program counter places the 16 bit address 2005H on the address bus

2. The control unit sends the Memory Read control signal (active low) to
enable the output buffer of the memory chip.

3. The instruction (4F) stored in the memory location is placed on the data
bus and transferred to the instruction decoder of the microprocessor.

4. The instruction is decoded and executed according to the binary pattern

of the instruction
ECE 3010
Example: Instruction Fetch Operation

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55
ECE 3010
FCST-MIIT
Communication and Bus Timing

 Shipping Company

1. A courier gets the address from the office; he or she drives the pickup van, finds the street, and

looks for your house number.

2. The courier rings the bell

3. Somebody in the house opens the door and gives the package to the courier, and the courier returns

to the office with the package.

4. The internal office staff disposes the package according to the instructions given by the customer.
ECE 3010
FCST-MIIT Communication and Bus Timing

Illustrate the steps and the timing of data flow when the
instruction code (0111 1000) (78H _MOV A, B) stored in location
A000 H, is being fetched.
Memory Instruction
A000h MOV A, B
ECE 3010
FCST-MIIT Timing Diagram
 Representation of Various Control signals generated during
Execution of an Instruction.

 Following Buses and Control Signals must be shown in a Timing

Diagram:
 Higher Order Address Bus.
 Lower Address/Data bus
 ALE
 RD
 WR
 IO/M
ECE 3010
FCST-MIIT Opcode Fetch Machine Cycle

 The MP places the 16-bit memory address from

the program counter on the address bus.

 The control unit sends the control signal 𝑅𝐷 to

enable the memory chip.

 The byte from the memory location is placed on

the data bus.

 The byte is placed in the instruction decoder of

the MPU, and the task is carried out according to
the instruction
ECE 3010
FCST-MIIT
Memory Read Machine Cycle

Instruction:
MVI A, 45H is stored in the
memory content of address:
A000H

Address Content
A000H 3E
A001H 45
ECE 3010
FCST-MIIT
Memory Read Machine Cycle

 Instruction: LXI A,F045h

is stored in the memory
content of address:
A000H.

Address Content
A000H 21
A001H 45
A002H F0
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FCST-MIIT
Memory Read Machine Cycle

Instruction: MOV A,M

is stored in the
memory content of
address: A000H.

Address Content
A000H 7E
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FCST-MIIT
Memory Write Machine Cycle

Instruction: MOV M,A

is stored in the
memory content of
address: A000H.

Address Content
A000H 77
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FCST-MIIT
Demultiplexing the Bus
ECE 3010
FCST-MIIT Instruction Cycle, Machine Cycle & T-State
 Time required to execute and fetch an entire instruction is called instruction cycle. It
consists:
 Fetch cycle – The next instruction is fetched by the address stored in program counter (PC)
and then stored in the instruction register.
 Decode instruction – Decoder interprets the encoded instruction from instruction register.
 Reading effective address – The address given in instruction is read from main memory
and required data is fetched. The effective address depends on direct addressing mode or
indirect addressing mode.
 Execution cycle – consists memory read (MR), memory write (MW), input output read
(IOR) and input output write (IOW)
 The time required by the microprocessor to complete an operation of accessing
memory or input/output devices is called machine cycle.
 One time period of frequency of microprocessor is called t-state. A t-state is measured
from the falling edge of one clock pulse to the falling edge of the next clock pulse.

Instruction cycle in 8085 microprocessor - GeeksforGeeks

ECE 3010
FCST-MIIT
Instruction Cycle
Fetch cycle takes four t-states and execution cycle takes
three t-states.

Instruction cycle in 8085 microprocessor - GeeksforGeeks

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FCST-MIIT
Input and Output (I/O) Devices

I/Os with 8-Bit Address

I/Os with 16-Bit Address
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FCST-MIIT
Input/Output Devices

The MPU communicates with “the outside world”

The MPU accept binary data as input from devices such as

keyboards and A/D converters

The MPU sends data to output devices such as LEDs or

printers.
ECE 3010
FCST-MIIT
Peripheral-Mapped I/O
 Peripheral-mapped I/O: The MPU uses eight address lines to identify an input or an output device

 The eight address lines can have 256 address (28 combinations)

 MPU can identify 256 input devices and 256 output devices with address range (00H~FFH)

 The input and output devices are differentiated by the control signals:

 MPU uses the I/O Read Control Signal for input devices

 MPU uses the I/O Write Control Signal for output devices

 In bus architecture, the devices (such as LED/Swithes )cannot be directly connected to the data bus or the
address bus

 All connections must be made through tri-state interfacing devices so they will be enabled and connected to the
buses only when the MPU choose to communicate with them
ECE 3010
FCST-MIIT
Memory-Mapped I/O

The MPU uses 16 address lines to identify an I/O device;

an I/O is connected as if it is memory register.

The MPU uses the same control signal and instructions

as those of memory.
ECE 3010
FCST-MIIT
Example of a Microcomputer System
ECE 3010
8085 Functional Block Diagram

72
FCST-MIIT
ECE 3010
FCST-MIIT 8085 Pin Description
 Single + 5V Supply
 4 Vectored Interrupts (One is Non Maskable)
 Serial In/Serial Out Port
 Decimal, Binary, and Double Precision Arithmetic
 Direct Addressing Capability to 64K bytes of memory
 The Intel 8085A is a new generation, complete 8 bit parallel
central processing unit (CPU).
 The 8085A uses a multiplexed data bus. The address is split
between the 8bit address bus and the 8bit data bus.
ECE 3010
FCST-MIIT
8085 Pins

 A6 - A1s (Output 3 State) Address Bus;

 The most significant 8 bits of the memory address or the 8 bits
of the I/0 address,3 stated during Hold and Halt modes.
 AD0 - 7 (Input/Output 3state) Multiplexed Address/Data Bus;
 Lower 8 bits of the memory address (or I/0 address) appear on
the bus during the first clock cycle of a machine state.
 It then becomes the data bus during the second and third clock
cycles. 3 stated during Hold and Halt modes.
ECE 3010
FCST-MIIT
8085 Pins
 ALE (Output) Address Latch Enable
 It occurs during the first clock cycle of a machine state and enables the address to get latched
into the on chip latch of peripherals.
 The falling edge of ALE is set to guarantee setup and hold times for the address information.
 ALE can also be used to strobe the status information. ALE is never 3stated.
 SO, S1 (Output)
 Data Bus Status. Encoded status of the bus cycle:
S1 S0
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
 S1 can be used as an advanced R/W status.
ECE 3010
FCST-MIIT
8085 Pins

 RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to
be read and that the Data Bus is available for the data
transfer.
 WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written
into the selected memory or 1/0 location.
Data is set up at the trailing edge of WR. 3stated during
Hold and Halt modes.
ECE 3010
FCST-MIIT
8085 Pins

 READY (Input)
 If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to
send or receive data.
 If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.
 HOLD (Input)
 HOLD; indicates that another Master is requesting the use of the Address and Data Buses.
 The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion
of the current machine cycle.
 Internal processing can continue.
 The processor can regain the buses only after the Hold is removed.
 When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
ECE 3010
FCST-MIIT
8085 Pins
 HLDA (Output)
 HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request
and that it will relinquish the buses in the next clock cycle.
 HLDA goes low after the Hold request is removed. The CPU takes the buses one
half clock cycle after HLDA goes low.
 INTR (Input)
 INTERRUPT REQUEST; is used as a general purpose interrupt.
 It is sampled only during the next to the last clock cycle of the instruction.
 If it is active, the Program Counter (PC) will be inhibited from incrementing and an
INTA will be issued.
 During this cycle a RESTART or CALL instruction can be inserted to jump to the
interrupt service routine.
 The INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted.
ECE 3010
FCST-MIIT
8085 Pins
 INTA (Output)
 INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during
the Instruction cycle after an INTR is accepted. It can be used to activate the 8259
 Interrupt chip or some other interrupt port.
 RST 5.5
 RST 6.5 - (Inputs)
 RST 7.5
 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they
cause an internal RESTART to be automatically inserted.
 RST 7.5 ~~ Highest Priority
 RST 6.5
 RST 5.5 o Lowest Priority
 The priority of these interrupts is ordered as shown above. These interrupts have a higher
priority than the INTR.
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 TRAP (Input)
 Trap interrupt is a nonmaskable restart interrupt.
 It is recognized at the same time as INTR. It is unaffected by any mask
or Interrupt Enable.
 It has the highest priority of any interrupt.
 RESET IN (Input)
 Reset sets the Program Counter to zero and resets the Interrupt
Enable and HLDA flipflops.
 None of the other flags or registers (except the instruction register) are
affected
 The CPU is held in the reset condition as long as Reset is applied.
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 RESET OUT (Output)

 Indicates CPlJ is being reset. Can be used as a system RESET. The
signal is synchronized to the processor clock.
 X1, X2 (Input)
 Crystal or R/C network connections to set the internal clock generator
X1 can also be an external clock input instead of a crystal. The input
frequency is divided by 2 to give the internal operating frequency.
 CLK (Output)
 Clock Output for use as a system clock when a crystal or R/ C network
is used as an input to the CPU. The period of CLK is twice the X1, X2
input period.
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 IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O
Tristated during Hold and Halt modes.
 SID (Input)
Serial input data line The data on this line is loaded into
accumulator bit 7 whenever a RIM instruction is executed.
 SOD (output)
Serial output data line. The output SOD is set or reset as
specified by the SIM instruction. Vcc +5 volt supply. Vss
Ground Reference