Combinational Circuits

Digital Electronics (Combinational Circuits)
1. The inputs to a 3-bit digital comparator are P=p2p1p0 and q = q2q1q3 and x2 : p2 ʘ q2,
x1=p1 ʘ q1, x0=p0 ʘ q0. The condition For P = Q is
(a) x 2 x1+ x1 x 0 + x 2 x 0 =1 (b) x2 .x1 .x0 =1
(c) x2+ x1+ x 0 =1 (d) x 2 x1+ x1 x 0 + x 2 x 0 =1
2. Find the output of the following circuit
(a) 1
(b) C
(c) C
(d) 0
3. Determine the size of ROM required to implement a 4 - bit Binary Adder with carry in and
carry out facilities.
(a) 1024  4 (b) 512  5
(c) 1024  5 (d) 256  4
4. What are the minimum number of transistors required to store 1 - bit in SRAM and DRAM
respectively.
(a) 2,1 (b) 6,4
(c) 1, 2 (d) 6,1
5. Consider the MUX shown below. The output of the 8:1 MUX is
(a) m(3, 4, 5, 9, 12, 13)

(b) m(3, 4, 5, 11, 12, 13)
(c) m(3, 4, 5, 9, 11, 12, 13)
(d) m(3, 4, 5, 7, 9, 11, 12, 13)
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6. A combinational circuit has 3 inputs and one output. The output is 1 when the decimal
value of the binary input is an even natural number. The expression for output is
(a) BC  ABC  AC (b) BC  ABC
(c) AC  BC (d) BC  ABC  AC
7. 3  8 decoder with two enable inputs is to be used to address 8 blocks of memory What
will be the size of each memory block when addressed form a sixteen bit bus with two MSB’s
used to enable the decoder?
(a) 2 K (b) 4 K
(c) 16 K (d) 64 K
8. The storage element for a static RAM is

(a) Diode (b) BJT
(c) MOSFET (d) Flip-Flop
9. A 4  1 MUX is used to implement a 3-input Boolean function as shown in ﬁgure. The

Boolean function F (A, B, C) implemented is
(a) F(A, B, C) =  (1, 2, 4, 6)
(b) F(A, B, C) = (1, 2, 6)
(c) F(A, B, C) = (2, 4, 5, 6)
(d) F(A, B, C) = (1, 5, 6)
10. How many 1-bit comparators, 2-input AND gates, 2-1nput OR gates required to design a
2-bit comparator.
(a) 2, 3, 2 (b) 2, 2, 3
(c) 2, 3, 3 (d) 2, 2, 2

11. What is the name of given circuit?
(a) Full Subtractor
(b) Full Adder
(c) 3-bit even parity generator
(d) 3-bit odd parity generator
12. In a 2-bit magnitude comparator circuit (A  A1 A 0 , B  B1B0 ) , the expression for A > B &
A < B is
A > B = A1 B1 + (A1  B1 ) A0 B0 A > B = A1 B1 + (A1  B1 ) A 0 B 0

(a) (b)
A < B = A1 B1 + (A1  B1 ) A0 B0 A < B = A1 B1 + (A1  B1 ) A 0 B 0
A > B = A1 B1 + (A1 B1 ) A 0 B0 A > B = A1 B1 + (A1 B1 ) A 0 B0

(c) (d)
A < B = A1 B1 + (A1 B1 ) A 0 B0 A < B = A1 B1 + (A1 B1 ) A 0 B0
13. In a N- bit digital comparator, the number of input combinations for which A > B is
N(N  1)
(a) (b) N(N  1)
2
N(N - 1)
(c) (d) 2N  1
2
14. An 8  1 multiplexer has inputs A, B and C connected to the selection input S2, S1, and S0,
respectively. The data inputs I0 through I7 are as follows:
I1 = I2 = I7 = 0; I3 = I5 = 1; I0 = I 4 = D; and I6 = D ;
The Boolean function that the multiplexer implements is
(a) Y = m(1, 6, 7, 9, 10, 11, 13) (b) Y = m(1, 6, 7, 9, 10, 11, 12)
(c) Y = m(4, 5, 7, 8, 9, 11, 15) (d) Y = m(0, 1, 3, 4, 5, 7, 9, 11)

15. In the following MUX, find the output f.
(a) C2 .C1S  C2C1 (A  B)
(b) C2 C1  C2C1  C2 C1S  C2C1 AB
(c) AB  S
(d) C2 C1  C2 C1S  C2C1 (AB)
16. The output of the 4  1 MUX shown below is
(a) x  y
(b) x+xy
(c) x+y
(d) xy
17. DRAMs have advantages over SRAMs in that
i. They have lower cost

ii. They required lower number of transistors
iii. They don't need to be refreshed frequently where SRAMs need this feature
iv. High packing density guarantees higher storage capacity in a single chip
(a) i, ii & iii (b) Only i

(c) i, ii & iv (d) ) i, ii, iii & iv

18. Implement the Boolean function using 4 x 1 MUX. F(A,B,C)=  (1,3,5, 6) choose B,C as
selection lines.
(a) I0  0,I1  1,I2  A & I3  A (b) I0  1,I1  0,I2  A & I3  A

(c) I0  0,I1  1,I2  A & I3  A (d) I0  0,I1  A,I2  A & I3  1
19. Implement the following Boolean function using 4X1 MUX F(A,B,C)=  m(1,3, 4, 6) With A
and B are selection lines.
(a) I0  C,I1  C,I2  I3  C (b) I0  C,I1  C,I2  C,I3  C

(c) I0  C,I1  C,I2  C,I3  C (d) I0  C,I1  C,I2  C,I3  0
20. Static RAM is preferred over dynamic RAM, where the requirement is at
(a) Slow speed of operation (b) Larger storage capacity

(c) Lower access time (d) None of these
21.
A(x,y,z) =  (l,2,4,6)
B(x,y,z) =  (0,1,6,7)
C(x,y,z) =  (2, 6)
D(x,y,z) =  (0,1,2,3,5,7)
The Boolean function is implemented using ROM. The memory contents at address 4 of the
ROM is
(a) 1000 (b) 0001

(c) 0111 (d) 1110
22. Minimum 4 line to 16 line decoders required to realize 8 line to 256 line decoder are
(a) 8 (b) 9
(c) 17 (d) 16

23. The minimum number of 2 × 1 multiplexers required to implement a half adder circuit
are [when only basic inputs are available, compliments are not available].
(a) 4 (b) 2
(c) 3 (d) 5
24. Two Half Adders are connected in cascade as shown in figure below. The output “S” and
“C” are
(a) S  A  B,C  AB
(b) S  AB,C  0
(c) S  A  B,C  0
(d) S  AB,C  0
25. Consider the logic circuit given below. The min terms in f(A,B,C,D) are _____.
(a) Σm(1, 3, 5, 6, 7, 11, 14)
(b) Σm(3,6, 7, 8, 11, 12, 14, 15)
(c) Σm(3, 6, 7, 8, 11, 12, 14, 15)
(d) Σm(3, 6, 7, 9, 11, 12, 14, 15)

26. Consider the logical circuit given below
Input at line I13 in 16 × 1 Mux corresponds to output at line In ′ of 1 × 16 De-Mux. The value
of ‘n’ is ______.
27. Which of the following statements is not true?
(a) ROM is a programmable logic device.

(b) Programmable logic devices are capable of implementing logic functions.
(c) Selective erasing is possible in EEPROM.
(d) All statements d. are correct

28. Consider the circuit given below
Which of the following statements is true for Y.
(a) Y  CD  DC(A  B)  CDS

(b) Y  CD  DC(A  B)  CDS
(c) Y  CD  (D  C)(A  B)  C D  S
(d) Y  CD  (D  C)(A  B)  C D  S
29. Consider a 3-bit number A and 2 bit number B are given to a multiplier. The output of
multiplier is realized using AND gate and one bit full adders. If minimum number of AND
gates required are X and one bit full adders required are Y, then X + Y = _____.
30. Consider the logic circuit given below
The minimized expression for F is
(a) C (b) I 0
(c) C (d) I0

31. Consider the circuit given below
The output of each converter is given to adder which adds them considering decimal
number. The output of adder is S. The value of S is______.
32. In the following circuit the function f( x2 , x1 , x0 ) is
(a)  M(0, 2, 4,5)

(b)  m(0,2, 4,5,7)
(c)  m(1,3, 6)
(d)  M(1,3, 6)
33. The network shown below implements
(a) NOR gate
(b) NAND gate
(c) XOR gate
(d) XNOR gate

34. The logic circuit of figure is a
(a) Half adder

(b) XOR
(c) Equality detector
(d) Full adder
35. A 2-to- 1 digital multiplexer having a switching delay of 1 μs is connected as shown in

figure. The output of the multiplexer is tied to its own select input S. The input which gets
selected when S = 0 is tied to 1 and the input that gets selected when S = 1 is tied to 0.The
output V0 will be
(a) 1
(b) 1
(c) pulse train of frequency 0.5 MHz
(d) pulse train of frequency 1.0 MHz
36. A combinational logic circuit has three inputs A. B and C and one output Y. The output Y
= 1 when at least two inputs are 1. Otherwise, Y = 0. In its minimized SOP realization, the
maximum number of two input terms is _______.
37. A 4x 1 multiplexer is used to implement 3 input Boolean function as shown In the below
figure. The F(A. B, C) is
(a)  m(0, 4,5, 6)
(b)  m(3, 4,5, 6)

(c) M(0, 4,5,6)
(d) M(3, 4,5,6)

38. A gate having two inputs (A, B) and one output (Y) is implemented using 4 :1 MUX as
1
shown in figure be1ow. A 1 (MSB) and A 0 are the control bits and I 0 to I 3 are the inputs to
the MUX. The gate is
(a) AND
(b) NOR
(c) OR
(d) EX-OR
39. A 1-bit full adder circuit takes 5ns to generate the carry-out bit and 10ns for the sum-bit,
when 3, 1- bit full adders are cascaded then the maximum rate of addition/second will be
_________ 107 .
40. Consider the digital circuit shown below. A single digit decimal number(B) is converted
into its 4 bit binary equivalent( B3B2B1B0 ) and then applied to the addend bits of the adder as
shown below:

If C4 =1 and S3S2S1S0 are given to the addend bits of the 4-bit binary parallel adder as shown
below. Then output of the circuit is
(a) 9’s complement of B (b) 10’s complement of B

(c) 11’s complement of B (d) 12’s complement of B

Solutions
1. Ans: (b)
Solution: P=Q only when all respective bits are equal i.e., p2 = q2, p1 = q1 and p0 = q0
i.e. x 2 x1 x 0 = 1
2. Ans: (c)
Solution: output of AND gate F1 =0
Output of OR gate, F=F1 C+F1 C =>F=C
3. Ans: (b)
Solution: Binary adder has 9 inputs and 5 outputs. So, the ROM size  29  5  512  5
4. Ans: (d)
5. Ans: (c)
Solution: Y = ABC(0) + ABC(D) + ABC(1) + ABC(0) + ABC(D) + ABC(D) + ABC(1) + ABC(0)
Y = ABCD + ABC(D +D) + ABCD + ABCD + ABC(D+D)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
Y = m(3, 4, 5, 9, 11, 12, 13)
6. Ans: (c)
Solution: Natural numbers are: 1,2,3 ---
Even natural numbers are: 2,4,6 ---
As number of inputs = 3
Input should be between 0 to 7.
 output is one for inputs 2,4,6 only.
Truth table

A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
K map is
Y  BC  AC
7. Ans: (a)
Solution: 16  (2  3)  11
Here 16 are given address bus bits.
2 for chip select.
And 3 for input to decoder
 211=2k is the size of the memory.
8. Ans: (d)
9. Ans: (a)
Solution: F(A, B, C) =AB C+ABC+BC+0 BC 
K-map for the above expression can be drawn as
F(A, B, C) = (1, 2, 4, 6)
10. Ans: (a)

Solution: Let A= A1 A0 , B = B1 B0 be the 2-bit numbers to be compared. A1 & B1 and A0 & B0
are compared separately using two 1-bit comparator modules. Then A > B if A1 > B1 (or) A1 =
B1 and A0 > B0

G = G1+ E1 G0
A = B if A1 = B1 and A 0 = B0
E = E1 E0
A < B if A1 < B1 (or) A1 = B1 and A 0 < B0
L = L1 + E1 L 0
11. Ans: (b)

Solution: For a full adder
A B C Sum (F1) Carry (F2)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
F1=m(1, 2, 4, 7)
F1=m(3, 5, 6, 7)
12. Ans: (b)

Solution: Let two 2-bit numbers A  A1 A 0 , B  B1B0
1. If A1 = 1 and B1 = 0, then A > B (or)
2. If A1 & B1 coincide and A0 =1 and B0 = 0, then A >B.
So the logic expression for A > B is A > B = A1 B1 + (A1B1 ) A0B0
1. If A1 = 0 and B1 = 1 then A < B (or)
2. If A1 and B1 coincide and A0=0 and B0=1, then A < B
So the logic expression for A < B is A < B = A1 B1+(A1B1 )A0 B0

13. Ans: (a)

Solution: For N=1
Only one combination is possible for A>B
Hence option (a) is correct
14. Ans: (b)

Solution: Y = ABCD + ABC + ABCD + ABC + ABCD
  
Y  ABCD + ABC D  D + ABCD + ABC D  D + ABCD 
Y  ABCD + ABCD  ABCD + ABCD + ABCD+ABCD + ABCD
Y = m(1, 6, 7, 9, 10, 11, 12)
15. Ans: (d)

Solution:
f  C2 C1I0  C2C1I1  C2 C1I2  C2C1I3  C2 C1  C2 C1S  C2C1 AB
16. Ans: (c)

Solution: Z  S1 S0I0  S1S0I1  S1 S0I2  S1S0I3  x  xy  x  y
17. Ans: (c)
18. Ans: (c)

Solution: F  A BC  ABC  ABC  ABC =A BC  B C  ABC
For 4 x 1 MUX , output F  B C I0  B CI1  B C I2  BCI3
Compare with given Boolean function we get
I0  0, I1  1, I2  A, I3  A

19. Ans: (a)

Solution: F  A BC  ABC  ABC  ABC
For 4 x 1 MUX, output F  A B I0  A B I1  AB I2  ABI3
Compare with given Boolean function we get,
I0  C, I1  C, I2  C, I3  C
20. Ans: (c)
21. Ans: (a)
22. Ans: (c)

256
Solution: Number of 4  16 decoders required=  16
16
16
 1
16
16+1 =17 Decoders are required
23. Ans: (c)

Solution: 3 2 x 1 MUX’s are required
24. Ans: (c)

Solution: S1  A  B , C1  AB
S  (A  B)  AB  (A  B).AB  (A  B).AB  (AB  AB)(A  B)  (AB  AB)(A,B)  AB  AB  AB  A  B
C  (A  B).AB  (AB  AB).AB  0

25. Ans: (c)

Solution: Y  AC  BC
f  YD  CD
   
f  (AC  BC)D  CD  AC B  B D  A  A BCD  A  A B  B CD   
f  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
Σm(3, 6, 7, 8, 11, 12, 14, 15)
26. Ans: 2
Solution: I13  A B C D
1 1 0 1
A  A B 1 1  0

B  BD  1.1  0
C  D  D  1
D  AC  0.1  0
In  ABCD
(ABCD)  (0010)  2
n2
27. Ans: (d)
28. Ans: (d)

Solution: Y  DC  DCAB  DCS  DC  (D C)(A B)  C D  S
29. Ans: 9
Solution: Let
A= a2 a1 a0
B= b1 b0
A B = a2b0 a1b0 a0b0
b1 a2 b1 a1 b1 a0
b1 a2 ( a2b0 + b1 a1 ) ( a1b0 + b1 a0 ) a0b0

C3 C2 C1 C0
Number of AND gates required=X=6

Number of one bit full adders required Y=3
X+Y=6+3=9

30. Ans: (a)

Solution: X  D0 D1 I0  (D0  D1 )I0  (AB  AB)I0  A I0
Y  D2 D3 I0  (D2  D3 )I0  (AB  AB)I0  AI0

Z  (X.Y)  X Y  A I0  AI0  I0
F  (CZ  CZ)  C(I0  I0 )  C
31. Ans: 1085

Solution: A  (EC)16  (1032)6
B  (20)10  (32)6
C  (15)8  (21)6
S  A  B  C  (1085)10
32. Ans: (b)

Solution: f   m(1,3,6)
=  m(0,2, 4,5, 7) .............min terms
=  M(1,3,6) ........max terms
33. Ans: (b)

Solution: S0  C·0  C·B  B·C

f  S0 ·1  S0 ·A  S0  S0 A  S0  A 
f  BC  A  B  C  A  ABC

34. Ans: (c)

Solution:
A B Y
0 0 1
0 1 0 Y  AB  AB
1 0 0
1 1 1
35. Ans: (c)

Solution: When output is 1, then S will be also 1and S will go to 1 after 1μsec and output
become zero, again S becomes 0 and switch will go to 0 after 1μsec and output to 1 this will
continue and we will get the waveform at output as
So, T=2μsec
Then,
1 1
f   0.5  106  0.5MHz
T 2  10 6
36. Ans: 3
Solution:

Y = AB + BC + CA
Hence, maximum number of two input terms is equal to 3.
37. Ans: (a)

 
Solution: F  BC  BCA  BCA  BC A  A  BCA  BCA  BCA  BCA  BCA  BCA
F  ABC  ABC  ABC  ABC

F   m  0, 4, 5, 6 
38. Ans: (a)

Solution: Since, A1  A and A 0  B
Y =  AB B  AB.A  AB B  AB .A  AB
Y = OR - gate output
39. Ans: 5
Solution: Given that,
Tcarry  5ns and Tsum  10ns
From the above circuit we have,

TC  5ns
1
TC  (5ns  5ns)  10ns

2
Ts  (10ns  10ns)  20ns

2
Here, we see the final (sum) result will take T = 20 ns

1 1 109
Maximum rate of addition/sec =   = 0.5  108  5  107
T 20ns 20

40. Ans: (b)

Solution: Augend=1001
Addend= B3B2 B1 B0 = B (say)
4-bit binary parallel adder output= (1001)2  B  1
= (1001)2  (2’s complement of B)
= (9)10  (B)10
= 9’s complement of B.
If C4 =1 and S3S2S1S0 is a valid 9’s complement number.
9’s complement number+ (0001)2 =10’s complement of the number.

We recommend you to take the Chapter Test first and then

check the Solutions.

Chapter Test Solutions

1. Ans: (d)
Solution: tsum=tEX-OR +tEX-OR=60 ns and tCarry =tEX-OR+t AND+tOR=50 ns
2. Ans: (b)
Solution: 1010 +1’s complement of BCD + C0 (= 1)
= 1010 + 2’s complement of BCD
=10 - BCD =10’s complement of BCD
3. Ans: (c)
Solution: Output of full adder
S = xy Q
Carry of fulladder
Q(t+1) = C =xy + x Q(t) + y Q(t)
4. Ans: (c)
5. Ans: (b)
Solution: output  1010  1's complement of BCD
 1001  2's comp of BCD
 9 - BCD
 9's complement of BCD
6. Ans: (d)
Solution: Z  D  ABC  ABC  ABC  ABC  ABC 
 
Z  D  AB  BC  ABC   D B(A  A C)  BC   D B(A  C)  BC 
     
Z  D BC  BC  AB   D BC  AB   D B  C AB 
     

7. Ans: 7
Solution: Y  S1 S0 I0  S1 S0 I1  S1S0 I2  S1S0I3
Hence total 7 NAND gates required.
8. Ans: (c)
Solution: The radix of the system is 18 and based on that we consider the carry.

9. Ans: (b)
Solution: Redraw the circuit
A B C D F
X X X 0 0
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 0
1 1 1 1 1
f  D(AC  AC)  D  AC
10. Ans: 4.42 to 4.45

Solution: Minimum propagation delay = (3  50+75) nsec=225 nsec
1
Maximum addition per second=  4.44  106 additions / sec
225nsec
A  4.44
11. Ans: (c)

Solution:
Output of counter
D3 D2 D1 D1 I1 I0 Y2
0 0 0 0 0 1 0
0 0 0 1 1 1 0
0 0 1 0 1 1 0
0 0 1 1 0 1 0
0 1 0 0 0 0 0
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 0 1 1 0 1

3
Duty cycle=  100  30%
10
12. Ans: 219

Solution: Decimal input=92
BCD=10010010
Output of gray code converter=11011011
Y0 Corresponds to Im with (Sn .......S0 ) is= (11011011)2
m=219
13. Ans: (a)

Solution: For an 'n' output DEMUX. let number of select lines required = m ,
as we know, n= 2m
log2n  log2 2m  m
m  log2n  log2 256
 m  log2  2  8log2 2  8
8
14. Ans: (a)

Solution: Let output of first MUX is Y  AB  AB  A  B
X  YC  YC  Y  C  A  B  C = ABC  ABC  ABC  ABC
15. Ans: (b)

Solution: Augend=1001
Addend= B3B2 B1 B0 = B (say)
4-bit binary parallel adder output= (1001)2  B  1
= (1001)2  (2’s complement of B)
= (9)10  (B)10
= 9’s complement of B.

Combinational Circuits

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Combinational Circuits

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Digital Electronics (Combinational Circuits)

2. Find the output of the following circuit

(a) m(3, 4, 5, 9, 12, 13)

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8. The storage element for a static RAM is

9. A 4  1 MUX is used to implement a 3-input Boolean function as shown in ﬁgure. The

(a) F(A, B, C) =  (1, 2, 4, 6)

(b) F(A, B, C) = (1, 2, 6)

(c) F(A, B, C) = (2, 4, 5, 6)

(d) F(A, B, C) = (1, 5, 6)

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11. What is the name of given circuit?

(a) Full Subtractor

(b) Full Adder

(c) 3-bit even parity generator

(d) 3-bit odd parity generator

A > B = A1 B1 + (A1  B1 ) A0 B0 A > B = A1 B1 + (A1  B1 ) A 0 B 0

A > B = A1 B1 + (A1 B1 ) A 0 B0 A > B = A1 B1 + (A1 B1 ) A 0 B0

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15. In the following MUX, find the output f.

(a) C2 .C1S  C2C1 (A  B)

(b) C2 C1  C2C1  C2 C1S  C2C1 AB

(d) C2 C1  C2 C1S  C2C1 (AB)

16. The output of the 4  1 MUX shown below is

17. DRAMs have advantages over SRAMs in that

i. They have lower cost

(a) i, ii & iii (b) Only i

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(a) I0  0,I1  1,I2  A & I3  A (b) I0  1,I1  0,I2  A & I3  A

(a) I0  C,I1  C,I2  I3  C (b) I0  C,I1  C,I2  C,I3  C

(a) Slow speed of operation (b) Larger storage capacity

(a) 1000 (b) 0001

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(a) Σm(1, 3, 5, 6, 7, 11, 14)

(b) Σm(3,6, 7, 8, 11, 12, 14, 15)

(c) Σm(3, 6, 7, 8, 11, 12, 14, 15)

(d) Σm(3, 6, 7, 9, 11, 12, 14, 15)

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26. Consider the logical circuit given below

27. Which of the following statements is not true?

(a) ROM is a programmable logic device.

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28. Consider the circuit given below

Which of the following statements is true for Y.

(a) Y  CD  DC(A  B)  CDS

30. Consider the logic circuit given below

The minimized expression for F is

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31. Consider the circuit given below

32. In the following circuit the function f( x2 , x1 , x0 ) is

(a)  M(0, 2, 4,5)

33. The network shown below implements

(a) NOR gate

(b) NAND gate

(c) XOR gate

(d) XNOR gate

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34. The logic circuit of figure is a

(a) Half adder

35. A 2-to- 1 digital multiplexer having a switching delay of 1 μs is connected as shown in

(c) pulse train of frequency 0.5 MHz

(d) pulse train of frequency 1.0 MHz

(a)  m(0, 4,5, 6)

(b)  m(3, 4,5, 6)