EEL2020 Digital Design Lab Report

Sem II AY 2023-24

Experiment No. : 05

Name : Ankit Shaw

Roll No. : B22EE009

Partner Name (Partner Roll No.) : Anuj Patil (B22EE010)

Objective
(i) Design, simulate, and implement a Priority Encoder

Logic Design
A Priority Encoder implements a priority function: If more than one input is 1, the input having highest
priority takes precedence. Here, the input having a higher index will take priority.

Source Description

- Design source module priority_encoder(input [3:0] D, output reg A, output reg B, output reg V);
always @(D) begin if (D[3]==1'b1) begin A = 1'b1; B = 1'b1; V = 1'b1; end
else if (D[2]==1'b1) begin A = 1'b1; B = 1'b0; V = 1'b1; end else if (D[1]==1'b1)
begin A = 1'b0; B = 1'b1;
V = 1'b1;
end else if
(D[0]==1'b1) begin
A = 1'b0; B = 1'b0;
V = 1'b1; end else
if (D==4'b0000)
begin A = 1'bx;
B = 1'bx;
V = 1'b0;
end end
endmodule

- Constraint file
The PYNQ XDC file was updated with the following changes:
 Ports Designation Pin Configuration
(from Verilog module) (Input/Output) PYNQ Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

V Output LED0 R14

A Output LED2 M14

B Output LED3 N16

The RPI XDC file was updated with the following changes:

Ports Designation Pin Configuration

(from Verilog module) (Input/Output) PYNQ Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

D[3] Input SWITCH RPIO_18 C20

D[2] Input SWITCH RPIO_19 Y8

D[1] Input SWITCH RPIO_20 A20

D[0] Input SWITCH RPIO_26 W9

- Simulation source

module testbench;
reg [3:0] D; wire A,B,V; priority_encoder
test(D,A,B,V); initial begin for (D = 4'b0000;
D<4'b1111; D=D+4'b0001) begin #20;
end D=4'b1111;
#20;
$finish; end
endmodule
Simulation Results (Timing diagram)

Truth Table

Input Output

D0 D1 D2 D3 A B V

0 0 0 0 X X 0

1 0 0 0 0 0 1

X 1 0 0 0 1 1

X X 1 0 1 0 1

X X X 1 1 1 1
Schematic

PYNQ Working Video

https://drive.google.com/file/d/1bS7SFU6KDFaGesAjfpRHe7fX4KiBfX9F/view?usp=classroom_web&au
thuser=0
Complete File
https://drive.google.com/file/d/1SFv3efXndxlfy8YU0M_xw8PpUsVpbgxj/view?usp=classroom_web&a
uthuser=0
Objective
(ii) Design and simulate a 4 × 16 decoder using 2 × 4 decoders (with Enable)

Logic Design
A 4 x 16 decoder can be made using five 2 x 4 decoders as shown in Fig.

Source Description

- Design source module decoder_2x4(input [1:0] w, input en,

output reg [0:3] y); always @(w, en) begin if (en == 1'b0)
y = 4'b0000; else if (w == 2'b00) y = 4'b0001; else
if (w == 2'b01) y = 4'b0010; else if (w == 2'b11) y
= 4'b1000; else if (w == 2'b10) y = 4'b0100; end
endmodule;

module decoder_4x16(input [3:0] A, output [15:0] I);

wire [3:0] enable; decoder_2x4
d0(A[3:2],1,enable[3:0]); decoder_2x4
d1(A[1:0],enable[0],I[3:0]); decoder_2x4
d2(A[1:0],enable[1],I[7:4]); decoder_2x4
d3(A[1:0],enable[2],I[11:8]); decoder_2x4
d4(A[1:0],enable[3],I[15:12]); endmodule

- Constraint file
The PYNQ XDC file was updated with the following changes:
 Ports Designation Pin Configuration
(from Verilog module) (Input/Output) PYNQ Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

I[6] Output LED3 M14

I[7] Output LED2 N16

I[8] Output LED1 P14

I[9] Output LED0 R14

I[10] Output RGB LED4_r N15

I[11] Output RGB LED4_g G17

I[12] Output RGB LED4_b L15

I[13] Output RGB LED5_r M15

I[14] Output RGB LED5_g L14

I[15] Output RGB LED5_b G14

The RPI XDC file was updated with the following changes:

Ports Designation Pin Configuration

(from Verilog module) (Input/Output) RPIO Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

A[0] Input SWITCH RPIO_18 C20

A[1] Input SWITCH RPIO_19 Y8

A[2] Input SWITCH RPIO_20 A20

A[3] Input SWITCH RPIO_26 W9

I[0] Output LED RPIO_25 F20

 I[1] Output LED RPIO_24 Y7

I[2] Output LED RPIO_23 W6

I[3] Output LED RPIO_22 U8

I[4] Output LED RPIO_13 W8

I[5] Output LED RPIO_12 B20

- Simulation source module testbench;

reg [3:0]A; wire
[15:0]I; decoder_4x16
test(A,I); initial begin

A=4'b0000;
#20;

A=4'b1110;
#20;

A=4'b1011;
#20;

A=4'b0110;
#20;

A=4'b1001;
#20;

A=4'b0010;
#20;

A=4'b1111;
#20;

A=4'b1010;
#20;

$finish;
end
endmodule
Simulation Results (Timing diagram)
Truth Table
Schematic

PYNQ Working Video

https://drive.google.com/file/d/1api7aLA8Kq34FczAH4NyzlnuD9-
oK8tU/view?usp=classroom_web&authuser=0

Complete File
https://drive.google.com/file/d/1lcI2QPEwPlXczKeQ6n3AoABZm3L5WiM6/view?usp=classroom_web
&authuser=0
Objective
(iii) Design, simulate, and implement a Binary-to-Gray Code Converter

Logic Design
A 4-bit Binary-to-Gray converter takes a 4-bit binary number and converts it to corresponding Gray
code.

Source Description

- Design source module BinToGray(

input b0,b1,b2,b3,
output g0,g1,g2,g3
);
assign g0 = b0 ^ b1 ; assign
g1 = b1 ^ b2 ; assign g2 = b2 ^
b3 ; assign g3 = b3 ;
endmodule
- Constraint file
The PYNQ XDC file was updated with the following changes:

Ports Designation Pin Configuration

(from Verilog module) (Input/Output) PYNQ Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

g3 Output LED3 M14

g2 Output LED2 N16

g1 Output LED1 P14

 g0 Output LED0 R14

The RPI XDC file was updated with the following changes:

Ports Designation Pin Configuration

(from Verilog module) (Input/Output) RPIO Component Type (from the PYNQ User
(Button/LED/Switch etc. along Manual)
with number, eg. LD01, BTN2, etc.)

b0 Input SWITCH RPIO_18 C20

b1 Input SWITCH RPIO_19 Y8

b2 Input SWITCH RPIO_20 A20

b3 Input SWITCH RPIO_26 W9

- Simulation source

module test; reg

b0,b1,b2,b3; wire
g0,g1,g2,g3;
BinToGray btg(.b0(b0), .b1(b1), .b2(b2), .b3(b3), .g0(g0), .g1(g1), .g2(g2), .g3(g3));
initial begin b0 = 1'b1; b1 = 1'b1; b2 = 1'b1; b3 = 1'b1;

repeat(2) begin
b3 = ~b3; b2 =
~b2; b1 = ~b1;
b0 = ~b0;
#5;
b0 = ~b0;
#5; b0 =
~b0;
b1=~b1;
#5; b0 =
~b0; #5;
b2 = ~b2;
b0=~b0;
b1=~b1;
#5;
b0=~b0;
#5;
b0=~b0;
b1=~b1;
#5;
b0=~b0;
#5; end
$finish; end

Simulation Results (Timing diagram)

Truth Table
Schematic

PYNQ Working Video

https://drive.google.com/file/d/1TAUU6tyUgJOFh3g-
3V7PLBNqlSnMEeaj/view?usp=classroom_web&authuser=0

Complete File
https://drive.google.com/file/d/1cGT_-
lbFxYLoI12ipv4nvmLUybGcSANj/view?usp=classroo
m_web&authuser=0