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TTC 2022
System Analysis
ESA M5 Envision mission, a Venus scientific orbiter planned to be launched in 2031, has been considered as reference
for the system analysis being the first mission asking for very high rate downlink with a potential need of parallel PN
ranging. Envision communication system foresees an X-X-Ka link to support downlink of about 81Gb/day science data
volume over a large Earth-S/C range distance (0.3 to 1.74 AU) and facing frequent occultation by Venus due to low orbit.
The science data will be mainly downloaded via the Ka-band link being the one with the largest bandwidth.
The analysis focused on the identification of the optimal symbol rates set and residual Doppler to be managed on Rx side.
The symbol rate set optimization was aimed to maximize the achievable data volume avoiding system oversizing and
considering the use of a variable rate scheme during pass.
The optimization consider the full science phase for all launch scenarios (i.e. from November 2034 to March 2040), the
use of 35m Estrack G/S, an on-board Communication system characterized by a Ka-band EIRP of 102dBm and takes into
account the link margin variability due to S/C elevation, solar noise and Venus noise, the latter playing a key role at short
Earth-S/C distances.
The resulting SNR dynamic range and variation during each downlink pass are the key parameters that, together with the
channel usage efficiency % and the constraint on the max number of rates during a pass identified by the SGICD (4 rates
per pass), lead to identify the range and the granularity of the optimal symbol rates set.
A geometric progression has been considered as the optimal alphabet implementing the symbol rate granularity since it
allows to best fit the SNR variation limiting at same time the number of rates. Assuming the use of Turbo coding scheme,
the resulting optimal set of symbol rates is made of 17 rates from 2.9Msps to 290Msps.
Concerning the Envision Doppler scenario and the Doppler compensation capabilities offered by the Ground Station,
which are bounded by the orbital prediction errors of up to 3 m/s in range-rate and 50 mm/s2 in range-rate-rate, and
considering a 20% margin added on top, the resulting Doppler figures and the relevant proposed requirement for the
receiver are reported in Fig. 1.
On board Transmitter Architecture
The stringent requirements in terms of TM symbol rate in GMSK mode implies a revision of the traditional modulation
scheme adopted for on-board GMSK telemetry generation.
In this chapter a review of the Digital Signal Processing (DSP) updates needed to fulfil this new scenario is analysed and
the modulator performance are evaluated.
Traditional DSP applicable to symbol rates up to 10 Msps is represented in the block diagram in Fig. 2.
According [1], incoming TM data are pre-coded in order to remove the differential encoding implicit in the GMSK
modulation thus improving the overall link performance.
Very high GMSK telemetry rate plus PN Ranging generation approach
The traditional DSP approach has to be revisited in view of achieving the required GMSK symbol rate up to 290 Msps.
A Parallel DSP architecture had to be designed in order to make the sampling frequency compatible with state-of-art
space-qualified FPGA and to match compatible D/A converter featuring a built-in 4 to 1 digital multiplexer (MuxDAC).
Consequently, the chosen number of samples per symbols for GMSK shaping is 4 to be compatible with said parallel
processing.
Fig. 1: Envision Doppler scenario (left) and receiver Doppler scenario with Doppler
compensation (right)
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Clock Domain @ Data Rate Clock Domain @ 8xData Rate
To DACs
TM Data Data I/F
Differential
Coding
Gaussian
Shaping CORDIC
sin/cos
The Pseudo-Noise Ranging (RNG) numeric signal is processed employing a dedicated parallel DSP chain that includes
chip-shaping and interpolator modules. TM symbol phase is added to the PN-RNG signal to obtain the total TM GMSK
plus RNG symbol phase.
The parallel DSP architecture designed for Very high-rate GMSK plus RNG modulation is reported in Fig. 3. It is
characterized by the main points outlined here below:
System clock is equal to 4Rs or 1.16 GHz, being the maximum symbol rate Rs=290 Msps. This clock is divided
by 4 by the MuxDAC(s) and then used as FPGA clock for the GMSK plus RNG blocks that perform the DSP.
All the GMSK plus RNG blocks inside the FPGA operate at symbol rate of 290 Msps. Data interface and the
pre-coding modules function in sequential mode. Subsequent blocks (i.e. Gaussian/PN shaping, phase integrator,
CORDIC-based trigonometric functions computation) are implemented in a parallel fashion at 4 samples per
symbols to minimize the sampling rate along the digital modulating chain.
The parallel interpolators include both integer interpolator stages (CIC filter based) and fractional (Farrow filter
based). CIC filters are in charge to interpolate by multiples of 4, Farrow filters are optimized to provide
interpolation from 1 to 4, thus covering all needed combinations.
Due to this flexible symbol rate scenario, a processor (either on-FPGA and/or on-board) is in charge to configure
the architecture parameters (e.g. interpolation factors, PN initialization values, modulation indexes) through a
dedicated data bus. Moreover it configures and interfaces to ancillary blocks (i.e. the external PLL that generates
the 1.16GHz clock reference) using a serial interface.
The in-phase and quadrature digital samples at the output of each CORDIC block is delivered to the relevant
MuxDAC which is in charge of digital multiplexing at system clock (1.16 GHz) and D/A conversion.
Integrator FPGA
CORDIC
FIR0 interpolator sin/cos
I/Q Modulating Analogue Signals
(to low-pass filters)
CORDIC
FIR1 interpolator sin/cos
TM Data
Differential muxDAC
Data I/F
Coding (I)
muxDAC
CORDIC
FIR2 interpolator
sin/cos
CORDIC
FIR4 interpolator
sin/cos
Clock domain :
4 x TLM symbol rate
Fclk/4
290 MHz
Fclk=
1.16 GHz
interpolator
interpolator
PN Ranging
Code Polyphase Integer PLL
Chip Shaping interpolator
Generator
interpolator
PN Ranging PLL
Serial
interface
Clock domain : 8 x PN ranging chip rate
TLM CLK
FROM OBC
uP
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Fig. 5. Overall ground receiver architecture
been designed with a normalized equivalent band BeqDLLTS = 10-5. The two loops for phase and timing recovery must work
together in order to effectively implement coherent discriminators, with better performance at lower Es/N0 values. The
telemetry receiver is equipped with a TM lock monitor whose work thresholds are set by the SNR estimator being
dependent on the application scenario. In order to locally reconstruct the TM signal to be able to cancel it on the ranging
side, specific algorithms have been designed to resolve the intrinsic ambiguities to the differential encoding and phase;
RG
furthermore, the reconstructed telemetry signal is oversampled with N OV , then it is resampled to obtain the pre-DLL
timing scale and, finally, it is correctly aligned with the signal at the input of the ranging receiver.
Concerning the ranging receiver, the local replica of the chip pulse is stored in a LUT and is aligned to the received signal
DLL
through a coherent DLL with a normalized equivalent band Beq TC = 10-7. This approach allows for firmware
simplification and, at DLL steady-state, returns an aligned chip for a direct local ranging reconstruction and cancellation
on the telemetry side. During the initial acquisition phase, an alternate local code (-1)n is used to avoid the code ambiguity,
the performance of which is slightly worse in terms of timing and phase jitter (Fig. 7-B), but still sufficient to initiate
ranging generation and cancellation. Thanks to the long integration times (0.01 s), the DLL performance in terms of jitter
loss does not depend on the ES N0 values and they are very close to the related Cramer Rao Bound (CRB). Also, the
Fig. 6. TM Symbol Error Rate (SER or BER). R = 0.0103 (A- left), R = 1.1022 (B- right)
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Fig. 7. Ranging performance. A-left: Lock monitor for different working cases. B-right: ranging
delay jitter with perfect TM cancellation
ranging receiver is equipped with a ranging lock monitor that, in addition to detect the unlock events, it is also used to
perform the alignment of TM for the purpose of cancellation.
Preliminary validation
The reception performance in terms of TM SER resulting from a complete test campaign, as well as the timing/phase
jitter curves related to the same scenarios, show that the presence of ranging signal causes more interference (greater TM
SER loss) for scenarios where RTM RRG and for high ranging modulation indexes mRG . Given the range of symbol/chip
rates requested by the application, these configurations are frequent. Therefore, although there are scenarios for which
ranging signal represents tolerable interference, the cancellation of the ranging signal at the input of the telemetry receiver
results necessary.
Fig. 6 shows the resulting SER curves for two scenario IDs, when the ranging signal is not cancelled, i.e., it acts as a full
interference. As expected, the worst case is represented by green curve ( mRG = 0.7) in Fig. 6A, where RTM = 290 Msps
and RRG = 3 Mcps. Taking into account the order of magnitude of the ranging delay jitter, the cancellation of the locally
reconstructed ranging on the overall signal appears very efficient, with a resulting telemetry SER coinciding with that
obtained in the absence of ranging signal.
On the other hand, the efficiency of telemetry cancellation depends on the SER, therefore on the ratio ES N0 . For any
target scenario, clearing the telemetry is absolutely necessary for the ranging DLL to converge. Fig. 7A shows the ranging
lock monitor for scenario RTM = 290 Msps and RRG = 3 Mcps, for six working cases, from left to right: perfect TM
cancellation, no cancellation (ranging acquisition is not possible), and cancellation with 4 different SER values.
Fig. 7B shows the ranging delay jitter vs EC N0 in the case of perfect TM cancellation, for TB2, TB4, and alternate
codes, in comparison with the related CRB.
PHASE 2 - IMPLEMENTATION
The second phase was aimed to the implementation of breadboards for both on-board transmitter and ground receiver and
the evaluation of their performance in terms of both telemetry and ranging, including end-to-end test campaign.
On board Transmitter: Breadboarding & Testing
In this section a brief overview the transmitter breadboard and test campaign is reported. The test setup includes a digital
section that mounts a XILINX Virtex6 FPGA and two E2V MuxDACs by Teledyne, an analogue section comprising I/Q
BalUns and reconstruction low-pass filters, the RF X-band 8 GHz downlink section which includes a HMC-8191 I/Q
modulator. The resulting downlink signal is analyzed using a Rohde&Shwarz Signal&Spectrum analyzer that includes a
Vector Signal Analyzer (VSA) and Demodulator function.
During VHRT transmitter test campaign the spectral properties and modulation vector were analyzed and the compliance
with the relevant ECSS recommendations in [1] was analyzed. Regarding spectral properties, the downlink signal
spectrum was compared to the recommended spectral masks. The emission mask test results is reported in Table 1 and
an example of measure is shown in Fig. 8. It was the ratio between the TM data and RNG chip rates is close to one, the
spectrum of VHRT TX signal fails to comply with the ECSS recommendation. In the other cases, the emission mask test
is passed.
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Table 1: VHRT spectral emission mask test results
TM Symbol EVM RMS I/Q subc. angle Amplitude Imbalance I/Q suppression
GMSK BT
Rate [MSps] (<5%) [%] offset (<5°) [degs] (<0.5 dB) [dB] (>21 dB) [dB]
0.25 3.61 3.83 0.26 28.96
290.000
0.5 4.61 4.38 0.28 27.84
0.25 2.00 3.52 0.14 30.01
163.125
0.5 2.26 3.7 0.16 29.64
0.25 1.80 0.19 0.08 46.93
68.818
0.5 2.10 0.25 0.07 46.94
0.25 1.92 0.48 0.18 39.16
21.775
0.5 2.06 0.46 0.18 39.17
0.25 1.73 0.43 0.16 40.03
9.186
0.5 1.65 0.35 0.14 41.51
0.25 1.63 0.39 0.14 41.48
2.907
0.5 1.41 0.35 0.14 41.51
Concerning the demodulation test, the transmitted constellation vectors (TM only) were measured according to the
specifications in [1] in terms of: Error Vector Modulation (EVM), I/Q subcarrier angle offset, Amplitude Imbalance, and
I/Q suppression. All the figures reported in Table 2 show full compliance with the ECSS recommendations.
Ground Modem: Breadboarding and End-to-End tesiting
Concerning the end-to-end test campaign, VHRT modulator and demodulator breadboards are integrated to verify the
complete function. The test bench proposed for validating the very high-rate GMSK with simultaneous PN ranging is
depicted in Fig. 9. It features the On-board Modulator Breadboard, On-ground Modem Breadboard, RF channel including
frequency conversion from X-Band to IF (530MHz), Additive White Gaussian Noise (AWGN), RF/IF filtering,
Frequency synthesizers for clock and Local Oscillator (LO) generation, data generation and BER testing for GMSK link
performance characterization, Spectrum analyzer for RF spectrum measurements, Logic Analyzer for FPGA(s)
debugging, Personal Computers (PC) for on-board and on-ground breadboards configuration and monitoring.
The On-Ground breadboard includes a XILINX Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit and the XM500
breakout board that is used as A/D front-end for the receiver demodulator. The On-board Modulator, the On-ground
Modem and the LO used to convert the down-link modulated signal to the receiver IF (i.e. 1.16 MHz, which 4 times the
maximum TLM symbol rate) share the same master oscillator at 10 MHz. This approach allows a precise control of the
frequency estimated by the On-ground Modem when demodulating the down-link signal; moreover, any kind of Doppler
profile can be programmed on the down-link carrier frequency and GMSK symbol rate. A dedicated high-rate Bit Error
Rate (BER) meter with configurable reference sequence was designed and implemented on the RX breadboard
specifically to handle the high TM data rates up to 290MSps.
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Logic Logic
Analyzer On-board Modulator Analyzer
Ground modem
Configuration & Debugging
Configuration & Debugging
Noise
UART Generator UART
Tx,CE Rx,CE
8.53 GHz
Demodulated
data
LO
TLM PN
BER generator
Meter
10 MHz
1.16 GHz
On-ground On-board
Modem 10 MHz
Tx
Freq. Ref. reference
Freq. Ref.
1,E+00
SER (theory)
SER TM only
1,E-01 Doppler +800Hz
Doppler -800Hz
3MCPS 0.2rad/pk
SER
1,E-02
3MCPS 0.35rad/pk
3MCPS 0.7rad/pk
1,E-03 24MCPS 0.2rad/pk
24MCPS 0.35rad/pk
REFERENCES
[1] ECSS-E-ST-50-05-C, “Radio frequency and modulation”, October 2011
[2] “Simultaneous Transmission of GMSK Telemetry and PN Ranging”, Informational Report Green Book, CCSDS
413.1-G-1, May 2017.
[3] M. Luise and R. Reggiannini, “Carrier Frequency Recovery in All-Digital Modems for Burst-Mode
Transmissions,” IEEE Transactions on Communications, vol. 43, no 2/3/4, pp. 1169-1178, April 1995.
TTC 2022