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NITTE MEENAKSHI INSTITUTE OF TECHNOLOGY

(AN AUTONOMOUS INSTITUTE AFFILIATED TO VTU, BELAGAVI)

3rd Semester Mid-Semester Examination BE Degree (MSE-1)

Academic year 2023-2024
Department of Information Science and Engineering
Digital Design (22ISG32)

Duration: 1 Hr Max. Marks:30

Semester: 3rd Date: 07.12.2023
Faculty: Pramod Jain S.A, Vani E S
Instructions
1. Q1 (6 Marks) & Q4 (4 Marks) - Compulsory questions.
2. Q2 and Q3 Choice-based questions for 10 marks each.
3. Missing Data (if any) can be suitably assumed.

Question No Question Marks CO; BL

Answer the following questions.
Q 1. a. What are Universal Gates? Realize Basic Gates Using Universal Gates 1; 2
2
b. Obtain Alternat logic gate representation of all the gates 1; 1
2
c. Implement EXOR Gate using 2:1 Multiplexer 2 2; 3
UNIT-I (10 marks)
Q 2. a. Apply K map Method to Obtain SOP and POS expression for the following:
6 2; 3
i) F(A,B,C,D) = πM(0,3,4,11,13)+dc(2,6,8,9,10)
b. Implement the following using only NAND Gates
4 1; 2
i) F(A,B) = A’B+A’B’+AB’ using only NAND Gates
OR
a. Apply K map Method to Obtain SOP and POS expression for the following: 2; 2
6
Y(A,B,C,D)= ∑m(0,1,5,7,10,13,14) + dc(2,4)
b. Using K map determine the minimal sum of product expression for the 1 ;3
4
following f(A,B,C,D)= A’B’C + AD+BD’+CD’+AC’+A’B’
UNIT-II (10 marks)
Q 3. a. Implement f(a,b,c,d) =∑m(0,1,5,7,9,10,15 ) Using 8:1 Mux with a, b, c as 2; 3
6
select lines
b. Construct 8:1 Multiplexer using 4:1 and 2:1 Multiplexer and obtain its Truth 1; 3
4
Table
OR
a. Implement f(a,b,c,d) =∑m(0,1,5,7,9,10,15 ) Using Only one 4:1 Mux with c , d 1;3
6
as select lines
b. Realize 4:16 Decoder using 3:8 Decoder and obtain its Truth Table 4 2; 2
Q 4. a. There are 4 parallel railway tracks A,B,C and D at a place. If 2 trains pass
adjacent on these tracks, a warning signal W flashes ON. 1 indicates
presence of train on track, 1 indicates warning signal is ON. 0 indicates
4 2;4
absence of train on track, 0 indicates warning signal is OFF . Design the
truth table and simplify the expression using K map . Draw the logic circuit
using only NAND gates .
Faculty Signature Scrutinizer signature HOD Signature

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