Lecture 02 EEL2020 Digital Design

Introduction to
Hardware Description
Language
Dr. Rajlaxmi Chouhan
Associate Professor
Department of Electrical Engineering
IIT Jodhpur

Reference: Brown & Vranesic, Ch. 2

A typical

CAD System
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A typical CAD system
Conception of what the circuit is supposed to do and the
formulation of its general structure

Design Entry
Entering a description of the
circuit being designed into the
CAD system

Schematic refers to a diagram

of a circuit in which circuit
elements, such as logic gates,
are depicted as graphical
symbols and connections
between circuit elements
are drawn as lines.

A typical CAD system

Conception of what the circuit is supposed to do and the
formulation of its general structure

Design Entry
Entering a description of the
circuit being designed into the
CAD system

A hardware description
language (HDL) is similar to a
typical computer programming
language except that an HDL is
used to describe hardware
rather than a program to be
executed on a computer.
E.g. IEEE Standards: VHDL &
Verilog
Verilog offers design portability. A typical CAD system
Logic Synthesis
Process of generating a logic
circuit from an initial
specification (design entry)
May manipulate the
user’s design to automatically
generate an equivalent, but
better circuit.

Functional Simulator
Simulates the logic expressions
to verify if the circuit will function
as expected
Results in the form of Timing
diagram

A typical CAD system

Physical Design
Maps a logic expressions into a
realization using resources
available on the target chip

Timing Simulator
Evaluates expected delays of
the designed logic circuit

Circuit Implementation
Chip fabrication
Configuration or programming
A typical CAD system
Which of the following is not an
example of Schematic Capture?

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Introduction to

Verilog
Introduction to Structural
Representation

Verilog (gate-level primitives)

Behavioral
Representation
(logic expressions)
Structural
Representation
(gate-level primitives)

Functional Output Inputs

name
Structural << all ports >>
Representation
(gate-level primitives)
Example: 2 x 1 Multiplexer
Example: 2 x 1 Multiplexer Structural Representation in Verilog
Example: 2 x 1 Multiplexer Behavioral Representation in Verilog
Represent gates with the following Verilog operators
AND &
OR |
NOT ~
The assign keyword provides a continuous
assignment for the signal f.

Concurrent
assignment
Exercise: Write a Verilog code to represent the following logic circuit.
Use continuous assignment.
The first line of the module would be

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Exercise: Write a Verilog code to represent the following logic circuit.
Use continuous assignment.

module example4 (x1, x2, x3, x4, f, g, h);

input x1, x2, x3, x4;

output f, g, h;

endmodule

Write the assign statements in your

notebooks.
The codes corresponding to continuous
assignment are

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Exercise: Write a Verilog code to represent the following logic circuit.
Use continuous assignment.
this comes under behavioral representation

module example4 (x1, x2, x3, x4, f, g, h);

input x1, x2, x3, x4;

output f, g, h;

assign g = (x1 & x3) | (x2 & x4);

assign h = (x1 | ~x3) & ( ~x2 | x4);
assign f = g | h;

endmodule
Example: 2 x 1 Multiplexer
Example: 2 x 1 Multiplexer Behavioral Representation in Verilog

Even higher levels of abstraction is possible.

The if-else statement is an example of a

Verilog procedural statement.

Verilog syntax requires that procedural

statements be contained inside a construct
called an always block.
Example: 2 x 1 Multiplexer Behavioral Representation in Verilog

Within the always block,

statements are evaluated in the order given in the
code

always @( )

Sensitivity list

The statements inside an always block are executed

by the simulator only when one or more of the signals
in the sensitivity list changes value.

If a signal is assigned a value using procedural

statements, then it should be declared as a variable
using the keyword reg
Example: 2 x 1 Multiplexer
If a signal is assigned a value using procedural statements,
then it should be declared as a variable using the keyword
_____.

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Reference
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd ed.,
McGraw Hill: New York, 2014, ch. 2.