Unit II

Carrier Transport Phenomena

• Fabrication materials
• MOS architecture
• Fabrication of integrated circuits
• Material growth and oxidation
• Doped silicon layers
• Lithography

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Fabrication Materials
Depending upon the resistivity of a material, There are three types of materials, as:
1. Insulators
2. Conductors
3. Semiconductors (SC) Conduction Band

Insulators
▪ Very high electrical resistance EG , Energy
Band Gap
▪ Strong Co-valent bond or Ionic bond
▪ Do not allow any flow of current through them
Valence Band
▪ Large energy band gap ≥ 5 eV
▪ In insulator energy gap slightly decrease with temperature Fig. 1 Energy band diagram
1
EG ∝
Temperature
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• Negative temperature co-efficient resistance property

R with Temperature

• Examples: Diamond, ceramic, Silicon dioxide, air, rubber, plastic, Bakelite

Conductors
• All metals are very good conductor of current
• Metallic Bond
• Unipolar (current is carried in metal only by electron)
• In metal electron concentration is very high.
𝑛 = 1028 /𝑚3
• In metals free electron concentration is independent of temperature (T).
• EG = 0 eV, at T = 0 K

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 Conduction Conduction
Band Band

Overlapping

Valance Band
Valance Band

T=0K T = 300 K

Fig 2: Energy band diagram, at different temperature.

• So positive temperature co-efficient of resistance

• In metal there will be only drift current
• Examples: Gold , Silver, copper, Aluminium, Iron

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Semiconductors
• Semiconductor belongs to 4th group of the periodic table
• Valence electron = 4
• Nature of Bonding Co-valent bonding
• Bi-polar (two different types of charge carriers) i.e, electron and holes
• Smaller energy gap
Empty Conduction
EG = 0.7 eV to 1.5 eV Band

• At, T = 0 K, carrier concentration are zero. There by conduction band is

empty. Thus, conductivity is Zero. Valance Band
• All Semiconductor are insulator at T = 0 K Filled
T=0K
Fig. 3: Energy Band diagram of Semiconductor.
• At, room temperature because of thermal energy a large no. of co-valent
Conduction
bonds will be broken and equal no. of electron and holes are created. Band
1
EG ∞
Temperature

• Semiconductor is a Negative Temperature Coefficient device.

Valance Band
R with T
• There is diffusion current in semi-conductor At, T = 300 K
• Examples: Silicon (Si), Germanium (Ge)
Fig. 4: Energy band diagram of intrinsic
semiconductor.
Two types of semi conductors

i. Intrinsic Semiconductor
ii. Extrinsic Semiconductor

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i. Intrinsic Semiconductor

• Intrinsic Semiconductor a pure semiconductor

• The concentration available in the pure semi conductor at a given temperature
n = p = ni
• The carrier concentration in an intrinsic semiconductor can be found using the equation:
𝐸𝐺
3 − 𝐾𝑇
𝑛𝑖2 = 𝐴𝑜 𝑇 𝑒
Where, 𝐴𝑜 = Material Constant
K = Boltzmann Constant
T = Temperature

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Doping of a Semiconductor
• The process of adding the impurities to the semiconductor is called doping. Doping increases doping
concentration and there by increases conductivity.
Acceptor / Trivalent Impurities : Boron (B), Aluminium (Al), Gallium (Ga)
Donor / Pentavalent Impurities : Phosphorus (P), Arsenic (As), Antimony (Sb)

Standard Doping Concentration

• Lightly Doped = 1: 1011

• Moderate Doped = 1: 106 to 108
• Highly/ Heavily Doped = 1: 103

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ii. Extrinsic Semiconductor
• Also called doped SC/Impurity SC

N-type SC or Donor SC : Impurity is pentavalent called as n-type semiconductor

P-type SC or Acceptor SC : Impurity in acceptor called as p-type semiconductor

• Doner energy level indicate the energy level of pentavalent atom added to the SC. Conduction Band

• In n-type semiconductor every impurity atom will be donating one electron into the
conduction band and therefore, it is called as donor SC.
• Donor level ionization indication indicate the 5th 𝑒 − moving from donor energy level
into the conduction band. Valance Band
• Donor level ionization increases with temperature. Donor energy level

Fig. 5 : Energy band diagram of n-type

semiconductor .
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• Acceptor energy level denote the energy level of all the trivalent atom added Acceptor energy level

to the pure SC.

• In p-type SC, every impurity atom will be receiving one electron to complete
Conduction Band
it co-valent bonding. Hence, it is called acceptor.
• In p-type SC, at room temperature, because of thermal energy a large number
of co-valent bonds will be broken and equal no. of electron and holes are
created. Valance Band
• Most of the electrons will be moving from valance band to acceptor energy
level. Fig. 6: Energy band diagram of p-
type semi conductor.
• The holes concentration in valance band is far greater than electron
concentration in conduction band.
• Thus, holes are majority carrier and electrons are minority carrier.

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Thermal Voltage (𝐕𝐓 )

• Voltage Equivalent of Temperature, KT

VT =
q

T = Temperature in Kelvin
q = charge (1.6 × 10−19 𝐶)
K = Boltzmann's constant = 1.38 × 10−23 Joule/ deg-Kelvin

• At, room temperature, 𝐕𝐓 (300K) = 26 mV

• For large variation of temperature there will be small variation in thermal voltage.

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Mobility of a Charge Carrier

• Mobility indicates how fast is the electron or hole is moving from one place to another.
Drift Velocity
• Mobility is defined as: μ = Field intensity

𝑉𝑑 𝑚𝑒𝑡𝑒𝑟Τ 𝑚2
• 𝜇=
𝜀
unit = 𝑉𝑜𝑙𝑡ൗ
𝑠𝑒𝑐
= 𝑉 𝑠𝑒𝑐
𝑚𝑒𝑡𝑒𝑟

• Electrons mobility are always greater than holes. There

Conductivity of a Semi Conductor (𝝈)

• Conductivity denotes the current carrying capacity of a material or device.

𝟏
• Unit - It is the reciprocal of resistivity, 𝝈=
𝛀 𝒄𝒎

𝝈 = 𝒎𝒉𝒐Τ𝒄𝒎

• C𝐨𝐧𝐝𝐮𝐜𝐭𝐢𝐯𝐢𝐭𝐲, 𝝈 = Carrier concentration n × Charge q × Mobility (μ)

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In Metal

• 𝜎 =𝑛×𝑞×𝜇
• Mobility decrease with temperature in metal.
• Carrier concentration and charge are independent of temperature in metal.
• Thus, the conductivity decrease in metal.

In Semi Conductor

• 𝜎 = 𝑛 × 𝑞 × 𝜇𝑛 + 𝑝 × 𝑞 × 𝜇𝑝
• As temperature increase mobility of charge carrier decreases slightly also large number of
electron and holes are created.
• Thus, this increase the conductivity with large volume. With increase in temperature.

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 Germanium (Ge) Silicon (Si)
• Atomic No. 32 • Atomic No. 14
• Leakage current in micro Amp. • Leakage current in nano Amp.
• Higher conductivity • Relatively more suitable for switching
• Suitable for High frequency application application
• Maximum operating temperature 75 deg. • Suitable for high power application
• Energy band gap 𝐸𝐺 ( 0 k) = 0.78 eV • Maximum operating temperature 175 deg.
𝐸𝐺 ( 300 k) = 0.72 eV • Energy band gap 𝐸𝐺 ( 0 k) = 1.21 eV
• Mobility, μ𝑛 = 3800 𝑐𝑚2ൗ 𝐸𝐺 ( 0 k) = 1.1 eV
𝑉𝑠𝑒𝑐

𝑐𝑚2ൗ • Mobility, μ𝑛 = 1300 𝑐𝑚2ൗ

μ𝑝 = 1800 𝑉𝑠𝑒𝑐 𝑉𝑠𝑒𝑐

μ𝑝 = 500 𝑐𝑚2ൗ
𝑉𝑠𝑒𝑐

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Advantages of Silicon Semiconductor

• Smaller Leakage current

• High temperature application
• Suitable for high power handling
• Plenty available on the surface of the earth
• Cheapest material
• Favourable properties to form SiO2 , used to provide isolation in-between the component inside the IC.

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 V0
P N Junction P − + N P N
≡

Fig. 7: (a) PN junction semiconductor diode (b) Symbol of PN junction.

• PN junction is formed only when a bonding force is created between the P-type and N-type SC.
• PN diodes are fabricated with any one of the following methods:
➢ Alloy junction Technique
➢ Diffusion Junction Technique
➢ Ground Junction
➢ Epitaxial Method
• In depletion layer mobile charge carrier are zero.
• Depletion layer is created due to the diffusion of majority carrier across the junction.
• Depletion layer oppose majority carrier in crossing the junction.
• Depletion layer consist of large number of charge particle i.e, large number of ions and co-valent bonds.

1
• The width of the depletion layer, 𝑊 =
𝐷𝑜𝑝𝑖𝑛𝑔 16
MOSFET
MOSFET
(Metal Oxide Semiconductor Field Effect Transistor)

Depletion MOSFET Enhancement MOSFET

(There is a pre existing channel) (No pre-existing Channel)

• It is a 4 terminal device: Source (S), Gate (G), Drain (D) and Substrate (SUB)
• Highest input resistance device. ( 𝑅𝑖 = 1010 𝑡𝑜 1015 )
• Symmetrical device, therefore source and drain terminal can be interchange practically.
• MOSFET is a Voltage Controlled Device (VCD).

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 Depletion MOSFET

N-channel Depletion MOSFET

• For N-channel Depletion MOSFET , substrate will be P-type.

• Channel are also called inversion layer.
• An insulating layer 𝑆𝑖𝑂2 is added over the substrate layer having thickness of
1000 to 2000 A.ሶ Fig. 8: n-channel Depletion MOSFET.
• Windows are cut into oxide layer to allow diffusion.
• Two separate n-regions, the source and the drain, are diffused into the surface of a
p-substrate through windows in the oxide.
• Depletion MOSFET there is pre existing channel.
• Channel in called Diffused channel.
• In the gate region a parallel plate capacitor is created.
• Aluminum (Al) plate and the semi-conductor channel will be working as the two
plate of capacitor and the 𝑆𝑖𝑂2 as dielectric medium.
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• MOSFET is basically a capacitor.

• MOSFET is Voltage Control Capacitor.

• The main advantage of MOSFET is the power dissipation is neglectable.

• MOSFET are widely used as switches in digital circuit.

• MOSFET is relatively more suitable for high frequency application than BJT.

• MOSFET is the fastest switch.

• N-MOS is faster than P-MOS (μ𝑛 > μ𝑝 ).

• The main Advantage of N-MOS is higher package density.

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Operation of N-channel Depletion MOSFET

Principle - The principle of the depletion mode is the applied Gate to source
voltage must reduce the majority carrier of the channel.
• In n-channel MOSFET drain is positively biased with respect to the source
and to operate under depletion mode Gate is negatively biased with respect to
the source.
Fig. 9: n-channel Depletion MOSFET
• In N-channel Depletion MOSFET under depletion mode. biasing.
(a) Channel potential increase from source to drain.
(b) Inversion charge decrease from source to drain.

ON Condition
• When, 𝑉𝐺𝑆 = 0 𝑉, is kept zero, inversion charge is zero and therefore, maximum number of negative charge will
be moving from source to drain and drain current (𝐼𝐷 ) is maximum and denoted by 𝐼𝐷𝑆𝑆 .

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• When, 𝑉𝐺𝑆 is applied, the Gate (G) is given with a −𝑣𝑒 and therefore, +𝑣𝑒 change are accumulated in the
semi conductor channel and due to recombination less number of −𝑣𝑒 charge will be reaching the drain and
𝐼𝐷 (Drain current ) decrease.

• If Gate is given with sufficient amount of −𝑣𝑒 voltage large number of +𝑣𝑒 charges are accumulated in the
semi conductor channel and results a total recombination. Hence, number −𝑣𝑒 charge will be reaching the
drain and 𝐼𝐷 decrease to zero and the channel is cutoff.

• Equation of drain current under depletion mode is :

2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝑃

VP = maximum pinch off voltage Fig. 10: Drain current characteristic w.r.t changing
Gate to Source voltage VGS .

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Enhancement MOSFET

Principle :
• The principle of enhancement mode is the applied gate to source voltage must
increase the majority carrier of the channel.
• In N-channel MOSFET drain is positively biased w.r.t source and to operate
under enhancement mode the gate is positively biased w.r.t source.

• In E-only MOSFET the source and drain regions will be kept apart and there,
the channel could not be formed in between the source and drain region.
• Enhancement MOSFET there is no pre existing channel. Fig. 11: n-channel Enhancement
MOSFET.
• In E-MOSFET Aluminium (Al) plate or metallic plates are replaced with poly
crystalline silicon material. Thus, we gets the following advantages:
(a) size of the MOSFET is reduced.
(b) the cost of the MOSFET is reduced.
(c) Fabrication process become easier.

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• In Enhancement MOSFET, channel has to be created by applying proper Gate (G) to Source (S) voltage.

• When Gate (G) to Source (S) voltage is applied and if the body of the MOSFET is grounded, VGS is also reflected
between Gate and Body of the MOSFET and due to the electric field intensity created, a channel is induced in
between the Source (S) and Drain (D) region.

• Enhance MOSFET channel is a induced flat channel.

• A parallel plate capacitor is created at the Gate (G) region with poly crystalline silicon Gate and induced channel
as the two plate of the capacitor and SiO2 as the di-electric material. The MOSFET is now works as a MOS
capacitor.

Note:

➢ In E-only MOSFET, if 𝑉𝐺 = 0 𝑉 than channel will disappear and

drain current 𝐼𝐷 = 0.
➢ In n-channel Enhancement MOSFET
▪ Channel potential increase from source to drain.
▪ Inversion charge decrease from source to drain. Fig. 12: Enhancement MOSFET drain current (I𝐷 )
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Comparison between Depletion MOSFET and Enhancement MOSFET
Depletion MOSFET
1. There in Pre existing channel
2. Not applicable
3. Diffused channel
4. when, VGS = 0, then ID = IDSS .
5. Continuous Channel
6. Relatively larger in size and difficult to
fabricate due to aluminium (Al) plate.
Enhancement MOSFET
1. No pre existing channel.
2. Channel has to be created by applying
proper gate to source voltage.
3. Induced channel
4. If VGS = 0, then ID .
5. Broken channel
6. Relatively smaller in size, easier to
fabricate and offers better performance
due to replacement of Al-plate with poly
crystalline silicon material.
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CMOS (Complementary MOSFET)

• It is the combination of P-MOS and N-MOS connected together.

• Input resistance, 1015 Ω.
• CMOS will not consume any power.
• The greatest advantage of CMOS is zero power dissipation.
• Major application of CMOS is as a inverter.
• In CMOS inverter whatever be the input signal applied, when one transistor is ON the other is OFF.

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 Comparison of CMOS and MOS characteristics
CMOS
1. Zero static power dissipation.
2. Power dissipated during logic
transition.
3. Requires 2N devices for N inputs for
complementary statics gates.
4. CMOS encourages regular layout
styles.
MOS
1. Power is dissipated in the circuit with
output of gate at ‘0’.
2. Power dissipated during logic
transition.
3. Requires (N+1) devices for N inputs.
4. Depletion, load and different driver
transistors create irregularity in layout.
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Fabrication of VLSI circuits

Different types of IC technologies are:

i. Monolithic Technology: For the fabrication of active components. Resistor in an exception which is a passive
component but is formed by monolithic technology.
ii. Thin Film Technology: Provides precision and performance.
iii. Thick Film Technology: Offers cost-effectiveness and widespread use in electronic devices.

➢ Both ii and iii are used for fabrication of passive components.

Note: Monolithic Technology is called as “Epitaxial Technology”. Almost all the entire IC is fabricated on a single
crystal is silicon.

➢ In thin film technology, the thickness of silicon wafer is 50 Å to 5000 Å.

➢ In thick Film technology, the thickness of silicon wafer is 125000 Å to 625000 Å.

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Advantages of IC fabrication

▪ Unbelievable cost reduction due to bulk manufacturing.

▪ Extremely smaller in size and also they can be easily portable.
▪ High reliability with minimum electrical and mechanical failures because no soldering is used for
the interconnection of components.
▪ Improved performance when compared to the discrete circuit components.

Disadvantages of IC’s

• Very sensitive to voltage fluctuations.

• Very sensitive to higher temperature (more than 480 C).
• Sensitive to humidity.

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IC Fabrication process

The following steps are involved in the process of IC fabrication.

1. Crystal Growth and preparation of silicon wafer
2. Epitaxial deposition
3. Oxidation
4. Lithography and Chemical Etching
5. Diffusion
6. Ion Implantation
7. Metallization
8. Circuit testing (not a direct part of the IC fabrication)

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Crystal Growth and preparation of silicon wafer
• It is the first step in the fabrication of the IC.
• Zone refining is used to make the silicon wafer with ultra pure (99.99% purity).
• CZ method (Czochralski method) is used to provide polycrystallization on the silicon wafer.
• The typical value of silicon wafer is 0.5 𝜇𝑚.
• The resistivity of the silicon wafer is 10 Ω − 𝑐𝑚.
Epitaxial Growth

• Epitaxing means creating a very thin single crystal layer of micrometre (𝜇𝑚) thickness on the substrate
material and the layer is called as ‘epi-layers’.
• In this CVD (Chemical Vapour Deposition) process is used in which a batch of silicon wafer is placed
a heated chamber at a temperature (900 – 1250 deg.).

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Oxidation

• It is the process by which SiO2 is deposited on the silicon wafer.

• Several properties of adding SiO2 layer are:
➢ An excellent insulator and it will protect the silicon surface against unwanted contaminations
called passivation.
➢ Serves as a mask against implant or diffusion of dopant into silicon.
➢ Acts as a component in MOS structures.
➢ Provides electrical isolation of multilevel metallization systems.

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Diffusion and Ion Implantation

• It refers to the introduction of the impurities or dopant into the epitaxial layer through the etched
window of SiO2 for the formation of junction such as emitter base junctions and collector base
junctions in BJT and to provide source and drain regions in the MOS transistor.

• Ion implantation is the introduction of ionized projectile atoms into targets with enough energy to
penetrate beyond surface regions.

• In Ion implantation technology it is possible to precisely control the number of implanted dopants.
This method is a low temperature process.

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Lithography
• Photo-lithography means photo engraving lithography refers to the process of transforming the
pattern (layout) on the working mask onto the silicon wafer.
• The silicon wafer is now coated with a photo-resist and the entire wafer will be exposed to ultra
violet light
• The exposer time extents from few hours to more than 24 hrs.
• Photoresists are two type:
(a) Positive resist : When exposed to the ultra violet light, positive resist becomes more
soluble to the developing chemicals.
(b) Negative resist: When exposed to the ultra violet light, negative resist will becpme less
soluble to the developing chemical.
• Positive resist is more popular than negative resist because of higher resolution.
• The exposed areas of the resist are removed, leaving the unexposed portions intact.
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Etching
• Etching is defined as the removal of material from unwanted areas.
• Wet etching: it is done by using hydrofluoric acid (HFCI)
• Perfect etching is not possible by using the wet etching.
• The disadvantage of wet etching is under cutting.
• Wet etching is also called Isotropic Etching.
• Wet etching is generally used when the chip sizes are greater than 2 𝜇𝑚.

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• In the wet etching, lateral etching is made almost equal to vertical etching.
• Dry etching: it is done by using one of the inert gases.
• In dry etching, there is no undercutting.
• Dry etching is also called ‘’anisotropic etching”.
• Dry etching is generally used where the chip size is less than 2 𝜇𝑚.

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• Ion Implantation is also used to reduce the threshold voltage of the MOSFET.
• Ion implantation is the alternate method of diffusion and it is the most common method and is
usually done at low temperature.

Advantage Ion Implantation

i. Precise doping of the window between SiO2 is possible.

ii. It is done at low temperature.
iii. It reduces the threshold voltage of the MOSFET.

𝑺𝒊𝑶𝟐 Role in I.C Fabrication

i. As an isolation layer between the junction
ii. As a passivation layer.
iii. As a dielectric between the poly silicon gate and semi conductor channel.
iv. As an isolation material between the devices.

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Metallization

• It is process of inter connection of components for final functioning of the designed circuits.
• Metallization is done by using sputtering in the sputtering technique hair like structures of gold is used
for the inter-connection of components.

Testing and Packaging

• After completing all the steps in the IC fabrication the IC is made and it is tested for its working and is
also used to test for quality control. The successfully tested IC will be labelled for its test.
• The test IC is subjected to a package such as to package (metallic package) or DIP (Dual – in -
package).

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