Advanced Control and Protection of Modular UPS

Power Systems
Electrical power has been the technological foundation of industrial

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and apply electrical energy have reached a high degree of maturity,
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**Power Systems is indexed in Scopus**
Editors
Jinghang Lu, Baoze Wei, Xiaochao Hou and Yao Sun
Advanced Control and Protection of

Modular Uninterruptible Power Supply
Systems
Editors
Jinghang Lu
Mechanical Engineering and Automation, Harbin Institute of
Technology, Shenzhen, China
Baoze Wei
Energy Technology, Aalborg University, Aalborg East, Denmark
Xiaochao Hou
Tsinghua University, Beijing, China
Yao Sun
Information Science and Engineering, Central South University,
Changsha, China
ISSN 1612-1287 e-ISSN 1860-4676

Power Systems
ISBN 978-3-031-22177-4 e-ISBN 978-3-031-22178-1
https://doi.org/10.1007/978-3-031-22178-1
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Preface
Nowadays, uninterruptible power supply (UPS) systems are commonly
implemented to provide reliable and ef icient power to critical loads,
such as IT communication systems, medical facilities, and data centers,
if the main grid suffers from power outage. The power capacity of a
UPS system varies in the market, from a small capacity of 300 VA with
the ability to support a computer to several megawatts that can
support a data center or a hospital. As a result, the UPS system is
receiving continuous attention from manufacturers and engineers.
Despite the rapid development of the UPS system, control and
protection of this device bring up a lot of challenges for engineers and
researchers.
This book provides a comprehensive and in-depth introduction
into the development of control and protection for the modular on-line
UPS system. For each topic, a theoretical introduction and overview is
backed by very concrete programming examples that enable the reader
to understand the topic. With this book, we intend to enable the reader
to get the latest knowledge on the operation, control, and protection of
the modular on-line UPS systems from the fundamental to the whole
picture.
The main research results of this book have been originally taken
from the authors who carried out the related research together for
almost 6 years, which is a comprehensive summary of the
authors’ latest research results. This book is likely to be of
interest to university researchers, R&D engineers, and
graduate students in electrical engineering who wish to learn the core
principles, control methods, and applications of the UPS system.
Jinghang Lu
Baoze Wei
Xiaochao Hou
Yao Sun
Shenzhen, China
Aalborg, Denmark
Beijing, China
Changsha, China
Acknowledgments
This book is supported in part by Shenzhen Overseas High Level Talent
Project (Peacock Plan), Shenzhen Stable Support Project under Grant
GXWD20201230155427003-2020082319352001.
The author would like to thank the postgraduate students Mr.
Shimiao Chen and Mr. Jiong Li for their contributions and proofreading.
Finally, the authors would like to thank the long-term support and
encouragement from their families.
List of Symbols
S i The converter output apparent power of DG-i
P i The active power of DG-i
The maximum values of the allowable active power
The minimum values of the allowable active power
Q i The reactive power of DG-i
The maximum values of the allowable reactive power
The minimum values of the allowable reactive power
V pcc The amplitude of common ac bus voltage
θ pcc The common ac bus voltage angle
X line The line impedance
R line The line resistance
Z line The impedance between converter and the common bus
Z load The common bus load
V g The amplitude of grid voltage
δ g The grid voltage angle
δ i The angle of output voltage of DG-i
V i The amplitude of output voltage of DG-i
ω i The angular frequency of DG-i
The maximum values of the allowable angular frequency
The minimum values of the allowable angular frequency
m i The active droop coef icient
n i The reactive droop coef icient
ω * The nominal angular frequency value
V * The nominal voltage value
T s The sampling period
C i(P i ) The cost function
P L The total load
The upper bound of load power
f i The DG-i actual frequency
f ∗ The DG-i reference frequency
ζ The damping factor
The sign function
A small perturbation around the steady state points
L f The ilter inductance
R f The ilter resistance
C f The ilter capacitance
i The grid current
i ∗ The reference grid current
ω c The cut-off frequency
Contents
1 Introduction
Jinghang Lu
Part I Front-End Recti ier Control of the Modular UPS System
2 An RGPI Observer-Based Resonant Super-Twisting Sliding Mode
Control
Jinghang Lu
3 An ESO for DC-Link Voltage Control of Three-Phase AC/DC
Converters
Jinghang Lu
Part II Distributed Control and Protection of the Modular UPS
System
4 Distributed Adaptive Virtual Impedance Control for Parallel-
Connected Voltage Source Inverters in Modular UPS System
Baoze Wei
5 Distributed Average Integral Secondary Control for Modular UPS
Systems-Based Microgrids
Baoze Wei
6 Regeneration Protection in Uninterruptible Power Supply
Jinghang Lu
7 DC-Link Protection and Control in Modular Uninterruptible
Power Supply
Jinghang Lu
8 Overload and Short-Circuit Protection Strategy for Voltage-Source
Inverter-Based UPS
Jinghang Lu
Part III Renewable Modular UPS System
9 Multi-mode Operation for On-line Uninterruptible Power Supply
System
Jinghang Lu and Xiaochao Hou
10 AC Microgrid Seamless Transition
Xiaochao Hou, Jinghang Lu and Yao Sun
Index
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023
J. Lu et al. (eds.), Advanced Control and Protection of Modular Uninterruptible Power Supply
Systems, Power Systems
https://doi.org/10.1007/978-3-031-22178-1_1
1. Introduction
Jinghang Lu1
(1) Harbin Institute of Technology (Shenzhen), Shenzhen, China
Jinghang Lu
Email: jinghang.lu@ieee.org
1.1 Uninterruptible Power Supply

The power quality and reliability is a major concern for an electric
power system. Especially, the critical loads, such as telecommunication
systems, network servers, database system, and medical equipment,
require a power supply of higher reliability and capability. Unexpected
failures of the power supply system will lead to serious accidents, not
only to the equipment but also to the human beings, like the patients in
the hospital.
In order to provide clean and reliable power to these kinds of
critical loads, an uninterruptible power supply (UPS) system is often
equipped. A UPS is an electrical power device that can feed power to
the loads under emergency, such as the failure of the input power
source.
Until now, there are various types of UPS system on the market,
such as off-line, line-interactive, on-line, double conversion, digital on-
line, in-line, etc. Most of the names are related with the market need.
According to the IEC 62040-3 standard, UPS systems are classi ied into
off-line, line-interactive, and on-line topologies. In the following sub-
sections, each kind of UPS system will be analyzed.
1.1.1 Off-line UPS System

The con iguration of the off-line UPS system is also known as the
standby UPS system, as is shown in Fig. 1.1. It comprises an AC/DC
converter, a DC/AC inverter, a static switch, and a battery bank.
Normally, the LC type or LCL type ilter is connected at the output of the
inverter to improve the quality of the output voltage. The static switch
is closed during the normal mode of operation when the grid voltage is
at normal condition. Hence, the critical load is directly supplied with
the power from the grid without any conditioning. In the off-line UPS
system, the AC/DC recti ier is mainly responsible to charge the battery;
as a result, the rating of the AC/DC recti ier is usually chosen to be a
small value, i.e., below 2 kVA, which leads to the low cost of the UPS
system. The inverter is switched on only when the grid voltage is
abnormal or not available. Therefore, when the UPS turns to the back-
up mode of operation, the power to the critical load is provided via the
inverter until the grid power returns to the normal condition again.
The duration of the transfer time from the normal mode to the back-up
mode usually takes about 1/4 of line cycle, which is normally enough
for most the of applications such as personal computers. It should be
pointed out that the DC/AC inverter is switched off in the normal mode
of operation for off-line UPS system. As a result, the off-line UPS system
cannot improve the power factor.
Fig. 1.1 Block diagram of off-line UPS system
The major bene its of this topology include simple design, low cost,
and small size of the converter. On the other hand, the lack of isolation
between the load and the grid voltage, no output voltage regulation,
long transfer time from the normal mode to the back-up mode, and the
poor performances are the main defects when the nonlinear load is
connected.
1.1.2 Line-Interactive UPS System

1.1.2.1 Traditional Line-Interactive UPS System
Figure 1.2 shows the typical topology of a line-interactive UPS system.
Normally, the line-interactive UPS is operated at medium-power rating
application. As is shown in the igure, it consists of a static bypass
switch, a series connected inductor, a bi-directional converter, and a
battery. When the grid voltage is normal, the grid power directly feeds
the load. Meanwhile, the battery can be charged through the bi-
directional converter, which plays the role of AC/DC converter. This
AC/DC converter can also have the active ilter capability to improve
the power factor of the load with the proper control strategy. In order
to have better regulation for the output voltage, a transformer may be
added at the expense of the bulky volume and expensive cost. On the
other hand, when the UPS system works in the back-up mode, the bi-
directional converter operates as a DC/AC inverter and supplies the
load with the power from the battery. The bypass switch disconnects
the grid to prevent the inverter’s back-feeding to the grid. The main
bene it of the line-interactive UPS system is the simple design
topology, leading to high reliability and low cost compared to the on-
line UPS system. In addition, the line-interactive UPS topology
possesses good performance in harmonic suppression from the grid
current, and the ef iciency is higher than the on-line UPS system.
Fig. 1.2 Block diagram of line-interactive UPS system

However, the lack of isolation between the load and the grid voltage
is the main disadvantage. Even the transformer embedded in the line-
interactive UPS system can solve this issue, but it will increase the cost
and the weight of the UPS system. Moreover, the grid voltage supplies
the load directly during the normal mode of operation, and this is not
possible to regulate the output voltage frequency.
1.1.2.2 Flexible Microgrid Based on Line-Interactive UPS

System
Recently, the lexible microgrid concept is proposed by parallel
connecting the UPS converters and combining the energy storage units,
such as PV and wind turbine. The difference between the lexible
microgrid from the traditional parallel UPS system lies in that the
lexible microgrid can be operated in grid-connected or islanded mode.
As is shown in Fig. 1.3, the microgrid includes small PV and wind
turbine generators, storage devices, and local critical loads with the
AC/DC and DC/AC power electronics converters. Conventionally, the
inverters have two different working modes: acting as a current source
when they connect to the grid or as a voltage source if they are
operated in islanded mode. However, with the lexible microgrid
topology and the proper control strategy, it is possible to achieve the
seamless transition between the grid-connecting mode and the
islanded mode.
Fig. 1.3 Block diagram of a lexible microgrid
1.1.3 On-line UPS System

The diagram of the on-line UPS system is depicted in Fig. 1.4, where it
consists of a recti ier, an inverter, a bypass switch, and a battery. Some
manufacturers include the DC/DC converter as well. The recti ier is
responsible for supplying the DC bus with the power. In addition, the
power rating of the recti ier needs to satisfy the 100% of the power
demanded by the load. When the grid voltage is not available, the
battery needs to provide the power at the back-up time. The duration
of the battery’s back-up time varies in different applications. Besides,
as the load power is always supplied via the inverter no matter if the
UPS system is operated in normal mode or back-up mode, there is no
transfer time associated with the transition between the normal mode
and the back-up mode. This is the main advantage of the on-line UPS
system. The bypass switch needs to be closed in case of overloading or
UPS malfunction. Typically, there are three operating modes with this
topology: normal mode, back-up mode, and bypass mode.
Fig. 1.4 Block diagram of on-line UPS system
In the normal mode of operation, the load power is continuously

provided through the combination of the recti ier and the inverter. This
topology is able to provide good line conditioning.
When the grid voltage is abnormal, the system shifts its operation
to the back-up mode. In this mode, the inverter and the battery
together maintain the power to the load. It should be pointed out that
when grid voltage returns to normal condition, a phase-locked loop
(PLL) should be applied to the UPS system to make the load voltage in
synchronization with the grid voltage. The bypass switch closes in case
of UPS overloading or UPS malfunction, such as overcurrent. It should
be noted that output voltage frequency should be the same as the grid
voltage frequency in order to make sure the seamless power transfer.
In general, the on-line UPS system is the most reliable UPS
con iguration due to its simplicity. Besides, the on-line UPS system
provides total isolation between input and output voltage amplitude
and frequency. Therefore, the high-quality voltage can be achieved.
However, typically, the ef iciency of the on-line UPS system is up to
94%, which is due to the double conversion. On-line UPS system is
usually adopted for the sensitive loads, and almost all the UPS systems
of over 5 kVA are on-line topology.
1.2 Modular UPS

The modular design concept of UPS appeared at later 1990s. Now the
modular UPS products can be found in many companies, such as ABB,
Delta, AEG power solutions, STATRON, etc.
The conventional centralized UPS system is mounted in a large
cabinet, which is very complicated for installation and maintenance
service. Concerning the power reliability of suppling critical loads,
there is usually one more of this large UPS cabinet for back-up system.
The system can be switched to the back-up UPS when the primary one
fails to provide power. Thus, it is dif icult to realize capacity expansion
for a centralized UPS system.
The modular UPS becomes popular for the ability of avoiding
interruption of operation during maintenance work or replacement.
With distributed control architecture, it conquers the drawback of
single point of failure of the centralized control and with less time-
consuming for maintenance and installation. Each module in the
system contains all the components that required for full operation
including the AC/DC and DC/AC converters, control board, display for
monitoring and control, static bypass switch, and battery back mode
transfer switch.
Normally, at least one extra power module will be mounted in a
modular UPS for redundancy beyond the power needed of the critical
loads. When any single module fails to feed power or otherwise needs
maintenance, it can be removed from the system, while the system
continues operations with full double conversion mode without
interruptions and no needs to transfer to bypass mode.
What is more, as the growth of the power needed for a critical load,
more power modules can be simply housed in the cabinet to reach the
rated power easily, with no need to change the entire system as the
conventional centralized system.
As a conclusion about the features and advantages of a modular
UPS, it has the features of easier installation, maximizing lexibility, and
reliability while reducing the cost of ownership, more availability
during maintenance or replacement of broken modules, it makes easier
to con igure the architecture of the system. Compared with the
conventional centralized UPS, the modular UPS has some advantages,
such as increasing the power capacity regardless of the rating limited
of switching devices, increasing the lexibility, reliability, and
maintainability of power supply systems.
Until now, there are two basic types of modular structures, as
shown in Fig. 1.5. Figure 1.5a shows only the DC/AC inverters are
modularized with one common AC/DC recti ier. In this structure, it is
more easier to control the system, as only one AC/DC recti ier needs to
be controlled. However, the power rating of the AC/DC recti ier has to
be able to support the whole system, and the battery’s capacity has to
be chosen to satisfy the whole power as well. In addition, the DC-link
voltage may suffer from large luctuation as the frequent plug-in or
plug-out of DC/AC modules inevitably increases the DC bus working
burden and affects the stable operation of DC bus. On the other hand,
Fig. 1.5b offers another option for the modular UPS system, and each
module has a small capacity and can work independently. However, in
this system structure, the bypass process is complicated.
Fig. 1.5 Two typical modular UPS structures. (a) Partial modular UPS system. (b) Total modular
UPS system
Overall, no matter which structure is selected, these two modular

UPS system structures have the common advantages. First, the
modular UPS system is highly reliable because of the redundancy. In
addition, it is easy to realize the solution of N+1 redundancy, where N
UPS modules supply the load and one additional unit remains in
reserve. Hence, modular UPS system is the user-friendly system
regarding the maintenance due to the N+1 redundancy. Finally, it is
easy to increase the capacity of the system and meet the requirements
of customers. And some redundant power modules can be put in a
modular UPS to ensure high availability, which is called N+X
con iguration. When one power module fails, a standby module can
take over the work to continue supply power to load. And the modular
concept makes it possible of fast design and manufacture of UPS with
speci ied rated power.
1.3 Organization of This Book

According to the preliminary introduction, this book would bring latest
research result on the system-level control and protection of the
modular on-line UPS system. This book can be divided into three parts.
The irst part is focused on the controls for the front-end recti ier of the
modular on-line UPS system, which is from Chaps. 2–3. The second part
presents the distributed control and protection of the modular on-line
UPS system that are included from Chaps. 6–8. And the third part
introduces the renewable-energy-based controls for modular on-line
UPS systems, which is from Chaps. 9–10. The overall structure of the
book is shown in Fig. 1.6.
Fig. 1.6 The overall structure of the book
Part I
Front-End Recti ier Control of the
Modular UPS System
https://doi.org/10.1007/978-3-031-22178-1_2
2. An RGPI Observer-Based Resonant

Super-Twisting Sliding Mode Control
Jinghang Lu1
Jinghang Lu
Keywords Disturbance rejection – Reduced-order generalized

proportional-integral observer – Sliding mode control – Three-phase
converter
2.1 Modeling of The AC/DC Converter

Figure 2.1 shows a typical grid-connected power converter system,
where a three-phase AC/DC converter is used to connect the grid to the
load. From Fig. 2.1, the L-type ilter is used as the output ilter of the
converter; r is the parasitic resistance of the ilter, and V DC is the DC-
link voltage. V t is the output voltage of the inverter, and V g is the grid
voltage at the Point of Common Coupling (PCC). By assuming a
balanced grid voltage, the system model in α − β reference frame is
expressed as
(2.1)
where V gα and V gβ indicate the grid voltage in the α − β reference
frame, V tα and V tβ are the output voltage of the converter, i α and i β are
the output current in the α − β reference frame, respectively.
Fig. 2.1 Con iguration of a grid-connected power converter
By balancing the injected power and the active power of the DC-link,
the DC-link voltage controller keeps the DC-link voltage constant. The
DC-link capacitor power balance in Fig. 2.1 can be expressed as follows:
(2.2)
where V DC is the DC-link voltage, C is the DC-link capacitance, P DC = V

DC I DC, which is equal to the recti ier AC side terminal power P t, P ext is
the external power that lows out of the DC capacitor. P loss is the power
loss in the converter circuit and expressed as ,Rp
represent the total switching loss of the system. Equation (2.2) stands
for the instantaneous power balance between the dc side and the AC
side of the three-phase AC/DC converter, on the left side of the Eq.
(2.2), meanwhile, in the right side of (2.2). When the AC side ilter
instantaneous power is ignored, the AC side terminal power P t equals
the grid side power P s. Given this fact, (2.1) can be written as
(2.3)
2.2 The Output Loop RGPIO-Based DC-Link
Voltage Controller Design
2.2.1 The Design of RGPIO
A reduced-order generalized proportional-integral observer (RGPIO) is
designed in this section to observe and actively cancel the lumped
disturbance caused by external disturbances and internal system
parameter variations.
The expression can be derived as follows by taking the Laplace
transfer function of both sides of (2.3):
(2.4)
where and P s are the system state and control input, respectively,
and P ext(s) is the system’s disturbance input.
By rearranging (2.2), the following expression is obtained:
(2.5)
where f total denotes the lumped disturbance, including the external

disturbance and the capacitance uncertainty ( ) and
other unmodeled disturbance, such as EMI of the DC-link capacitance.
These disturbances cannot be directly observed by the traditional PI
controller or a Luenberger observer; rather, in the following, the RGPIO
model will be used to model these disturbances.
DC-link state space modeling is expressed as follows for the full-
order GPIO design:
(2.6)
where , , u = P s,
, and
To enhance the accuracy of estimation and also to enable simpler
practical implementation, a new RGPIO is designed for DC-link voltage
control. Figure 2.2 shows that the control structure includes the outer
loop and inner loop control strategies. It is usually assumed that the
dynamic response of the current loop is much faster than that of the
voltage loop when designing the DC-link voltage control loop so as to
prevent dynamic interaction between the DC-link voltage control and
the inner loop current control [1], and thus the dynamic of the current
loop can be neglected when designing the DC-link voltage control loop.
Fig. 2.2 Reduced-order GPIO based block diagram of the dual-loop control structure for the
three-phase AC/DC converter
By rewriting (2.6), the following equations are derived:
(2.7)
(2.8)
Therefore, the RGPIO is designed as
(2.9)
where is the reduced-order GPIO gain, and z 2 andz 3 are the
estimated values of x 2 and x 3. In Eq. (2.9), the variable cannot be

directly measured, and hence, by manipulating into the left-
hand side of the equation, meanwhile, by adding and subtracting the

term , we derive the observer equations as follows:
(2.10)
Based on (2.10), it can be observed that signals f total and can

be observed by the proposed RGPIO. Nevertheless, cannot be
estimated by the ESO. It is true that RGPIO can estimate the derivative
of the lumped disturbances, while the ESO based observer cannot
achieve it. In addition, the RGPIO only has two orders, which reduces
the computational burden.
2.2.2 System Stability Analysis

The error equation of the proposed observer is obtained for stability
analysis by subtracting (2.7) from (2.9).
(2.11)
In (2.11), it can be observed that the system will be Hurwitz stable

if both of the roots of the characteristic polynomial in the matrix A e,
i.e.,
(2.12)
are in the left half-plane, and in order to simplify the design process, it
is assumed that the poles of the observer are both located at − ω 0 and
are expressed as
(2.13)
Therefore, β 1 = 2ω 0, . Equation (2.13) demonstrates that
the bandwidth of RGPIO (ω 0) is a function of the parameters k 1 and k 2.
Thus, choosing the appropriate bandwidth ω 0 is the key to success. By
considering the trade-off between the fast observation performance
and noise immunity, the observer’s bandwidth is normally set to be 5–
15 times larger than the DC-link voltage controller’s bandwidth [2]. The
bandwidth of the DC-Link voltage controller has been selected as 20
rad/s, while the bandwidth of RGPIO has been selected as 300 rad/s.
2.2.3 Frequency Domain Analysis for the RGPIO

By substituting z 2 − k 1 x 1 = ξ 2 and z 3 − k 2 x 1 = ξ 3, (2.10) is expressed
as
(2.14)
After replacing k 1 = 2ω 0 and into (2.14), the RGPIO is

constructed as
(2.15)
Equation (2.15) can be converted into transfer functions by taking

the following equation:
(2.16)
(2.17)
As z 2 − k 1 x 1 = ξ 2 and , k 1 = 2ω 0. Therefore, by combing

(2.11) and (2.12) and substituting z 2 − k 1 x 1 = ξ 2, the transfer function
of reduced-order GPIO is shown in Fig. 2.3. The modi ied model from u
0 to can be expressed as the transfer function :
(2.18)
Fig. 2.3 The equivalent transfer function of RGPIO in the DC-link voltage control
As a result of Eq. (2.18), within the RGPIO’s bandwidth ω 0, the

system transfer function is reduced to an integrator and is shown as
(2.19)
According to (2.19), the original plant is converted into an ideal

integrator within the range of ω 0 by incorporating the RGPIO into the
control strategy. It is noted that the modi ied plant returns to the
original plant beyond the bandwidth of ω 0.
2.2.4 Evaluation of the System Robustness Against

Parameter Variation
Dynamic performance and stability may be affected by the variation in
DC-link capacitance. Thus, the closed-loop poles of the system should
be evaluated to examine its robustness to variations in the capacitance
parameter. In this test, the nominal DC-link capacitance is set at 1100
μF. However, due to connections of the battery and UPS system in the
DC-link, the actual DC-link capacitance may vary from this value.
Therefore, when the actual capacitance changes from 1100 μF to 3300
μF, the poles’ location with the model is evaluated. It can be seen
from Fig. 2.4 that the closed-loop poles tend to move to the imaginary
axis when the DC-link capacitance increases, resulting in a more
unstable system. Even though the capacitance has been increased to
3300 μF, the dominant pole still has a distance from the imaginary axis,
so the system is still capable of providing satisfactory robustness.
Fig. 2.4 Pole’s movement when the DC-link capacitance value changes from 1100 to 3300 μF
2.2.5 DC-Link Voltage Controller

As demonstrated in the previous section, when the RGPIO is embedded
in the DC-link voltage control, the plant becomes an integrator (
), enabling the proportional controller to regulate the DC-
link voltage without steady-state error. Therefore, using the
approximated transfer function of the modi ied plant, the DC-link
voltage loop closed-loop transfer function is as follows:
(2.20)
Following the above discussion, it can be concluded that the

proposed RGPIOs are responsible for canceling lumped disturbances,
while a simple proportional controller is capable of tracking the voltage
reference without steady-state errors.
2.3 The Inner Loop RST-SMC Based Current

Tracking Design
The inner control loop is designed to ensure that the inductor’s
sinusoidal currents in the stationary frame i α and i β track the
reference currents and . Referencing currents are expressed as [3]
(2.21)
(2.22)
It is noted that the active power reference ( ) is generated from

the output of the DC-link voltage controller (see Fig. 2.2), and the
reactive power reference ( ) is set to the desired value.
2.3.1 Super-Twisting Control

As an inner loop controller, the SMC is typically used to achieve fast
current tracking. Although it has many bene its, the main disadvantage
of the traditional SMC is the chattering issue, which leads to a
discontinuous high switching frequency. Shtessel et al. [4] proposes an
ST-SMC to address this issue. The state trajectory of ST-SMC is a
second-order controller, and it shifts in a spiral pattern in the state
plane and converges asymptotically in inite time to the original state.
In general, consider a nonlinear controlled system
(2.23)
(2.24)
where is the stage vector, represents the control input,
σ(t, x) is the sliding variable, and and are the smooth
uncertain functions.
In the ST-SMC, the control goal is to force σ and its derivative to
zero. Hence, by differentiating the sliding variable σ(t, x) twice, the
following expression can be derived as
(2.25)
where and g(t, x, u) are bounded but unknown, and there
exist positive constant values Φ, Γm, ΓM, such that the following
conditions are satis ied:
(2.26)
(2.27)
Then, a differential inclusion can be expressed as
(2.28)
With the condition of (2.26) and (2.27), a differential inclusion is
obtained:
(2.29)
Thus, a control law based on a super-twisting algorithm (STA) can
be designed as
(2.30)
where λ and μ are the design parameters that can be determined by the
boundary conditions (2.26) and (2.27). To ensure that the sliding
variable σ can be converged to the sliding manifold in inite time, the
parameters can also be chosen as follows:
(2.31)
2.3.2 Current Tracking Loop

The ST-SMC must be designed in two steps in the current tracking loop.
The irst step is to choose a sliding surface that drives the system
states to zero. Second, we need to design a control law, which allows us
to keep the state of the system on the sliding surface at all times.
For the current control, the sliding surface equations are as follows:
(2.32)
(2.33)
A candidate Lyapunov function [4] is introduced to derive the
control law:
(2.34)
where σ αβ = [σ α σ β]T. The time derivative of the above Lyapunov

function is calculated as
(2.35)
According to Eqs. (2.1), (2.32), and (2.33), the time derivative of σ

αβ is expressed as
(2.36)
Therefore, as long as choosing an appropriate positive value of A

and B in Eq. (2.37), the following ST-SMC in Eq. (2.37) makes sure
. Hence, the system stability is guaranteed
(2.37)
In addition, in order to reject grid voltage disturbance and achieve

zero steady-state reference tracking, the resonant term is added
in (2.37), and the inal designed RST-SMC strategy is shown in (2.38)
and (2.39) in Laplace domain:
(2.38)
(2.39)
where parameters A and B are selected according to Eqs. (2.28)–(2.30).

In addition, by assuming the Γm = ΓM, the parameters for A and B are
selected as , B > M, where M is the upper bound of the
grid voltage amplitude. Parameter C is designed based on the resonant
controller’s design principle, and a simple method to determine the
parameter C is angular frequency squared times inductance [5].
Therefore, (2.38) and (2.39) describe the dynamic behavior of RST-
SMC, the system disturbance is rejected by the resonant term, and the
output current can only follow the reference AC current by ST-SMC in
the sliding surface with maximum stability.
A block diagram of the proposed RST-SMC strategy is shown in Fig.
2.5. And the full control diagram, including the proposed RGPIO-based
control and RST-SMC strategy, is shown in Fig. 2.6. For DC-link voltage
regulation, the RGPIO-based proportional controller is used to achieve
both DC-link voltage regulation and load disturbance rejection; for fast
current regulation, the inner loop RST-SMC strategy is utilized.
Fig. 2.5 Block diagram of the details of proposed RST-SMC

Fig. 2.6 Schematic diagram of the RGPIO-based RST-SMC strategy for the three-phase AC/DC
converter
The performance of the current controller is affected by the

variation in system parameters. As a result, (2.36) is written as
(2.40)
where ΔL represents the inductance’s parameter variation. In addition,

if the positive control gains for A and B are large enough, and the grid
voltage disturbances are rejected and canceled, the system stability
can be achieved as well and expressed as
(2.41)
where , and is expressed in Eq. (2.42):
(2.42)
2.4 Simulation Results

In this section, simulation results are provided for the proposed
control strategy and the standard control strategy. This chapter adopts
PI control strategy for DC-link voltage regulation and proportional
resonant (PR) control strategy for inner current regulation as standard
control strategy. The simulations are performed using Matlab/Simulink
and the AC/DC converter con iguration shown in Fig. 2.1. Table 2.1
gives the converter’s control parameters as well as its electric
parameters.
Table 2.1 System parameters
Parameter Value
Filter inductor L 1.8 mH
DC-link voltage 400 V
Inductor’s parasitic resistance 0.04 Ω
Grid RMS voltage 120 V
Sampling frequency f s 10 kHz
DC-link capacitance 1100 μF
Parameter A 35
Parameter B 10,000
Parameter C 500
Proportional gain (PR for comparison) 35
Resonant controller (PR for comparison) 1000
Parameter Value
Proportional gain (DC-link with PI) 0.2
Integral gain (DC-link with PI) 1
Proportional gain (RGPIO) 20
2.4.1 Operation Under Load Resistance Variation

Figure 2.7 illustrates the simulation results for the proposed control
strategy and for the PI control strategy by adjusting the sharp load
resistance from 1500 to 150 Ω. In order to have an accurate
comparison, both controllers must have the same bandwidth. It can be
observed that although the PI control strategy can recover to the
original voltage within 1s, it takes longer time than the proposed
control strategy. The undershoot with the proposed control strategy is
30 V. In contrast, 60 V of undershoot is observed with the PI control
strategy. Furthermore, with the proposed control strategy, the
transient current on the grid side exhibits a faster response time.
Fig. 2.7 Transient response of DC-link voltage and phase current. (a) DC-link voltage and phase
current with PI control strategy and (b) DC-link voltage and phase current with the proposed
control strategy
2.4.2 Operation with Current Command Step

The second simulation evaluates the current control strategy’s ability
to provide a desired amount of reactive power. The reactive power
command step is introduced from 0 to 1.6kVar. We evaluate both the PR
control strategy and the RST-SMC strategy’s response to the system.
Figure 2.8a shows that the current in frame has an overshoot of 3A
when the reactive power step changes. On the contrary, Fig. 2.8b shows
the current response when the same amount of the reactive power step
changes, and it is observed that the current almost does not cause
overshoot with the proposed control strategy.
Fig. 2.8 Transient response of the grid current in α − β frame with the reactive power step
change. (a) Grid current with standard PR control strategy and (b) grid current with the proposed
control strategy
2.5 Experimental Results

In order to verify the effectiveness of the proposed control strategy, an
AC/DC converter illustrated in Fig. 2.1 is built up in Fig. 2.9. The system
parameters are listed in Table 2.1. The sampling frequency is chosen to
be 10 kHz, the comparative experimental results are provided from the
standard control strategy (outer loop PI control with inner loop PR
control strategy) and the proposed control strategy, and these control
strategies are both controlled by dSPACE 1006 controller for
comparison. The experimental results are shown in Figs. 2.10, 2.11,
2.12 and 2.13 for both the standard method and the proposed control
strategy.
Fig. 2.9 Experimental setup

Fig. 2.10 Experimental results of the load variation. (a) DC-link voltage with PI control, (b) DC-
link voltage with proposed control strategy, and (c) phase A current with PI control; (d) phase A
current with the proposed control strategy
Fig. 2.11 Experimental results for the DC-link voltage reference increase. (a) DC-link voltage
with PI control, (b) DC-link voltage with the proposed control strategy, (c) active power with PI
control, and (d) active power with the proposed control strategy
Fig. 2.12 Experimental results for the transient response with reactive power step up. (a) d-axis
current with the standard control strategy, (b) d-axis current with the proposed control strategy,
(c) q-axis current with the standard control strategy, and (d) q-axis current with the proposed
control strategy
Fig. 2.13 Experimental results of the steady-state current with reactive power command. (a)
Current waveform for the PR control strategy, (b) current waveform for the proposed control
strategy, (c) spectrum of the current with PR control strategy, and (d) spectrum of the current
with the proposed control strategy
2.5.1 Dynamic Performance Under Load Step Change
Figure 2.10 shows the dynamic behavior of the standard PI control
strategy and the proposed control strategy with a sudden change in
external load from light load (1500 Ω) to full load (150 Ω). To avoid the
interaction of the voltage loop with the current loop and avoid stability
issues, the voltage loop of the DC-link control is typically 0.05–0.2
times the bandwidth of the current loop. Current loops are usually
chosen to be 0.1 times as wide as the sampling frequency. Thus, the
voltage loop is usually selected to be 0.005–0.02 times the sampling
frequency. It should be noted that a very fast DC-link voltage is not
needed, since the DC-link capacitor is generally large, and consequently,
the DC-bus voltage cannot be changed rapidly. The bandwidth is the
same for both DC-link voltage controllers, so a fair comparison can be
made, and both control laws can achieve DC-link voltage regulation.
However, their dynamic performances are quite different. Speci ically,
it is shown that with the PI control strategy, the DC-link voltage
undershoots by 60 V, and it takes around 1s to track the reference
voltage after the load is varied. With the proposed control strategy, the
RGPIO actively cancels the disturbance caused by the load variation,
resulting in a DC-link voltage dip of only 30 V and a recovery time of 0.4
s. Figure 2.10c and d shows the phase A output current with the load
variation. Compared to the PI control strategy, current with the
proposed control strategy has a faster speed. Furthermore, the PI
control strategy in the experiment works in the operating point, which
does not lead to the windup phenomenon in the system. In the event
that the system is overloaded by the proportional controller, the
proposed control strategy will not lead to a windup phenomenon. On
the contrary, the PI control strategy needs to add an anti-windup
algorithm to prevent the windup [5, 6].
2.5.2 Dynamic Performance Under DC-Link Voltage

Increase
Comparisons are made between the dynamic performance of the
standard and the proposed control strategies and the DC-link voltage
demand variations. Figure 2.11 shows the comparison results. Both
methods are capable of regulating the DC-link voltage to the settling
point. In this case, the DC-link voltage changes from 400 to 420 V, and
the new steady state is reached after 0.6 s in the PI control strategy. In
contrast, it takes only 0.3 s to reach the same steady-state operating
point, where response time is cut in half. Despite the fact that the
proposed controller could achieve a faster dynamic response, the
overshoot of active power reference in the proposed control strategy is
greater than in the PI strategy, but the settling time of active power
reference is shorter in the proposed strategy than in the PI strategy.
2.5.3 Current Loop Performance with Current Reference

Step Change
A comparison between the current PR control strategy and the
proposed PR control strategy is used to verify the proposed current
control strategy. The currents are transformed from the α − β frame to
the d − q frame to observe the differences between these two control
strategies. As illustrated in Fig. 2.12a, when the reference current is
changed from 0 to 8 A, the q-axis current overshoots by 2 A and the
settling time is 5 ms; meanwhile, the d-axis current overshoots by 1.7 A
due to this step change. However, the proposed control method
overshoots by 1 A with the settling time of 2 ms (see Fig. 2.12b). At the
same time, the coupling in luence of the proposed control strategy is
similar to that of PR. It is noted that excessive loading may cause the
output of the current controller to become saturated. There are several
ways to prevent the windup; one straightforward method is known as
back calculation [7].
2.5.4 THD of the Current at the Steady State

Figure 2.13 compares the steady-state current with the reactive power
command. Compared with the PR control strategy, the proposed
current control strategy has better performance, especially the 5th and
7th harmonics. Moreover, the current THD of the RGPIO-RST-SMC
strategy is 1.3%, while the standard one is 1.6%.
2.6 Conclusion
A three-phase AC/DC converter was proposed using an RGPIO-based
RST-SMC strategy in this chapter. Compared with the conventional
control strategy, the system’s dynamic response under the disturbance
was greatly improved, and the settling time was reduced by employing
the proposed RGPIO-based control strategy. Under the uncertainty of
system parameters, RST-SMC was proposed as a current control
strategy for tracking in an α − β frame. The experimental results
demonstrated the effectiveness of the proposed control strategy
compared to the standard control strategy.
References
1. A. Yazdani, R. Iravani, An accurate model for the DC-side voltage control of the neutral point
diode clamped converter. IEEE Trans. Power Delivery 21(1), 185–193 (2006)
[Crossref]
2. J.D.P.G.F. Franklin, M. Workman, Digital Control of Dynamic System (Addison Wesley Longman,
Boston, 1998)
3. R.I. Amirnaser Yazdani, Voltage-Sourced Converters in Power Systems : Modeling, Control, and
Applications (Wiley, Hoboken, 2010)
[Crossref]
4. C.E.Y. Shtessel, L. Fridman, A. Levant, Sliding Mode Control and Observation (Springer, New
York, 2014)
[Crossref]
5. S. Kamran, H. Lennart, N. Hans-Peter, N. Staffan, T. Remus, Design, Control and Application of

Modular Multilevel Converters for HVDC Transmission Systems (Wiley-IEEE Press, Hoboken,
2016), p. 416
6. F.D. Bosio, L.A.D.S. Ribeiro, F.D. Freijedo, M. Pastorelli, J.M. Guerrero, Discrete-time domain
modeling of voltage source inverters in standalone applications: enhancement of regulators
performance by means of smith predictor. IEEE Trans. Power Electron. 32(10), 8100–8114
(2017)
[Crossref]
7. L. Harnefors, K. Pietilainen, L. Gertmar, Torque-maximizing ield-weakening control: design,

analysis, and parameter selection. IEEE Trans. Ind. Electron. 48(1), 161–168 (2001)
[Crossref]
https://doi.org/10.1007/978-3-031-22178-1_3
3. An ESO for DC-Link Voltage Control of

Three-Phase AC/DC Converters
Jinghang Lu1
Jinghang Lu
Keywords DC-link voltage – Disturbance rejection – Enhanced state

observer – Robustness – Voltage control
3.1 ESO-Based DC-Link Voltage Control

Strategy
3.1.1 DC-Link Modeling
Figure 3.1 illustrates the power circuit of a three-phase AC∕DC
converter with DC-link voltage control based on ESO. The DC-link
voltage controller keeps the DC-link voltage constant by balancing
injected active power and output active power. Accordingly, the DC-
link’s power balance shown in Fig. 3.1 can be represented as
Fig. 3.1 Schematic diagram of the three-phase AC/DC converter with the proposed ESO-based
DC-link voltage control strategy
(3.1)
where V DC is the DC-link voltage, C is the DC-link capacitance, P DC = V

DC I DC, which is equal to the recti ier AC side terminal power P t. P ext is
the external power that lows out of the DC capacitor. R p represents the
total switching loss of the system. If the instantaneous power of AC
side ilter is not considered, the AC side terminal power P t is equal to
the grid side power P S. Considering this fact, (3.1) can be rewritten as
(3.2)
Taking the Laplace transform of both sides of (3.2) results in
(3.3)
where and P S are the system output and control input,

respectively, and P ext acts like a disturbance input.
3.1.2 Enhanced State Observer Design

Figure 3.2 shows a dual-loop control strategy for a three-phase AC/DC
converter. It consists of an inner current loop for regulating the
converter output current, as well as an outer voltage loop for
controlling the DC-link voltage. It is often considered that the
bandwidth of the inner loop should be much larger than that of the
outer loop, in order to avoid a dynamic interaction between them [1]. It
implies that, during the DC-link controller design, the dynamic of the
current regulation loop can be neglected and assume that P, where P S
and are reference and output active powers (see Fig. 3.2). DC-
link design can be simpli ied using this approximation without
affecting accuracy too much.
Fig. 3.2 Block diagram of dual-loop control diagram for the three-phase AC/DC converter
Figure 3.2 shows a DC-link controller with an ESO for
detecting/compensating system disturbances/uncertainties and a
simple proportional gain for regulating its voltage [2, 3]. The irst step
is to present the ESO analysis and design.
By applying some simple mathematical manipulations, (3.2) can be
rewritten as
(3.4)
where denotes the total disturbance that

includes the external disturbance and internally dynamic
variation ( )
In (3.4), is considered as a state variable and expressed as
, f total is considered as an augmented state variable
is the
system input and indicated as u = P s. is the coef icient of input.
Moreover, the time derivative of x 2 is signi ied h, and the expression is
shown as . Therefore, from the aforementioned analysis, the
state-space model is derived as
(3.5)
Based on (3.5), the ESO is constructed as
(3.6)
where z 1 and z 2 are the estimated values of the x 1 and x 2, and
is the gain vector of ESO which is designed using the pole placement
method in the next section.
3.1.3 Parameter Tuning and Stability Analysis

By subtracting (3.6) from (3.5), the error equation can be written as
(3.7)
From (3.7), it is known that the matrix A e will be Hurwitz stable, if

all the roots of characteristic polynomial of A e, i.e.,
(3.8)
are in the left half-plane. Suppose the ESO’s poles are all designed to be
located at − ω 0, which is expressed as
(3.9)
Therefore, β 1 = 2ω 0 and . (3.9) shows that the design of the
ESO can be simpli ied by tuning (ω 0) the bandwidth, which simpli ies
the whole design process. The selection of ω 0 has a signi icant impact
on the system’s performance. To ensure that the estimated state
dynamics have a fast tracking performance even when the actual state
dynamics vary, the observer’s bandwidth is typically chosen to be 5–15
times the DC-link voltage controller’s bandwidth. A large bandwidth for
ESO is not recommended, as this reduces noise immunity. Thus,
choosing the ESO’s bandwidth involves balancing speed of response
and noise immunity. To ensure that the ESO does not affect the current
controller’s performance, the bandwidth of ESO should also be
decoupled from that of the current controller. Based on the discussion
in this chapter, the current loop’s bandwidth is chosen to be 3000 rad/s
to achieve a quick dynamic response. A bandwidth (ω 0) of 300 rad/s is
chosen for the ESO, and a bandwidth of 20 rad/s is chosen for the DC-
link voltage controller. In this way, all of the three loops are decoupled
from one another; meanwhile, the ESO has a high dynamic response for
estimating the actual state.
3.1.4 Frequency Domain Analysis for ESO

By substituting β 1 = 2ω 0 and into (3.6), the ESO is described
as
(3.10)
Equation (3.10) is corresponding in the Laplace domain to (Fig. 3.3)
(3.11)
(3.12)
Fig. 3.3 The equivalent transfer function of ESO
By combing (3.11) and (3.12), the transfer function of ESO can be

expressed as
(3.13)
The modi ied model from the output of the controller to

can be expressed as the transfer function :
(3.14)
where is the output of the controller. It is
observed from (3.14) that within the ESO’s bandwidth ω 0, the system
transfer function is reduced to an ideal integrator and expressed as
(3.15)
On the contrary, at high frequencies, i.e., frequencies that exceed the

ESO’s bandwidth, the modi ied plant is expressed as
(3.16)
From (3.15) and (3.16), it is determined that the modi ied plant is
an ideal integrator without total disturbance in the ESO bandwidth.
While the modi ied plant follows the original plant’s response at high
frequencies, it does not change the response at low frequencies. In
addition, ω 0 is found to have a signi icant in luence on the shape of the
plant. So, the bandwidth ω 0 of ESO will be explored to examine the
pole’s location of . The movements of the poles of in (3.14) are
shown in the root loci plot in Fig. 3.4 with the system parameters in 3.1.
When the ESO’s bandwidth increases from 20 rad/s to 300 rad/s, two
poles caused by the ESO are moving further to the left in inity, and one
pole is at the origin. In our system design, the ESO’s bandwidth is
selected as 300 rad/s, and the closed-loop bandwidth of DC-link
controller is chosen as 20 rad/s. As the bandwidth of ESO (ω 0 =
300 rad/s) is 15 times of voltage closed-loop bandwidth 20 rad/s, two
poles caused by ESO are quite far away from the dominant pole. As a
result, the modi ied can be considered as an integrator and
expressed as , which corresponds to the analysis for (3.14).
Fig. 3.4 Root loci plot of the plant as ω 0 increases
Table 3.1 System and controller parameters
Parameter Value
Filter inductor L f 1.8 mH

Switching loss R p 1000 Ω
Normal DC-link capacitor 0.011 F

DC load 230 Ω
Converter rating 1.1 kVa
Phase-to-phase RMS voltage 4.4 A
Peak phase current 208 V
Bandwidth of ESO (for control) 300 rad/s
Current controller k pi (for control) 9.5
DC-link controller k p (for control) 20
Current controller k pr (for control) 200

DC-link proportional controller (comparative study) 0.02
Parameter Value
DC-link integral controller (comparative study) 0.1
3.1.5 System Robustness Assessment

The system performance and stability are affected by the DC-link
capacitance variations. Therefore, the closed-loop poles of need to
be examined to ensure the system robustness when the DC-link
capacitance varies. In our system, the normal capacitance is selected to
be 0.011 F, and the root loci of the modi ied model with the actual
capacitance ranged from 0.011 F to 0.033 F is shown in Fig. 3.5. It is
observed from Fig. 3.5 that with the increase of capacitance, one pole
moves toward the imaginary axis, and the system tends to become
more oscillatory with a reduced damping. But the system still has a
good robustness even the capacitance has reached 0.033 F, as this pole
is still far away from the imaginary axis.
Fig. 3.5 Root loci of the system with the capacitance change from 0.011 F to 0.033 F
3.1.6 Controller Design

As the ESO is employed for the DC-link voltage regulation, the modi ied
plant is reduced to an integrator . The result implies that a
simple proportional controller can ensure zero steady-state errors. It is
for this reason that a proportional gain was chosen for regulating the
DC-link voltage [4]. If the approximate transfer function for the
modi ied plant is considered, the closed-loop transfer function of the
DC-link control loop can be approximated as follows:
(3.17)
In this chapter, as mentioned before, the closed-loop bandwidth is

chosen to be 20 rad/s, which is corresponding to k p = 20.

As shown in Fig. 3.6, an AC/DC converter is constructed to demonstrate
the ef icacy of the ESO-based DC-link voltage control method. 208 V
phase-to-phase programmable AC grid simulator is connected to the
converter with a rated capacity of 1.1 kVA. The DC-link voltage is
maintained at 500 V. The inner loop current is tracked using a PR
controller. In Table 3.1, we list the parameters of the PR and ESO-based
DC-link voltage controllers. The dSPACE 1006 platform controls the
AC/DC converter. Throughout the experimental studies, the sampling
frequency f s is 10 kHz. A comparison between the feedforward-based
DC-link voltage controller, the traditional PI-based controller, and the
proposed technique with the same closed-loop bandwidth is
performed to illustrate the effectiveness of the proposed method. Table
3.1 shows the system parameters for the experimental results.
Fig. 3.6 Con iguration of setup
3.2.1 Test 1
In this test, the DC-link capacitance is 0.011 F; the disturbance is
generated by connecting a 230 Ω resistor in the DC-link to examine the
controller’s performance from no load to full load operating point. The
DC-link voltage performance under the traditional PI control strategy,
feedforward-based PI control strategy, and the proposed control
strategy is compared in Fig. 3.7. The traditional PI control technique
has the worst performance, and the proposed sensor-less controller
and the sensor-based PI feedforward controller have similar
performance. To be more exact from Fig. 3.8, the traditional PI control
method has a peak undershoot of 60 V and a settling time of 0.8 s, while
the proposed controller has an undershoot of 30 V and a response time
of 0.3 s. The overshoot in the feedforward-based PI control approach is
the same as the proposed controller. However, the dynamic response is
a little faster than the proposed control strategy.
Fig. 3.7 Comparative study of the PI control strategy, PI with feedforward control strategy, and
proposed ESO-based control strategy when the DC-link capacitor is 0.011 F
Fig. 3.8 Comparison of DC-link voltage performance in test 1 with the traditional PI controller, PI
with feedforward controller, and proposed control strategy
3.2.2 Test 2
Compared to test 1, the DC-link capacitance has increased to 0.022 F to
examine the controller’s performance under 100% increase of DC-link
capacitance. The control parameters are identical to test 1. The
experimental results are shown in Fig. 3.9 for the traditional PI control
strategy, the feedforward-based PI control strategy, and the proposed
control strategy [5]. Both test 1 and test 2 yield the same conclusions.
In terms of setting time and disturbance rejection, the traditional PI
controller performs poorly. A forward-based PI controller and the
proposed control strategy have similar performance. Speci ically, in
Fig. 3.10, all three of these control strategies are better at rejection
disturbances. While the traditional PI method has an undershoot of 50
V and the settling time is still 0.8 s, the proposed method has an
undershoot of 20V and 0.3 s of settling time. As with the proposed
controller, the feedforward-based PI controller also undershoots, while
the settling time is 0.4 s.
Fig. 3.9 Comparative study of the PI control strategy, PI with feedforward control strategy, and
proposed ESO-based control strategy when the DC-link capacitor is 0.022 F
Fig. 3.10 Comparison of DC-link voltage performance in test 2 with the traditional PI controller,
PI with feedforward controller, and proposed ESO-based controller
The ESO-based DC-link voltage control strategy is shown to be

robust to deal with the system parameter variation and to have a fast
dynamic response for estimating the total disturbance. Furthermore,
as the chapter shows, the estimation of and compensation for the
disturbance are strongly in luenced by an observer’s bandwidth. To
separate the current loop, observer, and voltage loop bandwidths, the
switching frequency and sampling frequency may be decreased from
10 kHz to 3–5 kHz in high-power converters and the observer’s
bandwidth as well. To increase its dynamic response, the observer has
to use prediction methods such as the Smith Predictor.
3.3 Conclusion
Using an ESO-based DC-link voltage control strategy, a simple three-
phase AC/DC converter control strategy is presented. As a result of the
proposed control strategy, additional sensors were not required for
optimizing dynamic response to disturbances, making it possible to
expand UPS modules and microgrids via plug and play. DC-link voltage
controllers based on ESOs can mitigate the DC-link voltage variation as
sensor-based feedforward controllers, but they have a greater effect on
reducing the settling time. In the experiment, the robustness of the
controller was also examined. Experimental results con irmed the
effectiveness of the proposed control strategy.
References
1. R.I.A. Yazdani, Voltage-Sourced Converters in Power Systems: Modeling, Control, and
Applications (Wiley, Hoboken, 2010)
[Crossref]
2. G. Zhiqiang, Scaling and bandwidth-parameterization based controller tuning, in Proceedings of

the American Control Conference, vol. 6 (2003), pp. 4989–4996
3. Z. Song, C. Xia, T. Liu, Predictive current control of three-phase grid-connected converters with
constant switching frequency for wind energy systems. IEEE Trans. Ind. Electron. 60(6),
2451–2464 (2013)
[Crossref]
4. J.D.P.G.F. Franklin, M. Workman, Digital Control of Dynamic System (Addison Wesley Longman
Inc., Boston, 1998)
5. A. Timbus, M. Liserre, R. Teodorescu, P. Rodriguez, F. Blaabjerg, Evaluation of current

controllers for distributed power generation systems. IEEE Trans. Power Electron. 24(3),
654–664 (2009)
[Crossref]
Part II
Distributed Control and Protection of
the Modular UPS System
https://doi.org/10.1007/978-3-031-22178-1_4
4. Distributed Adaptive Virtual

Impedance Control for Parallel-
Connected Voltage Source Inverters in
Modular UPS System
Baoze Wei1
(1) Aalborg University, Aalborg, Denmark
Baoze Wei
Email: bao@energy.aau.dk
Keywords Droop control – Adaptive virtual impedance – Modular

uninterruptible power supply system – Power sharing – Circulating
current
4.1 Basic Droop Control Strategy

An overview of the droop and virtual impedance framework is
presented in this section. This is one of the most popular ways of
controlling the paralleling UPS inverters [1–9]. Every UPS inverter
serves as a power supply. As depicted in Fig. 4.1, a voltage source
inverter (VSI) connected to an AC bus can be used to analyze the
conventional approach. Thus, the power that the VSI injects onto the AC
bus is given as follows [10, 11]:
(4.1)
(4.2)
where E and V pcc are the amplitude of the inverter output voltage and
the AC bus voltage, φ is the power angle of the inverter, and Z and θ
represent the amplitude and the phase of the output impedance. A
large ilter inductor connected to the AC bus typically produces a highly
inductive output impedance, which is traditionally assumed to be high.
In this case, assuming that the output impedance is purely inductive (θ
= 90∘ ), the active and reactive power expressions can be simpli ied as
(4.3)
(4.4)
Fig. 4.1 Equivalent circuit of a VSI connected to an AC bus
The output impedance of the closed-loop inverter determines the

droop control strategy [12]. Normally, the power angle φ is very small (
, ), then the active power P is mainly related to φ,
and the reactive power Q is mainly in luenced by the voltage error (E −
V pcc) [3, 12]. Thus, the conventional droop scheme P − ω and Q − V is
often used, so that the voltage and frequency droop functions are given
as [5, 13]
(4.5)
(4.6)
in which ω ∗ and E ∗ represent the frequency and voltage amplitude
references, and m p and m q are the droop coef icients [5, 13, 14].
Similarly, for a highly resistive output impedance (θ = 0∘), the active
and reactive power can be calculated as
(4.7)
(4.8)
Different from the conventional droop, the droop function should be

modi ied as [5, 14, 15]
(4.9)
(4.10)
The active power can be controlled by the output-voltage amplitude
of the inverter, while the reactive power can be controlled by the
frequency of the inverter—this is the opposite strategy of conventional
droop, so it is called reverse droop. [5, 16–18], and [19] discuss in
greater detail the choice of droop function and the analysis of output
impedance.
A highly inductive output impedance is required to decouple the
in luence of P and Q from frequency and voltage amplitude in the
conventional droop control scheme, since the output impedance
in luences the choice of the droop function [5, 13]. Commonly, the LCL
ilter will be interconnected with the inverter. The output impedance
can be adjusted by adding virtual impedance. Due to the similarity in
operation between three-phase and single-phase inverters, Fig. 4.2 can
be simpli ied to represent parallel three-phase inverters considering
the output impedances.
Fig. 4.2 Equivalent circuit of two parallel inverters

In Fig. 4.2, Z 1 and Z 2 are the output impedances of the two parallel
inverters, respectively, Z L is the load impedance, E 1 and E 2 are the
output voltages of the two inverters, I 1 and I 2 are the output currents,
E o is the common as bus voltage, and Io is the load current. In a
practical system, Z 1 and Z 2 will be unbalanced because of the different
values of ilters and line impedances or stray parameters. According to
literature [20], the circulating current can be de ined as
(4.11)
As shown in Fig. 4.2, the following equations can be written:
(4.12)
(4.13)
Assuming that the output impedances of the parallel inverters are

equal to each other, Z 1 = Z 2 = Z, then, substituting (4.12)–(4.13) into
(4.11) gives us
(4.14)
Based on the former analysis, if the output voltages and the output
impedances of the parallel inverters are equal to each other,
respectively, the circulating current can be eliminated to obtain the
target of average power sharing. The equivalent circuit of two parallel-
connected inverters with virtual impedances is shown in Fig. 4.3, and Z
vir1 and Z vir2 are the virtual impedances.
(4.15)
Fig. 4.3 Equivalent circuit of two parallel inverters with virtual impedances
Equation (4.15) depicts the virtual impedance for the k th inverter

in a system. The virtual impedance can be purely resistive, inductive,
or a combination of two of them based on the output impedance
differences between parallel inverters.
4.2 Stability Analysis and Stabilization

Methods
4.2.1 The Proposed DAVIC Method
LC ilters are applied instead of LCL ilters in the UPS project discussed
in this section, so the line impedance is mainly resistive in the low
voltage line. As a consequence, a virtual resistance impedance is
selected in order to avoid the reverse droop (4.9)–(4.10) is
implemented. To improve the accuracy of active power sharing
between parallel converter modules, an adaptive virtual impedance
control is proposed, which is implementable by using a distributed
control concept, as illustrated in Fig. 4.4. The adaptive virtual
impedance is calculated by dividing the active power of each power
module by the total voltage across the UPS. is the preset
virtual impedance, and is the adaptive virtual impedance. And
the total virtual impedance for a per power module is
.
Fig. 4.4 Control scheme for a number n modules in a modular UPS system
Assuming that there are a number of n power modules that operate

in parallel in a modular UPS, the control scheme considering the
adaptive virtual impedance control is shown in Fig. 4.4. The calculation
of the adaptive virtual impedance can be expressed as
(4.16)
The local active power will be compared with the

average active power P av, of the paralleled modules in the UPS. Then,
through the PI controller, the adaptive virtual impedance
is obtained. The reason of P i in the position of
minuend is that suppose that P i is higher than the average active
power of the parallel-connected modules, it means that the virtual
impedance of the i th module should increase to reduce the output
power of P i. In Fig. 4.4, will be positive through the
calculation using (4.16), so the inal total virtual impedance of ith
module will increase. The proposed adaptive virtual impedance control
diagram is shown in Fig. 4.5.
Fig. 4.5 The block diagram of the control structure with the adaptive virtual impedance control
4.2.2 The Design of the Control Parameters of the

Adaptive Virtual Impedance Loop
To give a design guideline of the parameters of the adaptive virtual
impedance control, a simple model considering two parallel-connected
inverters is built, which is shown in Fig. 4.6. R D1 and R D2 represent the
virtual impedance, which consist of the adaptive virtual impedance. R
line1 and R line2 represent the line impedances, and only resistive line
impedance is considered since it is mainly resistive in low voltage line
[18, 19].
Fig. 4.6 Equivalent circuit when two inverters connected in parallel
Based on Fig. 4.6, when considering both of the adaptive virtual

impedance and the line impedance, (4.12) and (4.13) will be changed
as
(4.17)
(4.18)
If I 1 = I 2, the following is obtained:
(4.19)
(4.20)
We consider R pre1 and R line1 as one parameter R l1 and R pre2 and R

line2 as R l2, (E 1 − E o) and (E 2 − E o) are represented by δ E1, δ E2,
respectively, and δ P1 and δ P2 are used to substitute (P 1 − P av) and (P 2
− P av). Then, (4.20) will be rewritten as
(4.21)
From (4.21), the following relationship will be obtained:

(4.22)
(4.23)
To simplify the design, only proportional control is considered
irstly and R l1 = R l2 = 0 in ideal condition. Thus, (4.22) will be rewritten
as
(4.24)
Thus, with (4.25), K Padp can be calculated, in which V ref represents the
reference voltage, η is a number of percentage, which represents the
maximum difference between the real output voltage and the reference
voltage that allowed for safety running of the system, and is the
maximum power of each power module.
(4.25)
As mentioned in the previous section, the maximum allowed in the

modular UPS project is 2%. In the simulation, each module has a
maximum active power of 10 kW. As a result, for each phase, can
be calculated as 0.00138. Normally, a low-pass ilter, , is
implemented with the power calculation, in which ω f is the cutoff
frequency that is normally smaller than a decade of the fundamental
frequency. Based on the experience relationship between proportional
and integral parameter, K Iadp equals , where τ is a time constant,
and here it mainly comes from the low pass ilter. In this chapter, the
cutoff frequency is selected as 2 Hz, and then K Iadp will be obtained as
(4.26)
Thus, with (4.25) and (4.26), we can calculate the approximate control
parameters for the proposed DAVIC. It should be noticed that
optimized parameters will be obtained further based on the simulation
and experiments. The control parameters are shown in Table 4.1, and it
can be seen that the optimized parameters for the DAVIC are close to
the calculated values.
Table 4.1 Electrical and control parameters in simulations and experiments
Coef icient Parameter Value
Voltage reference (RMS) V ref 230 V/50 Hz
Filter inductor L 200 μH
Filter capacitor C 60 μF
Equivalent resistor of ilter inductor at 50 Hz rL 0.0628 Ω
Voltage proportional controller K PV 0.8 A/V
Voltage resonant controller K RV 1000 As/V
Current proportional controller K PI 1.25 V/A
Current resonant controller K RI 600 Vs/A

Preset virtual impedance RD 0.5 Ω
Active power droop coef icient mP 0.00005 V/W

Reactive power droop coef icient mQ 0.00001 Hz/Var
Proportional controller of DAVIC K Padp 0.002 V/W

Integral controller of DAVIC K Iadp 0.004 V/Ws
Proportional controller of the secondary control K Psec 0.01

Integral controller of the secondary control K Isec 3.2
Total load power in the simulation – 20 kW

Total load power in the experiment – 24.75 kW
Digital controller – TMS320F28377D
Normal communication cycle for data exchange between power T c 20 ms
modules
4.2.3 The Selection of Virtual Impedance and the Stability

Analysis
The choice of the virtual impedance must be analyzed using the
proposed DAVIC method, since the output impedance affects the droop
characteristic. The controller will set a maximum virtual impedance to
ensure the stability of the system. In Fig. 4.7, a linear model for voltage
and current control loops without virtual impedance is depicted. G [V ]
(s) and G [I](s) represent the voltage and current controllers,
respectively. De ine the voltage and current controllers as
(4.27)
Fig. 4.7 Linear model of voltage and current control loops with virtual impedance
(4.28)
From Fig. 4.7, the closes-loop transfer function of the conventional

voltage and current control without the virtual impedance loop can be
derived as
(4.29)
In which, Z 0(s) represents the output impedance:
(4.30)
being
(4.31)
(4.32)
When considering the virtual impedance in the control loops in Fig.
4.7, where R D is the total virtual impedance that consists of the preset
virtual impedance and the adaptive virtual impedance, the closed-loop
transfer function will be
(4.33)
where
(4.34)
being
(4.35)
An effective closed-loop control for the inverter needs to have a

high output impedance. As indicated by the Bode diagram, Fig. 4.8
illustrates the frequency-domain behavior of the output impedance. In
this case, it is apparent that the impedance is highly resistive in the
vicinity of the frequency of interest, which includes the line frequency.
Figure 4.9 shows a zoomed-in Bode diagram around this range.
Fig. 4.8 Bode diagram of the output impedance, R D= 0 ∼ 1 Ω with increment of 0.1 Ω
Fig. 4.9 The zoomed-in Bode diagram of the output impedance around 50 Hz
As the range of virtual impedance (0.1–1.0 Ω) increases, the Bode

diagram shows a nearly resistive behavior of the output impedance,
which can be used for the proposed adaptive virtual impedance control
technique. For any virtual impedance value, the phase degree will
always cross a point around − 33∘ at 50 Hz. The Bode diagram of the
output impedance, shown in Fig. 4.10, shows the range of virtual
impedance values between 1.0 and 10.0 Ω. As the value of the virtual
impedance gets bigger than 1.0 Ω, the trend of the degree of the virtual
impedance is lower than − 0∘. A total virtual impedance of around 1.0 Ω
can be selected from the output impedance of the closed loop. As a
result, the output impedance of the system will be highly resistive,
which is suitable for the reverse droop function used in this section.
We chose a limit range of 0.3–1.1 Ω for the total virtual impedance,
which demonstrates good average power sharing. As R D = 0 Ω, phase
changes are sharp due to the PR controller effect, but as R D increases,
phase changes become latter.
Fig. 4.10 Bode diagram of the output impedance, R D= 0 ∼ 10 Ω with increment of 1
For system stability analysis, the characteristic function of the

system can be obtained from (4.34)
(4.36)
Since the virtual impedance and adaptive virtual impedance
controller are not shown in the characteristic function (4.32) or (4.36),
they have no impact on the stability of the system. According to the
pole map of the characteristic function shown in Fig. 4.11, there will be
no instability.
Fig. 4.11 Pole map of the characteristic function
4.3 Simulations
PLECS was used to build a UPS consisting of two inverter modules. The
model was used to test the effectiveness of the proposed adaptive
virtual impedance control. To analyze system dynamics when
considering unbalanced output impedances, different preset virtual
impedances were used in the simulation.
4.3.1 Performance Veri ication of the Proposed Adaptive

Virtual Impedance Control
4.3.1.1 Different Preset Virtual Impedance to Mimic
Unbalanced Output Impedances
For module 1 and module 2, the preset virtual impedances are 0.3 Ω
and 0.5 Ω, respectively, which simulate unbalanced output impedances.
To evaluate the effect of the proposed approach, adaptive virtual
impedance control was enabled at t = 0.2 s. By comparing Figs. 4.12,
4.13, 4.14 and 4.15, we can see that the proposed control provides
better average active and reactive power sharing performance under
unbalanced output impedances. As shown in Fig. 4.15, the virtual
impedances of the parallel modules are very close to each other once
the adaptive virtual impedance control is enabled, and the peak
circulating current between the two modules is about 60 mA. Figure
4.14 shows that power can be shared between parallel modules on an
approximately average basis.
Fig. 4.12 Simulation results when the adaptive virtual impedance control was enabled at t = 0.2 s
Fig. 4.13 Circulating current between the two modules
Fig. 4.14 Active and reactive power on Phase A of the two modules
Fig. 4.15 Total value of virtual impedance and the value of the adaptive virtual impedance for the
two modules
4.3.1.2 Different Preset Voltage References to Mimic the

Offset in Different Digital Controllers
To simulate the offset of different digital controllers, different preset
voltage references are applied to the parallel-connected modules. The
details are presented in Table 4.2. Even though voltage offset and gains
of different hardware platforms will exist in real applications, the
condition of different voltage reference sets will not occur.
Table 4.2 Parameters setting of different cases
Voltage reference
Module 1 230∗1.01 V(RMS)
Module 2 230 V(RMS)
A virtual impedance of adaptive nature was enabled at t = 0.1 s and

then Module 2 disconnected at t = 0.2 s and then reconnected at t = 0.4
s. As shown in Figs. 4.16, 4.17 and 4.18, the proposed adaptive virtual
impedance results in average power sharing performance. During the
transient time of 0.4 s, there is distortion in the output current of the
two power modules, and however the voltage and current at the load
side are quite stable.
Fig. 4.16 Voltage references of the two modules

Fig. 4.17 Simulation results with different preset voltage references
Fig. 4.18 Active and reactive power of the two modules
4.3.2 Dynamic Performance Test Under Different Output

Impedances
In this section, a more dynamic test is performed in order to con irm
the validity of the presented DAVIC. To simulate the unbalanced output
impedances of the parallel modules, virtual impedances were set in
both modules to 0.3 Ω and 0.5 Ω, respectively.
4.3.2.1 Conventional Virtual Impedance Control Method

When the dynamic test started at t = 0.15, module 2 was disconnected,
and then it was suddenly reconnected at t = 0.25. As shown in Figs. 4.19
and 4.20, once the output impedances of the parallel modules are
unbalanced, the conventional virtual impedance control is unable to
properly distribute power.
Fig. 4.19 Simulation results suing the conventional virtual impedance control
Fig. 4.20 Active and reactive power using the conventional virtual impedance control
4.3.2.2 Proposed DAVIC

Module 2 was disconnected at 0.1 s, reconnected at 0.2 s, and
subsequently enabled at 0.1 s in the simulation. Based on Figs. 4.19,
4.20, 4.21, 4.22 and 4.23, the average power sharing performance is
estimated during the dynamic test with the proposed DAVIC algorithm.
Figure 4.24 shows that the virtual impedance of the parallel modules
will be nearly equal once the DAVIC is enabled, which will result in
balanced output impedances. This will lead to an improved power
sharing capability. Parallel module output currents exhibited distortion
during transient periods between two fundamental cycles. Still, the
load currents were virtually unaffected by this distortion. In the real
UPS platform, distortion and overcurrent problems will be less evident
because of the inherent impedance of the hardware, as illustrated in
the next section.
Fig. 4.21 Voltage and current waveforms of the dynamic test
Fig. 4.22 Circulating current between the two modules of the dynamic test
Fig. 4.23 Active and reactive power on Phase A of the two modules during the dynamic test
Fig. 4.24 The adaptive virtual impedance and the total virtual impedance of the two modules in
one phasek
4.3.2.3 Veri ication of the Proposed Adaptive Virtual

Impedance Control with Communication Delay
During a real-world application, agents that need to share data may
experience communication delays. Here, the simulation results are
presented for when the parallel-connected power modules have a
communication delay. In the two modules, different preset virtual
impedances are applied, 0.3 Ω in Module 1 and 0.5 Ω in Module 2. It is
normal for the data communication cycle, T c, to be 20 ms between
modules. Module 1 of the proposed method was set to t = 0.6 s, and
then the communication cycle was changed from 20 to 40 ms in order
to test its effectiveness. According to the results shown in Figs. 4.25,
4.26 and 4.27, DAVIC is active at t = 0.2 s. Since the DAVIC control loop
only needs low-bandwidth communication and data received from the
communication link will be stored until it receives a new data, the
power sharing performance will not be affected by the communication
delay. As a result, even when there is a delay in communication for one
module, the update cycle for the register will only be changed, but the
controller will still be able to read the data received in the previous
cycle until new data arrives.
Fig. 4.25 Voltage and current when there is communication delay between the two modules
Fig. 4.26 Active and reactive power of Phase A when there is communication delay between the
two modules
Fig. 4.27 Data communication delay happens between the two modules
Table 4.3 shows the preset virtual impedances for the experiments
using a modular UPS platform. To verify the proposed control, two
unbalanced presets are used. Figure 4.28 illustrates the modular UPS
platform. In the control boards, the digital controller is a Del ino 32-bit
DSP from TI, TMS320F28377D.
Fig. 4.28 The modular UPS platform (courtesy of Salicru S.A.)
Table 4.3 Preset value of virtual impedances
Balanced Unbalanced preset 1 Unbalanced preset 2

Module 1 0.5 Ω 0.3 Ω 0.5 Ω
Module 2 0.5 Ω 0.5 Ω 0.8 Ω
In the experiments, four case studies were examined:

(1)
Using conventional virtual impedance controls, balancing preset
virtual impedances
(2)
Virtual impedances with unbalanced preset values using
conventional virtual impedance controls
(3)
Applications of proposed adaptive control of virtual impedances
to balance preset virtual impedances
(4)
In order to test the proposed adaptive virtual impedance control,
we used two different presets of unbalanced virtual impedances.
All experiments are conducted using plug and play, which means
one module will be disconnected and reconnected to the load in order
to verify the effectiveness of the proposed method under dynamic
conditions.
The experimental results are shown in Figs. 4.29, 4.30, 4.31, 4.32,
4.33, 4.34, 4.35, 4.36, 4.37, 4.38, 4.39 and 4.40. From Figs. 4.30 and 4.34,
we can notice that the power sharing performance of the conventional
control and the proposed DAVIC are almost the same under the
condition of the same preset virtual impedance. However, under the
condition of different preset virtual impedances that indicate different
output impedances, the performance of the proposed DAVIC was much
better than the conventional virtual impedance control, which are
shown in Figs. 4.32, 4.37, and 4.40, respectively. Notice that in this case
the average power sharing can still be guaranteed. More details are
shown below.
Fig. 4.29 Experimental results during the transient time under dynamic test. CH1: Phase A
current of Module 1, CH2: Phase A current of Module 2, CH3: Phase A voltage of Module 1, and
CH4: Phase A voltage of Module 2
Fig. 4.30 Steady state waveforms. CH1: Phase A current of Module 1, CH2: Phase A current of
Module 2, CH3: Phase A voltage of Module 1, and CH4: Phase A voltage of Module 2
Fig. 4.31 Experimental results during the transient time under dynamic test using the unbalanced
virtual impedance preset 1. CH1: Phase A current of Module 1, CH2: Phase A current of Module 2,
CH3: Phase A voltage of Module 1, and CH4: Phase A voltage of Module 2
Fig. 4.32 Steady-state waveforms without adaptive virtual impedance. CH1: Phase A current of
Module 1, CH2: Phase A current of Module 2, CH3: Phase A voltage of Module 1, and CH4: Phase A
voltage of Module 2
Fig. 4.33 Waveforms during the transient time using the adaptive virtual impedance control.
CH1: Phase A current of Module 1, CH2: Phase A current of Module 2, CH3: Phase A voltage of
Module 1, and CH4: Phase A voltage of Module 2
Fig. 4.34 Steady-state waveforms using the adaptive virtual impedance control. CH1: Phase A
current of Module 1, CH2: Phase A current of Module 2, CH3: Phase A voltage of Module 1, and
CH4: Phase A voltage of Module 2
Fig. 4.35 Waveforms during the transient time using the adaptive virtual impedance control with
unbalance output impedances (preset 1). CH1: Phase A current of Module 1, CH2: Phase A current
of Module 2, CH3: Phase A voltage of Module 1, and CH4: Phase A voltage of Module 2
Fig. 4.37 Experimental results under steady state with unbalance output impedances (preset 1).
Fig. 4.40 Experimental results under steady state with unbalance output impedances (preset 2).
4.4.1 The Same Preset Virtual Impedance in the Parallel

Modules Using Conventional Virtual Impedance Control
Figures 4.29 and 4.30 show the experimental results with the same
preset virtual impedance in the parallel modules using conventional
virtual impedance control.
4.4.2 Different Preset Virtual Impedance in the Parallel

Modules Using Conventional Virtual Impedance Control
In Fig. 4.32, the load current cannot be average shared between the
inverter modules using the conventional virtual impedance. The
conventional virtual impedance control cannot automatically ensure
good power sharing when output impedances are not balanced
between parallel power modules in real applications.
4.4.3 The Same Preset Virtual Impedance in the Parallel
Modules with Adaptive Virtual Impedance
Figures 4.33 and 4.34 demonstrate an excellent average power sharing
performance of the adaptive virtual impedance control under balanced
output impedances.
4.4.4 The Two Different Presets of Unbalanced Virtual

Impedances in the Parallel Modules Using the Proposed
Control
In this section, two different presets of unbalanced virtual impedances
are applied in the experiments to verify the proposed control method.
From Figs. 4.37 and 4.40, with unbalanced preset virtual
impedance, the transient time is a little bit longer than the results in
Fig. 4.33 with balanced virtual impedances, but inally the current will
be average shared between the parallel modules when using the
proposed DAVIC. When comparing Figs. 4.36 and 4.39, it will take a little
bit long time, a few fundamental cycles, to reach the stable state when
the output impedances are more unbalanced between the parallel
power modules. The results show the ability of tuning the output
impedances of the inverter modules automatically to guarantee the
performance of average power sharing using the proposed adaptive
virtual impedance control, which can strengthen the availability and
reliability of the modular UPS system.
4.5 Conclusion
Industrial applications with high levels of reliability are increasingly
using modular UPS systems, where the average power sharing
performance is an important factor. This section proposes an adaptive
virtual impedance control method to control modular UPS systems,
along with the procedure for designing control parameters for the
adaptive virtual impedance loop. A description of the selection criteria
for the virtual impedance is also included. PLECS was used to simulate
the performance and reliability of the proposed control using two
inverter modules. Experiments based on an industrial modular UPS
platform were performed. Comparatively to the conventional virtual
impedance control, the dynamic test can effectively suppress the
circulating current between parallel modules with different output
impedances, presenting a better average power sharing performance.
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[Crossref]
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[Crossref]
https://doi.org/10.1007/978-3-031-22178-1_5
5. Distributed Average Integral

Secondary Control for Modular UPS
Systems-Based Microgrids
Baoze Wei1
(1) Aalborg University, Aalborg, Denmark
Baoze Wei
Email: bao@energy.aau.dk
Keywords Distributed secondary control – CAN bus – Modular UPS –

Virtual impedance – Droop control – Parallel inverters – Power sharing
5.1 Distributed Control Framework

5.1.1 The Concept of the Conventional Distributed
Secondary Control
Figure 5.1 illustrates the control diagram for a conventional
distributed secondary control. With this control method, the output
voltages of all the inverters are shared over a communication bus (in
our case, the CAN), and each unit calculates the average voltage and
compares it with the reference voltage using a local PI controller to
obtain the voltage compensation value . From the distributed
secondary control, the frequency compensation value can also
be obtained. Describe the secondary controller in the following way:
(5.1)
(5.2)
where E ref and f ref are the references of voltage and frequency,
respectively. E i and f i are the voltage amplitude and frequency of the
ith module, respectively, K PEsec and K IEsec are the proportional and
integral coef icients of the voltage secondary controller, respectively,
and K Pfsec and K Ifsec are the coef icients of the frequency secondary
controller.
Fig. 5.1 The conventional distributed secondary control scheme
5.1.2 The Performance Veri ication and Problem

Expression of the Traditional Distributed Secondary
Control
Simulation was used to verify the performance of the conventional
distributed secondary control. Figure 5.2 shows the control diagram
for a modular UPS system using droop, virtual impedances, and
distributed secondary controls to operate a number of power modules
simultaneously. A diagram of the communication con iguration for the
distributed secondary control is shown in Fig. 5.3. According to
conventional distributed secondary control, the power module will
only send voltage and frequency information to the communication
link if it is delivering power to the load, which means only the modules
operating in parallel to support the load will be able to exchange
information. Accordingly, if a power module is disconnected without
delivering power to the load, it should stop sending voltage and
frequency information to the communication link because it is no
longer a part of the paralleled system.
Fig. 5.2 Control diagram of n parallel modules using droop, virtual impedance, and secondary
control
Fig. 5.3 Data communication setup for the distributed secondary control
PLECS was used to implement the simulations. To recreate the

experimental hardware accurately, a switching model was built in the
simulation, and the entire control scheme was written in C, similar to
the code used in the digital signal processor (DSP) unit of the real
modular UPS platform.
According to the simulation, the conventional distributed
secondary control was implemented as follows: before 0.15 s, two
inverter modules were connected to the load and were delivering
power to the load; then at 0.15 s, the module #2 was disconnected from
the load, and at 0.25 s, it was reconnected to the load. During the time
0.15 s to 0.25 s, the two modules exchanged voltage and frequency
information for the secondary control. The difference is that during
this time, the communication for data exchange between the two
modules was suspended, as module #2 had not delivered power to the
load. During this time, these two modules were not working in parallel,
so they would have used their own voltage and frequency information,
whereas the voltage and frequency information from a module that is
not supplying power to the load should not be used to control the rest
of the parallel-connected modules.
According to the simulation results shown in Fig. 5.4, the output
currents were about the same before 0.15 s, but after 0.25 s they were
signi icantly lower for #2 than for #1. As a result, the conventional
distributed secondary control method is unsuitable for the modular
UPS system. As long as the initial conditions are the same, the
secondary control operates well before 0.15 s. Nonetheless, for the UPS
system, each module has its own local control unit; therefore, after
reconnection at 0.25 s, the initial condition of the reconnected
converter is different from the one that continues to supply power to
the load. As a result, due to the different initial values, each converter
converges to a different operating point as shown in Figs. 5.5 and 5.6.
As shown in Fig. 5.5, the active and reactive power of the two modules
in the test can be shared evenly between them before 0.15 s. The active
power cannot be shared after the module #2 is reconnected after 0.25
s.
Fig. 5.4 Simulation results of the two parallel modules
Fig. 5.5 Phase A active and reactive power of the two parallel modules
Fig. 5.6 The three-phase output value of the secondary control of the two parallel modules
By Fig. 5.6, the output voltage from the second control module was
different from 0.15 s, and it cannot return to the same point at 0.25 s,
since the output voltage of the module #2 was already equal to the
reference. As a result, the secondary control already recovered the
voltage and is not responsible for the power sharing. Under dynamic
conditions, the conventional secondary control cannot guarantee the
convergence of the output voltages of all the parallel-connected
modules to the same reference voltage, resulting in poor power sharing
performance. In this section, a new secondary control distributed
across the parallel power modules is presented, which not only allows
voltage and frequency to be recovered but also demonstrates excellent
performance in sharing power.
5.1.3 The Proposed Distributed Averaging Integral

Secondary Control (DAISC)
A distributed averaging integral secondary control is proposed to
improve both the active and reactive power sharing capabilities of
conventional distributed secondary control. The voltage and frequency
compensation information is not shared, as is done in the general
distributed secondary control. Instead, the integral part of the
secondary control is shared through the communication link, and the
averaged integral value of the secondary control is added to the
proportional part to generate the inal voltage and frequency
compensation values. As a voltage controller, the DAISC functions as
follows:
(5.3)
where i = 1 ∼ n, δ Eisec is the secondary control output of voltage of the

ith module, is the averaged integral value of the voltage
secondary control loop of all the modules, and is the integral
value of voltage secondary control of the ith module. The DAISC for
frequency is proposed as follows:
(5.4)
where δ isec is the secondary control output of frequency of the ith

module, is the averaged integral value of the frequency
secondary control loop of all the modules, and is the integral
value of frequency secondary control of the ith module. The block
diagram of the DASIC is shown in Figs. 5.7 and 5.8. To obtain the
average value of the integral part, the integral part of the local
secondary controller will be sent to the CAN bus instead of the
conventional distributed secondary controller. The inal voltage and
frequency compensation value will then be added to the proportional
part of the local secondary control. Through the improvements, the
local integral part of secondary control will always be equal to the
average integral value once it is sent to the communication link,
preventing windup. An anti-windup capability is also determined from
the simulation results, along with the average power sharing
performance.
Fig. 5.7 Overall control diagram of the distributed control scheme
Fig. 5.8 Overall control diagram of the distributed control scheme

5.2 Stability Analysis
5.2.1 Stability Analysis of Voltage Considering the
Secondary Control
Stability analysis is presented to understand how the proposed DAISC
will affect the system. Under the case of resistive output impedance [1–
4], in the droop and secondary control, the voltage and frequency are
controlled separately based on the assumption that voltage is mainly
dependent and regulated by active power, while frequency is mainly
dependent and regulated by reactive power. Due to this, it is simpler to
analyze voltage and frequency separately [5, 6]. With a simple low-pass
ilter, an output voltage can be adjusted without any delay [5] to avoid
unnecessary technical complications:
(5.5)
The active power injection at the ith module takes the form:
(5.6)
where I oi is the output current of ith module. Normally, the power angel
ϕ is a small value especially when a resistive output impedance is
obtained, and thus is adopted. Then, (5.6) can be rewritten
as P i ≈ E i I oi. To simplify the stability analysis. From (5.3, (5.4), and
(5.6), we can obtain a dynamic system model as follows ][7]:
(5.7)
Let us de ine e 1 = E 1 − E ref and e 2 = E 2 − E ref. If we de ine a state

and an input, then the system (5.5) is changed
into a linear system
(5.8)
where
(5.9)
We only consider . The system is stable if all the
eigenvalues of A E are negative, i.e., E 1,2 converges to E ref. A E may not
have all negative eigenvalues throughout the entire range of
operations, which is dif icult to verify. Therefore, we will use
Lyapunov’s theorem in this study [8]. We can consider a candidate for a
Lyapunov function like this:
(5.10)
The time derivative of (5.10) can be expressed as follows:

(5.11)
If K PEsec > −1 − m p l o1 and K PEsec > −1 − m p l o2, then (4.11) is negative
semi-de inite, which means E 1,2 converges to E ref Thus, from (5.7),
, which means that is also stabilized based on
LaSalle’s theorem. Therefore, the system (5.9) is stable. Furthermore,
the output current for this modular UPS project will always be higher
than or equal to zero since it is unidirectional, which means the system
will be stable if K PEsec > −1. Figures 5.9 and 5.10 show the traces of the
eigenvalues of the vector A E when various secondary control
parameters are selected in order to further analyze the system. The
control parameters used in the simulation and experimental tests are
listed in Table 5.1. Based on Figs. 5.9 and 5.10, we can conclude that the
proposed control and the selected parameters can guarantee system
stability.
Fig. 5.9 Eigenvalue traces of the system (5.7) (a) for K PEsec if various from 0.01 to 0.2
Fig. 5.10 Eigenvalue traces of the system (5.7) (b) for K IEsec is various from 1 to 20
Table 5.1 Main control and hardware parameters in simulations and experiments
Nominal output voltage V orms 230 V
Fundamental frequency fo 50 Hz
Filter capacitance Cf 60 μF
Filter inductance Lf 200 μH
Virtual impedance R vir1 = R vir2 0.5 Ω

Droop coef icient of voltage m p1 = m p2 0.00005 V/W

Droop coef icient of frequency m q1 = m q2 0.00001 Hz/Var
Proportional controller of the secondary control K Psec 0.01
Integral controller of the secondary control K Isec 3.2
5.2.2 Stability Analysis of Frequency Considering the

Secondary Control
A similar model can be written as follows since the frequency
secondary control uses the same principle as the voltage:
(5.12)
At the ith module, reactive power is injected as follows:
(5.13)
The power angel is obtained as ϕ = Δω Δt, , and Δω
is the frequency difference between the inverter output voltage
frequency f i and the reference frequency f ref for the common bus
voltage, which is the common point of the power modules at the load
side in this chapter. As discussed in the former section, the power angle
is small, and then (5.12) can be rewritten as Q i ≈−E i I oi ϕ. Thus, similar
to the voltage, when considering two modules in the UPS system, we
can obtain a dynamic system model as follows:
(5.14)
Let us de ine e f1 = f 1 − f ref and e f2 = f 2 − f ref, a state

, and then the system (5.14) is changed into a
linear system
(5.15)
where
(5.16)
Considering the Q − f droop function, the reactive power is dominated

by the frequency difference, and E 1,2 can be approximated as constant
values in A f. In addition, E 1,2 converged to E ref based on the analysis in
the former section. Thus, similar to the voltage analysis, (5.14) is also
negative semi-de inite if we chose K Ifsec > −1, which means f 1,2
converges to f ref. Thus, from (5.14), , which means that
is also stabilized based on LaSalle’s theorem. Consequently, the
system (5.15) is also stable. The eigenvalue traces of the system (5.14)
are shown in Figs. 5.11 and 5.12 when various secondary control
parameters were selected. The change trend of the eigenvalues is
similar to the system (5.8) in the former section, which further
demonstrates that the proposed DAISC will guarantee the stability of
the system.
Fig. 5.11 Eigenvalue traces of the system (5.7). (a) K Pfsec from 0.01 to 0.1
Fig. 5.12 Eigenvalues trace of the system (5.7). (b) K Ifsec from 1 to 10
5.2.3 Circulating Current Analysis Regarding the Power
Sharing Performance
The equivalent circuit of two parallel-connected inverters with virtual
impedances is shown in Fig. 5.4, in which Z vir1 and Z vir2 are the virtual
impedances, Z line1 and Z line2 are the line impedances, and E 1 and E 2
are the capacitor voltages to be controlled. I 1 and I 2 are the output
currents of the parallel-connected power modules, Z L is the total load
impedance, and I o is the total load current. Then, the circulating
current can be de ined as follows:
(5.17)
As shown in Fig. 5.13, the following equations can be written as
(5.18)
(5.19)
By assuming that the output impedances of the parallel inverters are

equal to each other, Z vir1 + Z line1 = Z vir2 + Z line2 = Z, then substituting
(5.18)–(5.19) into (5.17) gives us
(5.20)
According to (5.20), the circulating current can be eliminated by having
the output voltage and output impedance of parallel inverters equal to
one another. By selecting an appropriate virtual impedance, both the
output voltage and the voltage frequency will converge to E [ ref], which
means that circulating current will be effectively suppressed. Due to
their similar power ratings, all parallel modules are selected with the
same virtual impedances in this chapter. As a consequence, the
equivalent output impedances of the converter modules in the modular
UPS will be very close due to the short connection lines between the
modules. When transmission lines are long or when power ratings
differ, the virtual impedances could be different for the applications.
Fig. 5.13 Eigenvalue traces of the system (5.7). (b) K Ifsec from 1 to 10

To verify the proposed DAISC approach, simulations have been
performed. Table 5.1 lists the parameters used in simulations and the
results of subsequent experiments. To test the static and dynamic
performance of the modular UPS system, two types of tests were
carried out. Figures 5.14, 5.15, and 5.16 show the results when module
#2 was disconnected and reconnected to the system, demonstrating
hot-swap and plug-and-play functionality. In 0.15 s, module #2 was
disconnected from the load; in 0.8 s, it was reconnected. By comparing
the distributed secondary control with the conventional distributed
secondary control, a good dynamic performance was obtained and the
power is always shared evenly among the parallel modules. Moreover,
it exhibits good transient performance, which is an important metric
when evaluating a modular UPS system, especially when critical loads
are supplied. Figure 5.16 also shows that the integral controller did not
experience windup during the dynamic test.
Fig. 5.14 Simulation results with the proposed distributed secondary control
Fig. 5.15 Output active and reactive powers
Fig. 5.16 Local and average values of the integral part of the secondary controller
The second dynamic test was performed by changing the load-step
from 0.5 p.u. to 1 p.u. and vice versa. The irst step is at 0.15 s, the load
power changed from 0.5 p.u. to 1 p.u., and the second step is at 0.4 s,
back to 0.5 p.u. The results are shown in Figs. 5.17, 5.18, 5.19, and 5.20.
During the transient time, a good dynamic performance is obtained
along with an excellent average power sharing performance. In Fig.
5.20, the output voltage frequency did not change much during the
transient period.
Fig. 5.17 Simulation results for load-step changes

Fig. 5.18 Active and reactive powers on phase A of the two modules in front of load-step changes
Fig. 5.19 Local and average values of the integral part of the secondary controller
Fig. 5.20 Output frequency of the two modules

Speci ically, the proposed method is intended to be applied to a
modular UPS project developed in cooperation between the Microgrids
Research Programme at the Energy Technology Department and
Salicru, a company that produces UPS systems in Barcelona. It utilizes a
three-level three-phase inverter called the TROY, which is based on
modular UPS technology. By doing experiments on a real modular UPS
system, experiments were done to verify the effectiveness of the
proposed DAISC strategy. Figure 5.21 shows the modular UPS platform.
A simpli ied diagram of the modular UPS is shown in Fig. 5.22. There is
a control unit, AC/DC and DC/AC converter in each module, as well as
an output relay connected to the load. All the modules can
communicate with each other via a CAN bus through the CAN interface
in each control unit.
Fig. 5.21 Modular UPS experimental platform
Fig. 5.22 Simpli ied diagram of the modular UPS system

In the experiments, we considered two kinds of dynamic tests.
During a constant load test, one of the modules will be disconnected
and plugged back in (hot-swap test). Also, all the modules are
connected to the load when performing a step-load dynamic test. A
further problem is that the outputs of the modules are directly
connected, so one module can be considered as a load for the other. The
proposed DAISC is also tested with four modules operating in parallel
to verify the power sharing and voltage recovery performance. The
effectiveness of the proposed method for different types of loads is
further demonstrated with experimental results on capacitive and
inductive loads.
In the experiment on the real commercial modular UPS platform,
the proposed distributed secondary control was shown to guarantee
the average power sharing performance of the UPS system; the voltage
and frequency remained stable under both dynamic and static loads. In
other words, a modular UPS can be operated simultaneously, and
voltage and frequency are always recovered and synchronized.
5.4.1 Operation of CAN Bus Communication

Control of the system uses CAN communication with a low bandwidth,
and the data sharing through the bus is updated every 20 ms, a
fundamental cycle. Table 5.2 illustrates the detail of the CAN
communication setup. A frame is one data transmission, and the frame
length is 108 bits, in which 64 bits are used for the data itself, and 44
bits are used for the CAN con iguration of how the data are handled,
such as identifying the data.
Table 5.2 Con iguration of the CAN bus
Parameters Value
Bit rate 500 kbps
Frame length 44 (bits data handling) + 64 (bits data) = 108 bits
Frame rate 500 kbps/108 bits = 4629.629
Frame time 1/4629.629 = 216 μs
1 data sending time 216 μs
Modules in the modular UPS platform have their own physical
identi iers. The module with the lowest physical ID is assigned priority
to send data to the CAN bus, and once the module receives the data, it
is recorded into the register. The average value of power will be
obtained when all the modules inish sending data.
5.4.2 Plug and play Performance Test

Figure 5.23 shows the voltage and current waveforms of the two
modules in steady state. The output currents are almost the same, and
a good average power sharing performance is obtained. Figure 5.24
shows the waveforms during the transient time when one module was
disconnected from the system, and the steady-state waveform is
shown in Fig. 5.25. Figure 5.26 shows the waveforms during the
transient time when module #2 was reconnected to the load, and the
steady state waveforms is shown in Fig. 5.27. From the experimental
results, a good dynamic performance is obtained, and the power can
always be averagely shared under parallel operation.
Fig. 5.23 Waveforms of voltage and current at steady state: CH1: Phase A current of module #1,
CH2: Phase A current of module #2, CH3: Phase A voltage of module #1, and CH4: Phase A voltage
of module #2
Fig. 5.24 Waveforms during the transient time when module #2 was disconnected from the
system: CH1: Phase A current of module #1, CH2: Phase A current of module #2, CH3: Phase A
voltage of module #1, and CH4: Phase A voltage of module #2
Fig. 5.25 Waveforms at the steady state after module #2 was disconnected: CH1: Phase A current
of module #1, CH2: Phase A current of module #2, CH3: Phase A voltage of module #1, and CH4:
Phase A voltage of module #2
Fig. 5.26 Waveforms during the transient time when module #2 was reconnected to the system:
CH1: Phase A current of module #1, CH2: Phase A current of module #2, CH3: Phase A voltage of
module #1, and CH4: Phase A voltage of module #2
Fig. 5.27 Waveforms of voltage and current at steady state after the dynamic test with proposed
distributed secondary control: CH1: Phase A current of module #1, CH2: Phase A current of
module #2, CH3: Phase A voltage of module #1, and CH4: Phase A voltage of module #2
5.4.3 Load-Step Changes Dynamic Test

In the experiments, the step-load was con igured as stepped from 1 p.u.
to 0.5 p.u. and then stepped back. The experimental results are shown
in Figs. 5.28 and 5.29. The currents can always be averagely shared
among the two modules along with a stable output voltage. Figure 5.30
shows the results when the output terminals of the two modules were
directly connected to each other suddenly, which is a serious occasion
for the modules under parallel operation. There was no signi icant
negative current lowing from one module to another, guaranteeing the
safety of the DC link of each module, which is also important to
evaluate the reliability of a modular UPS. Moreover, four modules in
parallel operation were tested, and Figs. 5.31 and 5.32 show the current
and voltage waveforms of the phase A of the four modules, respectively.
Moreover, the proposed DAISC is able to approximate the average
current sharing between the four modules, and the voltage can be
recovered to the reference value at the same time, proving its
effectiveness.
Fig. 5.28 Experimental results during the transient time with step-load: CH1: Phase A current of
module #1, CH2: Phase A voltage of module #1, CH3: Phase A current of module #2, and CH4:
Fig. 5.29 Experimental results under steady state with step-load: CH1: Phase A current of module
#1, CH2: Phase A voltage of module #1, CH3: Phase A current of module #2, and CH4: Phase A
voltage of module #2
Fig. 5.30 Dynamic test when the output terminals of the modules were directly connected: CH1:
Phase A current of module #1, CH2: Phase A voltage of module #1, CH3: Phase A current of
module #2, and CH4: Phase A voltage of module #2
Fig. 5.31 Current waveforms when four modules in parallel operation: CH1: Phase A current of
module #1, CH2: Phase A current of module #2, CH3: Phase A current of module #3, and CH4:
Phase A current of module #4
Fig. 5.32 Voltage waveforms when four modules in parallel operation: CH1: Phase A voltage of
module #1, CH2: Phase A voltage of module #2, CH3: Phase A voltage of module #3, and CH4:
5.4.4 Capacitive and Inductive Loads Tests

To further demonstrate the effectiveness of the proposed method,
experiments were conducted with capacitive or inductive loads. An
unexpected interruption occurs when the UPS module disconnects
from the load at the time t x. A capacitive load is connected in Fig. 5.33,
while an inductive load is connected in Fig. 5.34. This shows that the
load current can always be averaged across the parallel-connected
power modules, demonstrating that the proposed method can handle
resistive, inductive, and capacitive loads equally well. Therefore, the
proposed control strategy can guarantee an average power sharing as
well as the nominal output voltage and frequency independent of the
nature of the active/reactive power loads.
Fig. 5.33 Experimental results when capacitive load is connected: CH1: Phase A voltage of
module #1, CH2: Phase A voltage of module #2, CH3: Phase A current of module #1, and CH4:
Phase A current of module #2
Fig. 5.34 Experimental results when inductive load is connected: CH1: Phase A voltage of module
#1, CH2: Phase A voltage of module #2, CH3: Phase A current of module #1, and CH4: Phase A
current of module #2
5.5 Conclusion
We present for modular UPS systems a novel distributed secondary
control (DAISC). It improves the dynamic performance of parallel
operation of converter modules compared to existing distributed
secondary controls. As a result, a modular UPS system will attain
excellent power sharing capabilities, which is very important for a UPS
system. At the same time, the system ensures nominal output voltage
and frequency. In addition, a stability analysis is presented to verify the
availability of the DAISC. With PLECS simulations and experimental
results on a real modular UPS under dynamic load conditions with
resistive, capacitive, and inductive loads, the performance of the
improved distributed secondary control was demonstrated.
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https://doi.org/10.1007/978-3-031-22178-1_6
6. Regeneration Protection in
Uninterruptible Power Supply
Jinghang Lu1
Jinghang Lu
Keywords Active power sharing – DC-link voltage protection –

Uninterruptible power supply (UPS) – Virtual resistance
6.1 Issue of the Regeneration in the Modular

UPS System
Until now, most of the works analyzing the Dual DC Bus (DDB) UPS
system have focused on its normal operation. DDB UPS systems are
characterized by slight output voltage variations in the inverters that
occur under light loads, faults, or temporary overvoltages [1]. In the
AC/DC converter, the feeding active power cannot be delivered back to
the grid due to the unidirectional power low recti ier (unidirectional
power factor correction circuit). Due to this feeding power, the DC-link
voltage will increase, the active power sharing will be unequal, and
even the DC-link capacitor may be damaged. The regeneration
protection solution can address this issue by implementing a DC-link
Voltage Protection (DCVP) method and a power sharing strategy in the
DDB UPS system.
A DDB UPS system built on the PFC and two-level PWM inverters is
investigated here to analyze the regeneration issue (see Fig. 6.1). In
UPS systems, LC ilters are employed to simplify the process and avoid
resonant effects caused by LCL ilters. In normal operation of an online
UPS system, the battery should be fully charged and operate in standby
mode. Thus, Fig. 6.1 does not depict the battery system. Figure 6.1
illustrates how the power factor correction (PFC) delivers active power
unidirectionally from the grid to the DC-link (one-way blue arrow); the
inverters, on the other hand, can absorb or deliver active power
bidirectionally (two-way blue arrows). It is possible to experience a
circulating current from the parallel inverter with a higher voltage to
that with a lower voltage under light loads. If the DC-link is not
equipped with a DCVP method, then circulating current may cause the
DC-link voltage to increase in a short period and, consequently, activate
the DC-link protection. Thus, it is essential to explore an effective DCVP
algorithm.
Fig. 6.1 Active power feeding in the DDB UPS system
6.2 Regeneration Protection Strategy in the

Modular UPS System
6.2.1 Proposed DC-Link Voltage Protection Strategy
The regeneration issue may affect the DDB UPS system, as discussed in
Sect. 6.1. The DC-link voltage is monitored by DCVP controllers located
at each DC-link in the proposed strategy. By adjusting the virtual
resistance, the DCVP controller counteracts injected active power if the
measured DC-link voltage exceeds its prede ined limit. Firstly, suppose
that the output voltage of UPS inverter 2 in Fig. 6.2 drifts up. The DC-
link voltage increases in UPS 1 because of the excessive active power
that is injected into it. Its DC-link voltage should stop increasing and
stabilize in a new steady-state point if the UPS 1 can deliver more
active power and offset the injection of power by reducing its virtual
resistance. Figure 6.2 shows the details of the proposed method. The
DCVP controllers monitor their DC-link voltage in real time. In the
event that the DC-link voltage exceeds its prede ined upper limit
, the DCVP controller will automatically be activated. To
generate an adaptive virtual resistance, the error between the
prede ined upper limit of the DC-link voltage and the measured DC-link
voltage (V DC is fed through a proportional controller). Therefore, UPS
inverters generate more active power as a result of reducing the
adaptive virtual resistance of the inverter, in order to counteract the
injecting power and stabilize the DC-link voltage. The control strategy
is expressed as follows:
(6.1)
In (6.2), and , respectively, represent the adaptive
virtual resistance that is sent to the different inverters. K p is the
proportional controller. The single-edge dead-band block is included in
the DCVP controller due to the fact that the controller should not take
any action if the measured DC-link voltage is less than the DC-link
prede ined upper limit. In the control strategy, only proportional
controllers are employed rather than PI controllers. Instead of tracking
reference points, the control purpose is to generate an adaptive virtual
resistance.
Fig. 6.2 DC-link voltage protection controller
6.2.2 Proposed Power Sharing Strategy for UPS System

Using a simpli ied UPS equivalent circuit, we will irst discuss the UPS
power sharing principle. A virtual resistance adjustment-based power
sharing control strategy will also be presented. The line impedance is
the resistive characteristic of the UPS system shown in Fig. 6.1,
considering the low voltage rating for the application of the UPS
system. A droop control strategy is implemented in the UPS system to
enable active/reactive power sharing without communication.
Moreover, since the line resistance is quite low due to the short
distance between the output ilter and the load of the UPS system. To
enhance droop control stability, the virtual resistance is usually added
to the control strategy. An equivalent circuit of two inverters connected
at the point of common coupling (PCC) is shown in Fig. 6.3, where each
inverter is represented as a controlled voltage source with a virtual
resistance R v. The resistive line impedance is indicated by R [line] as
well. It is important to note that only resistive line impedance is taken
into account because low voltage lines display a resistive nature.
Fig. 6.3 The equivalent circuit of inverters
Thus, the total equivalent resistance R e is equal to the sum of

virtual resistance and physical line resistance and is expressed as
follows:
(6.2)
The active and reactive power injected into the PCC can be
expressed as [2]
(6.3)
(6.4)
where P and Q are, respectively, the active and reactive power injected
into the PCC, V droop is the voltage amplitude of the inverter, V pcc is the
voltage amplitude at PCC, and δ is the phase angle difference between
the V droop and V pcc.
Accordingly, from (6.3) and (6.4), it can be seen that the active
power can be controlled by regulating output voltage amplitude V droop,
and the reactive power can be controlled by regulating the phase angle
δ. However, the initial phase angle of the inverter is dif icult to obtain.
Hence, the angular frequency ω, instead of the phase angle, is regulated
to control the reactive power. So, the droop control strategy is given by
(6.5)
(6.6)
where ω ∗ and ω are the UPS nominal and reference angular frequency
and E ∗ and E are the UPS nominal and reference voltage amplitude. P
LPF and Q LPF are the output active and reactive power through a low-
pass ilter with cutoff frequency ω c, and D p and D Q are the droop
coef icients for regulating the UPS active power and reactive power,
respectively. In this chapter, the design of the droop coef icient is based
on the static deviation method, which ensures that the system is
stable. D Q and D P are de ined as and
, Δω and ΔV are the maximum frequency and voltage
deviations, and and are the maximum active and reactive
power delivered by the inverter, respectively [3].
For the power low through the feeder that consists of inductance
and resistance, the voltage drop on the impedance leads to the
expression [4]
(6.7)
where ΔV is the voltage drop on the impedance, P and Q are the active
and reactive power respectively, and R and X are the resistance and
inductance of the line feeder, respectively. In the UPS system, by
neglecting the inductance, the voltage drop on the resistance is
expressed as
(6.8)
From (6.8), the voltage drop on the resistance of UPS system is derived
as
(6.9)
(6.10)
where R e1 and R e2 are the equivalent total resistance of each inverter.

It is noted that as the frequency is a global state, the reactive power
sharing with the droop control strategy should always be accurate in
the steady state in UPS system. By subtracting (6.9) from (6.10), the
active power error is expressed as
(6.11)
It is observed from (6.11) that the active power sharing error is

related to two factors, i.e., the total resistance difference (R e1 and R e2)
and the voltage magnitude difference (V droop1 and V droop2). If the
circulating current (active power difference) is caused by the
difference between V droop1 and V droop2 due to active power feeding, it
is possible to mitigate the active power sharing difference by adjusting
each inverter’s virtual resistance (R v1 and R v2). Therefore, the
adjustable virtual resistance for the active power sharing is
expressed as
(6.12)
where P ref is the average active power and expressed as

, and is each UPS inverter’s output
active power through a low-pass ilter. It is noted that the P ref can be
obtained by the central or distributed communication system [4–6],
where each inverter updates its active power to the central
controller/distributed controller. After generating P ref by the central or
the distributed controller, it will be sent to each inverter again as the
reference signal of the active power sharing strategy.
Figure 6.4 illustrates the active power sharing control strategy.
Suppose that a regeneration problem in the DDB UPS system has
activated the DCVP method. Due to the active power sharing difference,
there is currently circulating current in the DDB UPS system. The active
power sharing strategy is initiated when the active power sharing
signal lag is switched from zero to one and sent to each inverter
module through a communication line. A PI controller is then used to
generate additional virtual resistance to equalize the output active
power of all inverters by comparing the output active power (P LPF) of
each inverter with the reference value (P ref).
Fig. 6.4 Active power sharing control strategy
In comparison with the power sharing strategy of [7], the proposed

sharing strategy does not disturb the frequency during the transient
process, which is bene icial for the loads that are sensitive to
luctuations in frequency.
As shown in Fig. 6.5, each UPS module is controlled by an outer loop
voltage controller that regulates the output ilter’s capacitor voltage
and an inner loop current control strategy that directly controls the
inductor’s current to limit the current during a transient for protection
purposes.
Fig. 6.5 Complete diagram of the UPS module with the proposed control method
The controllers for voltage and current regulation are expressed as
(6.13)
(6.14)
where k pv and k pi are the proportional terms and k rV and k ri are the
resonant term coef icient at ω o = 314 rad/s. The inner current loop is
designed to provide suf icient damping and protect the inductor’s
current from overcurrent.
The regeneration protection solution is based on DCVP and active
power sharing control. In other words, R v is the ixed virtual resistance
to make sure that the system is stable even when the adjustable virtual
resistance is subtracted.
6.2.3 Small-Signal Modeling and Analysis of the Virtual

Resistance
The previous section discussed the possibility of adjusting the virtual
resistance of the system to provide regeneration protection and active
power sharing. Therefore, in this section, small-signal modeling is used
to analyze the in luence of virtual resistance on the system’s dynamic
response.
First, the power low of the UPS system through a general line
impedance is expressed as
(6.15)
(6.16)
where P and Q are the instantaneous active and reactive power of the
UPS system that lows out of the general line impedance. E and V are
the amplitudes of the inverter output voltage and the common bus
voltage, respectively, and φ is the power angle. Z and θ are the
magnitude and phase of the output impedance.
Due to the fact that the virtual resistance in the UPS system is
added in the control system and that the distance from the load to the
UPS system is usually quite short, the line resistance can usually be
omitted. The UPS system’s power low is therefore expressed as
follows:
(6.17)
(6.18)
Hence, the active power and reactive power under the small-signal
disturbance of voltage amplitude and the phase angle is expressed as
(6.19)
(6.20)
where the operator Δ is the small-signal perturbation around the UPS’s

operating equilibrium point.
When there are some power luctuations during the protection or
active power sharing process, the small-signal response of (6.5)–(6.6)
are expressed as
(6.21)
(6.22)
(6.23)
(6.24)
where τ is the time constant of the low-pass ilter in the active and
reactive power calculation.
Considering that and by the simple manipulation of
(6.19)–(6.20), the dynamic performance of the UPS system yields the
following expression:
(6.25)
where, , ,
Figure 6.6 shows the root locus of the UPS system with different
values of the virtual resistance. Three eigenvalues are not zero and one
is zero in this system. In the meantime, only nonzero eigenvalues are
used in the study of dynamic response and stability [8]. It can be seen
from Fig. 6.6 that when virtual resistance increases, the dominant
eigenvalue of λ 3 determines the performance of the system. However,
even if the virtual resistance varies widely, system stability remains. It
stays far away from the imaginary axis as this eigenvalue is far from it.
Fig. 6.6 Root locus when the virtual resistance changes from 0.3 to 0.8 Ω

Figures 6.1 and 6.7 depict the con iguration of the DDB UPS system for
validation of the proposed control strategy. In this setup, two diode
types of recti iers are used, as well as two inverters. Through the DC-
link capacitors, two DC lines are formed. Testing of the real-time
control algorithm has been performed on the dSPACE 1006 platform.
Table 6.1 provides a summary of the system parameters.
Parameter Value
ESR of inductor 0.02 ohm
Fundamental frequency f o 50 Hz
Filter capacitance C f 27 μF
Filter inductance L f 1.8 mH

DC-link capacitor 2200 μF
Sampling frequency 10 kHz
Rated line to line RMS voltage 120 V
R–L load 50 Ω–1.8 mH
Proportional gain K p 0.2
Proportional gain 0.003

Parameter Value
Integral gain 0.01
Frequency droop D q 0.0001
Voltage droop D p 0.00005
Cutoff frequency ω c 30 rad/s

Virtual resistance R v1 0.6 Ω
Proportional gain K pv 0.2
Resonant gain K rv 100
Proportional K pi 5.6
Resonant gain K ri 500
6.3.1 Parallel UPS Transient Response in Plug-and-Play

Test
According to Fig. 6.8, the power sharing performance between the two
inverters is assessed in the UPS system plug-and-play process, where
both active and reactive power are equally distributed during the
transient process.
Fig. 6.8 UPS parallel power sharing performance

6.3.2 Active Power Back-Feeding Without DC-Link Voltage
Protection Strategy
It has been con igured to trip if the DC-link voltage exceeds 600 V,
which indicates that the system will trip if the DC-link voltage exceeds
600 V. V DC1 increases as the output voltage of the inverter 2 drifts up
from 100 V to 103 V at time t 1 s (Fig. 6.9). Despite the DC-link lacking a
DCVP controller, V DC1 inally reaches 600 V after 1 s (at t 2 s), which
triggers the UPS trip protection.
Fig. 6.9 The DC-link voltage 1 without a DCVP strategy
6.3.3 Active Power Back-feeding with DC-Link Voltage

Protection Strategy
A performance evaluation of the DCVP controller is needed in this
section. First, 570 V is set as the DC-link prede ined upper limit (
), so the DCVP controller needs to be activated if the DC-link
voltage is greater than 570 V. The inverter 2’s output voltage drifts
from 100 V to 103 V at t 1 s, resulting in a voltage increase of V DC1 (Fig.
6.10). Since the DCVP controller was installed, V DC1 is stabilized at 585
V at t 2 s. Figure 6.11 shows that the output active power difference
between P 1 and P 2, due to the active power regeneration, even though
the DC-link voltage is stabilized, leads to large amounts of circulating
current in the UPS system (see Fig. 6.12). In the next section, we will
address the issue of circulating current. Due to the parallel UPS
system’s active power difference, circulating current is generated
within the system. In the following section, we will activate the active
power sharing strategy, which will enable us to eliminate the
circulating current in the system.
Fig. 6.10 DC-link voltage and active power during the activation transient time
Fig. 6.11 Active power during the activation transient time

Fig. 6.12 Output current for inverter 1 (I o1) and inverter 2(I o2) during the DCVP activation
transient time. (Time Scale: 0.04s/div and Current Scale: 4A/div)
6.3.4 Active Power Sharing Control Strategy

Figure 6.13 illustrates the active power sharing process. As shown in
Fig. 6.13, the power sharing controller is activated at t 3 s, so UPS 1’s
active power begins to increase, while UPS 2’s active power begins to
decrease. Moreover, due to the Q − f droop control, it is shown that the
reactive power is almost immune to active power sharing except at the
beginning.
Fig. 6.13 Parallel UPS power sharing performance during the current sharing process
Finally, in the steady state, the active and reactive power and output
current of parallel UPS system are shown in Fig. 6.14, where it is
observed that the current is equally shared and there is no circulating
current due to the active power difference.
Fig. 6.14 UPS current and their errors at steady state after activation of current sharing control
strategy. (Time Scale: 0.02s/div and Current Scale: 4A/div)
6.4 Conclusion
Using DDB’s online UPS system, this section proposes a regeneration
protection method. First, a power regeneration protection technique
based on virtual resistance is proposed to prevent parallel UPSs from
having excessive DC-link voltages. To mitigate the circulating current
caused by the power back-feeding, a virtual resistance-based power
sharing control strategy is also proposed. We have described the
principle of the proposed control scheme and analyzed the dynamic
response and stability of the proposed control strategy with small-
signal modeling. The experimental results support the effectiveness of
the proposed control strategy.
References
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https://doi.org/10.1007/978-3-031-22178-1_7
7. DC-Link Protection and Control in

Modular Uninterruptible Power Supply
Jinghang Lu1
Jinghang Lu
Keywords Uninterruptible power supply (UPS) – DC-link voltage

protection – Current sharing – Consensus control – Anti-windup
7.1 Analysis of DC-Link Voltage Regeneration

Figure 7.1 shows a parallel UPS system combining a Silicon Controlled
Recti ier (SCR) and a two-level PWM inverter. For power transmission
between the AC input and the DC link, an SCR type recti ier is used. The
inverter works in Voltage Control Mode (VCM) in order to directly
regulate the capacitor voltage and current of the output
ilter’s inductor. Under overload conditions or when the UPS
is intended to operate in eco-mode, the bypass switch will be closed. To
avoid the resonance caused by the LCL type ilters, the LC type ilters
are also used. The UPS modules are interconnected with some critical
information, such as the output active power of each UPS.
Fig. 7.1 Active Power Feeding in the DDB UPS system
As speci ied in the IEC 62020-3:2011 standard [1], when the UPS
system is operating normally, the battery is fully charged and in
standby mode. From the grid to the DC link, the SCR delivers active
power in a unidirectional direction (Fig. 7.1 brown arrows). At the
same time, the inverter is capable of operating two-dimensionally and
bidirectionally (see Fig. 7.1 blue arrows). In Fig. 7.1, the UPS module
with the higher output voltage may be able to feed effective power to
the other UPS module under light load, depending on whether the
inverter has a low output voltage or an output fault (red arrow in Fig.
7.1). If the feeding power leads to an increase in the DC-link voltage (in
this case V DC1) and the DC-link voltage exceeds its upper limit without
the DCVP, then system protection is triggered. Additionally, when UPS
operates in the eco-mode, the bypass switch must be closed. If the grid
suffers a temporary overvoltage or amplitude synchronization is not
performed, the grid voltage may be higher than the voltage at the PCC.
Figure 7.1 green arrows: in this situation, both UPS modules might be
powered by grid power, leading to excessive DC-link voltages on both
UPS modules. Accordingly, excessive DC-link voltages cause inverter
operation to be interrupted. Therefore, DCVP control algorithms
should be investigated.
7.2 Proposed DC-Link Voltage Protection

Method
7.2.1 Proposed Method for DCVP
The DCVP principle has a local DCVP controller in each UPS module;
each UPS module detects its own local output active power P LPF (Fig.
7.2). If the detected active power P LPF falls below zero, which indicates
that the UPS module is absorbing active power (P LPF∗0), at this
time, the falling edge of active power signal (P LPF) is employed to
activate the DCVP controller. An additional voltage amplitude reference
is generated using the error generated by comparison of zero and the
negative active power P LPF through a proportional controller K p.
Added to the original voltage amplitude reference E 1 from
P − E droop controller, this additional
voltage amplitude reference will raise the voltage reference in order to
generate more active power. Therefore, the addition of active power
counteracts the injection of active power and prevents the DC-link
voltage from increasing any further. At last, the DC-link voltage will be
stabilized and operate at a new steady-state point.
Fig. 7.2 DC-link voltage protection in UPS system
The control strategy is expressed as

(7.1)
To better understand the principle of the proposed method, irst we
assume that when the output voltage of UPS 2 module drifts up (Fig.
7.1), a large amount of power is injected into UPS 1, causing UPS
1’s active power direction to reverse (Fig. 7.1 red arrow). In
UPS 1, the DC-link voltage begins to increase due to the injection of
active power. During this time, the UPS local DCVP controller
continually monitors its own output active power. DCVP controller is
activated when it detects that the active power has fallen below zero.
UPS 1’s output voltage amplitude will be increased using the
difference between 0 and the negative active power to generate
additional active power in order to counteract the injected active
power. Due to this, UPS 1’s DC-link voltage can be stabilized
by increasing the output voltage amplitude.
During the transition from normal mode to eco-mode of the UPS
system, the proposed DCVP controller can be applied to prevent active
power back-feeding. The bypass switch must be closed during the
transition so that active power can be fed directly to the load from the
grid. In normal operation, the voltage amplitude and frequency
between the PCC and grid voltages should be synchronized before the
bypass switch closes. In this case, the extra active power provided by
the grid will be injected into the UPS modules, which may result in
overvoltage of DC bus 1 and DC bus 2 and possibly damage the DC-link
capacitor. The DCVP controller, however, can effectively prevent active
power back-feeding from the grid.
7.2.2 Proposed Method for Current Sharing

During parallel UPS systems, power feeds or line resistance
mismatches can induce the circulating current. In order to suppress the
circulating current, the current sharing strategy among the UPS
modules should be maintained. It is essential to investigate
fundamental current sharing and harmonic current sharing. UPS
systems are generally integrated into the 120/220 V low voltage grid,
where the line impedance exhibits a resistive characteristic.
Additionally, since the distance between the output ilter of the UPS
system and the load is usually short, the line resistance is quite low.
The virtual resistance is embedded in the control strategy for
improving the stability of the droop control strategy [2]. Due to the
resistive nature of the line impedance, the reactive power-frequency
and active power-voltage magnitude droop control can be applied in LC
type ilter-based UPS systems. We can express the droop equation in
the following way:
(7.2)
(7.3)
where ω ∗ and ω are the UPS nominal and
reference angular frequency, and E ∗ and E are the UPS nominal
and reference voltage amplitude. P LPF and Q LPF are the output active
and reactive power through a low-pass ilter with cutoff frequency
ω c. D p and D Q are the droop coef icients for regulating the UPS
active power and reactive power, respectively. In this chapter, the
design of the droop coef icient is based on the static deviation method,
D Q and D P are de ined as and ,
Δω and ΔV are the maximum
frequency and voltage deviations, and and are the
maximum active and reactive power delivered by the inverter,
respectively.
As shown in Fig. 7.3, the parallel UPS modules are modeled as
controlled voltage sources (V ref) with virtual resistances R v,f at
fundamental frequency. The resistance of the line at the fundamental
frequency is indicated by R line,f. There is no way to omit the R Line,f even
though it is small. R L is modeled passively using the PCC load.
Fig. 7.3 Equivalent circuit for UPS at fundamental frequency
Normally, for the power low through the feeder that consists of
inductance and resistance, the voltage drop on the impedance leads to
the following expression:
(7.4)
where P and Q are the active and reactive instantaneous power that
lows out of the general line impedance, and R and X are the
corresponding resistive and inductive component of the line
impedance. E ∗ is the nominal voltage magnitude, and
ΔV is the voltage magnitude drop on the impedance.
In the UPS system, by neglecting the line inductance, the voltage
drop on the resistance is expressed as
(7.5)
Therefore, the relationship between the UPS output voltage and

PCC voltage is expressed as
(7.6)
(7.7)
where R e1 = R v,f1 + R Line,f1 and R

e2 = R v,f2 + R Line,f2. P 1 and P 2 are
the output active power of UPS 1 and UPS 2, respectively.
In steady-state operation of UPS systems, the reactive power
sharing with the droop control strategy should always be accurate as
the frequency is a global parameter for all UPS modules. Inactive power
sharing errors cause the fundamental circulating current. The active
power error is calculated by adding (7.6) and (7.7):
(7.8)
It can be observed from (7.8) that the active power sharing error is
related to two factors that include the total resistance difference (R e1
and R e2) of the two UPS system and the voltage magnitude difference
(V ref1 and V ref2). If the circulating current is caused by the difference
between V ref1 and V ref2 or line resistance mismatching (R Line1 and R
Line2), the best way to mitigate the circulating current is to adjust each
UPS’s virtual resistance (R v,f1 and R v,f2).
Meanwhile, the equivalent circuit at the harmonic frequencies
when connecting a nonlinear load to PCC is shown in Fig. 7.4. The
harmonic resistance is expressed as
(7.9)
where R line,H and R v,H are the physical feeder and virtual resistance at
the harmonic frequencies, respectively. The controlled harmonic
voltage source is considered zero in the system at harmonic frequency,
since the voltage source is considered short circuit at harmonic
frequency. According to Fig. 7.4, the decrease of UPS equivalent
resistance results in the increase of the corresponding harmonic
current and vice versa. As a result, by properly controlling the virtual
harmonic resistance, the circulating harmonic current caused by line
resistance mismatch can be mitigated.
Fig. 7.4 Equivalent circuit for UPS at harmonic frequency
Figure 7.5 illustrates the proposed method for sharing current at

fundamental and harmonic frequencies. It is assumed that the distance
between each UPS module and the critical load is different, resulting in
a mismatch in feeder resistance. Furthermore, the DC-link voltage
protection controller has been activated as a result of power back-
feeding. Parallel UPS systems circulate fundamental current (due to
mismatched line resistance and power feeding) and harmonic currents
(due to mismatched line resistance). By changing the lag from 0 to 1,
the fundamental current sharing signal activates the controller, which
compares the active power of each UPS module with the reference
power average. An additional adaptive fundamental virtual resistance
is generated by the comparison error through a PI controller until the
output fundamental currents for all UPS modules are equalized.
Fig. 7.5 Fundamental and harmonic current sharing strategy
The controller is expressed as
(7.10)
where , P ave,f is the active power reference for

all UPS modules, and indicates the active power of the ith UPS
module. As noted, the P ve,f can be obtained by using a central or
distributed communication system [3–5], in which each
inverter updates its active power to the central
controller/distributed controller. As the reference signal of the active
power sharing strategy, P ave,f is generated by the central or distributed
controller and sent to each inverter again. For each UPS module, the
active power is expressed as
(7.11)
where V cα and V cβ are the measured sinusoidal UPS
voltage in stationary frame, and I α,f and I β,f are the UPS
fundamental positive sequence currents. The ripples of active and
reactive powers are attenuated by the low-pass ilter with cutoff
frequency ω c [6, 7].
The harmonic virtual resistance will be regulated at the selected
harmonic frequencies by the harmonic power error, if the harmonic
current sharing signal is lipped from zero to one, as follows:
(7.12)
where , P ave,H is the harmonic power reference

for all UPS modules, and indicates the harmonic power of ith UPS
module. For each UPS module, the harmonic power is expressed as
(7.13)
where E ∗ is the rated UPS phase voltage. and are the
negative sequence component of UPS ifth harmonic current. and
are the positive sequence component of UPS seventh harmonic
current. Harmonic power is calculated by using only low-order
harmonic currents, as 5th and 7th harmonic currents comprise the
main components of harmonic orders. The SOGI-based sequence
decomposition method described in Fig. 7.6 can also be used to
separate fundamental and harmonic current of UPS. There are two
SOGI quadrature signal generators (SOGI-QSGs), each of which consists
of a harmonic decoupling network, a frequency locked loop (FLL), and
multiple frequency-locked loops. In highly distorted current conditions,
the SOGI-based sequence extraction method shows fast and accurate
results for detecting fundamental frequency and harmonic frequency
currents.
Fig. 7.6 Decomposition of fundamental sequence and harmonic component of the current
Additionally, a voltage drop on its corresponding virtual resistance

can be calculated once the virtual resistance is determined. R V,f and R
V,H represent fundamental and harmonic virtual resistance in Fig. 7.7,
respectively.
Fig. 7.7 Implementation of virtual resistance at the fundamental sequence and harmonic
frequencies
7.2.3 Anti-Windup Dynamic Consensus Algorithm

It has been demonstrated that the dynamic consensus algorithm
(DCA), which has been successfully applied to secondary distributed
control [8] in microgrids in order to share information effectively
among Distributed Generation (DG) systems, can be applied to UPS
systems as well.
Although it is important to emphasize that when DCA is
implemented in a secondary control, there will be a large amount of
overshoot in the voltage amplitude and frequency restoration process.
As a result of this issue, DCA controllers that have fast dynamic
responses outperform PI controllers with slow dynamic responses. To
overcome the overshoot issue, an anti-windup dynamic consensus
algorithm (ADCA) is proposed to reduce the fast dynamic response of
DCA in this section. The details of ADCA are shown in Fig. 7.8.
Fig. 7.8 Control structure for ADCA
The discrete form of consensus algorithm is presented as
(7.14)
where x i(k) indicates the information status of agent i at iteration k, a ij

is the connection status between node i and node j, and ε is the
consensus edge weight used for tuning the dynamic of DCA.
In order to ensure the convergence of consensus to accurate value
in dynamic system, a modi ied algorithm is applied in the chapter and
can be expressed as [9]
(7.15)
(7.16)
where δ ij(k) stores the cumulative difference between the two
agents.
In this chapter, x i(k) may indicate the frequency and voltage
amplitude. Figure 7.8 shows that the saturation block is inserted
between x i(k) and in order to prevent frequency or voltage
amplitudes from exceeding the permitted value. Even though the
uncertainty block is only added to the consensus algorithm, it will still
take a long time to wind up. A back calculation method [10] is adopted
to calculate the x i(k + 1), which prevents windup
and slows down dynamic response. Hence, x i(k + 1)
is updated as
(7.17)
From Eq. (7.17), it is seen that in steady state x i(k) does not exceed
the saturation value, , and therefore, Eq. (7.17) equals
with Eq. (7.15). However, in dynamic restoration process, x i(k)
exceeds the saturation block value, and the anti-windup part will force
the x i(k) to be lower than upper limitation value of saturation block to
alleviate the frequency and voltage amplitude overshoot.
Figure 7.9 contains the complete control diagram, including the
primary and secondary control levels. In addition to the droop control
strategy and DCVP method, voltage and current loops are included in
the primary control level. A secondary control level implements the
fundamental and harmonic current sharing strategies, as well as the
ADCA strategy. The section utilizes a dual loop control strategy with
harmonic compensators in order to achieve voltage tracking. To
regulate the output capacitor’s voltage, the outer loop voltage
controller is implemented. The inverter side current is regulated by an
inner loop current controller that is nestled inside the voltage control
loop. The voltage controller and the current controller are expressed as
follows:
(7.18)
(7.19)
where k pv and k pi are the proportional terms, k rV and k ri are the

resonant term coef icient at ω o = 314 rad/s.
k vh is the resonant coef icient term for the hth harmonics (5th, 7th).
Inductor current is protected from overload by the inner current loop,
which provides suf icient damping and dampens current low.
Additionally, it must be pointed out that DCVP is used to prevent power
back-feeding. DCVP can be activated to share currents between UPS
modules after the activation of the current sharing strategy. Due to the
line resistance mismatch, it can also be applied to current sharing. As
part of UPS normal operations, ADCA is used as the secondary control
strategy.
Fig. 7.9 Complete diagram of the UPS module with the proposed control method

Figure 7.10 shows a two-parallel DDB UPS setup that was developed to
test the feasibility of the proposed control strategies. In this setup, two
SCR type recti iers are used, along with two inverters. The DC buses are
formed by DC-link capacitors. dSPACE 1006 platform is used to test
real-time control of the control algorithm. Table 7.1 lists the
parameters of the system. Waveforms are captured by both the
oscilloscope and Control Desk.
Parameter Value
ESR of inductor 0.02 ohm
Fundamental frequency f o 50 Hz
Filter capacitance C f 27 μF
Filter inductance L f 1.8 mH
DC-link capacitor 2200 μF

Parameter Value
Sampling frequency 10 kHz
Rated line to line RMS voltage 120 V
R–L load 50 Ω–1.8 mH
Proportional gain K p 0.2
Proportional gain 0.002
Proportional gain K ( p H) 0.0002
Integral gain 0.0001
Integral gain K ( i H) 0.0001
Frequency droop D q 0.0001
Voltage droop D p 0.00005

Cutoff frequency ω c 30 rad/s
Virtual resistance R v1 0.4 Ω
Proportional gain K pv 0.2

Resonant gain K rv 100
Proportional gain K pi 5.6
Resonant gain K ri 500
Parameter K in ADCA 0.2
7.3.1 Parallel UPS Transient Response in Plug-and-Play

Process
In the UPS plug-and-play process, the capability of sharing power
between two UPS modules is evaluated. As can be seen in Fig. 7.11a, the
active and reactive power are equally shared after plug and play. As
shown in Fig. 7.11b, the output current for the two UPS modules, as
well as their errors, is almost zero due to the accurate active and
reactive power sharing. A connection between the D/A board and the
oscilloscope is responsible for the background noise.
Fig. 7.11 UPS parallel Power sharing performance. (a) process of active and reactive power
sharing and (b) current of UPS 1 and UPS 2 after power sharing
7.3.2 Power Feeding Without DC-Link Voltage Protection

Accordingly, as shown in Fig. 7.12, the DC-link voltage increases from
542 V to 600 V (the DC-link voltage upper limit) during the period
between 2.5 s and 2.9 s, effectively triggering the UPS protection
system, resulting in the shutdown of inverter 1 after 2.9 s.
Fig. 7.12 DC-link voltage of UPS 1 without DCVP strategy
7.3.3 Active Power Feeding with DC-Link Voltage

Protection
With the DCVP controller installed in the UPSs, at 4.4 s, a voltage
reference in UPS 2 steps up from 100 V to 103 V, resulting in active
power feeding from UPS 2 to UPS 1. The DCVP controller is activated
when the active power in UPS 1 falls below zero. To prevent further
feeding of active power, the DCVP controller increases the UPS 1
voltage reference. Figure 7.13 shows that the UPS 1 drops below zero
quickly after the negative power feeding occurs at 4.5s. To counteract
the injected power, the DCVP increases the voltage reference amplitude
of UPS 1 and activates the DCVP. Consequently, the active power
increased from − 20 W to 25 W at 4.6 s. Furthermore,
as shown in Fig. 7.14, the DC-link voltage increases from 542 V at 4.4 s
but stabilizes at 544 V at 4.6 s. As a result of the power feeding,
however, the active power P 2 is greater than P 1, resulting in the major
fundamental circulating current between the two UPS modules (Fig.
7.15). The issue can be resolved in the next subsection.
Fig. 7.13 UPS 1’s active power with DCVP

Fig. 7.14 DC-link voltage of UPS 1 with DCVP strategy
Fig. 7.15 Circulating current with DCVP
7.3.4 Fundamental Current Sharing

According to the previous subsection, after the DCVP controller has
been enabled, circulating current is present in the UPS system. In order
to mitigate the circulating current, the current sharing strategy should
be implemented. The lag signal at t 3 therefore enables the
fundamental current sharing controller to be activated. Based on Fig.
7.16, active power equalization for P 1 and P 2 is achieved with the
proposed control strategy, as well as the circulating current between I
o1 and I o2 is minimized.
Fig. 7.16 Circulating fundamental current
7.3.5 Harmonic Current Sharing

Integrated systems with nonlinear loads may experience harmonic
power sharing errors due to line impedance mismatches. Figure 7.17
shows a three-phase nonlinear load connected at the terminal. As the
line resistance for UPS 1 and UPS 2, the values of 0.4Ω and
0.2Ω are, respectively, adopted. According to Fig. 7.18, the line
resistance mismatching (the smaller value of line resistance on UPS 2
side) results in the higher output harmonic current before activating
the harmonic current sharing strategy. As shown in Fig. 7.19, harmonic
power begins to share when the harmonic current sharing signal lips
from zero to one; this process takes 25 s. Figure 7.20 shows that the
output harmonic current of UPS 1 and UPS 2 is equalized after
harmonic current sharing is completed.
Fig. 7.17 Terminal harmonic load type in the experiment
Fig. 7.18 Output current shown in the α − β frame

for UPS 1 and UPS 2 without harmonic current sharing. (a) Output current in
α − β frame for UPS 1 and (b) output current in
α − β frame for UPS 2
Fig. 7.19 Harmonic power sharing process
Fig. 7.20 Output current shown in α − β frame for

UPS 1 and UPS 2 after harmonic current sharing. (a) Output current in
α − β frame for UPS 1; (b) Output current in
α − β frame for UPS 2
7.3.6 Transient Performance for the Frequency and

Voltage Amplitude Restoration Under Load Change
Analyzing the performance of transient frequencies and voltage
amplitude under load disturbances is accomplished by comparing the
DCA and ADCA strategies. Figure 7.21a shows that the frequency drops
from 314.19 rad/s to 313.8 rad/s when the UPS’s load
switches from full to half load; while when ADCA is used the deviation
is reduced by 50% (Fig. 7.21b). With only DCA strategy, the voltage
amplitude deviation can reach 110 V, as shown in Fig. 7.22a.
Fig. 7.21 Comparison of frequency deviation with ADCA and DCA
Fig. 7.22 Comparison of voltage amplitude deviation with ADCA and DCA
7.4 Conclusion
As part of the modular UPS system, this section discussed DC-link
protection and control. We irst proposed a DCVP strategy for
protecting inverters from excessive DC-link voltage. Through DCVP
control, the power back-feeding problem can be signi icantly reduced.
To mitigate the impact of line resistance mismatches and power back-
feeding, a strategy for sharing fundamental and harmonic currents in
the UPS system is proposed. To prevent voltage and frequency
overshoots, a dynamic consensus algorithm is presented as an anti-
windup solution. Experiments have demonstrated the ef icacy of the
methods presented.
References
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specifying the performance and test requirements
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inverters in uninterruptible power systems. IEEE Trans. Power Electron. 31(7),
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https://doi.org/10.1007/978-3-031-22178-1_8
8. Overload and Short-Circuit Protection

Strategy for Voltage-Source Inverter-
Based UPS
Jinghang Lu1
Jinghang Lu
Keywords Uninterruptible power supply (UPS) – Short circuit –

Overload – overcurrent protection – Voltage-source inverter
8.1 Preliminaries and Notations

As part of the UPS, the fault detection and protection system plays a
major role. During overcurrent situations, switching devices are
vulnerable to damage. Overheating of the chip is a common cause for
the destruction of power switches. If the inverter malfunctions due to
overloading or short-circuiting, this kind of failure occurs. When
evaluating a power system’s reliability, short circuits should be an
important factor [1–4]. Speci ically, this chapter investigates the
overload and short-circuit protection of an inverter-based voltage-
source UPS. It is often necessary to limit the output current of an
inverter even under overload or short-circuit conditions [5–9]. Once
the fault has been cleared, an effective overcurrent control method can
enable the system to return to normal operation [10–12].
Overcurrent protection mainly consists of two types: hardware-
based and software-based. A fault-under-load (FUL) (at output phases)
will result in overcurrent, and a hard switching fault (HSF) will result in
short circuit [5, 13–15]. Before running the converter, the load is short-
circuited during HSF. In this type of short-circuit fault, the increasing
current rate is the same as under normal operating conditions. The
FUL differs from the HSF in that it usually occurs when the converter is
already running, and it typically causes a higher peak current than the
HSF [5]. Detecting FUL in more detail is given in [14, 15]. The following
describes the speci ic scenarios where an inverter might overcurrent
in [8]:
(i)
FUL: Inverter is working under strong overload.
(ii)
FUL: Single-phase (asymmetrical fault) or three-phase
(symmetrical) ground short-circuit fault.
(iii)
FUL: Phase-to-phase short circuit between two phases
(asymmetrical fault).
(iv)
HSF: Shoot-through of any phase of the inverter.
The main causes of HSF are the failure of the dead time, the
problem of the PWM modulation, or the problem with the driver
circuit. The focus of this chapter is protection in the event of a failure.
Switching devices must be detected quickly in order to avoid
overheating and destruction if there is an overcurrent or short-circuit
fault [5]. IGBTs have been proposed with many different types of short-
circuit protection [1, 13]. When a short circuit occurs, it is hard to ix
since the switching devices are usually damaged within a short period
of time. The most common method for detecting and protecting IGBT
short circuits is based on hardware circuits.
8.1.1 Primary Hardware Protection

In power systems, overcurrent backup protection methods such as
fuses [6], relays [16–19], or breakers serve as the primary hardware
protection. They are used to isolate the converter from the power
transmission line in case of overcurrent [6, 10, 20].
8.1.2 Driver-Circuit-Based Hardware Protection
Various switching devices under different working modes can also be
protected by hardware protection [21–26]. The driver circuit typically
incorporates a detection and protection logic circuit to cut the power
to the switching devices in case of a fault. Below are examples of
common methods for detecting or protecting the switching devices:
(1) VCE or VDS voltage monitoring [7, 22]. (2) VGE or VCE voltage
monitoring [26–29]. (3) Gate-charge monitoring [30, 31]. (4) Collector
current monitoring [32–34].
8.1.3 Main Power-Circuit-Based Hardware Protection or

Combined with Modi ied Algorithm Control Method
Other literatures describe methods of protecting a system by
substituting an auxiliary protection circuit into the main power circuit
or by using different software control methods when a fault occurs. An
auxiliary switch, along with a driving circuit, is used to provide
protection in [6]. It is connected between the positive rail of the DC bus
capacitors and the collector/drain terminal of the upper switching
transistor. Having to use an auxiliary drive circuit for switching the
protecting transistor [6] increases the complexity of the circuit.
Additionally, the authors of [6] propose another protection method
called linear current protection, which comprises additional auxiliary
switches and resistors for the protection circuit. In addition to
increasing costs and volume, this method will also increase power
losses due to the auxiliary components. There is a method in [35] to
protect against overcurrent using a 12-pulse thyristor recti ier bridge.
In [36], a fuse-based protection method was discussed. A hardware-
based method is proposed in [37], referred to as a hardware hysteresis
circuit. Once the fault occurs, this technique will detect the fault and
then transfer from voltage control mode (VCM) to current control
mode (CCM) to limit the current.
8.1.4 Based Overload or Short-Circuit Protection Method

According to [8], an overcurrent control strategy is based on
generating new current references based on a current limit function,
using an auxiliary control loop, and storing the original current
references in a lookup table. Using a hysteresis comparator circuit, a
method of current limiting was presented in [9], which switched to
current-controlled operation after overcurrent. There are several
disadvantages of this control method, including the complexity of the
auxiliary current control mode, the longer response time, and the need
to design a hysteresis comparator circuit for each phase as mentioned
in [9]. It proposed a short-circuit protection method in [20]. In
contrast, based on simulation and experimental results, the limited
output current value was not accurate, and the recovery after fault
clearance was slow. The protection method in [38] is based on virtual
impedance, but it has the same problem as [20] and it is not effective
for short-circuit faults since short circuits are not investigated in [38].
A lookup table-based method of current limiting for a single-phase
inverter was proposed in [39]. When overload happens, it will generate
a new voltage reference, instead of a current reference, to reduce the
output voltage, thereby limiting the output current. When an overload
occurs at different levels, it does not provide a ixed limit of current, so
the safety of the system cannot be ensured. Additionally, the system
has no short-circuit protection capability. A couple of algorithm-based
short-circuit protection methods were proposed in [40]. This chapter
compares the proposed method with these two methods, but both
present drawbacks.
Wang et al. [41] and Nuutinen et al. [42] discuss some additional
short-circuit protection methods. When a short circuit occurs, the
inverter will switch from VCM to CCM. This type of method is highly
dependent on fault detection algorithms. In the event of a delay in
detecting a fault or after it has been cleared, the switch between the
two modes cannot be instantaneous. A higher-level controller will also
require more resources since it must provide two kinds of operation
modes, VCM and CCM, which will increase the cost.
8.2 The System Model of the UPS System Under

Droop Control
The output of a three-phase UPS system will typically work with single
phase or three phases to make it adaptable to a variety of loads, while
also allows for greater lexibility. This chapter has proposed the control
under the ABC stationary coordinates frame, which is more convenient
for testing the effectiveness of the control strategy phase by phase or
three phases at the same time.
The topology of the NPC three-phase three-level inverter with an LC
ilter at the output is shown in Fig. 8.1. The control scheme is shown in
Fig. 8.2. As a conventional practice, anti-windup loops are added to
voltage and current PR controllers to avoid resonance controller
windups. However, it is not enough to simply have a high performance
overload and short-circuit protection based on this kind of control. To
achieve fast and accurate current limits under overload or short-circuit
conditions, in the proposed control scheme, the resonant component
of the PR controller in the current control loop is reset to zero when the
output current exceeds the limited value. Moreover, the ilter capacitor
voltage V c is fed forward into the output of the current control loop as
opposed to the traditional voltage and current control loops. By
controlling three parts of the control scheme, namely the anti-windup
loop in the voltage and current controllers, the capacitor voltage
feedforward control, and the reset of the resonant part of the current
controller when overcurrent occurs, an accurate and fast current limit
performance can be achieved. If overcurrent occurs, such as under a
short-circuit condition, the capacitor voltage can be feedforwarded to
suppress its in luence on the output current. By resetting the resonator
of the current controller, the modulation waveform can be reduced
quickly to a limited value, thereby preventing the inverter from
entering uncontrollable conditions or overshooting the current. For the
current limit under overload or short circuit, each of the three parts
has an important role.
Fig. 8.1 Topology of the NPC inverter
Fig. 8.2 The control diagram considering overload and short-circuit protection
Figure 8.3 shows the simpli ied linear control model for the voltage
inverter in the UPS, in which G V(s) represents the transfer function of
the voltage controller; G I(s) represents the transfer function of the
current controller, and G PWM(s) represents the transfer function of the
inverter. De ining that:
(8.1)
where K PV and K RV are the proportional and resonate coef icients of
the voltage PR controller, respectively; K PI and K RI are the proportional
and resonate coef icients of the current PR controller, respectively; and
for the three-level voltage-source inverter, the gain K PWM equals to V
dc∕2. Moreover, in order to suppress the in luence of the luctuation of
the DC bus voltage, the DC bus voltage will always be considered in the
control, and the PWM signal will be divided by V dc∕2 before sending to
the driver circuit. So that the gain of the path from the output of the
current controller to the inverter output, from the point PWM* to the
point V XO(s)(X = A, B, C) in Fig. 8.2, will be one. Accordingly, a unit
feedforward control is applied in this chapter, F(s) = 1.
Fig. 8.3 A simpli ied linear model of the control
8.3 Short-Circuit Protection Strategy

Since the PR controller plays an important role in maintaining control,
it is necessary to explain the proposed control method through its
analysis. In Fig. 8.4, the general PR controller diagram is shown. The
following is an illustration of the PR controller’s transfer function.
(8.2)
Considering an input error signal of same frequency with the PR like

, the Laplace transform of u error(t) is
(8.3)
After the resonant part of the PR controller, see y KR(s) in Fig. 8.4 and
applying (8.3), it yields to
(8.4)
By using reverse Laplace transform of (8.4), it gives as following:
(8.5)
Fig. 8.4 Control diagram of the PR controller
Take two different values of φ as examples to analyze the output of

resonant controller. When φ = 0∘, the output signal would be
(8.6)
when φ = 90∘ , the output signal would be
(8.7)
If the resonant controller is well tuned, the inal value of the
resonant controller will be a constant with a zero steady-state error if
applied in a control architecture. An error signal triggers the resonant
controller to operate. The resonant controller can also be observed as
only working when the input signal is non-zero. The result of this is
that over time, the output of the resonant controller will accumulate
with the error signal. If given enough time, a small error can turn into a
large one. As the error accumulates, the system is forced to correct it
until the steady-state error is zero. An integral or resonant controller
will always overshoot the controlled signal. Some tools can be applied
to evaluate a controller’s effectiveness in a control diagram.
Control schemes are often tested for effectiveness and stability
with step responses [43–48]. The power system must be capable of fast
dynamic response in order to reduce deviations in output voltage or
current during transient events [43]. Power electrical system unit step
response can be de ined as the time behavior of the system when the
input changes from 0 p.u. to 1 p.u. within a short amount of time [49].
As a practical matter, knowledge of how the system responds to a
sudden input is essential because large deviations from the long-term
steady state may have extreme effects on the controller, as well as on
other parts of the system that are dependent on it. In addition, the
overall system cannot act until the controller’s output reaches a point
near its inal state, so it takes longer for the overall system to respond.
It gives information on the stability of a dynamical system and on how
fast a system can reach a stationary state (if it starts from another
point of operation) if known the step response of the system [49].
Normally, we can obtain the following information from the system
step response: overshoot, settling time, and steady-state information.
In the event of an overload or a short circuit, the system moves to a
new operation point, from a load perspective, and it creates a large
load-step change, which requires more current to be supplied by the
converter. Besides reducing overshoot and settling times, we also need
to achieve an accurate current limit protection in order to protect the
hardware. By examining the step-response analysis of a closed-loop
system as well as the control strategy, the control can be improved in a
systematic way.
For the purpose of analyzing the step-response behavior of the
control architecture, three different con igurations of the control
architecture are considered:
Case 1 With only proportional control K PI in the current control loop

and the feedforward control V C, the closed-loop transfer function is
(8.8)
Case 2 Using PR controller in the current control loop without the V C

feedforward control, the closed-loop transfer function of the current
control loop is
(8.9)
where , and accordingly, one can obtain
(8.10)
in which
In (8.9), it is clearly showing that, without V C feedforward control,

the in luence of the capacitor voltage to the inductor current cannot be
eliminated. In (8.10), the term I o(s) can be seen as an external
interrupt.
Case 3 In order to decouple the capacitor voltage V C(s) and the
inductor current I L(s), V C feedforward control is added into the
current control loop, and then the closed-loop transfer function of the
current control loop will be
(8.11)
The capacitor voltage does not in luence the inductor current in

(8.11). Figure 8.5 shows the results for the unit step-response analysis
using Matlab for the three cases mentioned in Table 8.1. The waveform
oscillated with time at steady state in case 2 without the V _C
feedforward control. With V C feedforward control, it is possible to
predict that when serious overload or short circuit occurs, the output
current will overshoot and oscillate at steady state. As a result of V C
feedforward in case 3, overshoot suppression can be improved as well
as settling time. A further discovery was that if V C feedforward is
applied to the output with only the P controller, as shown in Case 1,
there is no overshoot, which indicates that the resonant controller is
causing the overshoot.
Fig. 8.5 Step response of different control con igurations
Table 8.1 Parameters of the controllers and hardware circuits in the experiments

Nominal output voltage V ref 230 V
Fundamental frequency ωo 314 rad/s

Filter capacitance Cf 60 μF
Filter inductance Lf 200 μH

Equivalent series resistance (ESR) of ilter inductor rL 0.05 Ω

Preset current amplitude limit value I limit 20 A

Switching frequency fs 20 kHz
Digital signal processer (DSP) – TMS320F28377D

Consequently, Case 1 contains a very positive hint for further
improving the overcurrent protection by resetting the output of the
resonator of the current controller to zero when overcurrent occurs,
which prevents the current from reaching uncontrollable levels.
An overshoot occurs when errors accumulate rapidly. Large errors
are accumulated by the general integrator. The term “integral wind-up”
refers to this. To suppress windup’s in luence, anti-windup loops are
often incorporated into PI or PR controllers. Imagine there is an error
in the resonator, and this error accumulates over time. The
accumulator’s output will rise over time. High resonant gain
exacerbates the overshoot. However, it also occurs with low gains.
Whether the system settles at the set point is not known. Depending on
the output voltage, disabling the accumulation action may improve
resonator performance. When overload or short circuit occurs, the
output of the resonant controller must be quickly reset.
According to the proposed control scheme for a fast overload and
short-circuit protection, it consists of three parts: anti-windup loops in
the PR controller, output voltage feedforward controls, and fast resets
of resonant controllers of current control loops. The parts of the
system play an important role in a quick response to overloads or short
circuits.
8.4 Case Study for the Short-Circuit Protection

A three-phase voltage-source inverter has been used to test the
effectiveness of the proposed overload and short-circuit protection
method. Three cases of faults causing overcurrent conditions have
been investigated: (i) overload, (ii) phase-to-ground short circuit, and
(iii) phase-to-phase short circuit. Control and platform con iguration
can be found in Table 8.1. Refer to Fig. 8.6 for a view of the NPC UPS
platform based on three phases. In Table 8.1, we present the
parameters for the ilters and controllers of three-stage inverters.
Fig. 8.6 The prototype of the NPC three-phase three-level topology-based UPS platform
The waveform of a normal working condition is shown in Fig. 8.7.

UPS systems should obtain a sinusoidal waveform of output voltage.
Figure 8.8 shows the waveform when overload occurs. Upon abruptly
connecting a load that is over the limit, the inverter will limit the
output current to the preset constant value. The output current can still
be controlled even under unknown overload conditions to prevent
damage to the load and to the UPS. It should also be noted that a UPS
system will not be shut down when overloaded, and it is necessary for
some of the most critical systems, such as telecommunications,
network servers, database systems, and medical equipment.
Fig. 8.7 Normal operation with single-phase load. CH1: Output voltage; CH4: Output current
Fig. 8.8 Overload happens with single-phase load. CH1: Output voltage; CH4: Output current
Figures 8.9 and 8.10 depict the waveforms when the UPS switches
from its normal working condition to overload mode. The simulation
shows the same phenomenon as the reset operation of the resonant
regulator of the current controller in the DSP when overload occurs.
Besides, since the current limit is set to 20 A, it shows an accurate
current limit. In the transient phase, the waveform looks good and the
presented control scheme does a good job.
Fig. 8.9 Single phase from normal to overload condition. CH1: Output voltage; CH2: Resonant
output of current controller in DSP; CH3: Inductor current; CH4: Output current
Fig. 8.10 Overload happens with single-phase load. CH1: Output voltage; CH2: Resonant output
of current controller in DSP; CH3: Inductor current; CH4: Output current
Figures 8.11 and 8.12 give the experimental results when phase-to-
ground short-circuit fault happens. It shows the dynamic performance
of the cases from normal to short circuit and the reverse. After clearing
the fault, the output current could be limited quickly to the preset value
and returned to normal operation as expected.
Fig. 8.11 Single phase from normal to phase-to-ground short circuit. CH1: Output voltage; CH4:
Output current
Fig. 8.12 Phase-to-ground short-circuit condition switch to normal working condition on single
phase. CH1: Output voltage; CH4: Output current
Figure 8.13 shows the results when the UPS was operated under
normal working conditions with a three-phase load. Figures 8.14 and
8.15 illustrate the waveforms of symmetric overload occurring in three
phases. By using the proposed method, it is still possible to limit the
current quickly and accurately from no load to overload condition
directly. These results demonstrate the usefulness of the control
method presented here. As there are no more channels on one
oscilloscope, Phase C results were not shown in the experimental
results. Figures 8.16, 8.17, and 8.18 show the experimental results
when a phase-to-phase short circuit occurs. When a fault occurs on one
of the phases, it does not affect the normal operation of the other
healthy phase, and it can quickly return to normal operation when it is
ixed. Very similar results are obtained as shown in the simulation.
Furthermore, the consistency of the simulation and experimental
results further supports the effectiveness and applicability of the
proposed method.
Fig. 8.13 Three-phase load normal working condition. CH1: Phase A output voltage; CH2: Phase
A output current; CH3: Phase B output current; CH4: Phase C output current
Fig. 8.14 Overload happens with three-phase load. CH1: Phase A output voltage; CH2: Phase B
output voltage; CH3: Phase A output current; CH4: Phase B output current
Fig. 8.15 Three-phase overload switch to no load condition. CH1: Phase A output voltage; CH2:
Phase B output voltage; CH3: Phase A output current; CH4: Phase B output current
Fig. 8.16 Normal operation to phase-to-phase short circuit. CH1: Phase A output voltage; CH2:
Phase A output current; CH3: Phase B output current; CH4: Phase C output current
Fig. 8.17 Phase-to-phase short circuit to normal operation. CH1: Phase A output voltage; CH2:
Phase A output current; CH3: Phase B output current; CH4: Phase C output current
Fig. 8.18 Normal operation to phase-to-phase short circuit. CH1: Phase A output voltage; CH2:
Phase B output voltage; CH3: Phase A output current; CH4: Phase B output current
The development of current limit tests for UPS inverters running in

parallel has been completed. To test effectiveness, two current limit
values were chosen. Figure 8.19a shows the results when the current
limit value is 24 A; Fig. 8.19b depicts the results when the current is
limited to 100 A when stronger load is connected. The results show
that even when inverters operate in parallel, an accurate current limit
performance can be obtained.
Fig. 8.19 Current limit results when UPS inverters operate in parallel. CH1: Phase A voltage of
inverter 1; CH2: Phase A voltage of inverter 2; CH3: Phase A current of inverter 1; CH4: Phase A
current of inverter 2. (a) 24 A current limit, (b) 100 A current limit
8.5 Conclusions
A control method is presented in this chapter to protect voltage-source
inverters-based UPS systems from overloads and short circuits. As a
result of the proposed control method, UPS output current can be
limited to a reference value within the safe operation area, so that a
voltage drop occurs when an overload or short circuit occurs. In
comparison with the state-of-the-art solutions, the proposed solution
has greater accuracy and validity for a greater range of overcurrent
issues, while being compatible with advanced current/voltage tracker
regulators based on resonant controllers. Moreover, the proposed
method is robust to not only symmetric faults in three-phase systems
but also asymmetric overloads and short circuits in single-phase
systems, and its healthy phase will not be disturbed by faults. Another
feature of the proposed controller is that it does not have to switch
between operation modes, which can result in instabilities and
oscillatory transients. This is in contrast to conventional methods in
which the control switches from voltage to current mode once
overloading or short-circuiting occurs and then back to voltage mode
once the fault has been cleared. As a result of this approach, once the
fault is resolved, the UPS system can return to normal operation
without changing the control mode. It would continue to act as a
voltage-controlled source. Testing of the proposed control method has
been conducted on a commercial UPS platform.
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Part III
Renewable Modular UPS System
https://doi.org/10.1007/978-3-031-22178-1_9
9. Multi-mode Operation for On-line

Uninterruptible Power Supply System
Jinghang Lu1 and Xiaochao Hou2
(2) Tsinghua University, Beijing, China
Jinghang Lu (Corresponding author)

Xiaochao Hou
Email: houxiaochao@tsinghua.edu.cn
Keywords Burn-in test mode – DC-link voltage – Disturbance

rejection – Enhanced eco-mode – Internal model control (IMC) – PV-
aided normal mode – Robustness – Seamless transfer – Uninterruptible
power supply (UPS)
9.1 IMC-Based DC-Link Voltage Control

Strategy
As shown in Fig. 9.1, the on-line UPS system in this chapter consists of
a PV panel, the battery, a recti ier, several inverters, the TVSS, and
DC/DC converters. According to this diagram, the PV and battery both
receive electrical power from boost-type DC/DC converters. Power is
supplied from the grid to the DC link by a three-phase PWM full-bridge
converter with an L-type ilter. The Paralleled inverters can be
connected into a VCM and can be used with plug–and-play control.
TVSS also guarantees the surge voltage and current will not interfere
with the stable operation of the UPS when the UPS system switches its
operating mode from the TNM to the EEM or BTM.
Fig. 9.1 The diagram of the on-line UPS system
Figure 9.2 shows the schematic diagram for the on-line UPS system
and its associated control strategy. There are two cascaded control
loops in the control diagram: the outer DC-link voltage control loop
described in this section and the inner current control loop. PV,
batteries, and inverter units are represented by the general load. The
DC-link voltage is regulated by the AC/DC converter. Therefore, a
robust control strategy for the DC-link voltage is quite important for a
stable UPS system. The proposed two-port IMC-based DC-link
controller will be illustrated in the following sections.
Fig. 9.2 Schematic diagram of the AC/DC converter with the proposed two-port IMC-based DC-
link voltage control in PV-aided UPS system
9.1.1 DC-Link Modeling

By balancing the injected and output active power of the DC link in the
on-line UPS system, the DC-link voltage remains constant. Hence, the
power balance across the DC link (see Fig. 9.2) is expressed as follows:
(9.1)
where V DC is the DC-link voltage, and C is the DC-link capacitance. The

injected active power P DC, which is equal to the recti ier AC-side
terminal power P t, is expressed as: P DC = V DC I DC. P ext is the external
power that lows out of the DC-link capacitor. R p represents the total
switching loss in the converter circuit. If the instantaneous power of
AC-side ilter is not considered, the AC-side terminal power P t is equal
to the AC-side power P S. A DC-link voltage model is thus derived and is
independent of the operating point:
(9.2)
where and P s are the output and control input, respectively.

Notice that P ext acts like a disturbance here. Taking the Laplace
transform of both sides of (9.2) results in
(9.3)
9.1.2 Two-Degree-of-Freedom (2-DOF) IMC-Based DC-

Link Voltage Controller Design
According to the analysis of section A, the DC link may be subject to
external and internal disturbances, such as: DC-link current changes
caused by the connection and disconnection of the load and system
parameter variations. The traditional method, such as PI control, may
not be able to effectively handle this disturbance. Due to the good
performance of the 2-DOF IMC-based controller in terms of rejection of
external disturbances and internal parameter variations without
measuring DC-link external power P ext, this control strategy will be
used for DC-link voltage regulation.
Figure 9.3 shows the structure of a 2-DOF IMC-based controller in
the Laplace domain. In Fig. 9.3, G P(s) is the actual plant, G m(s) is the
reference model and also named as the internal model, and C 1(s) and F
r(s) are the set-point tracking controller and the disturbance rejection
controller, respectively.
Fig. 9.3 The 2-DOF internal model controller structure
In Fig. 9.4, the control diagram is shown when the 2-DOF IMC-based
strategy is applied to the DC-link voltage controller. This control
structure consists of an inner current loop for controlling the recti ier
output current and an outer voltage loop for regulating the DC-link
voltage. It is often considered that the bandwidth of the inner loop
should be much larger than that of the outer loop in order to prevent
dynamic interactions between them. It implies that, during the DC-link
controller design, the dynamics of the current regulation loop can be
neglected, and assume that ref, where and P S are
the reference and output active powers, respectively (see Fig. 9.4).
Fig. 9.4 The 2-DOF internal model controller structure
From Fig. 9.4, the closed-loop transfer function for the DC-link
voltage is expressed as
(9.4)
where is the DC-link reference voltage, V DC is the regulated

DC-link voltage, and P ext is the external active power and considered as
the disturbance. is the designed reference model,
and G d indicates uncertainty. The relationship between G p and G m is
expressed as
(9.5)
The purpose of the IMC-based control strategy, by designing the
controller C 1(s) and F r(s), is achieving a robust tracking and high-
disturbance rejection ability in the presence of a considerable
uncertainty in the model. According to [1–3], the set-point tracking
controller C 1(s) is designed as and thus promises
the robust and fast tracking ability. Note that λ 1 is the tuning
parameter of C 1(s). Meanwhile, the disturbance rejection controller F
r(s) is designed as z. Note as well that λ 2 is the tuning parameter of F
r(s).
If the reference model is equal with actual plant, i.e., Gp(s) = Gm(s),
from (9.4) and (9.5), the closed-loop transfer function for the DC-link
voltage is expressed as
(9.6)
As the DC-link voltage is controlled at the frequency s = jω = 0, by

substituting s = 0 into (9.6), we have the expression:
(9.7)
Equation (9.7) shows that at the steady state, the 2-DOF IMC control
strategy is able to track the reference with zero-steady-state error. In
addition, the error of the feedback signal E(s) is expressed as
(9.8)
When there is the difference between the plant G P(s) and the
reference model G m(s), E( s) provides the information of the
disturbance and the plant mismatch. The robustness can be obtained
by compensating for the deviation appropriately.
In this chapter, the actual plant is expressed as: , and
the reference model is expressed as: , as the R p is considered
as the uncertainty in the system.
The parameter λ 1 of C 1(s) mainly decides the DC-link voltage
closed-loop bandwidth. In our system, the DC-link closed-loop
bandwidth is chosen to be 20 rad/s; hence, λ 1 = 1∕20. In addition, the
parameter λ 2 of Fr(s) is usually chosen to be much smaller than λ 1 to
make sure disturbance rejection controller’s bandwidth is large enough
to disturbance. But too large bandwidth may interact
with current controller’s bandwidth and, as a result, may cause stability
issue due to the coupling. Moreover, too large bandwidth may bring the
noise as well. Considering the above requirement, λ 2 = 1∕200[3–6].
9.1.3 Stability Analysis

The small gain theorem is applied in this section in order to ensure
system uncertainty stability. The necessary and suf icient conditions
for the stability of a system are
(9.9)
where H(s) is the upper limit , and if the model
mismatch exists, the model error is expressed as
(9.10)
So, when s = 0, F r(0) = 1. By substituting it into (9.9), the following
equation can be obtained:
(9.11)
By substituting and G d( s) = Gp(s) − G m(s)
into (9.11) and making some arrangement, the stability requirement
can be obtained:
(9.12)
From (9.12), it is seen that system is stable under the condition
that uncertainty value is no more than two times the plant.
9.1.4 Two-Port IMC-Based DC-Link Voltage Controller

Design
In order to enhance the tracking and disturbance rejection ability, a
feedback control block C2(s) is added in the 2-DOF IMC-based DC-link
voltage control diagram by using the two-port IMC structure [6, 7], as
shown in Fig. 9.5. Note that active power reference is limited in
practice, and the relationship between the input u and P ref is expressed
as
(9.13)
where is the maximum active power reference. The

controller of C 2(s) is designed as a proportional term, which is
expressed as
(9.14)
Fig. 9.5 Block diagram of the modi ied IMC method for DC-link voltage control
To simplify the analysis of the two-port IMC-based DC-link control

strategy, the saturation block is neglected by assuming: P ref = u. From
Fig. 9.5, the closed-loop expression for is expressed as
(9.15)
If the internal mode is accurate, i.e., G P(s) = G m(s), from (9.15), the
closed-loop transfer function for the DC-link voltage is expressed as
(9.16)
By comparing (9.16) with (9.6), it is observed that the parameter k

p of controller C 2(s) can be tuned properly to reduce the recovery time
in the presence of the load disturbance, i.e.,
It should be noted the parameter selection of C 2(s) should keep the
poles of closed-loop transfer function in Eq. (9.15) are all located in the
left half plane. In addition, the system stability is not affected by the
saturation block; according to [8], if the controller is a proper transfer
function with minimum phase, the stability will not be affected by the
saturation block. In our system, the controller C1(s) satis ies the above
requirement. But the DC-link voltage control transient dynamic
performance may be affected by the saturation block, which is called
windup. However, the controller C2(s) of two-port IMC-based control
strategy can compensate for the effect of saturation as anti-windup to
improve the tracking performance [6, 9].
9.1.5 Inner Loop Current Controller Design

In this AC/DC converter, the proportional–resonant controller is
adopted for the inner loop current control, which is expressed as
(9.17)
where k pc and k rc are the proportional and resonant gains of the

current controller, and ω 1 is the grid fundamental angular frequency.
For the parameter selection, two useful Eqs. (9.18) and (9.20) can
quickly help select the appropriate parameter [10], and the
proportional gain parameter is calculated as
(9.18)
where α c is the desired current controller closed-loop bandwidth. L is
the inductance value of the AC/DC converter. α c should be selected to
be
(9.19)
where ω s is the angular sampling frequency, which is expressed as:

, where f s is the sampling frequency of the system.
Finally, according to the system parameter listed in Table 9.1, k pc = 7.
Table 9.1 System and controller parameters
Parameter Value
Filter inductor L f 1.8 mH
Parameter Value
Switching loss R p 1000 Ω
Normal DC-link capacitor 0.011 F

DC load 230 Ω
Converter rating 1 kVa
Phase-to-phase RMS voltage 4.4 A
Peak phase current 208 V
λ 1 of set-point controller (control in DC link) 0.05
λ 2 of disturbance rejection controller (control in DC link) 0.005

k p of the controller (control in DC link) 0.2
Current controller k pc (control in DC link) 7

Current controller k rc (control in DC link) 420
Frequency droop D q (comparative study in DC link) 0.0001

Voltage droop D p (Droop Coef icient) 0.00005
Integral term k (droop coef icient) 0.007

Proportional controller (comparative study in DC link) 0.02
Integral controller (comparative study in DC link) 0.1
Proportional gain k pv (voltage control) 0.2
Resonant gain K iv (voltage control) 100
Proportional gain K pi (current control) 7

Resonant gain K ii (current control) 500
The selection of resonant gain k rc can be calculated by the

suggested formula :
(9.20)
where α 1 ≪ α c, in addition, according to the suggestion in [10] α 1 < ω 1.
In the system, α 1 is selected as α 1 = 30, so, k rc = 2 ∗ 30 ∗ 7 = 420.
9.2 Control Strategies for Multi-mode
Operation in the On-line UPS System
As previously stated in the Introduction section, when the grid is
normal, the operation mode is categorized as TNM, PNM, EEM, and
BTM (see Fig. 9.6). When a grid fault occurs, these modes need to
switch to back-up mode. This chapter is primarily focused on the
control strategies and the seamless transition between different
operating modes when the grid is normal; the discussion of the
transition between the grid normal operating mode and the back-up
mode is outside the scope of this chapter. In the following parts of this
section, we will discuss the details of the control strategy for these
modes.
Fig. 9.6 Operating modes of the on-line UPS system
9.2.1 PV-Aided Normal Mode of Operation

In the TNM operation of the on-line UPS system, the load power is
supplied by the grid through the AC∕DC recti ier and the DC/AC
inverters. When the small rating PV system is integrated into the on-
line UPS system, the load active power is supplied by the combination
of the PV system and the grid, as shown in Fig. 9.7. The battery has
been fully charged and is operating in standby mode, meaning it does
not supply power to the load in normal operation. To save electricity
from the grid, PV panels should always work in maximum power point
tracking (MPPT) mode.
Fig. 9.7 Power low in the PNM of the on-line UPS system
(1) Control Strategy for DC/AC Inverters in on-line UPS System Figure
9.8 shows the control strategy of the UPS system in the PNM operation.
The droop control strategy is implemented for the parallel-connected
inverter modules. Due to the short distance from the inverter to the
load in the UPS system, the line impedance is considerably small. And a
virtual resistance R v is embedded in the control diagram to increase
the system stability. As the output impedance shows a resistive nature
by adding the virtual resistance, Q ∼ ω and P ∼ E droop control strategy
is implemented in the control loop [11] and is expressed as
(9.21)
(9.22)
where ω ∗ and ω are the inverter nominal and reference frequencies. E ∗
and E are the inverter nominal and reference voltage magnitudes. D p
and D q are the droop coef icients for controlling the output active
power P LPF and reactive power Q LPF through a low-pass ilter,
respectively. The calculated active power P LPF and reactive power Q LPF
are expressed as
(9.23)
(9.24)
where τ is the time constant of the low-pass ilter. V cα and V cβ are the
output voltages through Clarke transformation. I oα and I oβ are the
output currents through Clarke transformation.
Fig. 9.8 The control strategy of the PNM in on-line UPS system
Furthermore, a dual-loop strategy using outer voltage

proportional–resonant (P+ R) control and inner current proportional–
resonant (P+ R) control strategy is employed to attain excellent
reference tracking of the output voltage and to limit the inductor’s
current during transients as a protection feature. The two controllers
are expressed as follows:
(9.25)
(9.26)
where k pv and k pi are the proportional terms, and k rV and k ri are the
resonant term coef icients at ω. k vh is the resonant coef icient term for
the hth harmonics . The inner current loop is designed to
provide a suf icient damping and protect the inductor’s current from
an overcurrent. To increase the harmonic rejection ability of the output
voltage, the harmonic compensation device should be added to the
voltage controller of the DC/AC converter if nonlinear loads are
connected as sensitive loads[12]. Figure 9.2 illustrates the control
scheme for the recti ier, and it will not be repeated in this section.
(2) PV System and the Control Diagram The PV panel is operated in

the MPPT as shown in Fig. 9.8, where the power of the PV panel is
expressed as
(9.27)
where V pv and I pv are the voltage and current at the terminal of the PV
panel. To extract the maximum amount of power from the system, a
number of MPPT algorithms can be applied, such as: Perturb & Observe
(P&O), Hill Climbing algorithm [13], and fuzzy-based method [14]. In
addition, a dual-loop PI controller is used in the system to control the
PV output voltage and prevent PV output overcurrent (Fig. 9.8). This
chapter does not discuss the complex MPPT algorithm since it is
beyond the scope of this chapter.
9.2.2 Enhanced Eco-mode and Seamless Transition

The UPS system operating mode may be transferred from the TNM to
the EEM when the PV system is not available. As shown in Fig. 9.9, the
grid provides the active power, and the DC/AC inverter provides the
reactive power for the load in the EEM. Furthermore, the transition
should be seamless between the TNM and EEM. During the transition,
the UPS output voltage should not change abruptly in amplitude or
frequency.
Fig. 9.9 Power low in the EEM of the on-line UPS system
The proposed control strategy of the EEM operation is shown in

Fig. 9.10, where the integral term is added in the P ∼ E droop control
strategy to achieve the active power tracking without a steady-state
error. Hence, by setting the active power reference to be zero, the
inverter is forced to deliver no active power. In other words, the active
power of the load is fully supplied by the grid. Meanwhile, if multiple
inverters cooperatively provide the reactive power to the load, the
reactive power reference of the droop control strategy in each inverter
should be Q ref,i = So, the droop control strategy in the EEM is
expressed as
(9.28)
(9.29)
Fig. 9.10 The control strategy of the EEM operation in on-line UPS system
By the comparison of Eqs. (9.21–9.22) and (9.28–9.29), it is easy to

observe that when the gains k and Q ref,i are both set to be zero, the EEM
operation returns to the TNM operation. Therefore, the seamless
transition can be realized by setting the desired value of the parameter
k and Q ref,i. Notice that the synchronization term ω syc is added in
(9.29), as all the DC/AC inverters should synchronize with the grid
before bypass switch close. In this chapter, the synchronization method
proposed in [15] is applied for voltage and phase synchronization.
Finally, it must be emphasized that the grid fault detection methods
[16–18] should be applied in the system to protect it against grid faults.
And the EEM has to be switched to the back-up mode in case of grid
fault. As this topic is out of the scope of this chapter, the details will not
be illustrated.
9.2.3 Burn-in Test Mode and Seamless Transition

The power low of the BTM is shown in Fig. 9.11. Speci ically, at no load
condition (see Fig. 9.11a), the active power drawn from the grid is fed
back again through the bypass switch. On the contrary, when the local
load is connected to the UPS system, the power low is shown in Fig.
9.11b, where the active power drawn from the grid lows to the local
load and delivers back to the grid, respectively.
Fig. 9.11 The power low in the BTM operation for the on-line UPS system. (a) No load
condition. (b) Local load condition
The proposed control strategy of the BTM operation is depicted in
Fig. 9.12. Notice that the control strategy is very similar to that of the
EEM. The expression of the droop control strategy in this mode is
shown as
(9.30)
(9.31)
where P ref,i and Q ref,i are the reference active and reactive powers,
respectively. The integral term forces the output active power to
follow the reference one; meanwhile, the reactive power reference for
each inverter is determined by calculating the load reactive power and
has the relationship . It is pointed out that at no load
condition, reactive power reference should be set to zero .
From the discussion above, the BTM can be easily realized by changing
the reference of droop control from the TNM as well. In this way, the
seamless transfer among different modes can be realized without
affecting the output voltage of the UPS system.
Fig. 9.12 The control strategy of the BTM operation in the on-line UPS system
9.2.4 Small-Signal Modeling and Analysis

From the discussions of Sects. 9.2.2 and 9.2.3, by adjusting the different
reference values, the EEM and the BTM can be achieved with the same
control strategy. The small-signal stability of the EEM and BTM
operation is studied in this section. First, the power low of the UPS
system through a general line impedance is obtained as [19]
(9.32)
(9.33)
where P and Q are the instantaneous active and reactive powers of the
UPS system that lows out of the general line impedance. E and V are
the amplitudes of the inverter output voltage and the common bus
voltage, respectively, and φ is the power angle. Z and θ are the
magnitude and phase of the output impedance.
As the line impedance in UPS applications usually exhibits a
resistive characteristic, the power low of the UPS can be expressed as
follows:
(9.34)
(9.35)
Accordingly, the active and reactive power variation according to

the UPS voltage amplitude and phase angle disturbance can be
obtained by
(9.36)
(9.37)
where the operator Δ indicates a small-signal perturbation around the
UPS’s operating equilibrium point.
When there are some power luctuation during the EEM or the BTM,
expanding the proposed control strategy in (9.28)–(9.29) or (9.30)–
(9.31) results in the small-signal responses of the UPS voltage, which
are expressed as
(9.38)
(9.39)
(9.40)
(9.41)
where τ is the time constant of the low-pass ilter in the active and
reactive power calculation.
Considering that , and by the simple manipulation of
(9.36)–(9.37), the dynamic performance of the UPS system in the EEM
or BTM operation yields the following expression:
(9.42)
where
The eigenvalues of (9.42) show the small-signal response of the

UPS system during EEM and BTM. In addition, notice that when k = 0,
the matrix N 2×2 is expressed as
(9.43)
and the corresponding matrix of (9.43) indicates the behavior of the

UPS system in the TNM and PNM operations.
The performance of the system with the different values of the
parameter k is evaluated and shown in Fig. 9.13. With UPS system
parameters listed in Table 9.1, Fig. 9.13 shows the root locus of the
proposed control strategy, where the droop control coef icient is ixed,
while the parameter k varies from 0.0033 to 0.0213. As illustrated, it is
a fourth-order system, and dynamic performance is mainly determined
by the dominant poles of λ 1 and λ 4. It can be observed that when k is
increased from 0.0033 to 0.0213, the system stability is improved but
has a underdamping response. Therefore, the selection of parameter k
involves a tradeoff between the system stability and the damping
response. In order to obtain the satis ied system damping and stability
performance, the parameter k is selected as 0.007.
Fig. 9.13 Root locus with the proposed control strategy when the parameter changes: 0.0033 < k
< 0.0213

In order to validate the feasibility of the proposed DC-link voltage
control strategy and multi-mode operation of the on-line UPS system,
the system diagram shown in Fig. 9.8 is built up and shown in Fig. 9.14.
The setup consists of an AC/DC converter, a DC/AC inverter, PV unit,
and the bypass switch. The DC bus is formed by the DC-link capacitors.
Fig. 9.14 Con iguration of the setup
The control algorithm is implemented in dSPACE 1006 platform for

real-time control. System parameters are listed in Table 9.1.
Waveforms are captured by the oscilloscope.
9.3.1 DC-Link Voltage Control Strategy
First, the effectiveness of the proposed IMC-based DC-link voltage
control strategy is veri ied by using the AC/DC converter of the setup in
Fig. 9.14. The PR controller is employed for inner loop current tracking,
while the two-port IMC-based DC-link voltage controller is
implemented for the DC-link voltage regulation (see Fig. 9.2). To
further highlight the effectiveness of the proposed method,
experimental comparisons are conducted among the traditional PI-
based DC-link voltage controller, standard IMC-based control strategy,
and the proposed IMC-based DC-link voltage controller with the same
closed-loop bandwidth [10]. In the experiment, the DC-link voltage
reference is set to be 500 V. A 230 Ω resistive load is connected to the
DC link to examine the controller’s performance from no load to full
load condition. This load is suddenly connected to the DC link to
examine the controller’s disturbance rejection ability. In addition, to
emulate the variation of the DC-link capacitance, a different value of
capacitance 0.0022 F is considered as the equivalent capacitance
change as well.
First, the DC-link capacitance is 0.0011 F; the disturbance is
generated by disconnecting a 230 Ω resistor from the DC link; the DC-
link voltage performances under the PI control strategy, standard IMC
control strategy, and the proposed IMC control strategy are compared
in Fig. 9.15 and summarized in Table 9.2. Speci ically, it is observed that
with PI control strategy, the voltage drop is 60 V with is of recovery
time. By applying standard IMC control strategy to the DC-link voltage
regulation, the voltage drop has reduced to 40 V with almost the same
recovery time. On the contrary, when the proposed two-port IMC-based
control strategy is applied in the DC-link voltage regulation, the voltage
drop reduced to 37 V with 0.6 s recovery time. Then, the DC-link
capacitance has changed to 0.0022 F to emulate the DC-link
capacitance variation. By employing the PI control strategy, the voltage
drop on the DC link is 50 V with 0.8 s recovery time with. Meanwhile,
when the standard IMC control strategy is applied to the DC-link
regulation, the voltage drop reduced to 30 V with the recovery time of
0.6 s. Finally, when the proposed control strategy is implemented in the
DC link, the voltage drop is the same as that with standard IMC control
strategy, but the recovery time has shortened to 0.4 s.
Fig. 9.15 The performance of PI controller and standard IMC control strategy and proposed IMC
control strategy under load disturbance
Table 9.2 Comparison among the different control strategy in response to the load step
Method Voltage drop Value

PI control strategy (1100 μF) 60 V 1s
Standard IMC (1100 μF) 40 V 1s
Proposed IMC (1100 μF) 37 V 0.6 s
PI control strategy (2200 μF) 50 V 0.8 s
Standard IMC (2200 μF) 30 V 0.6 s
Proposed IMC (2200 μF) 30 V 0.4 s
In general, the two-port IMC-based control strategy shown in this

chapter can reduce the voltage drop and the recovery time under
disturbances signi icantly compared to the other two methods.
9.3.2 Multi-mode Operation of the On-line UPS System

(1) Transition Between the TNM and PNM Operations of the On-line UPS
System In this section, the schematic diagram with the proposed
control strategy in Fig. 9.8 is tested with the setup in Fig. 9.14. Figure
9.16 shows the active and reactive power waveforms between the TNM
and PNM operations. As can be observed in Fig. 9.16, the load active
and reactive powers are, respectively, Pload = 700 W and Qload = 120 Var.
At the TNM operation, the active power delivered from the grid is Pin =
800 W (blue waveform). Notice that the difference between P in and P
load is caused by the power loss in the UPS system. When the operation
mode shifts to the PNM from TNM, the PV output active power is 250 W
(cyan waveform), so the active power delivery from the grid drops to
the 550 W. When the PV is unavailable, the operation of UPS system
returns to the TNM again, and the active power delivery from the grid
increases to 800 W again, as shown in Fig. 9.16. Meanwhile, it is
observed that the load active power and reactive power (green
waveform and purple waveform) do not change during the transition.
Finally, the load voltage waveform during the transition is shown in Fig.
9.17, where the load voltage is uninterruptible during the transition.
Fig. 9.16 Active and reactive powers in transfer between the TNM and PNM operations
Fig. 9.17 Load voltage in transfer between the TNM and PNM operations
(2) Transition between the TNM and EEM Operations of the On-line UPS
System In this test, the seamless transition between the TNM and the
EEM is evaluated. As shown in Fig. 9.18a, when the operation mode of
the UPS shifts from TNM to EEM, the load active power provided by the
inverter drops to zero (blue waveform), and the 520 W of active power
is directly provided by the grid through the bypass switch (purple
waveform). Meanwhile, the reactive power is still powered by the
inverter (cyan waveform). On the contrary, when the operation mode
of the UPS shifts from the EEM to the TNM, the load active power is
delivered from the inverter, and the active power goes through the
bypass switch decreased to zero. Figure 9.18b and c show the load
voltage waveforms during the transition, it is indicated that the
seamless.
Fig. 9.18 Waveform of transition between the traditional normal mode and the enhanced eco-
mode. (a) Overall waveform; (b) zoomed-in waveform from the traditional normal mode to the
enhanced eco-mode; (c) zoomed-in waveform from enhanced eco-mode to the traditional normal
mode
(3) Transition Between the Traditional Normal Mode and the Burn-in Test
Mode of the On-line UPS System
(a)
Case 1: No Load Condition.
Under no load conditions, the UPS system should feed back the energy
drawn from the grid by the inverter when switching from normal to
burn-in test mode. In case 1, the inverter’s output active power is set to
500 W (blue waveform), and since all loads are connected to the UPS
system, the 500 W of output active power is fed back into the grid by
the bypass switch (Fig. 9.19a). Meanwhile, the load voltage during the
transition is shown in Fig. 9.19b and c, where it is observed that the
seamless transition is realized as the output voltage has no abrupt
change in voltage amplitude and frequency.
(b)
Case 2: R–L Load Is Connected During the Transition
Fig. 9.19 Waveform of transition between the traditional normal mode and the burn-in
test mode at no load condition. (a) Overall waveform; (b) zoomed-in waveform from the
traditional normal mode to the burn-in test mode; (c) zoomed-in waveform from the burn-
in test mode to the traditional normal mode
When the R–L load with 550 W of active power and 120 Var of reactive
power connecting at the UPS system, as can be seen in Fig. 9.20 that the
inverter provides the load power. When the UPS system transfers its
working mode from TNM to BTM, the active power drawn by the
inverter is set to be 850 W (blue waveform), and the extra 300 W of
output active power is fed back into the grid through the bypass switch
(Fig. 9.20a purple waveform). Meanwhile, the load voltage during the
transition is shown in Fig. 9.20b and c, where it is observed that the
seamless transition is realized as the output voltage has no abrupt
change in voltage amplitude and frequency.
Fig. 9.20 Waveform of transition between the traditional normal mode and the burn-in test mode
at R–L load condition. (a) Overall waveform; (b) zoomed-in waveform from the traditional
normal mode to the enhanced eco-mode; (c) zoomed-in waveform from enhanced eco-mode to
the traditional normal mode.
9.4 Conclusion
An on-line UPS system with multiple modes of operations is presented
in this chapter. The sensor-less IMC-based DC-link voltage control
strategy has been presented to provide a robust power delivery in
multi-mode operation. To achieve seamless transition among the
different modes of operations, we present some strategies for PV-aided
normal mode, enhanced eco-mode, and the burn-in test mode. By
utilizing these three modes, the cost charged from the grid can be
greatly reduced. Additionally, these modes of operations can be easily
achieved by adjusting the reference value of the inverter within the on-
line UPS system. Experiments proved that the proposed strategies are
effective.
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https://doi.org/10.1007/978-3-031-22178-1_10
10. AC Microgrid Seamless Transition

Xiaochao Hou1 , Jinghang Lu2 and Yao Sun3
(1) Tsinghua University, Beijing, China
(3) Information Science and Engineering, Central South University,
Changsha, China
Xiaochao Hou
Email: houxiaochao@tsinghua.edu.cn
Jinghang Lu (Corresponding author)

Keywords Distributed coordination – Hierarchical control –

Microgrid – Seamless transition
10.1 Different Control Modes for the UPS

System
10.1.1 Physical and Control Structure of AC Microgrid
Figure 10.1 shows the typical topology of an AC microgrid, including
buses, transmission lines, and loads. The distributed communication
cyber overlays the physical power network. Each DG is only allowed to
communicate with its neighbors. Furthermore, at least one spanning
tree should be used to connect all the DGs to this distributed
communication network. Distributed control differs from central
control in that it uses sparse communication.
Fig. 10.1 AC microgrid with a sparse distributed communication network
For PCC and utility-grid connections, a static transfer switch is

required. By default, the microgrid works with STS= 1 when it is
connected to the grid. As soon as the power quality of the utility grid
fails to meet the operation criteria, the STS goes to 0, and an islanded
microgrid is formed. The active synchronization algorithm will be
activated after the utility grid is restored in order to connect the
microgrid to it again. It is important to achieve seamless transitions
between the two modes in order to ensure uninterruptible power
supplies and reduce rush currents.
In Fig. 10.1, DGs are divided into two types: leader DGs and follower
DGs. The leader DGs are chosen with a higher power rating and
installed close to the PCC. Most of the rest DGs work as follower DGs.
A mode-supervision controller is installed around the STS. The
compensation signals are sent to a few DGs near PCC, while the
remaining DGs exchange them with their neighbor DGs by using
distributed control. This prevents the failure of a communication node
from affecting the normal operation of the microgrid, in contrast to
traditional centralized control systems. Thus, the reliability and
stability of the microgrid are increased greatly. Furthermore, the
communication burden of tertiary control is greatly reduced by using
the proposed mode-supervisory controller. This tertiary mode of
supervisory control is not a traditional centralized control. Different
compensation signals are dictated based on the STS status to
accomplish control targets in four modes (GC mode, IS mode, and
transitions between them). Lastly, all DGs are responsible for achieving
the common consensus objects prescribed by the mode-supervisory
controller.
10.1.2 Control Targets Under Different Modes

These control targets are summarized under different operating states
of the GC, IS, and mode transitions [1–4]:
Accurate load power sharing in IS mode.
It is important to share load power demand among DGs in
accordance with their power capacities.
Excellent voltage/frequency quality in IS mode.
The voltage/frequency deviations caused by droop control
should be restored to ensure a satisfactory voltage quality.
Adjustable grid-injected power low in GC mode.
Grid-injected power needs to be lexible between microgrid and
utility grid, and it should be insensitive to grid-voltage luctuations.
Seamless transition from GC mode to IS mode.
In order to reduce the need for recon iguring the control
structure from GC to IS mode, a uni ied control strategy must be
developed.
Desired synchronization from IS mode to GC mode.
During pre-synchronization, a smooth transition should be
enabled for zero-inrush current.
As shown in Fig. 10.2, the above performance should be considered
from a systematic point of view for the four modes of operation.
Fig. 10.2 Control targets of four modes
10.2 Proposed Distributed Hierarchical

Control
The overall control block diagram of the proposed distributed
hierarchical control is shown in Fig. 10.3. This control scheme has
three main control levels: (i) the primary control scheme has three
main control levels: (ii) the primary control; (iii) the tertiary mode-
supervisory control.
Fig. 10.3 Proposed distributed hierarchical control scheme (leader DG-k; follower DG-i)
10.2.1 Primary Droop Control for Inverter-Based DGs

To proportionately share the load power demand and support the
frequency/voltage stability, the conventional droop control is a main
technique with local information feedback [5, 6].
(10.1)
(10.2)
where ω i and V i are the angular frequency and voltage amplitude
references of an inverter-based i-th DG, respectively. ω ∗ and V ∗ imply
the values of ω and V at no load. P i and Q i are output active power and
reactive power of i-th DG. m and n are droop coef icients of P − ω and Q
− V control, respectively.
Figure 10.4 illustrates a typical control scheme of an inverter-based
DG, which consists of three control loops: the dip loop, the voltage loop,
and the current loop. In addition, a virtual-impedance control is used to
ensure a largely inductive output impedance [6].
Fig. 10.4 A typical control scheme of an inverter-based DG
10.2.2 Secondary Distributed Leader–Follower Control

There are two parts to distributed coordination: frequency consensus
and voltage consensus.
For inverter-based DG-i, the frequency-active power control is
designed by combining primary frequency-droop and secondary
frequency control as
(10.3)
(10.4)
where Δω i is an additional regulation term for the primary droop

control in (10.3). Equation (10.4) is a secondary distributed frequency
control. a ij represents a distributed communication link. If there is an
adjacency communication link from DG-j to DG-i, a ij = 1 is set. If DG-i is
chosen as a leader-DG, γ i = 1; Otherwise, γ i = 0. Δω ∗ is a compensation
signal from tertiary mode-supervisory control. k ω is a positive control
gain, which can adjust the response speed of the secondary frequency
control.
From (10.4), Δω i = Δω j = Δω ∗ in steady state, which implies that a
uniform frequency shifting is obtained for all DGs. Figure 10.5 exhibits
the primary frequency-droop control before and after the secondary
distributed control for two DGs. From Fig. 10.5, the secondary
distributed control action can be regarded as a frequency recovery
with a shifting of Δω i.
Fig. 10.5 A uniform frequency shifting for primary droop control
For inverter-based DG-i, the voltage-reactive power control is

constructed by combining primary voltage-droop and secondary
distributed-voltage control as
(10.5)
(10.6)
where (10.6) is a secondary distributed-voltage control. b ij represents

a distributed communication link. k v is a positive control gain. ΔV ∗ is a
voltage compensation signal from tertiary mode-supervisory control.
For a leader DG-k, β k = 1 and b kj = 0. While for rest follower DGs, β i = 0
and b ij = 1. That is, only leader DG-k is responsible for the PCC voltage,
and other follower DGs participate in reactive-power sharing.
Figure 10.6 depicts the reactive-power sharing under Q − V droop
control before and after combining the secondary distributed-voltage
control for two DGs [7]. Since the mismatch line impedances X line−1 > X
line−2, reactive power is not shared under the primary voltage-droop
control. But, with the help of the secondary distributed-voltage control,
in steady state from (10.6), which implies that
accurate reactive power sharing is obtained among all DGs.
Fig. 10.6 Reactive power sharing under Q–V droop control
10.2.3 Tertiary Mode-Supervisory Control

The tertiary mode-supervisory control aims to manage different
operation modes and prescribe the compensation signals Δω ∗, ΔV ∗ for
secondary control of leader DGs. As shown in Fig. 10.7, mode-
supervisory controller is meant to automatically select the different
input signals according to the status of the STS (1 means ON; 0 means
OFF):
1. If microgrid works in islanded mode (IS), STS is 0.
Fig. 10.7 The mode-supervisory controller
2.
If microgrid works in grid-connected (GC) mode, STS is 1.
3. Microgrid works by mode transitioning from GC mode to IS mode
by disconnecting microgrid from utility grid due to grid fault,
switching STS from 1 to 0.
4.
As soon as the microgrid is connected back to the utility grid after
fault clearing, STS changes from 0 to 1.
Control Compensation Signals Δ ω ∗ , Δ V ∗ in IS Mode.
In IS mode, the compensation signals Δω ∗ and ΔV ∗ are set as
follows in order to restore the voltage/frequency amplitudes
(10.7)
where ω c and V c are the angular frequency and voltage amplitude of

PCC. ω n and V n are system nominal angular frequency and voltage
references. k pω1 and k iω1 are proportional-integral (PI) coef icients
of frequency-recovery control. k pv1 and k iv1 are PI coef icients of
voltage-recovery control.
Control Compensation Signals Δ ω ∗ , Δ V ∗ in GC Mode.
In GC mode, to lexibly manage the grid-injected active/reactive
power, the control compensation signals Δω ∗ and ΔV ∗ are designed
(10.8)
where P g and Q g are the calculated active and reactive powers

injected into utility grid in real time. P ∗ and Q ∗ are the grid-injected
active and reactive power references. k pω2 and k iω2 are PI
coef icients of active power control. k pv2 and k iv2 are PI coef icients
of reactive power control.
Control Compensation Signals Δ ω ∗ , Δ V ∗ in AS Mode.
A seamless transition from IS mode to GC mode requires the PCC
to synchronize the voltage amplitude, frequency, and phase of power
with the utility grid during active synchronization (AS). Thus, the
active synchronization compensation signals Δω ∗ and ΔV ∗ are given
by
(10.9)
where v gα and v gβ are the direct-/quadrature-axis voltage

components of utility grid. V g and δ g are the voltage amplitude and
phase of utility grid. v cα and v cβ are the direct-/quadrature-axis
voltage components of PCC. V c and δ c are the voltage amplitude and
phase of PCC. k pω3 and k iω3 are PI coef icients of voltage-phase pre-
synchronization control. k pv3 and k iv3 are PI coef icients of voltage-
amplitude pre-synchronization control.
It is worth noting that all control compensation signals Δω ∗ and
ΔV ∗ are derived by PI controllers, which are slow-dynamic averaged
values. As a result, these two DC components can only be modi ied
within a small range in several switching cycles [8], after which they
can be sent from the mode-supervisory controller to the leader DGs
via a low-bandwidth communication. The execution speed can reach
at 5Mb∕s with optical iber [9].
10.3 Stability Analysis

An eigenvalue analysis and a small-signal model are used in this
section to discuss system stability and control parameters of
distributed hierarchical control. Generally, the line impedance is mainly
inductive [6]. Therefore, active power is largely dependent on the
power angle, while reactive power depends mostly on voltage-
amplitude difference. To facilitate their individual designs, stability
analysis of P − ω and Q − V can be decoupled [10, 11].
10.3.1 Power Angle Stability Analysis

(1) Overall System Model of P-ω Control The frequency control
dynamics of multiple parallel DGs connected to a PCC can typically be
obtained from (10.3)
(10.10)
where the delivered active power is calculated as [6]
(10.11)
(10.12)
where V i and δ i are output voltage amplitude and angle of DG-i. V c and
δ c are voltage amplitude and angle of PCC. X i is the linking reactance
between i-th DG and PCC.
In (10.10), Δω i is presented as follows from (10.4):
(10.13)
where Δω ∗ is the control compensation signal, derived from the

tertiary mode-supervisory controller (10.7)–(10.9)
(10.14)
where
(10.15)
where V g, δ g, ω g are the voltage amplitude, angle, and angular

frequency of utility grid. X g is the grid reactance between PCC and
utility grid. is the nominal voltage angle reference of PCC in the grid-
connected mode.
In addition, according to the system constraint of supply demand
power balance, (10.16) is presented
(10.16)
where P L implies an active power value of total load demand.
(2) Linearization of Overall System Model As the power angle

is always small in microgrid, and
. Then, the linearization of the overall system model is
conducted:
(i) Linearization of Primary Droop Control (10.10)
(10.17)
where
(10.18)
(ii) Linearization of Secondary Distributed Control (10.13)

(10.19)
where
(10.20)
(iii) Linearization of Tertiary Control (10.14)–(10.15)
(10.21)
From (10.21), a uni ied form of Δω ∗ is obtained for both GC mode

and AS mode
(10.22)
where
(10.23)
Only the stability analysis of GC and AS modes (10.22) is presented

here for simplicity. The same analysis can also be applied to the IS
mode in (10.21).
(iv) Linearization of System Constraint (10.16)
(10.24)
(v) System State-Space Model of P-ω Control For the tracking phase
synchronization, a new state variable is set to facilitate the stability
analysis.
(10.25)
The system linearization is given by combining (10.17)–(10.24)
(10.26)
where
(10.27)
The state-space equations of the power angle stability are

presented as
(10.28)
where
(10.29)
(10.30)
where
(10.31)
(3) Eigenvalue Analysis of Aω To test the stability of the proposed
active power-frequency control scheme, the eigenvalues analysis of
matrix A ω is applied. According to the simulation system described in
Sect. 10.5, the root-locus plots are studied by varying the secondary
control gain k ω of (10.4) and tertiary PI control coef icients k pω, k iω of
(10.23).
Figure 10.8a shows the root-locus diagram as k ω increases from
0.1 to 10. As seen, the poles λ 1 and λ 2 are gradually moved to the
imaginary axis, which might lead to a poor dynamic response and even
instability. Therefore, k ω should choose a relatively small value.
Fig. 10.8 Root locus of system matrix A ω. (a) 0.1 < k ω < 10; (b) 0.3k pω < 10; (c) 0k iω < 10
Figure 10.8b depicts the root-locus diagram as k pω increases from

0.3 to 10. From (10.23), it also means 6e−7 < k pω2 < 2e−5 and 3e−6 < k pω3
< 1e−4. When k pω is small, λ 1 and λ 2 are the dominant poles. With
increasing k pω, λ 1 and λ 2 move away from the imaginary axis, and λ 3
moves close to the imaginary axis. To obtain a ine damping ratio of the
system, k pω = 5 is set in the simulation.
Figure 10.8c presents the root-locus diagram as k iω increases from
0 to 10. From (10.23), it also means 0 < k iω2 < 2e−5 and 0 < k iω3 < 1e−4.
When k iω increases, λ 1 and λ 2 turn into the dominant complex
conjugate poles, resulting in a second-order dynamic behavior.
However, a too large k iω would make the system easy to be unstable.
Thus, k iω = 0.5 is set in the simulation.
10.3.2 Voltage Stability Analysis

(1) Overall System Model of Q–V Control For multiple DGs connected to
PCC, their Q–V control dynamics are obtained from (10.5)
(10.32)
where
(10.33)
where V i and V c are the voltage amplitudes of i-th DG and PCC. X i is the
line reactance between i-th DG and PCC.
In (10.32), ΔV i is presented as follows from (10.6)
(10.34)
In (10.32), ΔV ∗ is the voltage control compensation signal, derived
from the tertiary mode-supervisory controller (10.7)–(10.9)
(10.35)
where
(10.36)
where is the nominal voltage amplitude reference of PCC in GC

mode.
Moreover, according to the system constraint of supply–demand
power balance, (10.37) is presented
(10.37)
where Q L implies a reactive power value of total load demand.
(2) Linearization of Overall System Model (i) Linearization of Primary

Droop Control (10.32)–(10.33)
(10.38)
(10.39)
where
(10.40)
(ii) Linearization of Secondary Distributed Control (10.34)
(10.41)
where
(10.42)
(iii) Linearization of Tertiary Mode-Supervisory Control (10.35)–

(10.36)
(10.43)
where
(10.44)
From (10.21), a uni ied form of ΔV ∗ is obtained for IS mode, GC

mode, and AS mode
(10.45)
where
(10.46)
(iv) Linearization of System Constraint (10.37)

(10.47)
Then,
(10.48)
where
(10.49)
(v) System State Space of Q–V Control The entire system linearization
is given from (10.38)–(10.49)
(10.50)
In this chapter, given
(10.51)
(10.52)
where
(10.53)
(3) Eigenvalue Analysis of AV To test the stability of the proposed Q −

V control scheme, the eigenvalues analysis of matrix AV is applied.
According to the simulation system in Sect. 10.5, the root-locus plots
are studied in Fig. 10.9 by varying the secondary control gain k v of
(10.6) and tertiary PI control coef icients k pv, k iv of (10.46).
Fig. 10.9 Root locus of system matrix Av. (a) 1e −3 < k v < 5; (b) 0.1 < k pv < 10; (c) 0.1 < k iv < 5
Figure 10.9 shows that the system dominant pole λ 1 is mainly

affected by k pv and k iv in Fig. 10.9b–c. With increasing k pv, λ 1 moves
close to the imaginary axis. On the contrary, increasing k iv makes λ 1
move away from the imaginary axis. To guarantee a satisfactory
dynamic response, k pv should choose a relatively small value, and k iv
should choose a relatively large value. In the simulation, k x=0.01, k
pk=2, and k jx=1 are set by consideration of the system dynamic
stability. Then, k pv1, k pv2, k pv3 and k iv1, k iv2, k iv3 are derived from the
equivalence relation in (10.46).

Simulations in the time domain verify the proposed distributed
hierarchical control. Table 10.1 lists the simulation parameters. Figure
10.3 shows the overall control scheme. Figure 10.10 shows a typical
4buses/4DGs microgrid con iguration, which has been widely studied
in microgrid case studies [8, 12–18]. Therefore, this con iguration can
represent the multibus/multi-DG microgrid system. The system
includes four inverter-based DGs (DG1 ∼ DG4), four independent local
loads , and a public load L 0. DG1 is chosen as the leader-DG
and acquires control compensation signals from the mode-supervisory
controller. DG2 ∼ DG3 are the follower DGs. From Fig. 10.10, the
associated adjacency matrices and are given by
(10.54)
Fig. 10.10 Simulated microgrid physical and communication models
Table 10.1 Comparison among the different control strategy in response to the load step
Parameters Symbol Value

Nominal voltage Vn 311 V
Nominal frequency fn 50 Hz
Line impedance Z 01 0.8 + j1.0 Ω

Grid impedance Xg j0.2 Ω
Parameters Symbol Value
Loads L 1 = L 2 = L 3 = L 4 P = 2 kW, Q = 2 kVar
Load L 0 P = 2 kW, Q = 2 kVar

P − ω droop coef icient mi 10−5
Q − V droop coef icient ni 10−3
Frequency control gain kω 0.1
Voltage control gain kv 0.01
Rated grid-injected active power P∗ 10 kW
Rated grid-injected reactive power Q ∗ 3 kVar
Frequency proportional term k pω 5

Frequency integral term k iω 0.5
Voltage proportional term k pv 2
Voltage integral term k iv 1
10.4.1 Case 1: Seamless Transition from GC Mode to IS

Mode
Under the distributed hierarchical control, this case switches from GC
mode to IS mode. Figures 10.11 and 10.12 show the simulation results
of case 1. Before t = 1 s, the microgrid operates in GC mode normally.
Due to the grid fault, the STS switches from ON to OFF at t = 1 s, and the
microgrid disconnects from the utility grid. As soon as time = 1 s
passes, the microgrid transitions from GC mode to IS mode, and the
tertiary mode-supervisory controller automatically switches to the
islanded-mode input signal.
Fig. 10.11 Results in case 1: (a) active-power-injected grid; (b) reactive-power-injected grid; (c)
grid current; (d) PCC frequency; (e) instantaneous PCC voltage; (f) PCC voltage amplitude
Fig. 10.12 Results of four DGs in case 1: (a) voltage amplitudes; (b) frequencies; (c) output
active power; (d) output reactive power
From Fig. 10.11a–b, the injected active and reactive powers into the
utility grid are P g = P ∗ = 10 kW and Q g = Q ∗ = 3 kVar at the beginning of
GC mode. After t = 1 s, the islanded microgrid is formed
and . In IS mode, Fig. 10.11d and f reveals that a nominal
system operation frequency and rated voltage amplitude
of are guaranteed in steady state. Moreover, Fig.
10.11c presents the grid-injected current, and Fig. 10.11e gives the
instantaneous voltage of PCC during t = 0.6 s∼1.4 s.
The simulation results of four DGs are shown in Fig. 10.12. From
Fig. 10.12a–b, DG1 ∼ DG4 achieve a seamless transition between GC
and IS modes with a satis ied voltage and frequency transition process.
Moreover, as seen in Fig. 10.12c–d, there is an accurate power sharing
between four DGs whether in GC or IS mode.
According to case 1, the proposed distributed hierarchical control
achieves all the required control targets and performances in both GC
and IS modes and under mode transitions from GC to IS.
10.4.2 Case 2: Active Synchronization from IS Mode to GC
Mode
In case 2, the proposed distributed hierarchical control scheme is
validated during the active synchronization (AS) from IS mode to GC
mode. The simulation results for case 2 are shown in Fig. 10.13.
Fig. 10.13 Results in case 2: (a) DGs voltage amplitudes; (b) DGs frequencies; (c) voltage
difference between grid and PCC; (d) voltage amplitudes of grid and PCC; (e) frequencies of grid
and PCC; (f) difference of frequency; (g) difference of phase angle; (h) grid current
Initially, the microgrid is disconnected from the utility grid and

operates as an island. Meanwhile, the tertiary mode-supervisory
controller chooses the control input signals of islanded mode.
A tertiary mode-supervisory controller switches to the active
synchronization control input signals at t = 1 s after grid-fault clearing,
and active synchronization control is initiated.
After few seconds, the frequency error between grid and PCC in Fig.
10.13f, phase angle error in Fig. 10.13g, and amplitude difference in Fig.
10.13d meet the microgrid synchronization criterion [19] at t = 2.7 s,
and STS switches from OFF to ON. The microgrid is reconnected to
utility grid in GC mode.
As seen in Fig. 10.13c, when active synchronization control is
activated, the voltage differences Δv between PCC and grid decrease
rapidly. At t = 2.7 s when the voltage of PCC meets the synchronization
criteria, the instantaneous voltage difference would be almost zero.
After closing STS, the instantaneous grid currents in Fig. 10.13h are
very small and mostly no current inrush. Thus, a seamless active
synchronization is attained. Moreover, Fig. 10.13a and b reveals that
output voltage amplitudes and frequencies of four DGs always lie in the
permissible ranges during the mode transition from IS mode to GC
mode, which veri ies the effectiveness of the proposed distributed
hierarchical control framework.
10.4.3 Case 3: Communication-Link-Failure Resiliency in

Active Synchronization Mode
Resiliency to a single communication-link failure is considered in
active synchronization mode as shown in Fig. 10.14. Compared with
case 2, the simulation process is similar, while the communication link
between DG2 and DG3 fails in Fig. 10.10. As there is also a spanning
tree between each DG and the tertiary mode-supervisory controller
after one link 2–3 failure, the proposed distributed hierarchical control
can remain operational. As seen in Fig. 10.14, the link 2–3 failure does
not impact on seamless transition from IS mode to GC mode, and a
satisfactory performance is guaranteed. It should be noted that the
recon iguration caused by the link failure just affects the Laplacian
matrix and dynamic response but not the steady-state performances.
Fig. 10.14 Results in case 3: (a) DGs voltage amplitudes; (b) DGs frequencies; (c) voltage
difference between grid and PCC; (d) grid current
In contrast, any link failure in the central-standard hierarchical

control [8, 12] would interrupt the information low and result in an
abnormal microgrid system. Therefore, the centralized-star-
communication network is vulnerable to the failure of a single point,
which limits its use for a practical multibus microgrid. Additionally,
with a sparse distributed communication network, the proposed
distributed hierarchical control overcomes the single-point failure.
Therefore, the proposed method provides higher communication
reliability than standard hierarchical control systems [8, 12].
10.4.4 Case 4: Plug-and-Play Capability in GC Mode

The proposed distributed hierarchical control scheme can
accommodate a plug-and-play and scalability environment so that new
DG can be augmented to the system. Figure 10.15 shows the
performance when DG5 plugs at t = 1 s and fails at t = 2 s, connected in
bus 4 of Fig. 10.10. A spanning tree still exists for the new graph, as the
DG5 gets its communication signal from the DG4. Meanwhile, since the
tertiary mode-supervisory controller was already pinning to DG4
before adding DG5, it is not necessary to direct pin DG5 to the tertiary
controller.
Fig. 10.15 Results of ive DGs in case 4: (a) output active power; (b) output reactive power; (c)
frequencies; (d) voltage amplitudes
As seen, DG5 becomes automatically synchronized with the existing

DG1∼DG4 in Fig. 10.15c, and the accurate power sharing has been
updated in Fig. 10.15a–b when DG5 comes into the system. Then, if DG5
fails at t = 2 s, DG5 can be disconnected from the rest system, and the
remaining control system is still functional. The proposed distributed
hierarchical control also readjusts the power sharing among the
remaining DG1∼DG4. Simultaneously, the output voltage amplitudes
are also regulated accordingly in Fig. 10.15d.
10.5 Conclusions
Our study presents a distributed hierarchical control scheme for AC
microgrids that takes into account all possible operating modes. It can
operate in both grid-connected modes, islanded mode and seamless
transition modes between them. The proposed control combines the
primary droop control, secondary distributed leader–follower control,
and tertiary mode-supervisory control. The mode-supervisory
controller at the top of the mode hierarchy provides compensation
signals to only a few DGs near the PCC. By using distributed consensus
protocol, the rest of the follower DGs would exchange information with
their neighbors. Finally, all DGs reach an agreement and achieve their
group targets in different ways. Overall, all major control targets are
met, and this method offers a cost-effective approach to building a
practical microgrid.
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Index
A
Active power sharing 57, 83, 109–111, 113–115,
121–122, 129, 130, 136
Adaptive virtual impedance 45–76, 110, 111
Anti-windup 28, 85, 132–135, 142, 148, 149, 153, 176
B
Burn-in test mode 182–183, 192–194
C
CAN bus 79, 85, 95, 98–99
Circulating current 47, 57, 59, 64, 75, 91–92, 109, 113114,
121, 122, 128, 129, 138, 139
Consensus control 132, 133, 198, 200, 220
Current sharing 101, 122, 128–132, 134, 135,
138–141
D
DC-link voltage 6, 11–18, 20–24, 26–28,
31–42, 109–111, 119–122,
125–135137–139, 141, 169–176,
186–189, 194
DC-link voltage protection (DCVP) 109–111, 114, 115, 120,
121, 125–135, 137–139, 141
Distributed coordination 200
Distributed secondary control 79–83, 85, 93, 98, 102, 104
Disturbance rejection 20, 39, 171, 173, 174, 188
Droop control 45–48, 111–113, 121, 128, 129, 134,
178, 180182, 199–202, 206, 211, 220
E
Enhanced eco-mode 180–182, 191, 193, 194
Enhanced state observer 32–34
H
Hierarchical control 199–205, 213, 216–221
I
Internal model control (IMC) 169–176, 187–189, 194
M
Microgrid 3–4, 42, 79–106, 132, 197–221
Modular uninterruptible power supply (UPS) system 1, 5–7,
45–76, 79–106, 109–122, 125–142
O
Overcurrent protection 145, 153
Overload 5, 27, 125, 135, 145–163
P
Parallel inverters 47, 48, 92
Power sharing 47, 55, 57, 58, 63, 68, 71–73, 7583, 85, 93, 98,
99, 101, 104, 109111–115, 118, 119, 121–122, 129,
130, 135, 136139, 141, 199, 201, 202, 217, 221
PV-aided normal mode 178–180, 194
R
Reduced-order generalized proportional-integral observer
(RGPIO) 12–17, 20–22, 27, 29
Robustness 16, 36, 42, 173
S
Seamless transfer 182
Seamless transition 4, 177, 180–184, 191, 192, 194,
197–221
Short circuit 130, 145–163
Sliding mode control 11–29
T
Three-phase converter 12, 21, 29, 31–45, 47, 84, 95, 139146,
148, 154, 155, 159, 160, 163, 169
U
Uninterruptible power supply (UPS), v 1–7, 16, 42,
45–76, 79–106, 109–122, 125–142,
145–163169–194, 197–199
V
Virtual impedance 45–76, 80, 81, 91, 92, 147, 200
Virtual resistance 48, 110–117, 119, 122, 128–132,
137, 178
Voltage control 11, 13, 16, 17, 31–42, 125, 135,
147169–176, 186–189, 194, 201, 202, 209, 215
Voltage source inverter (VSI) 45–76, 145–163

Advanced Control and Protection of Modular UPS

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Advanced Control and Protection of Modular UPS

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Power Systems

Electrical power has been the technological foundation of industrial

Advanced Control and Protection of

ISSN 1612-1287 e-ISSN 1860-4676

© The Editor(s) (if applicable) and The Author(s), under exclusive

The use of general descriptive names, registered names, trademarks,

This Springer imprint is published by the registered company Springer

1.1 Uninterruptible Power Supply

1.1.1 Off-line UPS System

Fig. 1.1 Block diagram of off-line UPS system

1.1.2 Line-Interactive UPS System

Fig. 1.2 Block diagram of line-interactive UPS system

1.1.2.2 Flexible Microgrid Based on Line-Interactive UPS

1.1.3 On-line UPS System

In the normal mode of operation, the load power is continuously

1.2 Modular UPS

Overall, no matter which structure is selected, these two modular

1.3 Organization of This Book

2. An RGPI Observer-Based Resonant

Keywords Disturbance rejection – Reduced-order generalized

2.1 Modeling of The AC/DC Converter

Fig. 2.1 Con iguration of a grid-connected power converter

where V DC is the DC-link voltage, C is the DC-link capacitance, P DC = V

where f total denotes the lumped disturbance, including the external

By rewriting (2.6), the following equations are derived:

where is the reduced-order GPIO gain, and z 2 andz 3 are the

estimated values of x 2 and x 3. In Eq. (2.9), the variable cannot be

hand side of the equation, meanwhile, by adding and subtracting the

Based on (2.10), it can be observed that signals f total and can

2.2.2 System Stability Analysis

In (2.11), it can be observed that the system will be Hurwitz stable

2.2.3 Frequency Domain Analysis for the RGPIO

After replacing k 1 = 2ω 0 and into (2.14), the RGPIO is

Equation (2.15) can be converted into transfer functions by taking

As z 2 − k 1 x 1 = ξ 2 and , k 1 = 2ω 0. Therefore, by combing

As a result of Eq. (2.18), within the RGPIO’s bandwidth ω 0, the

According to (2.19), the original plant is converted into an ideal

2.2.4 Evaluation of the System Robustness Against

2.2.5 DC-Link Voltage Controller

Following the above discussion, it can be concluded that the

2.3 The Inner Loop RST-SMC Based Current

It is noted that the active power reference ( ) is generated from

2.3.1 Super-Twisting Control

2.3.2 Current Tracking Loop

where σ αβ = [σ α σ β]T. The time derivative of the above Lyapunov

According to Eqs. (2.1), (2.32), and (2.33), the time derivative of σ

Therefore, as long as choosing an appropriate positive value of A

In addition, in order to reject grid voltage disturbance and achieve

where parameters A and B are selected according to Eqs. (2.28)–(2.30).

Fig. 2.5 Block diagram of the details of proposed RST-SMC

The performance of the current controller is affected by the

where ΔL represents the inductance’s parameter variation. In addition,

2.4 Simulation Results

2.4.1 Operation Under Load Resistance Variation

2.4.2 Operation with Current Command Step

2.5 Experimental Results

Fig. 2.9 Experimental setup

2.5.2 Dynamic Performance Under DC-Link Voltage

2.5.3 Current Loop Performance with Current Reference

2.5.4 THD of the Current at the Steady State

5. S. Kamran, H. Lennart, N. Hans-Peter, N. Staffan, T. Remus, Design, Control and Application of

7. L. Harnefors, K. Pietilainen, L. Gertmar, Torque-maximizing ield-weakening control: design,

3. An ESO for DC-Link Voltage Control of

Keywords DC-link voltage – Disturbance rejection – Enhanced state