21MHE408L – MEASUREMENT AND DATA ACQUISITION LABORATORY Page No

NAME: DANIEL THOMAS .T.B REG NO: RA2211018010034

EXERCISE 02
INTRODUCTION TO FPGA APPLICATION
DEVELOPMENT

In this exercise we are going to learn about how to create a FPGA file and FPGA
shared library and host main.
TASK 1:-
Connect the myRIO hardware to the PC and open the labview software and
connect the myRIO and go to the FPGA and save the file.
After saving the task was given to construct the circuit which should have the
LED blinking and a the #rd LED should ON when the pause button is pressed.

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The circuit was build and the output of the circuit was observed under the myRIO and
in front panel of the Labview software.
Creating a FPGA Testbench
Open the Labview software and create a new VI and then open a FPGA Module
palette in the block diagram side after placing a FPGA component inside the WHILE
LOOP connect them with the controls and the indicators and add a timer control inside
the while loop.

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Create a FPGA Shared Variables

Open a existing VI and select a project and go to the new variable and create a
new variables like “LED 0, LED 1, PAUSED, PAUSE, STOP, LOOP DELAY” and
add their types LED’s for blinking and pause is a button when it is pressed the LED
paused should glow Loop delay for increasing the count time and stop button is to stop
the whole program.

Create a RT main using a shared variable.

Create a new VI using a my computer and save the file name using the shared
variables drag and drop the variables in the flat sequence.

©DEPARTMENT OF MECHATRONICS ENGINEERING, SRMIST EXERCISE NO.

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Create a Run time in PC

Create a new VI and place the 3 LED’s and push button and stop button and
bound them by right clicking and then go to properties and select the data binding then
select the shared variables and browse the variable which you need select whether it
should be in read mode .
Creating a start up VI
Go to the build specification and select a real time and go to the source files and
select the VI needed. Now the start up VI is created.

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TASK 2:
Write about your key learnings in this laboratory exercise.
1. We learnt how to create a FPGA VI using a FPGA file and make the
LED’s control in the myRIO.
2. From FPGA file how to create a FPGA testbench.
3. TO create a FPGA shared variable.
4. Create a RT main for the same process.
5. Create a host main using the bounding of shared variables.
6. Creating a start up VI.
These are key learnings which were learnt while performing these activity.

©DEPARTMENT OF MECHATRONICS ENGINEERING, SRMIST EXERCISE NO.