ML-based Fast On-Chip Transient Thermal

Simulation for Heterogeneous 2.5D/3D IC Designs

Akhilesh Kumar, Norman Chang, David Geb, Haiyang He, Stephen Pan, Jimin Wen, Saeed Asgari, Mehdi Abarham, Chris Ortiz
email: {FirstName.LastName}@ansys.com
Ansys, San Jose, USA

Abstract— Large 3DIC designs with multiple chips require
several iterations of transient thermal analysis particularly for
fine-grain on-chip dynamic thermal management. This requires
a fast thermal analysis technology as opposed to traditional
CFD/FEA based methods which have severe runtime/capacity
2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) | 978-1-6654-0921-6/22/$31.00 ©2022 IEEE | DOI: 10.1109/VLSI-DAT54769.2022.9768082
usually not on optimal locations as described in [2][3][4] for
SoC designs due to the use of coarse mesh grid on-chip in
chip-package-system transient thermal simulation. However,
for the advanced 7nm/5nm designs such as the Vega 2.0 3DIC
from AMD, there are 64 on-chip thermal sensors in-place as

limitations for large chips (e.g., 2cmx2cm) in 3DIC while shown in Fig. 2. This implies that an accurate transient thermal
generating fine grained (e.g., 10umx10um) transient thermal simulation is needed with fine mesh grid to optimize the
response. The fast transient thermal analysis is based on the idea
placement of on-chip thermal sensors.
of combining the global, intermediate, and local transient
response curves generated from an ML-predictor. The local,
intermediate, and global transient response curves are scaled
based on the far-field and near-field transient decay surface
components respectively, computed using the trained ML decay
surface predictor, followed by linear superposition of the curves
for each power value in the transient power profile to generate
the effective transient response curve. The runtime for
generating thermal results for a large chip is in the order of
minutes, compared to several hours/days while using CFD/FEA
based tools with good accuracy correlation. The fast transient
thermal solver is implemented on distributed ML computing
platform for parallel computation of transient thermal inference
model.

Keywords—Thermal, VLSI, 2.5D/3D-IC, Machine Learning,

Reliability, FEA, CFD
I. INTRODUCTION
With the recently introduced wafer level front-end 3DIC
chip stacking technology as SoIC (System on Integrated Chips)
in Chip-on-Wafer (CoW) or Wafer-on-Wafer (WoW) stackings
that can also be assembled with backend 3DIC technologies such
as Chip on Wafer on Substrate (CoWoS) or Integrated Fan-out
(InFO) as shown in Fig. 1 [1], similar technology roadmap are
also available from other foundries [2].
Figure 2 Many more on-chip thermal sensors are placed in
advanced CPU/GPU 3DIC as the Vega2.0 from AMD for DTM
through fine-grain DVFS control.
Another emerging need on the advanced 3DIC is the early
estimation of transient thermal hotspot with partitions of
power in different chips in 3DIC. Particularly the thermal
interaction is significant in vertically stacked dies as in SoIC
with Chip-on-Wafer or Wafer-on-Wafer stack-up. Therefore,
the architecture-level transient thermal simulation is needed
with the transient power profile of different chips computed
from the vectors generated from emulation as shown in Fig. 3.

Figure 1 Industry trend on integrated frontend + backend holistic

3D heterogeneous integration
Several emerging design optimization techniques on
thermal consideration are needed for the new generation of
3DIC with closely packed chips and strong thermal interaction
among them. The most important one is the use of Dynamic
Thermal Management (DTM) with thermal throttling via
DVFS (Dynamic Voltage Frequency Scaling) techniques.
Traditionally, very few thermal sensors on-chip are placed and
XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE
Figure 3 Architecture-level fast transient thermal simulation is
much needed to help optimize the transient power partition of chips
in 3DIC during boot-up sequence or peak functional vector
operation
It is well understood that thermal issues can severely
degrade the performance and reliability of a chip
[7][9][10][11]. A large value of peak temperature and thermal
gradient on chip can severely have a negative impact on
transistor performance, stress, aging, electromigration (EM),

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voltage drops and timing [12][13]0. Performing fine-grained time and hence the temperature will vary with time instead of
transient thermal analysis on large 3D IC designs is virtually approaching a steady state value.
impossible using traditional CFD/FEA based solvers. To
address the above challenges, this paper proposes a novel fast
transient thermal solver which enables transient fine-grained
thermal analysis with extremely fast runtimes compared to
traditional FEA based thermal analysis.
In the following sections, we will describe the techniques
for fast transient thermal simulation as needed in architecture-
level thermal simulation as well as in layout-based transient
thermal simulation for 3D IC.
The paper is organized as follows. Section II describes the Figure 5 Transient power profile on each block of a chip
problem statement. Sections III to VII explain the ML-based
Fast Transient Thermal Solver. Section VIII describes the III. SOLUTION OVERVIEW
extension of the methodology to 3D IC case. Section IX Figure 6 shows the flow overview of the fast transient thermal
discusses the results of thermal analysis based on the solver. The inputs to this flow are the chip-pkg-system design
methodology in the paper on couple of example designs to inputs, boundary conditions and the transient power profile.
demonstrate the runtime and capacity improvements.
II. MOTIVATION AND PROBLEM DEFINITION
Traditional Finite Element Method (FEM) based numerical
simulations require prohibitively long run times even for
small simulation durations making it unviable to be used for
generating fine-grained transient thermal responses. Even
with distributed computing resources the run times will not
be good enough for such a transient thermal response
prediction.

Figure 4 Tile-based power map with 10ߤmx10ߤm resolution (left) Figure 6 Fast Transient Thermal Solver Flow Overview
and thermal profile of a 4mmx3mm test chip with 800k instances
(right) A trained ML model is used to predict the decay surface
models to characterize the local, intermediate, and global
Figure 4 shows an example of a fine grid power and thermal models. The ML predictor and the decay surface models will
maps for a 4mm x 3mm test chip at a resolution close to 10ߤm be described in later sections. The chip is partitioned into
in size. The chip has about 800k instances. Using a fine mesh size NxM tiles of size k(um)xk(um) on which the transient power
of 10ߤm on the silicon block, it took more than couple hours to is distributed to generate the fine-grained power map which
solve for the chip+package+PCB model using FEA to generate serve as the heat sources. With this transient power-map the
the steady state thermal response. Hence an FEA based method transient temperature curves are generated using a
is clearly not suitable for transient thermal response generation convolution-based approach described later for each tile
which is usually much longer than static thermal solve. One of location. Finally, the transient temperature curves for each of
the recent papers proposed a Deep Neural Networks (DNN) the tiles is linearly superimposed to generate the effective
based fast static thermal solver [8]. However, that work was transient response.
limited to performing only steady state thermal analysis. The
fast transient thermal solver methodology in this paper
generates a fine-grained (10umx10um) on-chip transient
thermal responses with the inputs as the time-varying on-chip
power profile. However, the methodology is flexible and can
be applied to smaller or larger mesh grids and any size of
chips.
Figure 5 shows an example transient power profile where the
average power changes with time. This average power can be
full chip power, per block power, or power at even finer
granularity such as cell-level instance. This transient power
will create a power map for the chip which will change with Figure 7 A 2-layer model (left) and a 3-layer die model (right)

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It is worthwhile here to explain the die model used in this
work. For this work two die models were considered, a 2-
layer silicon block model and a 3-layer die model as shown
in Figure 7. The 3-layer die model considers the thermal
models for the interconnect and insulation layers making it
more accurate for thermal analysis which is even more
applicable in the case of fine-grained thermal analysis.
Hence, for this work we selected the 3-layer die model for
thermal analysis of the chip.
IV. TRANSIENT DECAY SURFACE CHARACTERIZATION
Figure 8 shows an example transient decay surface
characterized for a 10umx10um heat source. This figure
shows the temperature change with time at various distances
from the heat source. This essentially models the temperature
at any location due to a given heat source as a function of time
and distance as in equation (1).
Figure 8 Example transient decay surface
οܶ௜௝ ൌ ݂൫݀௜௝ ǡ ‫ݐ‬൯( 1)
οܶ݅ ൌ  σ݆ ݆ܶ݅ ‫ܪ א ݆׊‬ǡ( 2)
‫ ݊݋݂݋ݐ݁ݏ݄݁ݐݏ݅ܪ݁ݎ݄݁ݓ‬െ ݄ܿ݅‫ݏ݁ܿݎݑ݋ݏݐ݄ܽ݁݌‬
The term οܶ௜௝ denotes the temperature change at the ith
location due to jth on-chip heat source. We assume a Linear
Time Invariant (LTI) system and therefore the contribution of
each of the on-chip heat sources can be linearly combined to
generate the total effective transient response at the ith
location as in equation (2). This operation is repeated for all
the tiles in the chip to generate the transient response curves
for each tile. For a chip size of 1cmx1cm, the number of tiles
will be 1M, and therefore for each tile the impact of 1M tiles
needs to be computed on a given tile. Repeating this operation
for each tile will lead to 1Mx1M operations which can be
prohibitively expensive computationally. Therefore, an
innovative solution has been developed where the number of
operations for each tile can be reduce using multi-scale decay
surface model. The thermal response at any given tile location
can be computed by considering the impact of heat sources
from nearby tiles, from intermediate distance tiles and from
far away tiles. These impacts are categorized as local impact,
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intermediate impact and global impact corresponding to local
tiles, intermediate tiles, and global tiles. These tiles then have
corresponding local level, intermediate level, and global level
decay surface models.
The decay surface at any level can be categorized by
considering an MxM array where M << no. of tiles on the
chip. For example, a local level decay surface can be
characterized with an array of 21x21 tiles with tile size as
10umx10um, whereas an intermediate level decay surface
can be categorized with an array of 10x10 tiles with tile size
as 210umx210um and the global level decay surface can
simply be the full chip-pkg-system level response at the
center of the chip with the power uniformly distributed on the
chip.
Figure 9 shows that how a decay surface can be characterized
for an MxM array. The tile array is placed on the chip and a
heat source of power Pchar is applied at the center of the array.
With this heat source the transient thermal response is
captured at all the MxM tiles. The set Ds={Pchar, ∆Tchar},
where , ∆Tchar is the set of all the transient curves for MxM
tiles, represents the decay surface model for this level.
Figure 9 Decay surface characterization for MxM array
The guiding principle is that for the local level decay surface
the smallest tile size is used for high accuracy to capture the
impact of local heat sources and coarser tile sizes are used for
intermediate level decay surfaces since the impact is an
aggregated effect. After the decay surfaces have been
characterized the output of this stage is the Ds_local,
Ds_intermediate and Ds_global. It is observed that the
thermal responses in the decay surfaces scales almost linearly
with power as:
οܶԢ
ൌ
ܲԢ
( 3)
ο݄ܶܿܽ‫ݎ‬ ݄ܲܿܽ‫ݎ‬
The other observation is that the thermal response of heat
source at tile i on tile j will be the same as the impact of the
same heat source at tile j on tile i. It should be noted that the
decay surface characterizations are performed with the full
chip-pkg-system model.
V. MACHINE LEARNING FOR DECAY SURFACE MODEL
Having described the fundamental idea of transient decay
surface in the previous section, it should be noted that for any
given chip-pkg-system, this initial characterization has to be
performed before the fast transient thermal analysis solver
can be used. To address this challenge a machine learning
(ML) based predictor was developed which can predict the
decay surfaces for a given chip-pkg-system.
This section illustrates our proposed ML-based transient
decay surface characterization. To accurately capture the far-
field and near-field transient decay surface components, ML-
based models for various levels are constructed and trained.
The precision of the models’ prediction is evaluated on
unseen cases/data.
Transient simulations have been carried out utilizing a high-
fidelity numerical solver (Ansys Mechanical APDL) for
simulating the transient response of the chip with its center
tile heated. Examples of the temperature response on the chip
are shown in Figure 10.
By adjusting the input system parameters of the simulation
model, different sets of data can be generated. The
corresponding system parameter space for the four decay
surface levels is provided in Table 1. It is worth noting that the
system parameters for the four different levels are almost the
same except for the tile size and the power applied on the tile.
Besides, one additional parameter, C scale, for modifying the
thermal capacitance of the system has been introduced as well.
Uniform random sampling has been employed to select values
from the predefined space for each system parameter. In total,
1000 distinct cases have been created for each decay surface
level.
(A) (B) (C)
Figure 10 Examples of transient response on chip. (A) Time
step=10, (B) Time step=45, (C) Time step=55, (D) Time step=65
DeepONet [7] based neural network has been built. The
network structure is depicted in Fig. 11, where the branch net
will take system parameters as input and the trunk net will
take time step as input. The information from branch net and
trunk net are combined through a merging layer and output
the temperature distribution on the chip.
Branch net
Merging
layer
Trunk net
Figure 11 ML model architecture
To validate the effectiveness of the trained model, unseen
system parameters are sampled and input to Ansys
Mechanical APDL for calculation. Then the same system
parameters are fed into the trained neural network for
prediction. Finally, the simulation results from the numerical
solver and the network prediction are compared and the
prediction error is calculated for evaluating the model
performance. An example of the ML-based model prediction
is shown in Figure 12, where the first subplot is the ground
truth solution from the numerical solver, the second subplot
is the neural network prediction and the last one is the
absolute error distribution for the prediction. It can be seen
from the color bar of the third subplot that the model is
making predictions with reasonable accuracy. The trained
model is further tested on a test dataset of 100 unseen cases
and the overall L2 relative error is less than 1%, which
verifies the accuracy of the trained model.
(D)

Table 1 Parameters for training data generation

System parameters Values / Ranges

Power per tile (mW) 500/1000/5000/20000 Figure 12 ML model for thermal response prediction
Heat Transfer Coefficient
(mW/Ɋm2•K) 1e -2e
-9 -5
VI. COMPUTING EFFECTIVE TRANSIENT RESPONSES
Die x / y length (Ɋm) 4000-30000 Given an on-chip power map with tile level heat sources, the
Die z height (Ɋm) [100, 200] transient thermal response at any tile i can be constructed by
Dielectric / interconnection layer
using the decay surface models and convolving it with the
thickness (Ɋm) 1-10 power map centered at the tile i with the thermal responses in
Insulation layer thickness (Ɋm) 0.01-0.05 the decay surface scaled based on the actual power
distribution as in equation (3). The convolution operation to
Tile size (Ɋm) 10/210/3200/16000 compute the temperature at any location (x,y) and time t can
Si substrate thermal conductivity
0.1305 be written as:
(mW/Ɋm•K)
Insulation layer thermal οܶሺ‫ݔ‬ǡ ‫ݕ‬ǡ ‫ݐ‬ሻ ൌ ‫ כ ݌‬οܶ݀‫ ݏ‬ൌ ෍ οܶ݀‫ݏ‬ሾ݆ǡ ݇ሿ‫݌‬ሾ‫ ݔ‬െ ݆ǡ ‫ ݕ‬െ ݇ሿ
conductivity (mW/Ɋm•K) 0.138e-2 ௝ǡ௞

C_scale 0.5-200 where οܶ݀‫ ݏ‬is the convolution kernel from the decay surface
Dielectric / interconnection layer model, and the p is the scaled power map with respect to the
thickness (μm) 0.00138--0.138 power used for characterizing the decay surface model. This
equation will calculate the contribution of the οܶሺ‫ݔ‬ǡ ‫ݕ‬ǡ ‫ݐ‬ሻdue
Since the input to the ML model includes different to the corresponding decay surface model οܶ݀‫ݏ‬.
combinations of system parameters along with the time step
and the output of the ML model is the corresponding
temperature distribution of the chip at the given time step, a

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 5. The above steps can be repeated for all the tiles/sensor
locations to generate the transient thermal response for
all the tiles/sensor locations.
6. Heat sources which have been accounted for at a certain
level are excluded from the other levels.

Figure 13 Convolution on the power map with the decay surface

kernel

Figure 13 shows the convolution of the scaled power map

decay surface kernel to obtain the temperature response. For
a given decay surface model this operation is repeated for
each time point and thus we get the transient thermal
response. The convolution with the local decay surface model
Figure 15 Generating the total on-chip transient thermal response
will capture the effect of the nearby tiles, the intermediate
decay surface model will capture the effect of the heat sources With the above steps the per tile total transient response can
at intermediate distances, whereas the global decay surface be generated as shown in Figure 15.
model will capture the full chip heating effects. As each
decay surface model kernels are limited in size to few VII. LINEAR SUPERPOSITION ACROSS TIME POINTS
hundred elements, the convolution is fast. While computing
the temperature response for a given tile, the power maps for
the intermediate decay surfaces are adjusted so that the heat
sources which have been accounted for in the convolution
with local decay surface are not considered to avoid double
counting. Similarly, while performing convolution with the
global decay surface the heat sources which have been
accounted for during the convolution with the local and
intermediate decay surface are ignored. Figure 14 shows how
the impact of heat sources are convolved with the decay
surface models to generate the effective transient thermal
response. Therefore, the following steps are used to generate
the effective transient thermal response at any given tile
location:
1. Generate the power map for the local, intermediate and Figure 16 Linear superposition of transient thermal responses
global levels at the tile of interest.
Figure 16 describes the methodology for generating the
effective transient responses as the power changes with time.
As shown in the example figure each of the power values P1
and P2 will have its own transient thermal response curve,
TR1 and TR2 respectively. When the power changes from P1
to P2, it can be considered as P1 reducing to zero and a new
power P2 being applied. This would mean that the chip will
cool down due to P1 reducing to zero but will heat up due
power P2. This is modeled by the negative (mirror image) -
TR1, representing cooling effect, starting at time t=t1 and the
heating curve TR2 starting at time t=t1. This can be done for
an arbitrary number of power changes such that the transient
Figure 14 Combining the thermal responses from decay surfaces power profile is represented by the set {Pi(ti,tj), i=1…N},
where ti, tj are the start and end time for power Pi. To
2. The local and intermediate level power maps are compute the effective transient response curve at any tile
centered at the tile for which transient thermal response location, all the curves, including the mirror image curves are
is being calculated. linearly added.
3. For any given level use the corresponding decay surface
VIII. EXTENSION TO 2.5D/3D IC
to generate the transient thermal responses due to all the
heat sources for the level. The methodology described in the previous sections were
4. Linearly combine the transient responses corresponding explained with illustrations on a single die case. However, the
to each decay surface level to capture the total transient methodology can be directly extended to a 2.5D/3D IC case.
thermal response for the tile. Figure 17 shows an example of 3DIC with stacked dies. The

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heat sources on a die can affect the neighboring dies through
thermal coupling and hence this effect needs to be modeled
to accurately predict the transient thermal response on any
die.

Figure 18 Example power map

The fast transient thermal analysis is performed for all the

2.56M locations on the chip for a total simulation time of 4
seconds. The runtime for this analysis is only about 15
Figure 17 Stacked die thermal coupling minutes given the pre-characterized or ML-based model with
predicted decay surface models. Figure 19 shows the
transient thermal response curves for the two probe locations.
The decay surface based transient thermal modeling can be
extended by computing decay surfaces for the given die and
the neighboring dies. This means that a decay surface needs
to be generated in the z dimension as well. Therefore while
characterizing the decay surface models, each such model
(local, intermediate and global) will be generated for the
neighboring dies too. This can also be performed by the ML-
based predictor which has been trained for predicting the
decay surface, dS(x,y,z), in the x,y,z dimensions. The transient
thermal impact due to a power map on a die on to other dies
can be calculated using equation (4). The equation (5) then
computes the total thermal response on the die of interest.
Figure 19 Transient curves at two different temperature probe
locations
ܶሺ݀ܵǡ ‫݌ܽܯ݌‬ሻ௫ǡ௬ǡ௭ ൌ σௗ௭ୀିௗ ݂ሺ݀ܵ௭ ǡ ‫݌ܽܯ݌‬௭ ሻ( 4)
ܶ௫ǡ௬ǡ௭ ൌ σௗௌǡ௣ெ௔௣ ܶ௫ǡ௬ǡ௭ ሺ݀ܵǡ ‫݌ܽܯ݌‬ሻ( 5)

In the above equations, ݀ܵ௭ is the decay surface and ‫݌ܽܯ݌‬௭

is the power map at die with location at z.
IX. RESULTS AND DISCUSSIONS
To show the correctness, runtime and capacity improvements
from the fast transient thermal analysis methodology
described in this paper, two test cases were selected. The first
test case is a large chip on which a fine grained (10umx10um
resolution) thermal analysis cannot be performed using
traditional FEA methods because of runtime/capacity
limitations of such tools. This large test case is for showing
the runtime improvement. The second test case is a smaller
case to show the accuracy of the proposed methodology
where the golden results are generated from a FEA based Figure 20 Temperature map at t=4s
software tool.
A. Example: Runtime Improvement Figure 20 shows the temperature map at t=4s for the above
transient thermal analysis. Since this is a relatively large chip,
To demonstrate the dramatic improvement in runtime and
the decay surface models at the resolutions of (10umx10um,
capacity an example chip of size 1.6cmx1.6cm was selected
21x21), (210umx210um, 21x21), (3200umx3200um, 9x9)
along with an example package and board. Four different
and the global decay surface model were used.
power maps were randomly generated and applied for 1
second duration each in sequence similar to what is shown in B. Example: Accuracy correlation with a small chip
Figure 5. Each of the power map has a resolution of To demonstrate the accuracy of the fast transient thermal
10umx10um with a total of 2.56 Million heat sources. An solver, a small chip of 4mmx4mm was selected and
example power map is shown in Figure 18. appropriate boundary conditions were applied. An FEA

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based solver was used to run transient power-on thermal
analysis. This power-on transient thermal analysis simulation
was of 5 seconds duration. A randomly generated power map
as shown in Figure 21was applied such that the total power is
790mW.
Figure 21 Randomly generated power map for 4mmx4mm chip
With the above power map, the FEA solver and the fast
transient thermal solver were used for generating the transient
response curves at the center of chip for correlation. The local
and global decay surface models were used in the fast
transient thermal solver since this is a small chip.
Figure 22 Comparing the power-on transient between the FEA
based solver and Fast Transient Thermal Solver
As shown in Figure 22 the fast transient thermal solver
matches the results very closely with the FEA based solver.
For this small case, the fast transient solver is about 120X
faster than FEA based thermal solver.
Figure 23 Temperature components from different decay surface
models
Figure 23 shows another example with a different power map
with the temperatures probed at the center of the chip and an
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off-center location. The fast transient thermal solver matches
well with the FEA based thermal solver for both the probe
locations. The figure also shows the contributions of the
different components of the decay surface model to the total
temperature curve. At the steady state, the local decay surface
contributes about 9.5 degree Celsius, and the global decay
surface contributes about 112 degrees Celsius. These two
components added with the ambient temperature of 20
degrees Celsius leads to a total temperature of 141.5 degrees
Celsius. The contribution of the global decay surface is small
since this is a small chip and the intermediate level decay
surface covers most of the part of the chip for the given
temperature probe point. The figure also plots the difference
between the results from the FEA based solver (golden) and
fast transient thermal solver.
Figure 24 Results with transient power profile
Finally, in Figure 24 we show the results of five different
power maps applied sequentially for 2 seconds each,
resulting in power changing every 2 seconds on the
4mmx4mm chip. This figure also shows that accuracy of the
proposed methodology is good with very small errors.
X. SUMMARY
This work proposes a novel methodology to address the
critical problem of fast transient thermal analysis for large
designs. The technique proposed in this paper will enable
fine-grained transient thermal analysis for larger chips and is
directly extendible to 3D IC thermal analysis by generating
appropriate decay surface models. It was shown that the
method is accurate and can perform fine grained transient
thermal analysis for large designs where FEA would fail to
provide any solution due to extremely large runtimes and
capacity challenges. For our future work we plan to run large
3D IC cases with the fast transient thermal solver and perform
silicon correlation.
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