CMOS image sensor with adaptive readout scheme
for low power applications
2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) | 978-1-6654-2461-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/MWSCAS47672.2021.9531910
Varun Kumar, Bibhudatta Satapathy, Wilfred Kisku, Amandeep Kaur, and Deepak Mishra
Indian Institute of Technology Jodhpur, Rajasthan, India.
Email: {kumar.129, satapathy.1, kisku.1, amandeepkaur, dmishra}@iitj.ac.in
Abstract—An adaptive readout scheme for low-power CMOS
image sensors is proposed in this paper. In the first step, the entire
pixel array is partitioned into square blocks. Subsequently, the
intensity range of each block is divided into a fix number of bins
which are adapted to the intensity range of the block. For this
purpose, the maximum and minimum intensity values in each
block are obtained using winner take all circuit.The proposed
scheme is implemented and simulated on standard test images.
The observed peak signal-to-noise ratio for the Cameraman and
Thermal image is 40.37 dB and 41.16 dB, respectively for 8×8
block size and 16 bins, with 54% saving in the total power
compared to the conventional readout. An additional power
saving can be observed by reducing the total number of threshold
levels.
I. I NTRODUCTION
The applications of CMOS image sensors (CIS) have in-
creased manifold ranging from battery-operated devices like
mobile phones, medical devices to IoT applications like
surveillance, agriculture, remote health monitoring, and others.
A wider range of wireless applications imposes requirements
on power consumption, bandwidth, and data processing [1]. A
CIS consists of a pixel array, readout circuit, memories, and
output buffers. Among these components, the most power-
hungry element is the readout electronics which consists
of double sampling circuits followed by analog to digital
converters (ADCs). A wide range of literature is available to
reduce readout power at the circuit level. For instance, in cyclic
ADC, op-amps consume a large amount of power. The power
reduction can be achieved by using an inverter as an amplifier
[2]. Similarly, the power of digital to analog converter (DAC)
in SAR ADC can be reduced by introducing a pilot DAC
switching scheme [3]. The power reduction in slope ADC is
achieved by introducing multiple steps in slope ADC instead
of a single step [4]. However, in all the above techniques, the
power reduction is achieved without taking advantage of the
characteristics of the input signal.
Thinking beyond the traditional ways of reducing power at
the circuit level, a significant power reduction can be achieved
at the architecture level using the properties of the input
signal. In natural images, the neighboring pixels carry similar
information. Various techniques to achieve low power and
reduced bandwidth requirements are reported in [5]–[9]. The
reduction in power is achieved by reducing the total number
of pixels to be read or by reducing the number of bits to
be resolved. In [5], the number of pixels to be resolved by
ADC are selected randomly and later reconstructed off-chip
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using numerical optimization algorithms. The work reported
in [6] reads the difference between consecutive pixels. The
current pixel is read-only if the difference is greater than the
quantization step of the ADC. In [7], power saving is achieved
at the column level by reducing the number of conversion
cycles. The current pixel is operated only for δ difference
between the two pixels. The most significant bits (MSBs)
are copied from the previous reference pixel and the ADC
is operated only for δ difference, which reduces the total
power consumption of the ADC. Other techniques to reduce
power are reported in [8] and [9], where the concepts of re-
configurable ADC and on-array compressive acquisition are
employed to reduce the power.
Motivated from the above studies that use pixel correlation,
this work proposes an adaptive readout scheme to reduce the
ADC power. The pixel array is divided into a given block
size which is sensed for the minimum and maximum intensity
values. The values are divided into the desired number of bin
thresholds which are only resolved by the ADC to reduce the
power. This is analogous to rule-based artificial intelligence
(AI) systems where the comparators can be observed as
implementing different rules to infer the value of the pixel
under consideration. The paper is organized as follows. Section
II explains the proposed algorithm, section III reports the
simulation results, and the paper is concluded in section IV.
II. P ROPOSED ALGORITHM
A CIS mainly consists of a pixel array, readout circuit,
memories, bias circuit, row, and column decoders as shown
in Fig. 1 (a). The conventional approach of reading pixels is
to read them sequentially through a common readout circuit
placed at the chip level. This approach has limitations in
terms of high pixel resolution and high frame rate. In the
proposed readout scheme, the total number of pixels to be
read is reduced based on the amount of power saving required
in the readout. In addition, the threshold values are block
adaptive which is decided by the difference in maximum (max)
and the minimum (min) intensity for a particular block under
consideration. These thresholds are the only sampled values
to be read by the ADC to reduce power. The blocks with
a lesser intensity difference would need a lesser number of
thresholds and vice versa. In addition, thresholds or the bin
size are decided according to targeted values of compression.
To implement this algorithm, the proposed CIS requires an
additional Winner Take All circuit and an interpolation circuit
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 The obtained VCmax and VCmin values are fed to the
interpolation circuit, shown in Fig. 3 which consists of a
resistor ladder followed by a set of comparators. The two ends
of the interpolation circuit are connected to the predetermined
maximum and minimum pixel voltages and the remaining
threshold voltages are generated internally through the ladder.
At a time, the number of thresholds for all the blocks is
fixed and is determined for a given power saving factor. For
instance, if the power saving is 75% and block size = 8×8, the
number of threshold levels obtained will be 16. The generated
threshold values are sequentially processed using 10-bit chip-
level ADC and the corresponding digital bits are stored in the
memory. At the same time, the pixel values of a given block
are compared with the thresholds to generate a decision bit.
For a given pixel value, the output logic level of comparator
Vcom,k is observed and the corresponding 10-bit digital code
for the threshold value where Vcom,k is low is filled.
Accordingly, all the pixels of a given block are filled with
the digitized values stored in the memory, and, therefore, saves
Fig. 1. Block diagram considering (8 × 8) block size and 16 threshold level
the readout power. The same winner take all circuit and the
interpolation circuit will be then reused by another 8 × 8
block for resolving other set of pixel values. In this example,
compared to the traditional read-out technique where the ADC
was used 64 times considering 8 × 8 block, the proposed
scheme operates the ADC only 16 times, which significantly
reduces the power. The proposed algorithm is summarized as
follows:

Algorithm 1: Proposed Algorithm

Result: newImage
blockRow ← 8;
blockCol ← 8;
levels ← ((100 - compression)/100)*(blockRow *
blockCol);
img ← imageAquisition();
for i ← 0 to imgRow do
for j ← 0 to imgCol do
imgBlock ← extractImageBlock(img,i,j);
Fig. 2. Winner take all circuit for (8 × 8) block size max, min ← Of(imgBlock);
diff ← {max, min};
bins ← getBins(diff, levels);
as shown in Fig. 1 (b). The fixed bin size is achieved using for ii ← 0 to blockRow do
the interpolation circuit shown in Fig. 3. The absolute value for kk ← 0 to blockCol do
of thresholds is decided based on the minimum and maximum newBin ← compare{pixels,bins};
intensity value present in the block using winner take all circuit newPixelValue ← newBin;
[10] as shown in Fig. 2. The circuit used to measure the end
maximum intensity consists of a number of N-input source end
followers (SFs), shown in Fig. 2(A). The number of SFs is end
decided by the block size, for example, 8 × 8. All the sources end
are shorted and the bias current is generated through the simple
current mirror circuit. Similarly, a number of P-input source
followers (SFs), shown in Fig. 2(B) are used to determine the
minimum intensity present in the block. All the pixel voltages III. R ESULTS AND A NALYSIS
in a given block are sensed by the winner take all circuit This section presents simulation results of the proposed
and the resultant maximum (VCmax ) and minimum voltages adaptive readout scheme. The algorithm is implemented and
(VCmin ) are stored in the load capacitor. evaluated in MATLAB as a proof of concept for the set

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 Fig. 3. Interpolation circuit for 16 threshold levels.
(a) (b)
Fig. 4. (a) Original cameraman image, (b) Image obtained using the proposed
scheme with 16 threshold levels and 8 × 8 block size. The observed PSNR
is 40.37 dB
(a) (b)
Fig. 5. (a) Considered a thermal image from FLIR Dataset (b) Corresponding
image obtained using the proposed scheme with 16 threshold levels and 8 × 8
block size. The observed PSNR is 41.16 dB.
of standard images and circuit simulations are performed in
CADENCE. Two sample images (cameraman and a thermal
image) are shown in Fig. 4 (a) and Fig. 5 (a), respectively.
The images obtained using the proposed scheme considering
8×8 block size and 16 threshold levels are shown in Fig. 4 (b)
and Fig. 5 (b), respectively. The observed peak signal-to-noise
ratio for the cameraman and thermal images are 40.37 dB
and 41.16 dB, respectively, reflecting a good quality of the
produced image.
Further, the variation in PSNR is studied for varying number
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Fig. 6. PSNR in dB with respect to threshold levels for varying block size,
plotted for a cameraman image.
Fig. 7. PSNR in dB with respect to threshold levels for varying block size,
plotted for a thermal image.
of thresholds at different block sizes and the observations are
plotted in Fig. 6 and Fig. 7. It can be seen from the plots that
for the given block size, the PSNR increases with an increase
in the number of thresholds as the pixel values are filled with
better estimates. Similarly, for a given number of thresholds,
the PSNR is higher for smaller block sizes in most cases. Small
block sizes tend to have a small range of intensity resulting in
small bins. However, a small block size also leads to a large
number of blocks resulting in higher power consumption due
to a linear increment in the total number of ADC runs. As a
trade-off 8 × 8 block size is used for the other test images.
The observed PSNR values are listed in Table I and com-
pared with [11], [12], [13], and [14] the different amounts of
compression or saving in ADC runs. A number of thresholds
are calculated using the targeted amount of saving. The
proposed technique outperforms the existing techniques in all
experiments except for the House image where it shows the
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 TABLE I R EFERENCES
PSNR FOR RECONSTRUCTION OF 512 × 512 TEST IMAGES WITH
COMPRESSION OF BLOCKS SIZED 8 × 8 AND COMPARISONS [1] X. Zhong, B. Zhang, A. Bermak, C.-Y. Tsui, and M.-K. Law, “A low-
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[14] 30.49 33.36 32.33 31.41
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for a fixed block size of (8 × 8) for both conventional and proposed scheme. J.-H. Park, J.-K. Shin, and S.-T. Ryu, “A delta-readout scheme for low-
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The power-saving of the proposed scheme is evaluated by [9] A. Kaur, D. Mishra, K. Amogh, and M. Sarkar, “On-array compressive
using the ADC and comparator data reported [15]. The pro- acquisition in cmos image sensors using accumulated spatial gradients,”
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the interpolation circuit which consumes power of 3.52 mW [10] J. A. Starzyk and Y.-W. Jan, “A voltage based winner takes all circuit for
and 2.30 mW, respectively for 64 pixels. Compared to the analog neural networks,” Proceedings of the 39th Midwest Symposium
conventional readout scheme which consumes 27.84 mW of on Circuits and Systems, vol. 1, pp. 501–504, 1996.
[11] D. Mishra, A. Kaur, and M. Sarkar, “A super-pixel based on-chip image
power for 64 pixels, the proposed scheme consumes only compression for high speed cmos image sensors,” in 2017 International
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imately 54% power saving. pp. 1–2.
[12] A. Kaur, D. Mishra, S. Jain, and M. Sarkar, “Content driven on-
Furthermore, at the system level, the ADC power saving is chip compression and time efficient reconstruction for image sensor
observed for a given 8 × 8 block size with respect to threshold applications,” IEEE Sensors Journal, vol. 18, no. 22, pp. 9169–9179,
levels. The conventional CIS consumes a constant power as 2018.
[13] N. Ansari and A. Gupta, “Image reconstruction using matched wavelet
all the pixels are read sequentially, which is represented by estimated from data sensed compressively using partial canonical iden-
a constant line in the graph shown in Fig. 8. However, using tity matrix,” IEEE Transactions on Image Processing, vol. 26, no. 8, pp.
the adaptive readout scheme, a significant reduction in power 3680–3695, 2017.
[14] A. Kaur, D. Mishra, K. M. Amogh, and M. Sarkar, “On-array com-
is observed, plotted in the same figure. The power reduces pressive acquisition in cmos image sensors using accumulated spatial
from 27.84 mW (conventional image sensor) to 14.52 mW gradients,” IEEE Transactions on Circuits and Systems for Video Tech-
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levels is reduced to four. The above graph is plotted using a
reference ADC power reported in [15].

IV. C ONCLUSION
In this paper, an adaptive readout scheme based CMOS
image sensor is proposed wherein the bin thresholds are
adapted to the intensity range of the given block. The ADC is
operated only for these bin threshold values which results in
reduction in readout power. The algorithm is implemented and
simulated in MATLAB and Cadence as a proof of concept. For
8 × 8 block, the proposed scheme reduces the conventional
CIS power of 27.84 mW to 12.78 mW for 16 thresholds
resulting in 54% power saving. The adaptive readout scheme
is, therefore, suitable for low power applications.

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