Advanced VLSI Design and Verification Course

Timings
Number
Date Days Module No. (or) Name Elearn topics of Start End Start End
session Time Time Time Time
per day
Introduction & Course Flow
Getting you familiar with the
28-Feb-2024 DAY 1 2:00 PM 3:30 PM
system and Elearn

Blended VLSI - M1 -
9:00 AM 10:30 AM
29-Feb-2024 DAY 2 Introduction to VLSI
Joining Formality Session 4.00 PM 5.30 PM
Blended VLSI - M2 - Advanced
1-Mar-2024 DAY 3 Number systems 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
4-Mar-2024 DAY 4 Codes Assignment-1 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
5-Mar-2024 DAY 5 Logic Gates and Boolean Algebra Assignment-2 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
6-Mar-2024 DAY 6 Logic Gates and Boolean Algebra Assignment-2 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
7-Mar-2024 DAY 7 Combinational- Adders, SubtractorsAssignment-3 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
8-Mar-2024 DAY 8 Combinational- Encoders, DecodersAssignment-3 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced Combinational- Multiplexers,
11-Mar-2024 DAY 9 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design DemultiplexersAssignment-3
Blended VLSI - M2 - Advanced
12-Mar-2024 DAY 10 Sequential - LatchesAssignment-4 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced Sequential - Flip-flops, Flip-flop
13-Mar-2024 DAY 11 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design conversionsAssignment-4

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 Blended VLSI - M2 - Advanced
14-Mar-2024 DAY 12 Sequential - Registers, Counter basicsAssignment-5 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
15-Mar-2024 DAY 13 Sequential - Counter design, Shift register counters 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced Sequential - Counter design, Shift register
18-Mar-2024 DAY 14 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design countersAssignment-5
Blended VLSI - M2 - Advanced
19-Mar-2024 DAY 15 FSM- Melay , Moore sequence detectorsAssignment-6 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
20-Mar-2024 DAY 16 FSM- Practical applications, Arbiter FSMAssignment-6 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced
21-Mar-2024 DAY 17 FSM- Practical applications, Arbiter FSM 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
Blended VLSI - M2 - Advanced FSM- Practical applications, Arbiter FSMAsssignment-
22-Mar-2024 DAY 18 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design 7
Blended VLSI - M2 - Advanced Glitches and Hazards, Memories: classification ,
25-Mar-2024 DAY 19 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design composition of memoriesAsssignment-7
Blended VLSI - M2 - Advanced
26-Mar-2024 DAY 20 FIFO depth calculationAsssignment-7 2 9:30 AM 11:30 AM 2:30 PM 4:30 PM
Digital Design
27-Mar-2024 DAY 21 Blended VLSI - M4 - Linux Linux Linux Labs 1 9:30 AM 12:00 PM
Blended VLSI - M5 - Verilog Verilog abstraction levels Write only RTL codes for few
28-Mar-2024 DAY 22 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL combinational circuits.
28-Mar-2024 Digital module test - 40 minutes
Blended VLSI - M5 - Verilog
29-Mar-2024 DAY 23 Data-typesLab1 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
1-Apr-2024 DAY 24 Data-typesLab1 assignments 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
2-Apr-2024 DAY 25 OperatorsLab1 assignments - Lab1 review 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
3-Apr-2024 DAY 26 Operators Operators practise 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
4-Apr-2024 DAY 27 ProcessesLab2 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL

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 Blended VLSI - M5 - Verilog
5-Apr-2024 DAY 28 ProcessesLab3 - Lab2 review 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog Structured ProceduresLab3 assignments - Lab3
8-Apr-2024 DAY 29 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL review
Blended VLSI - M5 - Verilog
9-Apr-2024 DAY 30 Structured ProceduresLab4 assignments 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog Compiler directives & system tasksLab4 assignments -
10-Apr-2024 DAY 31 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL Lab4 review
Blended VLSI - M5 - Verilog
11-Apr-2024 DAY 32 Compiler directives & system tasksLab5 assignments 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
12-Apr-2024 DAY 33 Synthesis guidelinesLab5 assignments 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
15-Apr-2024 DAY 34 Synthesis guidelinesLab5 assignments - Lab5 review 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
16-Apr-2024 DAY 35 FSMLab6 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
17-Apr-2024 DAY 36 FSMLab6 assignments - Lab6 review 2 9:30 AM 11:30 AM 11:00 AM 12:00 PM
HDL
Blended VLSI - M5 - Verilog
18-Apr-2024 DAY 37 Router Design SpecificationFIFO 1 2:00 PM 3:00 PM
HDL
18-Apr-2024 Verilog module test - 30 minutes
Blended VLSI - M5 - Verilog
19-Apr-2024 DAY 38 Router Design FIFO 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
22-Apr-2024 DAY 39 -Synchronizer - Router review
HDL
Blended VLSI - M5 - Verilog
23-Apr-2024 DAY 40 Router Design SYNC 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
24-Apr-2024 DAY 41 -FSM
HDL
Blended VLSI - M5 - Verilog
25-Apr-2024 DAY 42 Router Design FSMRegister 1 2:00 PM 3:00 PM
HDL
26-Apr-2024 DAY 43 Design Test - 1.30 Hrs

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 Blended VLSI - M5 - Verilog
29-Apr-2024 DAY 44 Router Design REGRouter top - Router review 1 2:00 PM 3:00 PM
HDL
30-Apr-2024 DAY 45 Coding Test - 1.30 Hrs
Blended VLSI - M5 - Verilog
2-May-2024 DAY 46 Router Design TOP 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
3-May-2024 DAY 47 RISC V 1 2:00 PM 4:00 PM
HDL
Blended VLSI - M5 - Verilog
6-May-2024 DAY 48 DC TheoryDC on Labs 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
7-May-2024 DAY 49 DC TheoryDC on Labs 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
8-May-2024 DAY 50 RISC VDC on Router 1 2:00 PM 4:00 PM
HDL
Blended VLSI - M5 - Verilog
9-May-2024 DAY 51 Linting Linting on router 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
10-May-2024 DAY 52 Linting Linting on router 1 2:00 PM 3:00 PM
HDL
Blended VLSI - M5 - Verilog
13-May-2024 DAY 53 Linting on RISCV soc - Lint review
HDL
Blended VLSI - M6 - Advanced
14-May-2024 DAY 54 Advanced Verilog Advanced Verilog assignments 1 2:00 PM 3:30 PM
Verilog & Code coverage
Blended VLSI - M6 - Advanced
15-May-2024 DAY 55 Advanced Verilog Lab1,2 1 2:00 PM 3:30 PM
Verilog & Code coverage
Blended VLSI - M6 - Advanced
16-May-2024 DAY 56 Advanced Verilog assignments - Review1
Verilog & Code coverage
Blended VLSI - M3 - Static
17-May-2024 DAY 57 STA 1 2:00 PM 3:00 PM
Timing Analysis
20-May-2024 DAY 58 STA 1 2:00 PM 3:00 PM
Blended VLSI - M8 - CMOS
21-May-2024 DAY 59 CMOS 1 2:00 PM 4:00 PM
Fundamentals
Blended VLSI - M7 - FPGA
22-May-2024 DAY 60 FPGA 1 2:00 PM 4:00 PM
Architecture

Maven Silicon Softech Pvt Ltd.

21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | www.maven-silicon.com
 Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | www.maven-silicon.com