1.

Explain the basic components of Generic Computing system regardless of its internal architecture
with practical real time examples.
There are two main types of computing systems: CISC and RISC. CISC systems aim to do tasks in as few steps as possible, like
multiplying numbers with a single "MUL" instruction. RISC systems prefer simpler instructions that each take just one step.
For example, multiplying numbers with RISC requires three separate steps: loading, processing, and storing. Despite needing
more lines of code, RISC instructions are faster to execute, making tasks efficient. So, both CISC and RISC offer different ways
to handle tasks in computing systems.

2. Explain the phases involved in Instruction cycle with the help of necessary timing diagrams?
An instruction cycle involves three stages: Fetch, Execute, and Interrupt.

 During Fetch, the processor retrieves the next instruction from memory. The address in the PC is moved to the
MAR for a memory read, fetching the instruction into the MBR and then to the IR. Concurrently, the PC is
incremented for the next fetch.
 In Execute, the instruction's opcode is interpreted, and the operation is executed. This can include various tasks
like data transfer, memory access, or ALU operations.
 In case of Interrupts, if enabled and detected, the current process state is saved. The PC content is stored in the
MBR for memory storage, while a special memory location is loaded into the MAR. The PC is set to the interrupt
routine's address, readying the processor for the next instruction cycle after the interrupt handling.

3. Sketch the internal organization of CPU out with its functionalities and block diagram.

4. Write about hierarchy of buses, bus signals and its functionalities.

In a computer system, buses play a key role in managing data transfer. When many devices are connected, performance can
suffer due to coordination overheads and data transfer bottlenecks. To address this, modern systems use a hierarchy of
buses.

The traditional setup includes three buses: local, system, and expanded. High-speed buses are added for demanding tasks
like video processing and network interfaces. These buses have dedicated functions or serve multiple tasks at different
times.
Arbitration manages bus access among devices. It can be centralized, with a single controller, or distributed, with each
device controlling access.

Bus timing can be synchronous (based on a clock signal) or asynchronous (based on previous events).

In summary, buses and their signals efficiently manage data transfer in computer systems, ensuring smooth operation and
optimal performance.

5. Elaborate how CPU is concordant with its Input & Output devices and explain the interfacing
modules involved?
The CPU manages input and output devices to facilitate data exchange in a computer system. Input devices like keyboards
and mice provide digital information, stored in memory for processing. The Arithmetic and Logic Unit (ALU) performs
computations using data fetched from memory. Output units transmit processed results to users through devices like
monitors and printers. The control unit coordinates these activities, fetching instructions, generating control signals, and
regulating timing for data transfers between the CPU, memory, and input/output devices. This ensures efficient
communication and operation within the system.

6. Demonstrate how the Compatibility between CPU & Bidirectional IO components are devised using
its interfacing modules

7. List out the general aspects of ROM, RAM and IO interfacing modules.
ROM serves as non-alterable storage for fixed data, typically used for instructions and lookup tables. It includes types like
Masked ROM, PROM, EPROM, and EEPROM, often employing MOS technology for customization. RAM, on the other hand,
is volatile and allows both reading and writing. It comes in two main types: Static RAM (SRAM) and Dynamic RAM (DRAM).
SRAM uses MOS or bipolar technology, while DRAM stores data as charges on capacitors, requiring refreshing for data
integrity. SRAM cells are organized into rows and columns, while DRAM cells utilize MOSFET and capacitor pairs per bit.
Interfacing with ROM involves address decoding and data control through MOS transistors, while RAM interfaces include
enabling write or read signals and managing charge flow for data storage.

8. Design a relatively simple computer which incorporates 8K RAM, 8K ROM, IO interfacing modules
along with processor.

9. Identify the crucial features to design the instruction set architecture for a specific purpose
processor?

10. Describe the Instruction set Architecture of simple computer.

11. Justify importance of Backward Compatibility in Processor design with practical examples

12. Differentiate SRAM and DRAM.

Table Comparison Between SRAM and DRAM

Static RAM Dynamic RAM

1 Contains less memory cells per unit area.
2 Less access time hence faster memories
3 Consists of number of flip-flops. Each flip-flop stores
one bit.
4 Refreshing circuitry is not required.
5 Cost is more.
Contains more memory cells as compared to static RAM
per unit area.
Access time is greater than static RAMs.
Stores the data as a charge on the capacitor. It consists
of MOSFET and the capacitor for each cell.
Refreshing circuitry is required to maintain the charge
on the capacitors after every few milliseconds. Extra
hardware is required to control refreshing. This makes
system design complicated.
Cost is less.
13. What is an instruction cycle and write the phases of Instruction cycle?
An instruction cycle involves retrieving instructions from memory into the processor during the Fetch stage. In the Execute
phase, the processor interprets and performs the indicated operation, which may include accessing operands in memory. If
interrupts occur, the Interrupt phase saves the current process state and handles the interrupt. These phases ensure the
orderly execution of instructions in a computer system.

14. With a neat flowchart, explain how the control unit determines the instruction after decoding an
instruction.

15. Write the basic instruction formats for IO, Register and Memory Reference instructions.

16. With a neat schematic, explain the steps involved in fetch and decode phases using register
transfer instructions.

17. Demonstrate the general configuration of Micro programmed Control unit with a neat block
diagram.

18. Present a Simple digital computer and show how it can be micro programmed with the help of
necessary formats and notations.

19. Write about hardware organization of micro programmed control unit.