SSRN Id4088086

Grinding and lapping induced surface integrity of silicon wafers and its
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effect on chemical mechanical polishing
Shang Gaoa,*, Honggang Lia, Han Huangb, Renke Kanga
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a Key Laboratory for Precision and Non-Traditional Machining Technology of Ministry of
Education, Dalian University of Technology, Dalian 116024, China
b School of Mechanical and Mining Engineering, The University of Queensland, QLD 4072,
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Australia
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The corresponding author email: gaoshangf@gmail.com
Abstract: Grinding and lapping are two widely used machining processes for silicon wafer
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planarization. Their resultant surface integrity has a significant impact on subsequent polishing
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and hence the overall manufacturing cost. In this work, the morphologies and damage patterns
of the ground and lapped silicon surfaces were comparatively investigated and the effect of
surface integrity on subsequent chemical mechanical polishing (CMP) was understood. In the
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regime of ductile removal, the ground silicon surface had regularly distributed striations, but
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the lapped surface consisted of randomly and homogeneously distributed scratches. The lapped
surface had a softer damage layer than the ground one because more stacking faults were
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induced in the silicon sublayer. In the subsequent process of CMP, the roughness of the lapped
surface was decreased faster, but its corresponding material removal rate (MRR) was lower, in
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comparison to the CMP of the ground surface with the same starting roughness value. A bearing
area ratio model was developed to elucidate the removal mechanism involved in polishing. The
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lapped surface was found to have a higher bearing area ratio than the ground, indicating that a
larger surface area was removed, thus leading to a lower MRR.
This preprint research paper has not been peer reviewed. Electronic copy available at: https://ssrn.com/abstract=4088086
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Keywords: Silicon, Grinding, Lapping, Surface morphology, Subsurface damage, Material
removal
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1 Introduction
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Monocrystalline silicon wafers are the most widely used substrates in integrated circuit
(IC) manufacturing, which need to have extremely high surface quality and flatness. Grinding
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or lapping is the mainstream process for silicon wafer planarization, both aiming to efficiently
remove the surface damage and waviness caused by the previous processing procedure [1, 2].
However, either grinding or lapping is not immune to surface damage that affects the surface
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integrity of silicon wafers, and subsequent polishing or even CMP must be used to achieve a
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damage-free surface that meets the IC packaging criteria [3]. It is well documented that and
reported that CMP has an extremely low material removal rate, hence high cost, and produces
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additional waste of polishing slurry that is not environmentally friendly [4, 5]. The surface
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integrity of a brittle crystal would significantly affect the machining time of subsequent
polishing [6]. Apparently, the damage layer on the wafer surface left by grinding or lapping has
a considerable impact on the removal efficiency of further polishing and hence overall
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manufacturing cost. Therefore, it is of great importance to understand how the ground and
lapped surface integrity affects the removal of CMP.

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Silicon wafers are a typical brittle solid. Without special care, the material removal
involved in grinding or lapping can cause substantial surface/subsurface damage on brittle

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materials [7, 8]. Previous studies [9, 10] have demonstrated the necessity of ductile removal for
machining silicon wafers. This is because the ductile removal can result in a much thinner
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damage layer than brittle removal, which helps reduce the removal stock in the subsequent
polishing. Liu et al. [11] conducted in-situ nano-cutting to understand the material removal
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behavior of single crystal silicon and the subsurface damage caused by ductile removal. A great
deal of recent studies was also concerned with the formation of the surface/subsurface damage
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of silicon wafers induced by grinding and lapping, aiming at minimizing the time of subsequent
polishing. For example, Goel et al. [12] revealed the material deformation behavior of silicon
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in ductile regime machining. Zhang et al. [13] simulated the nano-grinding of silicon with an
atomistic model and investigated the mechanical properties and formation of the subsurface
damage layer. Yin et al. [14] proposed an analytical model to predict the subsurface damage
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depth of silicon wafers and found that increasing the grinding speed reduced the subsurface
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damage. Konneh et al. [15] developed a low-cost and fracture-free lapping technology for
silicon wafers. Ozturk et al. [16] conducted a multiple nonlinear regression analysis on the
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lapping process for silicon wafers and obtained the lapping parameters for the best possible
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surface quality. Dobrescu and Dorin [17] pointed out that lapping is a complex process and the
variations in size and shape of abrasive grains could have a great effect on the lapped surface.
Huang et al. [18] studied the effect of different abrasive particle shapes on the surface damage
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of silicon wafers in nano-grinding by molecular dynamics simulation. Lin et al. [19] analyzed
the effect of abrasive grits shape, size, and spatial distribution on the material removal and
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surface damage formation during lapping. The existing studies clearly showed that the damage
patterns of the ground and lapped surfaces appear different. This difference should be
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considered when selecting the parameters for subsequent polishing. Nevertheless, no research
has been carried out to understand the effect of the surface integrity discrepancy between
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lapping and grinding on the removal efficiency in the subsequent polishing.
Surface morphology is another factor affecting polishing efficiency [20]. Kim et al. [21]
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investigated the effect of asperity contact between wafer and pad on the material removal rate
(MRR) in CMP and found that the contact morphology of the wafer-to-pad would affect the
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polishing efficiency. Shi et al. [22] and Zhou et al. [23] demonstrated that even the atomic scale
topography of a wafer surface would affect the CMP removal and the wafer surface with narrow
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average step width could produce a higher MRR. Similarly, Lin et al. [24] pointed out that
surface morphology would affect polishing efficiency in CMP. The surface morphology of
silicon wafers generated by grinding is apparently different from that created by lapping.
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Bhagavat et al. [25] revealed that grinding and lapping result in different surface morphologies
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or grooving patterns due to the different kinematics of their cutting grits involved in material
removal. Chang et al. [26] indicated that the mechanical removal mechanisms in a lapping
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process could involve both two-body and three-body abrasion. Chen and Chao [27] suggested
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that free-abrasive machining would produce more random grooving patterns than fixed-
abrasive machining. Yang et al. [28] analyzed the principal and parasitic movements between
workpiece and pad during lapping and demonstrated that the lapped surface had a topography
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with a complex reticular distribution. Nevertheless, a systematic investigation on the effect of
ground and lapped surface morphology on the removal of CMP is lacking.

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In this work, we comparatively investigated the surface morphology and subsurface
damage patterns of silicon wafers induced by grinding and lapping. We then select the ground
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and lapped surfaces that have the same roughness values for further CMP studies. A bearing
area ratio model was proposed to analyze the effect of surface integrity on polishing efficiency.
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2 Experimental details
2.1 Silicon samples after grinding and lapping

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To compare the difference in surface integrity between ground and lapped surfaces, silicon
wafers were machined to make sure that each group of the ground and lapped surfaces have
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almost the same value of arithmetic average height Sa. Silicon samples used for comparison had
four different grades of roughness, including roughing to finishing process, as shown in Table
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1. The samples are square of 15×15 mm2, which were laser-cut from an 8-inch commercial
silicon wafer after grinding or lapping. CMP was performed on the ground and lapped samples
to investigate the effect of the surface integrity on its removal efficiency.
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Table 1. Surface roughness values of the silicon samples after grinding and lapping.
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Sample sign Ground surface Sa (μm) Lapped surface Sa (μm)
A 0.538 0.557
B 0.246
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C 0.126 0.118
D 0.011 0.011
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2.2 Grinding, lapping, and CMP experiments
Grinding was performed on an ultra-precision wafer grinder (VG401 MK II, Okamoto,

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Japan), which is equipped with two rotational spindles for a grinding wheel and a work table,
as shown in Fig. 1(a). Both the spindles have a high dynamic and static stiffness, and the feed
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rate of the grinding wheel can reach less than 1 μm/min. An 8-inch commercial silicon wafer
was attached to a vacuum chuck for grinding. Lapping was carried out on an ultra-precision
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lapping machine (ZYP230, Mike Shenyang, China), as shown in Fig. 1(b). A lapping plate
made of cast iron is 230 mm in diameter, using SiC abrasives as lapping slurry, while a wafer
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for lapping was mounted on the top chuck. The grinding and lapping parameters are shown in
Table 2, where diamond wheels and SiC abrasives of different grit sizes were used to obtained
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the same surface roughness for grinding and lapping.
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Fig. 1. Silicon wafer planarization: (a) grinding, (b) lapping, and (c) CMP.
Table 2. The experimental parameters for grinding and lapping.

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Machining parameters Sample A Sample B Sample C Sample D
Mesh size of wheels #120 #600 #1500 #3000

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Bond type Resin Resin Resin Resin
Grits size (μm) 125 25 10 5

Grinding
Wheel rotational speed (r/min) 2400 2400 2400 2400
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Table rotational speed (r/min) 120 120 120 120
Wheel feed rate (μm/min) 20 20 10 5

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The grade of abrasives W15 W5 W2 W0.4
Grits size (μm) 15 5 3 0.4
Lapping plate rotational speed (r/min) 40 40 40 40

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Lapping Chuck rotational speed (r/min) 45 45 45 45
Lapping pressure (Kpa) 30 30 30 30
Slurry flux (ml/min) 30 30 30 30

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Lapping time (min) 30 30 30 60
To assess the effect of the surface damage induced by grinding and lapping on polishing
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efficiency, the same CMP conditions were used to polish all the silicon samples. A polishing
machine (ZYP230, Mike Shenyang, China) used for CMP is shown in Fig. 1(c). The polishing
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liquid used in the CMP experiment was 80 nm SiO2 slurry (FUJIMI, Japan), and the polishing
pad is made of polyurethane with a porous structure. The polishing parameters are shown in
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Table 3. The surface roughness and MRR of the sample were measured every 20 minutes during
the polishing period of 100 minutes.
Table 3. The experimental parameters for CMP.
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Polishing parameters Values
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Polishing pad rotational speed (r/min) 40
Chuck rotational speed (r/min) 55
Polishing pressure (Kpa)

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Slurry flux (ml/min) 30
Polishing time (min) 100

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2.3 Characterization
Surface roughness, morphology, and damage, sub-surface damage, and hardness of the
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surface damaged layer were used to characterize the surface integrity of a silicon wafer. The
surface roughness and morphology of a sample were measured by the use of an optical
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interference profiler (Newview9000, Zygo, USA). Surface damage was examined using an
optical microscope with an ultra-depth of field (VHX-600E, KEYENCE, Japan). Sub-surface

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damage was determined utilizing cross-section angle polishing microscopy.
As shown in Fig. 2, the red lines refer to the surface after grinding or lapping. The ground
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or lapped surface (bottom) was bonded with a dummy polished sample (top), and the bonded
sample was then polished with a specific inclined angle to form a cross-sectional surface. A
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solution that consists of H2O: HF49%: Cr2O3=500 ml: 500 ml: 75 g was used to corrode the
cross-section after being polished. so that subsurface damage induced by grinding or lapping
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could be exposed. The depth of subsurface damage (SSD) was calculated by Eq. (1), where L
refers to the depth of subsurface damage measured on the inclined surface and β refers to the
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inclined angle, which was 5.7° in this case. The subsurface damage was further examined using
the Keyence microscope.
SSD  L  sin β (1)
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Fig. 2. Schematic illustration of the sample preparation for examining sub-surface damage layer.
Because the subsurface damage patterns cannot be exactly detected using cross-section
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angle polishing microscopy, the cross-sectional specimens of sample D after grinding and
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lapping were made to examine the subsurface damage using a transmission electron microscope
(TEM) (F20, FEI Tecnai, USA) operated at 200 kV. TEM specimens were prepared using FEI
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Scios Focused ion beam (FIB)Dual Beam Scanning Electron Microscope (SEM) system.
The hardness of the surface damaged layer was measured by nanoindentation tests.
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Nanoindentation was performed on a nanomechanical testing system (TI950, Hysitron, USA).
A Berkovich indenter of tip radius of 100 nm was used. The applied normal peak load was 8
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mN. The test procedure had 15 seconds in loading, 5 seconds in holding at peak load, and 15
seconds in unloading. Samples C, D, after grinding, lapping and CMP were chosen for
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nanoindentation. For each sample, 20 indents were made in an array mode. The spacing
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between two neighboring indents was 100 μm to avoid interference.
The removal in CMP is at the nanoscale. In this work, a micro-indentation method was
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developed to measure the MRR of CMP. As shown in Fig. 3(a), a Vickers indenter was used to
make an indent on the silicon sample before polishing. An optical interference profiler
(Newview9000, Zygo, USA) was then employed to measure the surface profile of the indent
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before and after CMP, as shown in Fig. 3(b). The height difference between the profiles before
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(A) and after (B) polishing was used to determine the MRR, as shown in Fig. 3(c).
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Fig. 3. Schematic illustration of the method for measuring MRR of CMP. (a) Make an indent on the sample
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surface before CMP, (b) measure the indent profiles before and after CMP, and (c) determine the difference
between the indent profiles before and after polishing to obtain the removal height.
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3 Results
3.1 Surface characteristics

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Figure 4 presents the roughness values of the ground and lapped silicon surfaces. For all
the samples, the Sa values after grinding and lapping are very close, which are 0.540, 0.250,
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0.120, and 0.011 μm for Samples A, B, C, and D, respectively. Although the surface roughness
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Sa values after grinding and lapping are the same, the Sz values are distinctly different. The
roughness values of Sz represent the maximum height of peak-to-valley of the surface. In
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general, the Sz value of a ground surface is higher than that of the lapped surface, such as in the
cases of Samples A, B, and C. When the Sa value is relatively small, such as in the case of
Sample D, the Sz value of the ground surface is lower than that of the lapped surface.
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Fig. 4. Surface roughness values after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d)
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D.
Figure 5 shows the comparison of the morphologies of the ground and lapped surfaces.
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For the same surface roughness Sa, the morphologies of ground and lapped surfaces are different.
The ground surface morphology consists of scratching grooves with regular patterns, whereas
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the lapped surface morphology has a random distribution of grooves with broken pits. The
lower the surface roughness of the sample, the more different features presented in surface
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morphology.
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Fig. 5. Surface morphologies after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d) D.
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The surface characteristics of the ground and lapped surfaces were compared for the same
Sa value, as shown in Fig. 6. Visually, the surface damage of the samples after grinding or
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lapping reduced with the decreased roughness value, corresponding to a decreased grit size of
the grinding wheel or lapping media. The fragmented spots on Samples A, B, and C after
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grinding appear more than the respective lapped surfaces, as shown in Figs. 6(a), (b), and (c).
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However, for the smoother surfaces being generated in Sample D as shown in Fig. 6(d), the
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ground surface has no visible brittle damage, but the lapped surface still presents some small
chipping spots.
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Fig. 6. Surface images of Samples (a) A, (b) B, (c) C and (d) D after grinding and lapping.
3.2 Subsurface damage and property

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Subsurface damage reflects the removal depth of wafer polishing. Figure 7 displays the
subsurface damage of the ground and lapped samples obtained using the cross-section angle
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polishing microscopy. According to Eq. (1), the SSD values of the ground surfaces measured
from the images are 10.102, 7.633, 4.794 and 0.792 μm, and those of the lapped surfaces are
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5.843, 2.746, 2.158, and 1.654 μm for Samples A, B, C, and D, respectively. The SSD induced
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by grinding is greater than that by lapping for Samples A, B, and C, but smaller for Sample D.
These results agree with our previous findings of surface roughness Sz values, as shown in Fig.
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4. In the roughing stage, grinding would bring severe subsurface damage than lapping within
the same surface roughness. Conversely, in the finishing stage, subsurface damage below the
ground surface is less than the lapped surface. It is also observed in Fig.7 that the crack
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distribution of the lapped surfaces appears more homogeneous, but the crack distribution of the
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ground surfaces is more scattered.
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Fig. 7. Subsurface damage after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d) D.
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Nanoindentation was performed on Samples C and D after grinding and lapping, as well
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as on which samples after CMP. Their hardness values are shown in Fig. 8. Given that the
grooves and broken pits were distributed on the machined silicon surface, the error bar of the
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sample C and D values was relatively large. The hardness value was the average level of the
indentation tests repeated 20 times. The ground surface hardness is slightly greater than the
respective lapped surface for either Sample C or D. But the hardness of the ground surface of
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Sample D is very close to that of CMP.
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Fig. 8. The nanoindentation hardness values of the surface after grinding, lapping, and CMP.
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3.3 Surface roughness and MRR of CMP samples

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The CMP experiments were performed on the ground and lapped surfaces for Samples A,
B, C, and D. The roughness values of Sa of the CMPed samples are plotted as a function of
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polishing time in Fig. 9. As mentioned earlier, the samples after grinding and lapping that have
similar Sa values were polished at the same time. For all the samples during CMP, the roughness
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of the polished sample decreased rapidly at the early stage of polishing, then gradually
approached their respective saturated values. The decreasing rate for grinding is slower than
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that for lapping for the four samples, but at the later stages the difference in surface roughness
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between grinding and lapping decreases, eventually reaching the same roughness value of 2
nm. It should be noted that the polishing times required to reach the roughness minimum value
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are different for the samples of different roughness values, also different for the ground and
lapped surfaces. The polishing time of the lapped surface to reach the roughness minimum value
is obviously shorter than that of the ground surface.
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Fig. 9. Surface roughness values of Samples (a) A, (b) B, (c) C and (d) D plotted as a function of polishing time.
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Figure 10 presents the MRR values of Samples A, B, C and D plotted as a function of
polishing time. A greater surface roughness obtained from the previous process, grinding or
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lapping, resulted in a higher MRR, particularly in the initial stage of CMP. The MRR values of
the ground samples are also greater than the respective values of the lapped ones. In the later
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stage of polishing, the difference in MRR between the grinding and lapping became
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insignificant, eventually with a constant rate of ~18 nm/min. As expected, the rougher samples
require a longer time to achieve the stable MRR.
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Fig. 10. The MRR values of Samples (a) A, (b) B, (c) C and (d) D plotted as a function of polishing time.
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4 Discussion
4.1 Damage induced by grinding and lapping

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Surface damage would affect the strength of a silicon wafer. The residual stress induced
by the damaged layer can cause warpage in a silicon wafer and thus affect its total thickness
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variation (TTV) [29]. Therefore, the damage layer must be removed in the subsequent CMP
process. The depth of the damage layer is in fact the removal depth in CMP, so it's critical to
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minimize surface damage during grinding or lapping without sacrificing removal efficiency.
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Comparative analysis of the damage mechanism in grinding and lapping can help understand
its effect on polishing efficiency.
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Grinding and lapping belong to abrasive machining. The material removal modes of brittle
solids involved in abrasive machining are basically classified into two modes: brittle and ductile
removal [30]. In the mode of brittle removal, the brittle fracture occurs and fractured and
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fragmented features are overwhelmed on the machined surface and the subsurface is prone to
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developing median cracks [10]. As a result, the surface quality or integrity produced by brittle
removal is poor. Ductile removal can greatly reduce cracking in brittle solids. In the regime of
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ductile removal, the ductile or ductile-like grooves are generated on the surface through
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repeated interaction between abrasive grits and workpiece material, and subsurface damage is
often at nanoscale and consists of the defects caused by plastic deformation [31]. The grit depth
of cut involved in abrasive machining of a brittle material is a key parameter that determines
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the material removal mode. A smaller grit cutting depth would cause less damage to the ground
surface, thus promoting more ductile removal [32]. For the grinding and lapping process, the
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grit depth of cut is induced by different process conditions. The cutting depth of grit in grinding
was related to the wheel characteristic, workpiece properties, and grinding parameters [33], but
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the grit depth of cut in lapping is determined by grit size and lapping pressure [34]. Because
abrasive grits are free in a lapping slurry, material removal in such a lapping process is
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accompanied by grits random rolling, squeezing, and scratching, which belongs to the three-
body abrasion. In contrast, the material removal in grinding is carried out through regular
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abrasive scratching with deterministic trajectories in the grinding wheels, which belongs to two-
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body abrasion. The non-uniform grits size effect under three-body abrasion could lead to severe
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surface damage [35]. The large size of grit would take on higher pressures, resulting in
increased damage. Therefore, lapping is more unpredictable than grinding, and the grit depth
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of cut in lapping is more determined by grit size. As a result, to achieve higher surface quality
the grit size in the lapping slurry should be smaller.
Ductile removal is an ideal mode to obtain a low-damage surface in abrasive machining
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of a brittle material, and the machined surface favors the subsequent CMP polishing too.
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Although the material is removed in the ductile regime, different abrasive abrasions would also
affect the deformation behaviors of materials. Our results showed that the damage layer patterns
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of the ground and lapped surfaces are different due to the difference in the abrasion mode of
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the two processes. Figure 11 shows the cross-sectional transmission electron microscope (TEM)
images of the ground and lapped surfaces of Sample D that have the smallest surface roughness.
The damage layer depth of the ground surface is 145 nm, that of the lapped surface is 320 nm.
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No cracks were observed in the subsurface layers, but the layer depth is deeper for lapping than
grinding. In the scratching of silicon, the subsurface defects usually include amorphous phases,
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stacking faults, lattice distortions, and dislocations [36]. But grinding is the process with a
higher scratching speed. The strain rate effect associated with the scratching speed difference
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between grinding and lapping might cause the variation in both damage patterns and residual
stress decays in the ground and lapped subsurface layers [37]. In other words, grinding would
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produce a more obvious "skin" effect. Our TEM examination indicated that in comparison to
the lapped subsurface the density of stacking faults in the ground subsurface is lower, and the
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location of stacking faults in the ground subsurface is close to the amorphous layer. The residual
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stress on the machined surface was positively correlated with the degree of lattice distortion in
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the surface layer [38]. In the high-resolution TEM images shown in Figure 11(c) and (f), both
the ground and lapped surfaces show obvious lattice distortion accompanied by dislocation slip
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due to the existence of residual stress. The stacking faults induced by larger amounts of plastic
deformation can also affect the mechanical properties of silicon damaged layers, ultimately
resulting in smaller elastic recovery [39]. More severe stacking faults were generated in the
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lapped subsurface, which is associated with the lower hardness of the lapped surface.
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Fig. 11. Cross-sectional TEM images of the ground and lapped surfaces of Sample D, (a), (b) and (c) presents the
ground surface, (d), (e) and (f) presents the lapped surface.
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4.2 Effect of surface morphology on polishing efficiency
As can be seen from Figs. 9 and 10 that during polishing the roughness Sa of the lapped
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surface reduced faster than that of the ground surface, but the corresponding MRR of the ground
surface was higher than that of the lapped surface. The difference in surface morphology
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between the ground and lapped surfaces should be responsible for these results. The different
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removal properties caused by different abrasion mechanisms would be reflected in the surface
morphology [40]. Figures 12(a) and (c) shows the surface morphology images of the ground
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and lapped surfaces of Sample D. It can be found that the ground surface consists of scratching
grooves, which are oriented along the grinding direction, while the lapped surface presents
evenly and randomly distributed peaks and valleys. The cross-sectional profiles of the ground
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(which was taken perpendicular to the grinding direction) and lapped surfaces are shown in
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Figs. 12 (b) and (d), respectively. The arithmetic average height Sa is used to characterize the
average deviation of the surface profile heights from the mean surface over the sampling area
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[41]. The distribution of profile peaks in the surface profile would affect the arithmetic mean
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height Sa value. The Sa value decreases as the number of peaks decreases. Because the surface
profile peaks are first removed during CMP, the surface roughness Sa would decrease much
faster in the earlier stage of polishing. As can be seen in Figs. 12(b) and (d), the peaks of the
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ground sample are much more than that of the lapped one for the same sampling area. Therefore,
removing the peaks on the ground surface would take a longer time for CMP. This suggests
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that the surface roughness of the ground surface would drop at a slower rate than the lapped
surface for the same polishing time, as shown in Fig. 9.

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Fig. 12. (a) Surface morphology and (b) cross-sectional profile of the ground surface; (c) surface morphology
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and (d) cross-sectional profile of the lapped surface.
The MRR in CMP was also affected by the morphology. As shown in Fig. 10, the MRR
of the ground sample was greater than that of the lapped one surface in the first 20 minutes of
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polishing, but the rates were almost the same for both ground and lapped samples after 60
minutes. The material removal mechanism of CMP relies on the various physical and chemical
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reactions that occur at the wafer-pad interface, so the real contact area between the wafer and
the polishing pad has a significant impact on the MRR [42]. During polishing, the contact area
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varies with the variation in surface morphology, which in turn affects the MRR. During the
initial stage of CMP, because the contact area between the lapped surface and the polishing pad
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is greater than that between the ground surface and the polishing pad, the MRR in the lapped
surface is expected to be lower than that in the ground surface. When the polishing pad is in
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full contact with the workpiece surface in the later stage of polishing, the rates of both samples
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should be the same and is the lowest, which is supported by the experimental results shown in
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Fig. 10.
A model was developed to further elucidate the removal mechanism, which is based on
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the bearing area ratio of surface contact defined by the Abbott Firestone curve [43, 44]. From
the Abbott Firestone curve, the bearing area ratio is determined by the contact area between the
surface profile and the polishing pad. The three-dimensional morphology of a surface can be
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described as a free surface z = F(x, y), and the cross-sectional profiles can be defined as z = f (
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x), as shown in Fig. 13. If the depth of removal is ∆h for a unit time of ∆t, the MRR can thus
be expressed as er
h
MRR  (2)
t
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Assuming that the volume of silicon removed by CMP is constant, the polishing removed
area ∆S in ∆t should be constant, which is the light grey area in Fig. 13. Therefore, the
bearing area ratio Bar(t) can be written as Eq. (3), which is the total length of the red segments
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displayed in Fig. 13. The bearing area ratio Bar(t) is a dynamic parameter as the contact area
varies with polishing time. As the removal areas in grinding and lapping remained the same,
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the changes in bearing area ratio would represent the difference of their material removal
heights ∆h, as shown in Fig. 13. The contact area variation of the grinding and lapping surface
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during the CMP can thus be well characterized by the bearing area ratio Bar(t).
S  f  x  dx
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Bar (t )   (3)
h MRR  t
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Fig. 13. Schematic illustration of the bearing area ratio models for the polishing of (a) ground and (b) lapped
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surfaces.
In our model, the bearing area ratio was calculated using the following steps. First, in a
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scanning area of three-dimensional morphology, 283×212 μm2 in this case, the surface profile
was composed of a set of discrete data points, where x   0, m  , y   0, n  , z   hmax , hmin  .

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All the data points formed a matrix of order m by n. Second, the data points of k were deleted
to represent a material removal of ∆h in depth, expressed as

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k
k   Pk  x, y, z  z ≥ hmax ‒ ∆h (4)
i 1
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Third, the bearing area ratio for a polishing time of ∆t was calculated by
k
Bar (t )  (5)
m n
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In this work, the surface morphology of the samples was measured by an optical
interference profiler (Newview9000, Zygo, USA) during polishing, which was digitized using
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the MATLAB software, and the bearing area ratio curves were obtained.
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24
ed
v iew
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er
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Fig. 14. The bearing area ratio curves of the ground and lapped surfaces during polishing for Samples (a) A, (b)
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B, (c) C and (d) D.
Figure 14 shows that the bearing area ratio of the lapped surface is higher than that of the
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ground surface. This suggests that the lapped surface morphology would generate a larger
contact area during polishing, which would decrease the MRR of CMP, which is consistent
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with the results shown in Fig. 10. A greater bearing area ratio also means a higher proportion
of peaks of the surface profile being removed, leading to a decreased surface roughness, as
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agreed by the results shown in Fig. 9. As the peaks and valleys in the cross-sectional profiles
were completed removed in CMP, and the bearing area rate would continue to increase till
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reaching 100%. When the polishing pad was in full contact with the sample surface, the
corresponding MRR would reach the lowest, and an ultra-smooth surface would be obtained.
25
5 Conclusions
ed
The surface morphology and subsurface damage generated by grinding and lapping were
comparatively investigated in this work. Grinding and lapping produced distinct surface
iew
morphologies, as well subsurface damage patterns. The ground surfaces exhibit regular
distributed grinding striations, while the lapped surfaces present randomly distributed striations
with shallow chipping spots. Both the ground and lapped sublayers have crystallographic
v
defects mainly including amorphous phases, dislocations and stacking faults. For the same
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surface roughness values, the lapped subsurface has a higher density of stacking faults than that
the ground subsurface, thus leading to a lower surface hardness.

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In CMP, the surface roughness of the lapped surface was decreased faster than that of the
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ground surface, but the removal rate for the lapped surface was lower than that for the ground
surface, although both the lapped and ground surfaces had almost the same starting values of
average surface roughness. These were mainly attributed to the distinct morphologies of the
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two surfaces: the lapped surface had more randomly distributed peaks corresponding to a larger
contact area during polishing, but the ground surface had an oriented distributed grooves with
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a smaller contact area.
The bearing area ratio model developed in this study helped elucidate the removal
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mechanism of silicon wafers in mechanical polishing. The lapped surface with a morphology
of homogeneous distributed peaks would produce a higher bearing area ratio, while the ground
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surface with a morphology of regularly distributed striations would lead to a smaller ratio. A
higher bearing area ratio reflects a larger contact area, thus resulting in a lower MRR in CMP.
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This model can be extended for any ultraprecision abrasive machining process of brittle
26
materials.
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CRediT author statement
iew
Shang Gao: Conceptualization, Methodology, Investigation, Writing - Original Draft.
Honggang Li: Data Curation, Formal analysis, Writing - Review & Editing. Han Huang:
Writing - Review & Editing, Methodology. Renke Kang: Supervision, Funding acquisition,
v
Resources.
re
Funding er
This research is financially supported by the National Natural Science Foundation of
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China (51991372, 51975091, 51735004), the National Key Research and Development
Program of China (2018YFB1201804-1), and the Australian Research Council (ARC
DP210102061).
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Figures include in the manuscript
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Fig. 1. Silicon wafer planarization: (a) grinding, (b) lapping, and (c) CMP.
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Fig. 2. Schematic illustration of the sample preparation for examining sub-surface damage layer.
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Fig. 3. Schematic illustration of the method for measuring MRR of CMP. (a) Make an indent on the sample
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surface before CMP, (b) measure the indent profiles before and after CMP, and (c) determine the difference
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between the indent profiles before and after polishing to obtain the removal height.
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Fig. 4. Surface roughness values after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d)
D.
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Fig. 5. Surface morphologies after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d) D.
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Fig. 6. Surface images of Samples (a) A, (b) B, (c) C and (d) D after grinding and lapping.
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Fig. 7. Subsurface damage after grinding and lapping are displayed for Samples (a) A, (b) B, (c) C and (d) D.
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Fig. 8. The nanoindentation hardness values of the surface after grinding, lapping, and CMP.
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Fig. 9. Surface roughness values of Samples (a) A, (b) B, (c) C and (d) D plotted as a function of polishing time.
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Fig. 10. The MRR values of Samples (a) A, (b) B, (c) C and (d) D plotted as a function of polishing time.
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Fig. 11. Cross-sectional TEM images of the ground and lapped surfaces of Sample D, (a), (b) and (c) presents the
ground surface, (d), (e) and (f) presents the lapped surface.
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Fig. 12. (a) Surface morphology and (b) cross-sectional profile of the ground surface; (c) surface morphology
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and (d) cross-sectional profile of the lapped surface.
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Fig. 13. Schematic illustration of the bearing area ratio models for the polishing of (a) ground and (b) lapped
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surfaces.
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Fig. 14. The bearing area ratio curves of the ground and lapped surfaces during polishing for Samples (a) A, (b)
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B, (c) C and (d) D.

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Tables includes in the manuscript
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Table 1. Surface roughness values of the silicon samples after grinding and lapping.
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Sample sign Ground surface Sa (μm) Lapped surface Sa (μm)
A 0.538 0.557
B 0.246 0.258
C 0.126 0.118
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D 0.011 0.011
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Table 2. The experimental parameters for grinding and lapping.
Machining parameters Sample A Sample B Sample C Sample D
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Mesh size of wheels #120 #600 #1500 #3000
Bond type Resin Resin Resin Resin
Grits size (μm) 125 25 10 5

Grinding
Wheel rotational speed (r/min) 2400 2400 2400 2400
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Table rotational speed (r/min) 120 120 120 120
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Wheel feed rate (μm/min) 20 20 10 5
The grade of abrasives W15 W5 W2 W0.4
Grits size (μm) er 15 5 3 0.4
Lapping plate rotational speed (r/min) 40 40 40 40
Lapping Chuck rotational speed (r/min) 45 45 45 45

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Lapping pressure (Kpa) 30 30 30 30
Slurry flux (ml/min) 30 30 30 30
Lapping time (min) 30 30 30 60

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Table 3. The experimental parameters for CMP.
Polishing parameters Values
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Polishing pad rotational speed (r/min) 40
Chuck rotational speed (r/min) 55
Polishing pressure (Kpa) 50
Slurry flux (ml/min) 30
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Polishing time (min) 100
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50

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Grinding and lapping induced surface integrity of silicon wafers and its

Shang Gaoa,*, Honggang Lia, Han Huangb, Renke Kanga

Education, Dalian University of Technology, Dalian 116024, China

larger surface area was removed, thus leading to a lower MRR.

lapped surface integrity affects the removal of CMP.

involved in grinding or lapping can cause substantial surface/subsurface damage on brittle

lapping and grinding on the removal efficiency in the subsequent polishing.

with a complex reticular distribution. Nevertheless, a systematic investigation on the effect of

ground and lapped surface morphology on the removal of CMP is lacking.

In this work, we comparatively investigated the surface morphology and subsurface

2.1 Silicon samples after grinding and lapping

to investigate the effect of the surface integrity on its removal efficiency.

2.2 Grinding, lapping, and CMP experiments

Grinding was performed on an ultra-precision wafer grinder (VG401 MK II, Okamoto,

the same surface roughness for grinding and lapping.

Table 2. The experimental parameters for grinding and lapping.

Mesh size of wheels #120 #600 #1500 #3000

Grits size (μm) 125 25 10 5

Table rotational speed (r/min) 120 120 120 120

Wheel feed rate (μm/min) 20 20 10 5

The grade of abrasives W15 W5 W2 W0.4

Grits size (μm) 15 5 3 0.4

Lapping plate rotational speed (r/min) 40 40 40 40

Lapping Chuck rotational speed (r/min) 45 45 45 45

Lapping pressure (Kpa) 30 30 30 30

Slurry flux (ml/min) 30 30 30 30

Lapping time (min) 30 30 30 60

the polishing period of 100 minutes.

Table 3. The experimental parameters for CMP.

Chuck rotational speed (r/min) 55

Polishing pressure (Kpa)

Slurry flux (ml/min) 30

Polishing time (min) 100

optical microscope with an ultra-depth of field (VHX-600E, KEYENCE, Japan). Sub-surface

damage was determined utilizing cross-section angle polishing microscopy.

the Keyence microscope.

SSD  L  sin β (1)

Nanoindentation was performed on a nanomechanical testing system (TI950, Hysitron, USA).

3.1 Surface characteristics

roughness values of Sz represent the maximum height of peak-to-valley of the surface. In

3.2 Subsurface damage and property

3.3 Surface roughness and MRR of CMP samples

is obviously shorter than that of the ground surface.

Figure 10 presents the MRR values of Samples A, B, C and D plotted as a function of

require a longer time to achieve the stable MRR.

4.1 Damage induced by grinding and lapping

its effect on polishing efficiency.

the grit size in the lapping slurry should be smaller.

Ductile removal is an ideal mode to obtain a low-damage surface in abrasive machining

4.2 Effect of surface morphology on polishing efficiency

surface for the same polishing time, as shown in Fig. 9.

was composed of a set of discrete data points, where x   0, m  , y   0, n  , z   hmax , hmin  .

to represent a material removal of ∆h in depth, expressed as

B, (c) C and (d) D.

the ground subsurface, thus leading to a lower surface hardness.

a smaller contact area.

Program of China (2018YFB1201804-1), and the Australian Research Council (ARC

perspectives, Int. J. Mach. Tools Manuf, 48 (2008) 1297-1307.

Eng B-J Eng, 225 (2011) 1153-1162. https://doi.org/10.1177/2041297510393620

fabrications, Microelectron. Int. 36 (2019) 150-159.

CMP of silicon wafers, Wear, 270 (2011) 312-316.

chemical mechanical planarization, J. Mater. Res. 36 (2021) 235-257.

mechanism of GO/SiO2 nanoslurries in fixed abrasive lapping, J. Mater. Process. Tech.