Q61.

How to arrive at the value of utilization factor and aspect ratio during
initial floorplan?
Utilization Percentages:
The Assumption is that the Standard Cells occupies 70 % of Base Layers and the remaining 30 % is
utilized for Routing. If the area of macros is more than utilization can be increased
accordingly.

 Blockages, macros, and pads are combined in the denominator of the effective Utilization.

 The effective utilization definition is that all standard cells are placed outside of the blockage
areas. This includes buffers, which (for the purposes of computing utilization) are assumed to
be placed outside of non-buffer blockage areas.

Best Aspect Ratio:

 Consider a five-layer design in which layers 1, 3, and 5 are horizontal and layers 2 and 4 are
vertical. Usually, layer 1 is occupied by the standard cell geometries and is unusable for
routing. Metal layer 2 often connects to metal layer 1 pins through vias. These vias tend to
obstruct about 20 percent of the potential vertical routing on metal layer 2. If routing pitch is
the same on all layers, the ratio between horizontal and vertical layers is approximately 2:
1.8. This means that the available vertical routing resource is less than the horizontal routing
resource, which dictates a chip aspect ratio that is wider than it is high.

 Using the ratio of horizontal-to-vertical routing resources, the best aspect ratio is 1.11;
therefore, the chip aspect ratio is rectangular rather than square and is wider than it is high:

 Next, consider a four-layer design. metal layer 1 is not usable for routing, and metal layer 2 is
20 percent obstructed by vias connecting layer 1 andlayer 2. Layer 3 is horizontal and fully
available, and layer 4 is vertical and fully available. For this case, there is 80 percent more
vertical routing resource than there is horizontal resource. Therefore, the ratio of horizontal
to vertical routing resource is 0.56, and the vertical dimension of this chip is larger than its
horizontal dimension. aspect ratio = W/H = 1/1.8 = .56

The assumptions is that metal layer 1 is unavailable for routing and that metal layer 2 is 20 percent
obstructed by vias.
Q62. What is an HALO? How is it different from the blockage?
Block halos can be specified for hard macros, black boxes, or committed partitions. When you add a
halo to a block, it becomes part of the blocks properties. If you move the block, the halo moves with
it. Blockages can be specified for any part of the design. If we move a block, the blockage will not.

Q63. How much utilization is used in the design?

There is no hard and fast rule, even though if the following values maintained then the design can be
closed without much congestion.

 Floor Plan - 70 %

 Placement - 75 %

 CTS - 80 %

 Routing - 85 %

 During GDSII Generation – 100 %

Q64. What is the difference between standard cells and IO cells? Is there any
difference in the IR operating voltages? If so why is it?
 Std Cells are logical cells. But the IO cells interact between Core and Outside world.

 IO cells contains some protection circuits like short circuit, over voltage.

 There will be difference between Core operating Voltage and IO operating voltage. That
depends on technology library used. For 130 nm generic library the Core voltage is 1.2 v and
IO voltage is 2.5/3.3.

Q65. What is the significance of simultaneous switching output (SSO) file?

 SSO: The abbreviation of “Simultaneously Switching Outputs”, which means that a certain
number of I/O buffers switching at the same time with the same direction (H ! L, HZ ! L or L !
H, LZ ! H). This simultaneous switching will cause noise on the power/ground lines because
of the large di/dt value and the parasitic inductance of the bonding wire on the I/O
power/ground cells.
  SSN: The noise produced by simultaneously switching output buffers. It will change the
voltage levels of power/ground nodes and is so-called “Ground Bounce Effect”. This effect is
tested at the device output by keeping one stable output at low “0” or high “1”, while all other
outputs of the device switch simultaneously. The noise occurred at the stable output node is
called “Quiet Output Switching “(QOS). If the input low voltage is defined as Vil, the QOS of
“Vil” is taken to be the maximum noise that the system can endure.

 DI: The maximum copies of specific I/O cell switching from high to low simultaneously
without making the voltage on the quiet output “0” higher than “Vil” when single ground cell is
applied. We take the QOS of “Vil” as criterion in defining DI because “1” has more noise
margin than “0”. For example, in LVTTL specification, the margin of “Vih” (2.0V) to VD33
(3.3V) is 1.3V in typical corner, which is higher than the margin of “Vil” (0.8V) to ground (0V).
DF: “Drive Factor” is the amount of how the specific output buffer contributes to the SSN on
the power/ground rail. The DF value of an output buffer is proportional to dI/dt, the derivative
of the current on the output buffer. We can obtain DF as: DF = 1 / DI

Q66. Is there any checklist to be received from the front end related to switching
activity of any nets to be taken care of at the floor planning stage?
Yes. The Switching activities of Macros will be available in checklist; it contains the power
consumption of each macro at different frequencies are also available

Q67. What is power trunk?

Power trunk is the piece of metal connects the IO pad and Core ring.

Q68. How to handle hotspot in a chip?

Increasing the number of power straps or increasing the width of power strap will help us to reduce
hot spot created by voltage drop and to maintain the voltage drop less than 10 %.

Q69. What is power gating?

Power gating is one of power reduction technique. This helps by shutting down the particular area of
chip from utilizing power.

Q70. Whether macro power ring is mandatory or optional?

For hierarchical design the macro power ring is mandatory. For flat design the macro power ring is
optional.