Q91. How did you handle all those clocks?

 Multiple clocks →synthesize separately →balance the skew →optimize the clock tree Are
they come from separate external resources or PLL?

 If it is from separate clock sources (i.e. Asynchronous; from different pads or pins) then
balancing skew between these clock sources becomes challenging.

 If it is from PLL (i.e. Synchronous) then skew balancing is comparatively easy.

Q92. Why buffers are used in clock tree?

To balance skew (i.e. flop to flop delay)

Q93. Which is more complicated when u have a 48 MHz and 500 MHz clock
design?
500 MHz; because it is more constrained (i.e. Lesser clock period) than 48 MHz design.

Q94.What is congestion?
If the number of routing tracks available for routing is less than the required tracks, then it is known
as congestion.

Q95. What kinds of timing violations are in a typical timing analysis report?
 Setup time violations - Hold time violations

 Minimum delay - Maximum delay

 Slack - External delay

Q96. Can a latch based design be analyzed using STA?

Setup and Hold Checking for Latches Latch-based designs typically use two-phase, non-overlapping
clocks to control successive registers in a data path. In these cases, Timing Engine can use time
borrowing to lessen the constraints on successive paths. For example, consider the two-phase,
latch-based path shown in Figure 1 All three latches are level-sensitive, with the gate active when
the G input is high. L1 and L3 are controlled by PH1, and L2 is controlled by PH2. A rising edge
launches data from the latch output, and a falling edge captures data at the latch input. For this
example, consider the latch setup and delay times to be zero.

Figure 2 shows how Timing Engine performs setup checks between these latches. For the path from
L1 to L2, the rising edge of PH1 launches the data. The data must arrive at L2 before the closing
edge of PH2 at time=20. This timing requirement is labeled Setup 1. Depending on the amount of
delay between L1 and L2, the data might arrive either before or after the opening edge of PH2 (at
time=10), as indicated by the dashed-line arrows in the timing diagram. Arrival after time=20 would
be a timing violation.

If the data arrives at L2 before the opening edge of PH2 at time=10, the data for the next path from
L2 to L3 gets launched by the opening edge of PH2 at time=10, just as a synchronous flip-flop would
operate. This timing requirement is labeled Setup 2a. If the data arrives after the opening edge of
PH2, the first path (from L1 to L2) borrows time from the second path (from L2 to L3). In that case,
the launch of data for the second path occurs not at the opening edge, but at the data arrival time at
L2, at some time between the opening and closing edges of PH2. This timing requirement is labeled
Setup 2b. When borrowing occurs, the path originates at the D pin rather than the G pin of L2.
For the first path (from L1 to L2), Timing Engine reports the setup slack as zero if borrowing occurs.
The slack is positive if the data arrives before the opening edge at time=10, or negative (a violation)
if the data arrives after the closing edge at time=20. To perform hold checking, Timing Engine
considers the launch and capture edges relative to the setup check. It verifies that data launched at
the start point does not reach the endpoint too quickly, thereby ensuring that data launched in the
previous cycle is latched and not overwritten by the new data. This is depicted in Figure 3.

Q97. How delays vary with different PVT conditions? Show the graph?

 P increase ➜ delay increase

 P decrease ➜ delay decrease

 V increase ➜ delay decrease

 V decrease ➜ delay increase

 T increase ➜ delay increase

 T decrease ➜ delay decrease

Q98. What is cell delay and net delay?

Gate delay

 Gate delay =function of (i/p transition time, Cnet+Cpin).

  Cell delay is also same as Gate delay.

Cell delay

 For any gate it is measured between 50% of input transition to the corresponding 50% of
output transition.

 Intrinsic delay

 Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

 It is defined as the delay between an input and output pair of a cell, when a near zero slew is
applied to the input pin and the output does not see any load condition. It is predominantly
caused by the internal capacitance associated with its transistor.

 This delay is largely independent of the size of the transistors forming the gate because
increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

 The difference between the time a signal is first applied to the net and the time it reaches
other devices connected to that net.

 It is due to the finite resistance and capacitance of the net. It is also known as wire delay.

 Wire delay =fn(Rnet , Cnet+Cpin)

Q99. What are delay models and what is the difference between them?
 Linear Delay Model (LDM)

 Non Linear Delay Model (NLDM)

 Composite current source modeling (CCS)

Q100. What is wire load model?

Wire load model is NLDM which has estimated R and C of the net